1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Memory Encryption Support
5 * Copyright (C) 2019 SUSE
7 * Author: Joerg Roedel <jroedel@suse.de>
10 #define pr_fmt(fmt) "SEV: " fmt
12 #include <linux/sched/debug.h> /* For show_regs() */
13 #include <linux/percpu-defs.h>
14 #include <linux/cc_platform.h>
15 #include <linux/printk.h>
16 #include <linux/mm_types.h>
17 #include <linux/set_memory.h>
18 #include <linux/memblock.h>
19 #include <linux/kernel.h>
22 #include <asm/cpu_entry_area.h>
23 #include <asm/stacktrace.h>
25 #include <asm/insn-eval.h>
26 #include <asm/fpu/xcr.h>
27 #include <asm/processor.h>
28 #include <asm/realmode.h>
29 #include <asm/traps.h>
34 #define DR7_RESET_VALUE 0x400
36 /* For early boot hypervisor communication in SEV-ES enabled guests */
37 static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE);
40 * Needs to be in the .data section because we need it NULL before bss is
43 static struct ghcb __initdata *boot_ghcb;
45 /* #VC handler runtime per-CPU data */
46 struct sev_es_runtime_data {
47 struct ghcb ghcb_page;
50 * Reserve one page per CPU as backup storage for the unencrypted GHCB.
51 * It is needed when an NMI happens while the #VC handler uses the real
52 * GHCB, and the NMI handler itself is causing another #VC exception. In
53 * that case the GHCB content of the first handler needs to be backed up
56 struct ghcb backup_ghcb;
59 * Mark the per-cpu GHCBs as in-use to detect nested #VC exceptions.
60 * There is no need for it to be atomic, because nothing is written to
61 * the GHCB between the read and the write of ghcb_active. So it is safe
62 * to use it when a nested #VC exception happens before the write.
64 * This is necessary for example in the #VC->NMI->#VC case when the NMI
65 * happens while the first #VC handler uses the GHCB. When the NMI code
66 * raises a second #VC handler it might overwrite the contents of the
67 * GHCB written by the first handler. To avoid this the content of the
68 * GHCB is saved and restored when the GHCB is detected to be in use
72 bool backup_ghcb_active;
75 * Cached DR7 value - write it on DR7 writes and return it on reads.
76 * That value will never make it to the real hardware DR7 as debugging
77 * is currently unsupported in SEV-ES guests.
86 static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data);
87 DEFINE_STATIC_KEY_FALSE(sev_es_enable_key);
89 /* Needed in vc_early_forward_exception */
90 void do_early_exception(struct pt_regs *regs, int trapnr);
92 static __always_inline bool on_vc_stack(struct pt_regs *regs)
94 unsigned long sp = regs->sp;
96 /* User-mode RSP is not trusted */
100 /* SYSCALL gap still has user-mode RSP */
101 if (ip_within_syscall_gap(regs))
104 return ((sp >= __this_cpu_ist_bottom_va(VC)) && (sp < __this_cpu_ist_top_va(VC)));
108 * This function handles the case when an NMI is raised in the #VC
109 * exception handler entry code, before the #VC handler has switched off
110 * its IST stack. In this case, the IST entry for #VC must be adjusted,
111 * so that any nested #VC exception will not overwrite the stack
112 * contents of the interrupted #VC handler.
114 * The IST entry is adjusted unconditionally so that it can be also be
115 * unconditionally adjusted back in __sev_es_ist_exit(). Otherwise a
116 * nested sev_es_ist_exit() call may adjust back the IST entry too
119 * The __sev_es_ist_enter() and __sev_es_ist_exit() functions always run
120 * on the NMI IST stack, as they are only called from NMI handling code
123 void noinstr __sev_es_ist_enter(struct pt_regs *regs)
125 unsigned long old_ist, new_ist;
127 /* Read old IST entry */
128 new_ist = old_ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
131 * If NMI happened while on the #VC IST stack, set the new IST
132 * value below regs->sp, so that the interrupted stack frame is
133 * not overwritten by subsequent #VC exceptions.
135 if (on_vc_stack(regs))
139 * Reserve additional 8 bytes and store old IST value so this
140 * adjustment can be unrolled in __sev_es_ist_exit().
142 new_ist -= sizeof(old_ist);
143 *(unsigned long *)new_ist = old_ist;
145 /* Set new IST entry */
146 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], new_ist);
149 void noinstr __sev_es_ist_exit(void)
154 ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
156 if (WARN_ON(ist == __this_cpu_ist_top_va(VC)))
159 /* Read back old IST entry and write it to the TSS */
160 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist);
164 * Nothing shall interrupt this code path while holding the per-CPU
165 * GHCB. The backup GHCB is only for NMIs interrupting this path.
167 * Callers must disable local interrupts around it.
169 static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state)
171 struct sev_es_runtime_data *data;
174 WARN_ON(!irqs_disabled());
176 data = this_cpu_read(runtime_data);
177 ghcb = &data->ghcb_page;
179 if (unlikely(data->ghcb_active)) {
180 /* GHCB is already in use - save its contents */
182 if (unlikely(data->backup_ghcb_active)) {
184 * Backup-GHCB is also already in use. There is no way
185 * to continue here so just kill the machine. To make
186 * panic() work, mark GHCBs inactive so that messages
187 * can be printed out.
189 data->ghcb_active = false;
190 data->backup_ghcb_active = false;
192 instrumentation_begin();
193 panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use");
194 instrumentation_end();
197 /* Mark backup_ghcb active before writing to it */
198 data->backup_ghcb_active = true;
200 state->ghcb = &data->backup_ghcb;
202 /* Backup GHCB content */
203 *state->ghcb = *ghcb;
206 data->ghcb_active = true;
212 /* Needed in vc_early_forward_exception */
213 void do_early_exception(struct pt_regs *regs, int trapnr);
215 static inline u64 sev_es_rd_ghcb_msr(void)
217 return __rdmsr(MSR_AMD64_SEV_ES_GHCB);
220 static __always_inline void sev_es_wr_ghcb_msr(u64 val)
225 high = (u32)(val >> 32);
227 native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high);
230 static int vc_fetch_insn_kernel(struct es_em_ctxt *ctxt,
231 unsigned char *buffer)
233 return copy_from_kernel_nofault(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);
236 static enum es_result __vc_decode_user_insn(struct es_em_ctxt *ctxt)
238 char buffer[MAX_INSN_SIZE];
241 insn_bytes = insn_fetch_from_user_inatomic(ctxt->regs, buffer);
242 if (insn_bytes == 0) {
243 /* Nothing could be copied */
244 ctxt->fi.vector = X86_TRAP_PF;
245 ctxt->fi.error_code = X86_PF_INSTR | X86_PF_USER;
246 ctxt->fi.cr2 = ctxt->regs->ip;
248 } else if (insn_bytes == -EINVAL) {
249 /* Effective RIP could not be calculated */
250 ctxt->fi.vector = X86_TRAP_GP;
251 ctxt->fi.error_code = 0;
256 if (!insn_decode_from_regs(&ctxt->insn, ctxt->regs, buffer, insn_bytes))
257 return ES_DECODE_FAILED;
259 if (ctxt->insn.immediate.got)
262 return ES_DECODE_FAILED;
265 static enum es_result __vc_decode_kern_insn(struct es_em_ctxt *ctxt)
267 char buffer[MAX_INSN_SIZE];
270 res = vc_fetch_insn_kernel(ctxt, buffer);
272 ctxt->fi.vector = X86_TRAP_PF;
273 ctxt->fi.error_code = X86_PF_INSTR;
274 ctxt->fi.cr2 = ctxt->regs->ip;
278 ret = insn_decode(&ctxt->insn, buffer, MAX_INSN_SIZE, INSN_MODE_64);
280 return ES_DECODE_FAILED;
285 static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
287 if (user_mode(ctxt->regs))
288 return __vc_decode_user_insn(ctxt);
290 return __vc_decode_kern_insn(ctxt);
293 static enum es_result vc_write_mem(struct es_em_ctxt *ctxt,
294 char *dst, char *buf, size_t size)
296 unsigned long error_code = X86_PF_PROT | X86_PF_WRITE;
299 * This function uses __put_user() independent of whether kernel or user
300 * memory is accessed. This works fine because __put_user() does no
301 * sanity checks of the pointer being accessed. All that it does is
302 * to report when the access failed.
304 * Also, this function runs in atomic context, so __put_user() is not
305 * allowed to sleep. The page-fault handler detects that it is running
306 * in atomic context and will not try to take mmap_sem and handle the
307 * fault, so additional pagefault_enable()/disable() calls are not
310 * The access can't be done via copy_to_user() here because
311 * vc_write_mem() must not use string instructions to access unsafe
312 * memory. The reason is that MOVS is emulated by the #VC handler by
313 * splitting the move up into a read and a write and taking a nested #VC
314 * exception on whatever of them is the MMIO access. Using string
315 * instructions here would cause infinite nesting.
320 u8 __user *target = (u8 __user *)dst;
323 if (__put_user(d1, target))
329 u16 __user *target = (u16 __user *)dst;
332 if (__put_user(d2, target))
338 u32 __user *target = (u32 __user *)dst;
341 if (__put_user(d4, target))
347 u64 __user *target = (u64 __user *)dst;
350 if (__put_user(d8, target))
355 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size);
356 return ES_UNSUPPORTED;
362 if (user_mode(ctxt->regs))
363 error_code |= X86_PF_USER;
365 ctxt->fi.vector = X86_TRAP_PF;
366 ctxt->fi.error_code = error_code;
367 ctxt->fi.cr2 = (unsigned long)dst;
372 static enum es_result vc_read_mem(struct es_em_ctxt *ctxt,
373 char *src, char *buf, size_t size)
375 unsigned long error_code = X86_PF_PROT;
378 * This function uses __get_user() independent of whether kernel or user
379 * memory is accessed. This works fine because __get_user() does no
380 * sanity checks of the pointer being accessed. All that it does is
381 * to report when the access failed.
383 * Also, this function runs in atomic context, so __get_user() is not
384 * allowed to sleep. The page-fault handler detects that it is running
385 * in atomic context and will not try to take mmap_sem and handle the
386 * fault, so additional pagefault_enable()/disable() calls are not
389 * The access can't be done via copy_from_user() here because
390 * vc_read_mem() must not use string instructions to access unsafe
391 * memory. The reason is that MOVS is emulated by the #VC handler by
392 * splitting the move up into a read and a write and taking a nested #VC
393 * exception on whatever of them is the MMIO access. Using string
394 * instructions here would cause infinite nesting.
399 u8 __user *s = (u8 __user *)src;
401 if (__get_user(d1, s))
408 u16 __user *s = (u16 __user *)src;
410 if (__get_user(d2, s))
417 u32 __user *s = (u32 __user *)src;
419 if (__get_user(d4, s))
426 u64 __user *s = (u64 __user *)src;
427 if (__get_user(d8, s))
433 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size);
434 return ES_UNSUPPORTED;
440 if (user_mode(ctxt->regs))
441 error_code |= X86_PF_USER;
443 ctxt->fi.vector = X86_TRAP_PF;
444 ctxt->fi.error_code = error_code;
445 ctxt->fi.cr2 = (unsigned long)src;
450 static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
451 unsigned long vaddr, phys_addr_t *paddr)
453 unsigned long va = (unsigned long)vaddr;
459 pgd = __va(read_cr3_pa());
460 pgd = &pgd[pgd_index(va)];
461 pte = lookup_address_in_pgd(pgd, va, &level);
463 ctxt->fi.vector = X86_TRAP_PF;
464 ctxt->fi.cr2 = vaddr;
465 ctxt->fi.error_code = 0;
467 if (user_mode(ctxt->regs))
468 ctxt->fi.error_code |= X86_PF_USER;
473 if (WARN_ON_ONCE(pte_val(*pte) & _PAGE_ENC))
474 /* Emulated MMIO to/from encrypted memory not supported */
475 return ES_UNSUPPORTED;
477 pa = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
478 pa |= va & ~page_level_mask(level);
485 /* Include code shared with pre-decompression boot stage */
486 #include "sev-shared.c"
488 static noinstr void __sev_put_ghcb(struct ghcb_state *state)
490 struct sev_es_runtime_data *data;
493 WARN_ON(!irqs_disabled());
495 data = this_cpu_read(runtime_data);
496 ghcb = &data->ghcb_page;
499 /* Restore GHCB from Backup */
500 *ghcb = *state->ghcb;
501 data->backup_ghcb_active = false;
505 * Invalidate the GHCB so a VMGEXIT instruction issued
506 * from userspace won't appear to be valid.
508 vc_ghcb_invalidate(ghcb);
509 data->ghcb_active = false;
513 void noinstr __sev_es_nmi_complete(void)
515 struct ghcb_state state;
518 ghcb = __sev_get_ghcb(&state);
520 vc_ghcb_invalidate(ghcb);
521 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_NMI_COMPLETE);
522 ghcb_set_sw_exit_info_1(ghcb, 0);
523 ghcb_set_sw_exit_info_2(ghcb, 0);
525 sev_es_wr_ghcb_msr(__pa_nodebug(ghcb));
528 __sev_put_ghcb(&state);
531 static u64 get_jump_table_addr(void)
533 struct ghcb_state state;
538 local_irq_save(flags);
540 ghcb = __sev_get_ghcb(&state);
542 vc_ghcb_invalidate(ghcb);
543 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_JUMP_TABLE);
544 ghcb_set_sw_exit_info_1(ghcb, SVM_VMGEXIT_GET_AP_JUMP_TABLE);
545 ghcb_set_sw_exit_info_2(ghcb, 0);
547 sev_es_wr_ghcb_msr(__pa(ghcb));
550 if (ghcb_sw_exit_info_1_is_valid(ghcb) &&
551 ghcb_sw_exit_info_2_is_valid(ghcb))
552 ret = ghcb->save.sw_exit_info_2;
554 __sev_put_ghcb(&state);
556 local_irq_restore(flags);
561 int sev_es_setup_ap_jump_table(struct real_mode_header *rmh)
563 u16 startup_cs, startup_ip;
564 phys_addr_t jump_table_pa;
566 u16 __iomem *jump_table;
568 jump_table_addr = get_jump_table_addr();
570 /* On UP guests there is no jump table so this is not a failure */
571 if (!jump_table_addr)
574 /* Check if AP Jump Table is page-aligned */
575 if (jump_table_addr & ~PAGE_MASK)
578 jump_table_pa = jump_table_addr & PAGE_MASK;
580 startup_cs = (u16)(rmh->trampoline_start >> 4);
581 startup_ip = (u16)(rmh->sev_es_trampoline_start -
582 rmh->trampoline_start);
584 jump_table = ioremap_encrypted(jump_table_pa, PAGE_SIZE);
588 writew(startup_ip, &jump_table[0]);
589 writew(startup_cs, &jump_table[1]);
597 * This is needed by the OVMF UEFI firmware which will use whatever it finds in
598 * the GHCB MSR as its GHCB to talk to the hypervisor. So make sure the per-cpu
599 * runtime GHCBs used by the kernel are also mapped in the EFI page-table.
601 int __init sev_es_efi_map_ghcbs(pgd_t *pgd)
603 struct sev_es_runtime_data *data;
604 unsigned long address, pflags;
608 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT))
611 pflags = _PAGE_NX | _PAGE_RW;
613 for_each_possible_cpu(cpu) {
614 data = per_cpu(runtime_data, cpu);
616 address = __pa(&data->ghcb_page);
617 pfn = address >> PAGE_SHIFT;
619 if (kernel_map_pages_in_pgd(pgd, pfn, address, 1, pflags))
626 static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
628 struct pt_regs *regs = ctxt->regs;
633 exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0;
635 ghcb_set_rcx(ghcb, regs->cx);
637 ghcb_set_rax(ghcb, regs->ax);
638 ghcb_set_rdx(ghcb, regs->dx);
641 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_MSR,
644 if ((ret == ES_OK) && (!exit_info_1)) {
645 regs->ax = ghcb->save.rax;
646 regs->dx = ghcb->save.rdx;
653 * This function runs on the first #VC exception after the kernel
654 * switched to virtual addresses.
656 static bool __init sev_es_setup_ghcb(void)
658 /* First make sure the hypervisor talks a supported protocol. */
659 if (!sev_es_negotiate_protocol())
663 * Clear the boot_ghcb. The first exception comes in before the bss
664 * section is cleared.
666 memset(&boot_ghcb_page, 0, PAGE_SIZE);
668 /* Alright - Make the boot-ghcb public */
669 boot_ghcb = &boot_ghcb_page;
674 #ifdef CONFIG_HOTPLUG_CPU
675 static void sev_es_ap_hlt_loop(void)
677 struct ghcb_state state;
680 ghcb = __sev_get_ghcb(&state);
683 vc_ghcb_invalidate(ghcb);
684 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_HLT_LOOP);
685 ghcb_set_sw_exit_info_1(ghcb, 0);
686 ghcb_set_sw_exit_info_2(ghcb, 0);
688 sev_es_wr_ghcb_msr(__pa(ghcb));
692 if (ghcb_sw_exit_info_2_is_valid(ghcb) &&
693 ghcb->save.sw_exit_info_2)
697 __sev_put_ghcb(&state);
701 * Play_dead handler when running under SEV-ES. This is needed because
702 * the hypervisor can't deliver an SIPI request to restart the AP.
703 * Instead the kernel has to issue a VMGEXIT to halt the VCPU until the
704 * hypervisor wakes it up again.
706 static void sev_es_play_dead(void)
710 /* IRQs now disabled */
712 sev_es_ap_hlt_loop();
715 * If we get here, the VCPU was woken up again. Jump to CPU
716 * startup code to get it back online.
720 #else /* CONFIG_HOTPLUG_CPU */
721 #define sev_es_play_dead native_play_dead
722 #endif /* CONFIG_HOTPLUG_CPU */
725 static void __init sev_es_setup_play_dead(void)
727 smp_ops.play_dead = sev_es_play_dead;
730 static inline void sev_es_setup_play_dead(void) { }
733 static void __init alloc_runtime_data(int cpu)
735 struct sev_es_runtime_data *data;
737 data = memblock_alloc(sizeof(*data), PAGE_SIZE);
739 panic("Can't allocate SEV-ES runtime data");
741 per_cpu(runtime_data, cpu) = data;
744 static void __init init_ghcb(int cpu)
746 struct sev_es_runtime_data *data;
749 data = per_cpu(runtime_data, cpu);
751 err = early_set_memory_decrypted((unsigned long)&data->ghcb_page,
752 sizeof(data->ghcb_page));
754 panic("Can't map GHCBs unencrypted");
756 memset(&data->ghcb_page, 0, sizeof(data->ghcb_page));
758 data->ghcb_active = false;
759 data->backup_ghcb_active = false;
762 void __init sev_es_init_vc_handling(void)
766 BUILD_BUG_ON(offsetof(struct sev_es_runtime_data, ghcb_page) % PAGE_SIZE);
768 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT))
771 if (!sev_es_check_cpu_features())
772 panic("SEV-ES CPU Features missing");
774 /* Enable SEV-ES special handling */
775 static_branch_enable(&sev_es_enable_key);
777 /* Initialize per-cpu GHCB pages */
778 for_each_possible_cpu(cpu) {
779 alloc_runtime_data(cpu);
783 sev_es_setup_play_dead();
785 /* Secondary CPUs use the runtime #VC handler */
786 initial_vc_handler = (unsigned long)kernel_exc_vmm_communication;
789 static void __init vc_early_forward_exception(struct es_em_ctxt *ctxt)
791 int trapnr = ctxt->fi.vector;
793 if (trapnr == X86_TRAP_PF)
794 native_write_cr2(ctxt->fi.cr2);
796 ctxt->regs->orig_ax = ctxt->fi.error_code;
797 do_early_exception(ctxt->regs, trapnr);
800 static long *vc_insn_get_reg(struct es_em_ctxt *ctxt)
805 reg_array = (long *)ctxt->regs;
806 offset = insn_get_modrm_reg_off(&ctxt->insn, ctxt->regs);
811 offset /= sizeof(long);
813 return reg_array + offset;
816 static long *vc_insn_get_rm(struct es_em_ctxt *ctxt)
821 reg_array = (long *)ctxt->regs;
822 offset = insn_get_modrm_rm_off(&ctxt->insn, ctxt->regs);
827 offset /= sizeof(long);
829 return reg_array + offset;
831 static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
832 unsigned int bytes, bool read)
834 u64 exit_code, exit_info_1, exit_info_2;
835 unsigned long ghcb_pa = __pa(ghcb);
840 ref = insn_get_addr_ref(&ctxt->insn, ctxt->regs);
841 if (ref == (void __user *)-1L)
842 return ES_UNSUPPORTED;
844 exit_code = read ? SVM_VMGEXIT_MMIO_READ : SVM_VMGEXIT_MMIO_WRITE;
846 res = vc_slow_virt_to_phys(ghcb, ctxt, (unsigned long)ref, &paddr);
848 if (res == ES_EXCEPTION && !read)
849 ctxt->fi.error_code |= X86_PF_WRITE;
855 /* Can never be greater than 8 */
858 ghcb_set_sw_scratch(ghcb, ghcb_pa + offsetof(struct ghcb, shared_buffer));
860 return sev_es_ghcb_hv_call(ghcb, true, ctxt, exit_code, exit_info_1, exit_info_2);
863 static enum es_result vc_handle_mmio_twobyte_ops(struct ghcb *ghcb,
864 struct es_em_ctxt *ctxt)
866 struct insn *insn = &ctxt->insn;
867 unsigned int bytes = 0;
872 switch (insn->opcode.bytes[1]) {
873 /* MMIO Read w/ zero-extension */
881 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
885 /* Zero extend based on operand size */
886 reg_data = vc_insn_get_reg(ctxt);
888 return ES_DECODE_FAILED;
890 memset(reg_data, 0, insn->opnd_bytes);
892 memcpy(reg_data, ghcb->shared_buffer, bytes);
895 /* MMIO Read w/ sign-extension */
903 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
907 /* Sign extend based on operand size */
908 reg_data = vc_insn_get_reg(ctxt);
910 return ES_DECODE_FAILED;
913 u8 *val = (u8 *)ghcb->shared_buffer;
915 sign_byte = (*val & 0x80) ? 0xff : 0x00;
917 u16 *val = (u16 *)ghcb->shared_buffer;
919 sign_byte = (*val & 0x8000) ? 0xff : 0x00;
921 memset(reg_data, sign_byte, insn->opnd_bytes);
923 memcpy(reg_data, ghcb->shared_buffer, bytes);
927 ret = ES_UNSUPPORTED;
934 * The MOVS instruction has two memory operands, which raises the
935 * problem that it is not known whether the access to the source or the
936 * destination caused the #VC exception (and hence whether an MMIO read
937 * or write operation needs to be emulated).
939 * Instead of playing games with walking page-tables and trying to guess
940 * whether the source or destination is an MMIO range, split the move
941 * into two operations, a read and a write with only one memory operand.
942 * This will cause a nested #VC exception on the MMIO address which can
945 * This implementation has the benefit that it also supports MOVS where
946 * source _and_ destination are MMIO regions.
948 * It will slow MOVS on MMIO down a lot, but in SEV-ES guests it is a
949 * rare operation. If it turns out to be a performance problem the split
950 * operations can be moved to memcpy_fromio() and memcpy_toio().
952 static enum es_result vc_handle_mmio_movs(struct es_em_ctxt *ctxt,
955 unsigned long ds_base, es_base;
956 unsigned char *src, *dst;
957 unsigned char buffer[8];
962 ds_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_DS);
963 es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES);
965 if (ds_base == -1L || es_base == -1L) {
966 ctxt->fi.vector = X86_TRAP_GP;
967 ctxt->fi.error_code = 0;
971 src = ds_base + (unsigned char *)ctxt->regs->si;
972 dst = es_base + (unsigned char *)ctxt->regs->di;
974 ret = vc_read_mem(ctxt, src, buffer, bytes);
978 ret = vc_write_mem(ctxt, dst, buffer, bytes);
982 if (ctxt->regs->flags & X86_EFLAGS_DF)
987 ctxt->regs->si += off;
988 ctxt->regs->di += off;
990 rep = insn_has_rep_prefix(&ctxt->insn);
994 if (!rep || ctxt->regs->cx == 0)
1000 static enum es_result vc_handle_mmio(struct ghcb *ghcb,
1001 struct es_em_ctxt *ctxt)
1003 struct insn *insn = &ctxt->insn;
1004 unsigned int bytes = 0;
1008 switch (insn->opcode.bytes[0]) {
1015 bytes = insn->opnd_bytes;
1017 reg_data = vc_insn_get_reg(ctxt);
1019 return ES_DECODE_FAILED;
1021 memcpy(ghcb->shared_buffer, reg_data, bytes);
1023 ret = vc_do_mmio(ghcb, ctxt, bytes, false);
1031 bytes = insn->opnd_bytes;
1033 memcpy(ghcb->shared_buffer, insn->immediate1.bytes, bytes);
1035 ret = vc_do_mmio(ghcb, ctxt, bytes, false);
1044 bytes = insn->opnd_bytes;
1046 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
1050 reg_data = vc_insn_get_reg(ctxt);
1052 return ES_DECODE_FAILED;
1054 /* Zero-extend for 32-bit operation */
1058 memcpy(reg_data, ghcb->shared_buffer, bytes);
1061 /* MOVS instruction */
1067 bytes = insn->opnd_bytes;
1069 ret = vc_handle_mmio_movs(ctxt, bytes);
1071 /* Two-Byte Opcodes */
1073 ret = vc_handle_mmio_twobyte_ops(ghcb, ctxt);
1076 ret = ES_UNSUPPORTED;
1082 static enum es_result vc_handle_dr7_write(struct ghcb *ghcb,
1083 struct es_em_ctxt *ctxt)
1085 struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
1086 long val, *reg = vc_insn_get_rm(ctxt);
1090 return ES_DECODE_FAILED;
1094 /* Upper 32 bits must be written as zeroes */
1096 ctxt->fi.vector = X86_TRAP_GP;
1097 ctxt->fi.error_code = 0;
1098 return ES_EXCEPTION;
1101 /* Clear out other reserved bits and set bit 10 */
1102 val = (val & 0xffff23ffL) | BIT(10);
1104 /* Early non-zero writes to DR7 are not supported */
1105 if (!data && (val & ~DR7_RESET_VALUE))
1106 return ES_UNSUPPORTED;
1108 /* Using a value of 0 for ExitInfo1 means RAX holds the value */
1109 ghcb_set_rax(ghcb, val);
1110 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WRITE_DR7, 0, 0);
1120 static enum es_result vc_handle_dr7_read(struct ghcb *ghcb,
1121 struct es_em_ctxt *ctxt)
1123 struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
1124 long *reg = vc_insn_get_rm(ctxt);
1127 return ES_DECODE_FAILED;
1132 *reg = DR7_RESET_VALUE;
1137 static enum es_result vc_handle_wbinvd(struct ghcb *ghcb,
1138 struct es_em_ctxt *ctxt)
1140 return sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WBINVD, 0, 0);
1143 static enum es_result vc_handle_rdpmc(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
1147 ghcb_set_rcx(ghcb, ctxt->regs->cx);
1149 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_RDPMC, 0, 0);
1153 if (!(ghcb_rax_is_valid(ghcb) && ghcb_rdx_is_valid(ghcb)))
1154 return ES_VMM_ERROR;
1156 ctxt->regs->ax = ghcb->save.rax;
1157 ctxt->regs->dx = ghcb->save.rdx;
1162 static enum es_result vc_handle_monitor(struct ghcb *ghcb,
1163 struct es_em_ctxt *ctxt)
1166 * Treat it as a NOP and do not leak a physical address to the
1172 static enum es_result vc_handle_mwait(struct ghcb *ghcb,
1173 struct es_em_ctxt *ctxt)
1175 /* Treat the same as MONITOR/MONITORX */
1179 static enum es_result vc_handle_vmmcall(struct ghcb *ghcb,
1180 struct es_em_ctxt *ctxt)
1184 ghcb_set_rax(ghcb, ctxt->regs->ax);
1185 ghcb_set_cpl(ghcb, user_mode(ctxt->regs) ? 3 : 0);
1187 if (x86_platform.hyper.sev_es_hcall_prepare)
1188 x86_platform.hyper.sev_es_hcall_prepare(ghcb, ctxt->regs);
1190 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_VMMCALL, 0, 0);
1194 if (!ghcb_rax_is_valid(ghcb))
1195 return ES_VMM_ERROR;
1197 ctxt->regs->ax = ghcb->save.rax;
1200 * Call sev_es_hcall_finish() after regs->ax is already set.
1201 * This allows the hypervisor handler to overwrite it again if
1204 if (x86_platform.hyper.sev_es_hcall_finish &&
1205 !x86_platform.hyper.sev_es_hcall_finish(ghcb, ctxt->regs))
1206 return ES_VMM_ERROR;
1211 static enum es_result vc_handle_trap_ac(struct ghcb *ghcb,
1212 struct es_em_ctxt *ctxt)
1215 * Calling ecx_alignment_check() directly does not work, because it
1216 * enables IRQs and the GHCB is active. Forward the exception and call
1217 * it later from vc_forward_exception().
1219 ctxt->fi.vector = X86_TRAP_AC;
1220 ctxt->fi.error_code = 0;
1221 return ES_EXCEPTION;
1224 static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt,
1226 unsigned long exit_code)
1228 enum es_result result;
1230 switch (exit_code) {
1231 case SVM_EXIT_READ_DR7:
1232 result = vc_handle_dr7_read(ghcb, ctxt);
1234 case SVM_EXIT_WRITE_DR7:
1235 result = vc_handle_dr7_write(ghcb, ctxt);
1237 case SVM_EXIT_EXCP_BASE + X86_TRAP_AC:
1238 result = vc_handle_trap_ac(ghcb, ctxt);
1240 case SVM_EXIT_RDTSC:
1241 case SVM_EXIT_RDTSCP:
1242 result = vc_handle_rdtsc(ghcb, ctxt, exit_code);
1244 case SVM_EXIT_RDPMC:
1245 result = vc_handle_rdpmc(ghcb, ctxt);
1248 pr_err_ratelimited("#VC exception for INVD??? Seriously???\n");
1249 result = ES_UNSUPPORTED;
1251 case SVM_EXIT_CPUID:
1252 result = vc_handle_cpuid(ghcb, ctxt);
1255 result = vc_handle_ioio(ghcb, ctxt);
1258 result = vc_handle_msr(ghcb, ctxt);
1260 case SVM_EXIT_VMMCALL:
1261 result = vc_handle_vmmcall(ghcb, ctxt);
1263 case SVM_EXIT_WBINVD:
1264 result = vc_handle_wbinvd(ghcb, ctxt);
1266 case SVM_EXIT_MONITOR:
1267 result = vc_handle_monitor(ghcb, ctxt);
1269 case SVM_EXIT_MWAIT:
1270 result = vc_handle_mwait(ghcb, ctxt);
1273 result = vc_handle_mmio(ghcb, ctxt);
1277 * Unexpected #VC exception
1279 result = ES_UNSUPPORTED;
1285 static __always_inline void vc_forward_exception(struct es_em_ctxt *ctxt)
1287 long error_code = ctxt->fi.error_code;
1288 int trapnr = ctxt->fi.vector;
1290 ctxt->regs->orig_ax = ctxt->fi.error_code;
1294 exc_general_protection(ctxt->regs, error_code);
1297 exc_invalid_op(ctxt->regs);
1300 write_cr2(ctxt->fi.cr2);
1301 exc_page_fault(ctxt->regs, error_code);
1304 exc_alignment_check(ctxt->regs, error_code);
1307 pr_emerg("Unsupported exception in #VC instruction emulation - can't continue\n");
1312 static __always_inline bool is_vc2_stack(unsigned long sp)
1314 return (sp >= __this_cpu_ist_bottom_va(VC2) && sp < __this_cpu_ist_top_va(VC2));
1317 static __always_inline bool vc_from_invalid_context(struct pt_regs *regs)
1319 unsigned long sp, prev_sp;
1321 sp = (unsigned long)regs;
1325 * If the code was already executing on the VC2 stack when the #VC
1326 * happened, let it proceed to the normal handling routine. This way the
1327 * code executing on the VC2 stack can cause #VC exceptions to get handled.
1329 return is_vc2_stack(sp) && !is_vc2_stack(prev_sp);
1332 static bool vc_raw_handle_exception(struct pt_regs *regs, unsigned long error_code)
1334 struct ghcb_state state;
1335 struct es_em_ctxt ctxt;
1336 enum es_result result;
1340 ghcb = __sev_get_ghcb(&state);
1342 vc_ghcb_invalidate(ghcb);
1343 result = vc_init_em_ctxt(&ctxt, regs, error_code);
1345 if (result == ES_OK)
1346 result = vc_handle_exitcode(&ctxt, ghcb, error_code);
1348 __sev_put_ghcb(&state);
1350 /* Done - now check the result */
1353 vc_finish_insn(&ctxt);
1355 case ES_UNSUPPORTED:
1356 pr_err_ratelimited("Unsupported exit-code 0x%02lx in #VC exception (IP: 0x%lx)\n",
1357 error_code, regs->ip);
1361 pr_err_ratelimited("Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n",
1362 error_code, regs->ip);
1365 case ES_DECODE_FAILED:
1366 pr_err_ratelimited("Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n",
1367 error_code, regs->ip);
1371 vc_forward_exception(&ctxt);
1377 pr_emerg("Unknown result in %s():%d\n", __func__, result);
1379 * Emulating the instruction which caused the #VC exception
1380 * failed - can't continue so print debug information
1388 static __always_inline bool vc_is_db(unsigned long error_code)
1390 return error_code == SVM_EXIT_EXCP_BASE + X86_TRAP_DB;
1394 * Runtime #VC exception handler when raised from kernel mode. Runs in NMI mode
1395 * and will panic when an error happens.
1397 DEFINE_IDTENTRY_VC_KERNEL(exc_vmm_communication)
1399 irqentry_state_t irq_state;
1402 * With the current implementation it is always possible to switch to a
1403 * safe stack because #VC exceptions only happen at known places, like
1404 * intercepted instructions or accesses to MMIO areas/IO ports. They can
1405 * also happen with code instrumentation when the hypervisor intercepts
1406 * #DB, but the critical paths are forbidden to be instrumented, so #DB
1407 * exceptions currently also only happen in safe places.
1409 * But keep this here in case the noinstr annotations are violated due
1412 if (unlikely(vc_from_invalid_context(regs))) {
1413 instrumentation_begin();
1414 panic("Can't handle #VC exception from unsupported context\n");
1415 instrumentation_end();
1419 * Handle #DB before calling into !noinstr code to avoid recursive #DB.
1421 if (vc_is_db(error_code)) {
1426 irq_state = irqentry_nmi_enter(regs);
1428 instrumentation_begin();
1430 if (!vc_raw_handle_exception(regs, error_code)) {
1431 /* Show some debug info */
1434 /* Ask hypervisor to sev_es_terminate */
1435 sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST);
1437 /* If that fails and we get here - just panic */
1438 panic("Returned from Terminate-Request to Hypervisor\n");
1441 instrumentation_end();
1442 irqentry_nmi_exit(regs, irq_state);
1446 * Runtime #VC exception handler when raised from user mode. Runs in IRQ mode
1447 * and will kill the current task with SIGBUS when an error happens.
1449 DEFINE_IDTENTRY_VC_USER(exc_vmm_communication)
1452 * Handle #DB before calling into !noinstr code to avoid recursive #DB.
1454 if (vc_is_db(error_code)) {
1455 noist_exc_debug(regs);
1459 irqentry_enter_from_user_mode(regs);
1460 instrumentation_begin();
1462 if (!vc_raw_handle_exception(regs, error_code)) {
1464 * Do not kill the machine if user-space triggered the
1465 * exception. Send SIGBUS instead and let user-space deal with
1468 force_sig_fault(SIGBUS, BUS_OBJERR, (void __user *)0);
1471 instrumentation_end();
1472 irqentry_exit_to_user_mode(regs);
1475 bool __init handle_vc_boot_ghcb(struct pt_regs *regs)
1477 unsigned long exit_code = regs->orig_ax;
1478 struct es_em_ctxt ctxt;
1479 enum es_result result;
1481 /* Do initial setup or terminate the guest */
1482 if (unlikely(boot_ghcb == NULL && !sev_es_setup_ghcb()))
1483 sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST);
1485 vc_ghcb_invalidate(boot_ghcb);
1487 result = vc_init_em_ctxt(&ctxt, regs, exit_code);
1488 if (result == ES_OK)
1489 result = vc_handle_exitcode(&ctxt, boot_ghcb, exit_code);
1491 /* Done - now check the result */
1494 vc_finish_insn(&ctxt);
1496 case ES_UNSUPPORTED:
1497 early_printk("PANIC: Unsupported exit-code 0x%02lx in early #VC exception (IP: 0x%lx)\n",
1498 exit_code, regs->ip);
1501 early_printk("PANIC: Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n",
1502 exit_code, regs->ip);
1504 case ES_DECODE_FAILED:
1505 early_printk("PANIC: Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n",
1506 exit_code, regs->ip);
1509 vc_early_forward_exception(&ctxt);