arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define APIC_BROADCAST                  0xFF
  72 #define X2APIC_BROADCAST                0xFFFFFFFFul
  73
  74 #define VEC_POS(v) ((v) & (32 - 1))
  75 #define REG_POS(v) (((v) >> 5) << 4)
  76
  77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  78 {
  79         *((u32 *) (apic->regs + reg_off)) = val;
  80 }
  81
  82 static inline int apic_test_vector(int vec, void *bitmap)
  83 {
  84         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  88 {
  89         struct kvm_lapic *apic = vcpu->arch.apic;
  90
  91         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  92                 apic_test_vector(vector, apic->regs + APIC_IRR);
  93 }
  94
  95 static inline void apic_set_vector(int vec, void *bitmap)
  96 {
  97         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline void apic_clear_vector(int vec, void *bitmap)
 101 {
 102         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 106 {
 107         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 111 {
 112         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 struct static_key_deferred apic_hw_disabled __read_mostly;
 116 struct static_key_deferred apic_sw_disabled __read_mostly;
 117
 118 static inline int apic_enabled(struct kvm_lapic *apic)
 119 {
 120         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 121 }
 122
 123 #define LVT_MASK        \
 124         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 125
 126 #define LINT_MASK       \
 127         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 128          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 129
 130 static inline int kvm_apic_id(struct kvm_lapic *apic)
 131 {
 132         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 133 }
 134
 135 #define KVM_X2APIC_CID_BITS 0
 136
 137 static void recalculate_apic_map(struct kvm *kvm)
 138 {
 139         struct kvm_apic_map *new, *old = NULL;
 140         struct kvm_vcpu *vcpu;
 141         int i;
 142
 143         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 144
 145         mutex_lock(&kvm->arch.apic_map_lock);
 146
 147         if (!new)
 148                 goto out;
 149
 150         new->ldr_bits = 8;
 151         /* flat mode is default */
 152         new->cid_shift = 8;
 153         new->cid_mask = 0;
 154         new->lid_mask = 0xff;
 155         new->broadcast = APIC_BROADCAST;
 156
 157         kvm_for_each_vcpu(i, vcpu, kvm) {
 158                 struct kvm_lapic *apic = vcpu->arch.apic;
 159                 u16 cid, lid;
 160                 u32 ldr;
 161
 162                 if (!kvm_apic_present(vcpu))
 163                         continue;
 164
 165                 /*
 166                  * All APICs have to be configured in the same mode by an OS.
 167                  * We take advatage of this while building logical id loockup
 168                  * table. After reset APICs are in xapic/flat mode, so if we
 169                  * find apic with different setting we assume this is the mode
 170                  * OS wants all apics to be in; build lookup table accordingly.
 171                  */
 172                 if (apic_x2apic_mode(apic)) {
 173                         new->ldr_bits = 32;
 174                         new->cid_shift = 16;
 175                         new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
 176                         new->lid_mask = 0xffff;
 177                         new->broadcast = X2APIC_BROADCAST;
 178                 } else if (kvm_apic_sw_enabled(apic) &&
 179                                 !new->cid_mask /* flat mode */ &&
 180                                 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
 181                         new->cid_shift = 4;
 182                         new->cid_mask = 0xf;
 183                         new->lid_mask = 0xf;
 184                 }
 185
 186                 new->phys_map[kvm_apic_id(apic)] = apic;
 187
 188                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 189                 cid = apic_cluster_id(new, ldr);
 190                 lid = apic_logical_id(new, ldr);
 191
 192                 if (lid)
 193                         new->logical_map[cid][ffs(lid) - 1] = apic;
 194         }
 195 out:
 196         old = rcu_dereference_protected(kvm->arch.apic_map,
 197                         lockdep_is_held(&kvm->arch.apic_map_lock));
 198         rcu_assign_pointer(kvm->arch.apic_map, new);
 199         mutex_unlock(&kvm->arch.apic_map_lock);
 200
 201         if (old)
 202                 kfree_rcu(old, rcu);
 203
 204         kvm_vcpu_request_scan_ioapic(kvm);
 205 }
 206
 207 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 208 {
 209         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 210
 211         apic_set_reg(apic, APIC_SPIV, val);
 212
 213         if (enabled != apic->sw_enabled) {
 214                 apic->sw_enabled = enabled;
 215                 if (enabled) {
 216                         static_key_slow_dec_deferred(&apic_sw_disabled);
 217                         recalculate_apic_map(apic->vcpu->kvm);
 218                 } else
 219                         static_key_slow_inc(&apic_sw_disabled.key);
 220         }
 221 }
 222
 223 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 224 {
 225         apic_set_reg(apic, APIC_ID, id << 24);
 226         recalculate_apic_map(apic->vcpu->kvm);
 227 }
 228
 229 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 230 {
 231         apic_set_reg(apic, APIC_LDR, id);
 232         recalculate_apic_map(apic->vcpu->kvm);
 233 }
 234
 235 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 236 {
 237         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 238 }
 239
 240 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 241 {
 242         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 243 }
 244
 245 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 246 {
 247         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 248                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 249 }
 250
 251 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 252 {
 253         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 254                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 255 }
 256
 257 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 258 {
 259         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
 260                 apic->lapic_timer.timer_mode_mask) ==
 261                         APIC_LVT_TIMER_TSCDEADLINE);
 262 }
 263
 264 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 265 {
 266         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 267 }
 268
 269 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 270 {
 271         struct kvm_lapic *apic = vcpu->arch.apic;
 272         struct kvm_cpuid_entry2 *feat;
 273         u32 v = APIC_VERSION;
 274
 275         if (!kvm_vcpu_has_lapic(vcpu))
 276                 return;
 277
 278         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 279         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 280                 v |= APIC_LVR_DIRECTED_EOI;
 281         apic_set_reg(apic, APIC_LVR, v);
 282 }
 283
 284 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 285         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 286         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 287         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 288         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 289         LVT_MASK                /* LVTERR */
 290 };
 291
 292 static int find_highest_vector(void *bitmap)
 293 {
 294         int vec;
 295         u32 *reg;
 296
 297         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 298              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 299                 reg = bitmap + REG_POS(vec);
 300                 if (*reg)
 301                         return fls(*reg) - 1 + vec;
 302         }
 303
 304         return -1;
 305 }
 306
 307 static u8 count_vectors(void *bitmap)
 308 {
 309         int vec;
 310         u32 *reg;
 311         u8 count = 0;
 312
 313         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 314                 reg = bitmap + REG_POS(vec);
 315                 count += hweight32(*reg);
 316         }
 317
 318         return count;
 319 }
 320
 321 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 322 {
 323         u32 i, pir_val;
 324         struct kvm_lapic *apic = vcpu->arch.apic;
 325
 326         for (i = 0; i <= 7; i++) {
 327                 pir_val = xchg(&pir[i], 0);
 328                 if (pir_val)
 329                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 330         }
 331 }
 332 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 333
 334 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 335 {
 336         apic->irr_pending = true;
 337         apic_set_vector(vec, apic->regs + APIC_IRR);
 338 }
 339
 340 static inline int apic_search_irr(struct kvm_lapic *apic)
 341 {
 342         return find_highest_vector(apic->regs + APIC_IRR);
 343 }
 344
 345 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 346 {
 347         int result;
 348
 349         /*
 350          * Note that irr_pending is just a hint. It will be always
 351          * true with virtual interrupt delivery enabled.
 352          */
 353         if (!apic->irr_pending)
 354                 return -1;
 355
 356         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 357         result = apic_search_irr(apic);
 358         ASSERT(result == -1 || result >= 16);
 359
 360         return result;
 361 }
 362
 363 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 364 {
 365         struct kvm_vcpu *vcpu;
 366
 367         vcpu = apic->vcpu;
 368
 369         apic_clear_vector(vec, apic->regs + APIC_IRR);
 370         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 371                 /* try to update RVI */
 372                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 373         else {
 374                 vec = apic_search_irr(apic);
 375                 apic->irr_pending = (vec != -1);
 376         }
 377 }
 378
 379 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 380 {
 381         struct kvm_vcpu *vcpu;
 382
 383         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 384                 return;
 385
 386         vcpu = apic->vcpu;
 387
 388         /*
 389          * With APIC virtualization enabled, all caching is disabled
 390          * because the processor can modify ISR under the hood.  Instead
 391          * just set SVI.
 392          */
 393         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 394                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 395         else {
 396                 ++apic->isr_count;
 397                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 398                 /*
 399                  * ISR (in service register) bit is set when injecting an interrupt.
 400                  * The highest vector is injected. Thus the latest bit set matches
 401                  * the highest bit in ISR.
 402                  */
 403                 apic->highest_isr_cache = vec;
 404         }
 405 }
 406
 407 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 408 {
 409         int result;
 410
 411         /*
 412          * Note that isr_count is always 1, and highest_isr_cache
 413          * is always -1, with APIC virtualization enabled.
 414          */
 415         if (!apic->isr_count)
 416                 return -1;
 417         if (likely(apic->highest_isr_cache != -1))
 418                 return apic->highest_isr_cache;
 419
 420         result = find_highest_vector(apic->regs + APIC_ISR);
 421         ASSERT(result == -1 || result >= 16);
 422
 423         return result;
 424 }
 425
 426 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 427 {
 428         struct kvm_vcpu *vcpu;
 429         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 430                 return;
 431
 432         vcpu = apic->vcpu;
 433
 434         /*
 435          * We do get here for APIC virtualization enabled if the guest
 436          * uses the Hyper-V APIC enlightenment.  In this case we may need
 437          * to trigger a new interrupt delivery by writing the SVI field;
 438          * on the other hand isr_count and highest_isr_cache are unused
 439          * and must be left alone.
 440          */
 441         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 442                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 443                                                apic_find_highest_isr(apic));
 444         else {
 445                 --apic->isr_count;
 446                 BUG_ON(apic->isr_count < 0);
 447                 apic->highest_isr_cache = -1;
 448         }
 449 }
 450
 451 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 452 {
 453         int highest_irr;
 454
 455         /* This may race with setting of irr in __apic_accept_irq() and
 456          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 457          * will cause vmexit immediately and the value will be recalculated
 458          * on the next vmentry.
 459          */
 460         if (!kvm_vcpu_has_lapic(vcpu))
 461                 return 0;
 462         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 463
 464         return highest_irr;
 465 }
 466
 467 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 468                              int vector, int level, int trig_mode,
 469                              unsigned long *dest_map);
 470
 471 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 472                 unsigned long *dest_map)
 473 {
 474         struct kvm_lapic *apic = vcpu->arch.apic;
 475
 476         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 477                         irq->level, irq->trig_mode, dest_map);
 478 }
 479
 480 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 481 {
 482
 483         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 484                                       sizeof(val));
 485 }
 486
 487 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 488 {
 489
 490         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 491                                       sizeof(*val));
 492 }
 493
 494 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 495 {
 496         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 497 }
 498
 499 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 500 {
 501         u8 val;
 502         if (pv_eoi_get_user(vcpu, &val) < 0)
 503                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 504                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 505         return val & 0x1;
 506 }
 507
 508 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 509 {
 510         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 511                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 512                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 513                 return;
 514         }
 515         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 516 }
 517
 518 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 519 {
 520         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 521                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 522                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 523                 return;
 524         }
 525         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 526 }
 527
 528 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 529 {
 530         struct kvm_lapic *apic = vcpu->arch.apic;
 531         int i;
 532
 533         for (i = 0; i < 8; i++)
 534                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 535 }
 536
 537 static void apic_update_ppr(struct kvm_lapic *apic)
 538 {
 539         u32 tpr, isrv, ppr, old_ppr;
 540         int isr;
 541
 542         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 543         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 544         isr = apic_find_highest_isr(apic);
 545         isrv = (isr != -1) ? isr : 0;
 546
 547         if ((tpr & 0xf0) >= (isrv & 0xf0))
 548                 ppr = tpr & 0xff;
 549         else
 550                 ppr = isrv & 0xf0;
 551
 552         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 553                    apic, ppr, isr, isrv);
 554
 555         if (old_ppr != ppr) {
 556                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 557                 if (ppr < old_ppr)
 558                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 559         }
 560 }
 561
 562 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 563 {
 564         apic_set_reg(apic, APIC_TASKPRI, tpr);
 565         apic_update_ppr(apic);
 566 }
 567
 568 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 569 {
 570         return dest == (apic_x2apic_mode(apic) ?
 571                         X2APIC_BROADCAST : APIC_BROADCAST);
 572 }
 573
 574 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 575 {
 576         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 577 }
 578
 579 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 580 {
 581         int result = 0;
 582         u32 logical_id;
 583
 584         if (kvm_apic_broadcast(apic, mda))
 585                 return 1;
 586
 587         if (apic_x2apic_mode(apic)) {
 588                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 589                 return logical_id & mda;
 590         }
 591
 592         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 593
 594         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 595         case APIC_DFR_FLAT:
 596                 if (logical_id & mda)
 597                         result = 1;
 598                 break;
 599         case APIC_DFR_CLUSTER:
 600                 if (((logical_id >> 4) == (mda >> 0x4))
 601                     && (logical_id & mda & 0xf))
 602                         result = 1;
 603                 break;
 604         default:
 605                 apic_debug("Bad DFR vcpu %d: %08x\n",
 606                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 607                 break;
 608         }
 609
 610         return result;
 611 }
 612
 613 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 614                            int short_hand, unsigned int dest, int dest_mode)
 615 {
 616         int result = 0;
 617         struct kvm_lapic *target = vcpu->arch.apic;
 618
 619         apic_debug("target %p, source %p, dest 0x%x, "
 620                    "dest_mode 0x%x, short_hand 0x%x\n",
 621                    target, source, dest, dest_mode, short_hand);
 622
 623         ASSERT(target);
 624         switch (short_hand) {
 625         case APIC_DEST_NOSHORT:
 626                 if (dest_mode == 0)
 627                         /* Physical mode. */
 628                         result = kvm_apic_match_physical_addr(target, dest);
 629                 else
 630                         /* Logical mode. */
 631                         result = kvm_apic_match_logical_addr(target, dest);
 632                 break;
 633         case APIC_DEST_SELF:
 634                 result = (target == source);
 635                 break;
 636         case APIC_DEST_ALLINC:
 637                 result = 1;
 638                 break;
 639         case APIC_DEST_ALLBUT:
 640                 result = (target != source);
 641                 break;
 642         default:
 643                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 644                            short_hand);
 645                 break;
 646         }
 647
 648         return result;
 649 }
 650
 651 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 652                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 653 {
 654         struct kvm_apic_map *map;
 655         unsigned long bitmap = 1;
 656         struct kvm_lapic **dst;
 657         int i;
 658         bool ret = false;
 659
 660         *r = -1;
 661
 662         if (irq->shorthand == APIC_DEST_SELF) {
 663                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 664                 return true;
 665         }
 666
 667         if (irq->shorthand)
 668                 return false;
 669
 670         rcu_read_lock();
 671         map = rcu_dereference(kvm->arch.apic_map);
 672
 673         if (!map)
 674                 goto out;
 675
 676         if (irq->dest_id == map->broadcast)
 677                 goto out;
 678
 679         if (irq->dest_mode == 0) { /* physical mode */
 680                 if (irq->delivery_mode == APIC_DM_LOWEST)
 681                         goto out;
 682                 dst = &map->phys_map[irq->dest_id & 0xff];
 683         } else {
 684                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 685
 686                 dst = map->logical_map[apic_cluster_id(map, mda)];
 687
 688                 bitmap = apic_logical_id(map, mda);
 689
 690                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 691                         int l = -1;
 692                         for_each_set_bit(i, &bitmap, 16) {
 693                                 if (!dst[i])
 694                                         continue;
 695                                 if (l < 0)
 696                                         l = i;
 697                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 698                                         l = i;
 699                         }
 700
 701                         bitmap = (l >= 0) ? 1 << l : 0;
 702                 }
 703         }
 704
 705         for_each_set_bit(i, &bitmap, 16) {
 706                 if (!dst[i])
 707                         continue;
 708                 if (*r < 0)
 709                         *r = 0;
 710                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 711         }
 712
 713         ret = true;
 714 out:
 715         rcu_read_unlock();
 716         return ret;
 717 }
 718
 719 /*
 720  * Add a pending IRQ into lapic.
 721  * Return 1 if successfully added and 0 if discarded.
 722  */
 723 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 724                              int vector, int level, int trig_mode,
 725                              unsigned long *dest_map)
 726 {
 727         int result = 0;
 728         struct kvm_vcpu *vcpu = apic->vcpu;
 729
 730         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 731                                   trig_mode, vector);
 732         switch (delivery_mode) {
 733         case APIC_DM_LOWEST:
 734                 vcpu->arch.apic_arb_prio++;
 735         case APIC_DM_FIXED:
 736                 /* FIXME add logic for vcpu on reset */
 737                 if (unlikely(!apic_enabled(apic)))
 738                         break;
 739
 740                 result = 1;
 741
 742                 if (dest_map)
 743                         __set_bit(vcpu->vcpu_id, dest_map);
 744
 745                 if (kvm_x86_ops->deliver_posted_interrupt)
 746                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 747                 else {
 748                         apic_set_irr(vector, apic);
 749
 750                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 751                         kvm_vcpu_kick(vcpu);
 752                 }
 753                 break;
 754
 755         case APIC_DM_REMRD:
 756                 result = 1;
 757                 vcpu->arch.pv.pv_unhalted = 1;
 758                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 759                 kvm_vcpu_kick(vcpu);
 760                 break;
 761
 762         case APIC_DM_SMI:
 763                 apic_debug("Ignoring guest SMI\n");
 764                 break;
 765
 766         case APIC_DM_NMI:
 767                 result = 1;
 768                 kvm_inject_nmi(vcpu);
 769                 kvm_vcpu_kick(vcpu);
 770                 break;
 771
 772         case APIC_DM_INIT:
 773                 if (!trig_mode || level) {
 774                         result = 1;
 775                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 776                         apic->pending_events = (1UL << KVM_APIC_INIT);
 777                         /* make sure pending_events is visible before sending
 778                          * the request */
 779                         smp_wmb();
 780                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 781                         kvm_vcpu_kick(vcpu);
 782                 } else {
 783                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 784                                    vcpu->vcpu_id);
 785                 }
 786                 break;
 787
 788         case APIC_DM_STARTUP:
 789                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 790                            vcpu->vcpu_id, vector);
 791                 result = 1;
 792                 apic->sipi_vector = vector;
 793                 /* make sure sipi_vector is visible for the receiver */
 794                 smp_wmb();
 795                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 796                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 797                 kvm_vcpu_kick(vcpu);
 798                 break;
 799
 800         case APIC_DM_EXTINT:
 801                 /*
 802                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 803                  * before NMI watchdog was enabled. Already handled by
 804                  * kvm_apic_accept_pic_intr().
 805                  */
 806                 break;
 807
 808         default:
 809                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 810                        delivery_mode);
 811                 break;
 812         }
 813         return result;
 814 }
 815
 816 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 817 {
 818         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 819 }
 820
 821 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 822 {
 823         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 824             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 825                 int trigger_mode;
 826                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 827                         trigger_mode = IOAPIC_LEVEL_TRIG;
 828                 else
 829                         trigger_mode = IOAPIC_EDGE_TRIG;
 830                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 831         }
 832 }
 833
 834 static int apic_set_eoi(struct kvm_lapic *apic)
 835 {
 836         int vector = apic_find_highest_isr(apic);
 837
 838         trace_kvm_eoi(apic, vector);
 839
 840         /*
 841          * Not every write EOI will has corresponding ISR,
 842          * one example is when Kernel check timer on setup_IO_APIC
 843          */
 844         if (vector == -1)
 845                 return vector;
 846
 847         apic_clear_isr(vector, apic);
 848         apic_update_ppr(apic);
 849
 850         kvm_ioapic_send_eoi(apic, vector);
 851         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 852         return vector;
 853 }
 854
 855 /*
 856  * this interface assumes a trap-like exit, which has already finished
 857  * desired side effect including vISR and vPPR update.
 858  */
 859 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 860 {
 861         struct kvm_lapic *apic = vcpu->arch.apic;
 862
 863         trace_kvm_eoi(apic, vector);
 864
 865         kvm_ioapic_send_eoi(apic, vector);
 866         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 867 }
 868 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 869
 870 static void apic_send_ipi(struct kvm_lapic *apic)
 871 {
 872         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 873         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 874         struct kvm_lapic_irq irq;
 875
 876         irq.vector = icr_low & APIC_VECTOR_MASK;
 877         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 878         irq.dest_mode = icr_low & APIC_DEST_MASK;
 879         irq.level = icr_low & APIC_INT_ASSERT;
 880         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 881         irq.shorthand = icr_low & APIC_SHORT_MASK;
 882         if (apic_x2apic_mode(apic))
 883                 irq.dest_id = icr_high;
 884         else
 885                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 886
 887         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 888
 889         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 890                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 891                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 892                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 893                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 894                    irq.vector);
 895
 896         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 897 }
 898
 899 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 900 {
 901         ktime_t remaining;
 902         s64 ns;
 903         u32 tmcct;
 904
 905         ASSERT(apic != NULL);
 906
 907         /* if initial count is 0, current count should also be 0 */
 908         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 909                 apic->lapic_timer.period == 0)
 910                 return 0;
 911
 912         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 913         if (ktime_to_ns(remaining) < 0)
 914                 remaining = ktime_set(0, 0);
 915
 916         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 917         tmcct = div64_u64(ns,
 918                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 919
 920         return tmcct;
 921 }
 922
 923 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 924 {
 925         struct kvm_vcpu *vcpu = apic->vcpu;
 926         struct kvm_run *run = vcpu->run;
 927
 928         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 929         run->tpr_access.rip = kvm_rip_read(vcpu);
 930         run->tpr_access.is_write = write;
 931 }
 932
 933 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 934 {
 935         if (apic->vcpu->arch.tpr_access_reporting)
 936                 __report_tpr_access(apic, write);
 937 }
 938
 939 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 940 {
 941         u32 val = 0;
 942
 943         if (offset >= LAPIC_MMIO_LENGTH)
 944                 return 0;
 945
 946         switch (offset) {
 947         case APIC_ID:
 948                 if (apic_x2apic_mode(apic))
 949                         val = kvm_apic_id(apic);
 950                 else
 951                         val = kvm_apic_id(apic) << 24;
 952                 break;
 953         case APIC_ARBPRI:
 954                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 955                 break;
 956
 957         case APIC_TMCCT:        /* Timer CCR */
 958                 if (apic_lvtt_tscdeadline(apic))
 959                         return 0;
 960
 961                 val = apic_get_tmcct(apic);
 962                 break;
 963         case APIC_PROCPRI:
 964                 apic_update_ppr(apic);
 965                 val = kvm_apic_get_reg(apic, offset);
 966                 break;
 967         case APIC_TASKPRI:
 968                 report_tpr_access(apic, false);
 969                 /* fall thru */
 970         default:
 971                 val = kvm_apic_get_reg(apic, offset);
 972                 break;
 973         }
 974
 975         return val;
 976 }
 977
 978 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 979 {
 980         return container_of(dev, struct kvm_lapic, dev);
 981 }
 982
 983 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 984                 void *data)
 985 {
 986         unsigned char alignment = offset & 0xf;
 987         u32 result;
 988         /* this bitmask has a bit cleared for each reserved register */
 989         static const u64 rmask = 0x43ff01ffffffe70cULL;
 990
 991         if ((alignment + len) > 4) {
 992                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 993                            offset, len);
 994                 return 1;
 995         }
 996
 997         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 998                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 999                            offset);
1000                 return 1;
1001         }
1002
1003         result = __apic_read(apic, offset & ~0xf);
1004
1005         trace_kvm_apic_read(offset, result);
1006
1007         switch (len) {
1008         case 1:
1009         case 2:
1010         case 4:
1011                 memcpy(data, (char *)&result + alignment, len);
1012                 break;
1013         default:
1014                 printk(KERN_ERR "Local APIC read with len = %x, "
1015                        "should be 1,2, or 4 instead\n", len);
1016                 break;
1017         }
1018         return 0;
1019 }
1020
1021 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1022 {
1023         return kvm_apic_hw_enabled(apic) &&
1024             addr >= apic->base_address &&
1025             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1026 }
1027
1028 static int apic_mmio_read(struct kvm_io_device *this,
1029                            gpa_t address, int len, void *data)
1030 {
1031         struct kvm_lapic *apic = to_lapic(this);
1032         u32 offset = address - apic->base_address;
1033
1034         if (!apic_mmio_in_range(apic, address))
1035                 return -EOPNOTSUPP;
1036
1037         apic_reg_read(apic, offset, len, data);
1038
1039         return 0;
1040 }
1041
1042 static void update_divide_count(struct kvm_lapic *apic)
1043 {
1044         u32 tmp1, tmp2, tdcr;
1045
1046         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1047         tmp1 = tdcr & 0xf;
1048         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1049         apic->divide_count = 0x1 << (tmp2 & 0x7);
1050
1051         apic_debug("timer divide count is 0x%x\n",
1052                                    apic->divide_count);
1053 }
1054
1055 static void apic_timer_expired(struct kvm_lapic *apic)
1056 {
1057         struct kvm_vcpu *vcpu = apic->vcpu;
1058         wait_queue_head_t *q = &vcpu->wq;
1059
1060         /*
1061          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1062          * vcpu_enter_guest.
1063          */
1064         if (atomic_read(&apic->lapic_timer.pending))
1065                 return;
1066
1067         atomic_inc(&apic->lapic_timer.pending);
1068         /* FIXME: this code should not know anything about vcpus */
1069         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1070
1071         if (waitqueue_active(q))
1072                 wake_up_interruptible(q);
1073 }
1074
1075 static void start_apic_timer(struct kvm_lapic *apic)
1076 {
1077         ktime_t now;
1078         atomic_set(&apic->lapic_timer.pending, 0);
1079
1080         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1081                 /* lapic timer in oneshot or periodic mode */
1082                 now = apic->lapic_timer.timer.base->get_time();
1083                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1084                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1085
1086                 if (!apic->lapic_timer.period)
1087                         return;
1088                 /*
1089                  * Do not allow the guest to program periodic timers with small
1090                  * interval, since the hrtimers are not throttled by the host
1091                  * scheduler.
1092                  */
1093                 if (apic_lvtt_period(apic)) {
1094                         s64 min_period = min_timer_period_us * 1000LL;
1095
1096                         if (apic->lapic_timer.period < min_period) {
1097                                 pr_info_ratelimited(
1098                                     "kvm: vcpu %i: requested %lld ns "
1099                                     "lapic timer period limited to %lld ns\n",
1100                                     apic->vcpu->vcpu_id,
1101                                     apic->lapic_timer.period, min_period);
1102                                 apic->lapic_timer.period = min_period;
1103                         }
1104                 }
1105
1106                 hrtimer_start(&apic->lapic_timer.timer,
1107                               ktime_add_ns(now, apic->lapic_timer.period),
1108                               HRTIMER_MODE_ABS);
1109
1110                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1111                            PRIx64 ", "
1112                            "timer initial count 0x%x, period %lldns, "
1113                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1114                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1115                            kvm_apic_get_reg(apic, APIC_TMICT),
1116                            apic->lapic_timer.period,
1117                            ktime_to_ns(ktime_add_ns(now,
1118                                         apic->lapic_timer.period)));
1119         } else if (apic_lvtt_tscdeadline(apic)) {
1120                 /* lapic timer in tsc deadline mode */
1121                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1122                 u64 ns = 0;
1123                 struct kvm_vcpu *vcpu = apic->vcpu;
1124                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1125                 unsigned long flags;
1126
1127                 if (unlikely(!tscdeadline || !this_tsc_khz))
1128                         return;
1129
1130                 local_irq_save(flags);
1131
1132                 now = apic->lapic_timer.timer.base->get_time();
1133                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1134                 if (likely(tscdeadline > guest_tsc)) {
1135                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1136                         do_div(ns, this_tsc_khz);
1137                         hrtimer_start(&apic->lapic_timer.timer,
1138                                 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1139                 } else
1140                         apic_timer_expired(apic);
1141
1142                 local_irq_restore(flags);
1143         }
1144 }
1145
1146 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1147 {
1148         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1149
1150         if (apic_lvt_nmi_mode(lvt0_val)) {
1151                 if (!nmi_wd_enabled) {
1152                         apic_debug("Receive NMI setting on APIC_LVT0 "
1153                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1154                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1155                 }
1156         } else if (nmi_wd_enabled)
1157                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1158 }
1159
1160 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1161 {
1162         int ret = 0;
1163
1164         trace_kvm_apic_write(reg, val);
1165
1166         switch (reg) {
1167         case APIC_ID:           /* Local APIC ID */
1168                 if (!apic_x2apic_mode(apic))
1169                         kvm_apic_set_id(apic, val >> 24);
1170                 else
1171                         ret = 1;
1172                 break;
1173
1174         case APIC_TASKPRI:
1175                 report_tpr_access(apic, true);
1176                 apic_set_tpr(apic, val & 0xff);
1177                 break;
1178
1179         case APIC_EOI:
1180                 apic_set_eoi(apic);
1181                 break;
1182
1183         case APIC_LDR:
1184                 if (!apic_x2apic_mode(apic))
1185                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1186                 else
1187                         ret = 1;
1188                 break;
1189
1190         case APIC_DFR:
1191                 if (!apic_x2apic_mode(apic)) {
1192                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1193                         recalculate_apic_map(apic->vcpu->kvm);
1194                 } else
1195                         ret = 1;
1196                 break;
1197
1198         case APIC_SPIV: {
1199                 u32 mask = 0x3ff;
1200                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1201                         mask |= APIC_SPIV_DIRECTED_EOI;
1202                 apic_set_spiv(apic, val & mask);
1203                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1204                         int i;
1205                         u32 lvt_val;
1206
1207                         for (i = 0; i < APIC_LVT_NUM; i++) {
1208                                 lvt_val = kvm_apic_get_reg(apic,
1209                                                        APIC_LVTT + 0x10 * i);
1210                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1211                                              lvt_val | APIC_LVT_MASKED);
1212                         }
1213                         atomic_set(&apic->lapic_timer.pending, 0);
1214
1215                 }
1216                 break;
1217         }
1218         case APIC_ICR:
1219                 /* No delay here, so we always clear the pending bit */
1220                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1221                 apic_send_ipi(apic);
1222                 break;
1223
1224         case APIC_ICR2:
1225                 if (!apic_x2apic_mode(apic))
1226                         val &= 0xff000000;
1227                 apic_set_reg(apic, APIC_ICR2, val);
1228                 break;
1229
1230         case APIC_LVT0:
1231                 apic_manage_nmi_watchdog(apic, val);
1232         case APIC_LVTTHMR:
1233         case APIC_LVTPC:
1234         case APIC_LVT1:
1235         case APIC_LVTERR:
1236                 /* TODO: Check vector */
1237                 if (!kvm_apic_sw_enabled(apic))
1238                         val |= APIC_LVT_MASKED;
1239
1240                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1241                 apic_set_reg(apic, reg, val);
1242
1243                 break;
1244
1245         case APIC_LVTT: {
1246                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1247
1248                 if (apic->lapic_timer.timer_mode != timer_mode) {
1249                         apic->lapic_timer.timer_mode = timer_mode;
1250                         hrtimer_cancel(&apic->lapic_timer.timer);
1251                 }
1252
1253                 if (!kvm_apic_sw_enabled(apic))
1254                         val |= APIC_LVT_MASKED;
1255                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1256                 apic_set_reg(apic, APIC_LVTT, val);
1257                 break;
1258         }
1259
1260         case APIC_TMICT:
1261                 if (apic_lvtt_tscdeadline(apic))
1262                         break;
1263
1264                 hrtimer_cancel(&apic->lapic_timer.timer);
1265                 apic_set_reg(apic, APIC_TMICT, val);
1266                 start_apic_timer(apic);
1267                 break;
1268
1269         case APIC_TDCR:
1270                 if (val & 4)
1271                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1272                 apic_set_reg(apic, APIC_TDCR, val);
1273                 update_divide_count(apic);
1274                 break;
1275
1276         case APIC_ESR:
1277                 if (apic_x2apic_mode(apic) && val != 0) {
1278                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1279                         ret = 1;
1280                 }
1281                 break;
1282
1283         case APIC_SELF_IPI:
1284                 if (apic_x2apic_mode(apic)) {
1285                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1286                 } else
1287                         ret = 1;
1288                 break;
1289         default:
1290                 ret = 1;
1291                 break;
1292         }
1293         if (ret)
1294                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1295         return ret;
1296 }
1297
1298 static int apic_mmio_write(struct kvm_io_device *this,
1299                             gpa_t address, int len, const void *data)
1300 {
1301         struct kvm_lapic *apic = to_lapic(this);
1302         unsigned int offset = address - apic->base_address;
1303         u32 val;
1304
1305         if (!apic_mmio_in_range(apic, address))
1306                 return -EOPNOTSUPP;
1307
1308         /*
1309          * APIC register must be aligned on 128-bits boundary.
1310          * 32/64/128 bits registers must be accessed thru 32 bits.
1311          * Refer SDM 8.4.1
1312          */
1313         if (len != 4 || (offset & 0xf)) {
1314                 /* Don't shout loud, $infamous_os would cause only noise. */
1315                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1316                 return 0;
1317         }
1318
1319         val = *(u32*)data;
1320
1321         /* too common printing */
1322         if (offset != APIC_EOI)
1323                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1324                            "0x%x\n", __func__, offset, len, val);
1325
1326         apic_reg_write(apic, offset & 0xff0, val);
1327
1328         return 0;
1329 }
1330
1331 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1332 {
1333         if (kvm_vcpu_has_lapic(vcpu))
1334                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1335 }
1336 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1337
1338 /* emulate APIC access in a trap manner */
1339 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1340 {
1341         u32 val = 0;
1342
1343         /* hw has done the conditional check and inst decode */
1344         offset &= 0xff0;
1345
1346         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1347
1348         /* TODO: optimize to just emulate side effect w/o one more write */
1349         apic_reg_write(vcpu->arch.apic, offset, val);
1350 }
1351 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1352
1353 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1354 {
1355         struct kvm_lapic *apic = vcpu->arch.apic;
1356
1357         if (!vcpu->arch.apic)
1358                 return;
1359
1360         hrtimer_cancel(&apic->lapic_timer.timer);
1361
1362         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1363                 static_key_slow_dec_deferred(&apic_hw_disabled);
1364
1365         if (!apic->sw_enabled)
1366                 static_key_slow_dec_deferred(&apic_sw_disabled);
1367
1368         if (apic->regs)
1369                 free_page((unsigned long)apic->regs);
1370
1371         kfree(apic);
1372 }
1373
1374 /*
1375  *----------------------------------------------------------------------
1376  * LAPIC interface
1377  *----------------------------------------------------------------------
1378  */
1379
1380 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1381 {
1382         struct kvm_lapic *apic = vcpu->arch.apic;
1383
1384         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1385                         apic_lvtt_period(apic))
1386                 return 0;
1387
1388         return apic->lapic_timer.tscdeadline;
1389 }
1390
1391 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1392 {
1393         struct kvm_lapic *apic = vcpu->arch.apic;
1394
1395         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1396                         apic_lvtt_period(apic))
1397                 return;
1398
1399         hrtimer_cancel(&apic->lapic_timer.timer);
1400         apic->lapic_timer.tscdeadline = data;
1401         start_apic_timer(apic);
1402 }
1403
1404 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1405 {
1406         struct kvm_lapic *apic = vcpu->arch.apic;
1407
1408         if (!kvm_vcpu_has_lapic(vcpu))
1409                 return;
1410
1411         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1412                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1413 }
1414
1415 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1416 {
1417         u64 tpr;
1418
1419         if (!kvm_vcpu_has_lapic(vcpu))
1420                 return 0;
1421
1422         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1423
1424         return (tpr & 0xf0) >> 4;
1425 }
1426
1427 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1428 {
1429         u64 old_value = vcpu->arch.apic_base;
1430         struct kvm_lapic *apic = vcpu->arch.apic;
1431
1432         if (!apic) {
1433                 value |= MSR_IA32_APICBASE_BSP;
1434                 vcpu->arch.apic_base = value;
1435                 return;
1436         }
1437
1438         if (!kvm_vcpu_is_bsp(apic->vcpu))
1439                 value &= ~MSR_IA32_APICBASE_BSP;
1440         vcpu->arch.apic_base = value;
1441
1442         /* update jump label if enable bit changes */
1443         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1444                 if (value & MSR_IA32_APICBASE_ENABLE)
1445                         static_key_slow_dec_deferred(&apic_hw_disabled);
1446                 else
1447                         static_key_slow_inc(&apic_hw_disabled.key);
1448                 recalculate_apic_map(vcpu->kvm);
1449         }
1450
1451         if ((old_value ^ value) & X2APIC_ENABLE) {
1452                 if (value & X2APIC_ENABLE) {
1453                         u32 id = kvm_apic_id(apic);
1454                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1455                         kvm_apic_set_ldr(apic, ldr);
1456                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1457                 } else
1458                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1459         }
1460
1461         apic->base_address = apic->vcpu->arch.apic_base &
1462                              MSR_IA32_APICBASE_BASE;
1463
1464         /* with FSB delivery interrupt, we can restart APIC functionality */
1465         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1466                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1467
1468 }
1469
1470 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1471 {
1472         struct kvm_lapic *apic;
1473         int i;
1474
1475         apic_debug("%s\n", __func__);
1476
1477         ASSERT(vcpu);
1478         apic = vcpu->arch.apic;
1479         ASSERT(apic != NULL);
1480
1481         /* Stop the timer in case it's a reset to an active apic */
1482         hrtimer_cancel(&apic->lapic_timer.timer);
1483
1484         kvm_apic_set_id(apic, vcpu->vcpu_id);
1485         kvm_apic_set_version(apic->vcpu);
1486
1487         for (i = 0; i < APIC_LVT_NUM; i++)
1488                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1489         apic->lapic_timer.timer_mode = 0;
1490         apic_set_reg(apic, APIC_LVT0,
1491                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1492
1493         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1494         apic_set_spiv(apic, 0xff);
1495         apic_set_reg(apic, APIC_TASKPRI, 0);
1496         kvm_apic_set_ldr(apic, 0);
1497         apic_set_reg(apic, APIC_ESR, 0);
1498         apic_set_reg(apic, APIC_ICR, 0);
1499         apic_set_reg(apic, APIC_ICR2, 0);
1500         apic_set_reg(apic, APIC_TDCR, 0);
1501         apic_set_reg(apic, APIC_TMICT, 0);
1502         for (i = 0; i < 8; i++) {
1503                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1504                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1505                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1506         }
1507         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1508         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1509         apic->highest_isr_cache = -1;
1510         update_divide_count(apic);
1511         atomic_set(&apic->lapic_timer.pending, 0);
1512         if (kvm_vcpu_is_bsp(vcpu))
1513                 kvm_lapic_set_base(vcpu,
1514                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1515         vcpu->arch.pv_eoi.msr_val = 0;
1516         apic_update_ppr(apic);
1517
1518         vcpu->arch.apic_arb_prio = 0;
1519         vcpu->arch.apic_attention = 0;
1520
1521         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1522                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1523                    vcpu, kvm_apic_id(apic),
1524                    vcpu->arch.apic_base, apic->base_address);
1525 }
1526
1527 /*
1528  *----------------------------------------------------------------------
1529  * timer interface
1530  *----------------------------------------------------------------------
1531  */
1532
1533 static bool lapic_is_periodic(struct kvm_lapic *apic)
1534 {
1535         return apic_lvtt_period(apic);
1536 }
1537
1538 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1539 {
1540         struct kvm_lapic *apic = vcpu->arch.apic;
1541
1542         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1543                         apic_lvt_enabled(apic, APIC_LVTT))
1544                 return atomic_read(&apic->lapic_timer.pending);
1545
1546         return 0;
1547 }
1548
1549 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1550 {
1551         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1552         int vector, mode, trig_mode;
1553
1554         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1555                 vector = reg & APIC_VECTOR_MASK;
1556                 mode = reg & APIC_MODE_MASK;
1557                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1558                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1559                                         NULL);
1560         }
1561         return 0;
1562 }
1563
1564 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1565 {
1566         struct kvm_lapic *apic = vcpu->arch.apic;
1567
1568         if (apic)
1569                 kvm_apic_local_deliver(apic, APIC_LVT0);
1570 }
1571
1572 static const struct kvm_io_device_ops apic_mmio_ops = {
1573         .read     = apic_mmio_read,
1574         .write    = apic_mmio_write,
1575 };
1576
1577 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1578 {
1579         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1580         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1581
1582         apic_timer_expired(apic);
1583
1584         if (lapic_is_periodic(apic)) {
1585                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1586                 return HRTIMER_RESTART;
1587         } else
1588                 return HRTIMER_NORESTART;
1589 }
1590
1591 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1592 {
1593         struct kvm_lapic *apic;
1594
1595         ASSERT(vcpu != NULL);
1596         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1597
1598         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1599         if (!apic)
1600                 goto nomem;
1601
1602         vcpu->arch.apic = apic;
1603
1604         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1605         if (!apic->regs) {
1606                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1607                        vcpu->vcpu_id);
1608                 goto nomem_free_apic;
1609         }
1610         apic->vcpu = vcpu;
1611
1612         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1613                      HRTIMER_MODE_ABS);
1614         apic->lapic_timer.timer.function = apic_timer_fn;
1615
1616         /*
1617          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1618          * thinking that APIC satet has changed.
1619          */
1620         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1621         kvm_lapic_set_base(vcpu,
1622                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1623
1624         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1625         kvm_lapic_reset(vcpu);
1626         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1627
1628         return 0;
1629 nomem_free_apic:
1630         kfree(apic);
1631 nomem:
1632         return -ENOMEM;
1633 }
1634
1635 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1636 {
1637         struct kvm_lapic *apic = vcpu->arch.apic;
1638         int highest_irr;
1639
1640         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1641                 return -1;
1642
1643         apic_update_ppr(apic);
1644         highest_irr = apic_find_highest_irr(apic);
1645         if ((highest_irr == -1) ||
1646             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1647                 return -1;
1648         return highest_irr;
1649 }
1650
1651 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1652 {
1653         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1654         int r = 0;
1655
1656         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1657                 r = 1;
1658         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1659             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1660                 r = 1;
1661         return r;
1662 }
1663
1664 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1665 {
1666         struct kvm_lapic *apic = vcpu->arch.apic;
1667
1668         if (!kvm_vcpu_has_lapic(vcpu))
1669                 return;
1670
1671         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1672                 kvm_apic_local_deliver(apic, APIC_LVTT);
1673                 if (apic_lvtt_tscdeadline(apic))
1674                         apic->lapic_timer.tscdeadline = 0;
1675                 atomic_set(&apic->lapic_timer.pending, 0);
1676         }
1677 }
1678
1679 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1680 {
1681         int vector = kvm_apic_has_interrupt(vcpu);
1682         struct kvm_lapic *apic = vcpu->arch.apic;
1683
1684         if (vector == -1)
1685                 return -1;
1686
1687         /*
1688          * We get here even with APIC virtualization enabled, if doing
1689          * nested virtualization and L1 runs with the "acknowledge interrupt
1690          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1691          * because the process would deliver it through the IDT.
1692          */
1693
1694         apic_set_isr(vector, apic);
1695         apic_update_ppr(apic);
1696         apic_clear_irr(vector, apic);
1697         return vector;
1698 }
1699
1700 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1701                 struct kvm_lapic_state *s)
1702 {
1703         struct kvm_lapic *apic = vcpu->arch.apic;
1704
1705         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1706         /* set SPIV separately to get count of SW disabled APICs right */
1707         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1708         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1709         /* call kvm_apic_set_id() to put apic into apic_map */
1710         kvm_apic_set_id(apic, kvm_apic_id(apic));
1711         kvm_apic_set_version(vcpu);
1712
1713         apic_update_ppr(apic);
1714         hrtimer_cancel(&apic->lapic_timer.timer);
1715         update_divide_count(apic);
1716         start_apic_timer(apic);
1717         apic->irr_pending = true;
1718         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1719                                 1 : count_vectors(apic->regs + APIC_ISR);
1720         apic->highest_isr_cache = -1;
1721         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1722         kvm_make_request(KVM_REQ_EVENT, vcpu);
1723         kvm_rtc_eoi_tracking_restore_one(vcpu);
1724 }
1725
1726 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1727 {
1728         struct hrtimer *timer;
1729
1730         if (!kvm_vcpu_has_lapic(vcpu))
1731                 return;
1732
1733         timer = &vcpu->arch.apic->lapic_timer.timer;
1734         if (hrtimer_cancel(timer))
1735                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1736 }
1737
1738 /*
1739  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1740  *
1741  * Detect whether guest triggered PV EOI since the
1742  * last entry. If yes, set EOI on guests's behalf.
1743  * Clear PV EOI in guest memory in any case.
1744  */
1745 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1746                                         struct kvm_lapic *apic)
1747 {
1748         bool pending;
1749         int vector;
1750         /*
1751          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1752          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1753          *
1754          * KVM_APIC_PV_EOI_PENDING is unset:
1755          *      -> host disabled PV EOI.
1756          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1757          *      -> host enabled PV EOI, guest did not execute EOI yet.
1758          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1759          *      -> host enabled PV EOI, guest executed EOI.
1760          */
1761         BUG_ON(!pv_eoi_enabled(vcpu));
1762         pending = pv_eoi_get_pending(vcpu);
1763         /*
1764          * Clear pending bit in any case: it will be set again on vmentry.
1765          * While this might not be ideal from performance point of view,
1766          * this makes sure pv eoi is only enabled when we know it's safe.
1767          */
1768         pv_eoi_clr_pending(vcpu);
1769         if (pending)
1770                 return;
1771         vector = apic_set_eoi(apic);
1772         trace_kvm_pv_eoi(apic, vector);
1773 }
1774
1775 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1776 {
1777         u32 data;
1778
1779         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1780                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1781
1782         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1783                 return;
1784
1785         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1786                                 sizeof(u32));
1787
1788         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1789 }
1790
1791 /*
1792  * apic_sync_pv_eoi_to_guest - called before vmentry
1793  *
1794  * Detect whether it's safe to enable PV EOI and
1795  * if yes do so.
1796  */
1797 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1798                                         struct kvm_lapic *apic)
1799 {
1800         if (!pv_eoi_enabled(vcpu) ||
1801             /* IRR set or many bits in ISR: could be nested. */
1802             apic->irr_pending ||
1803             /* Cache not set: could be safe but we don't bother. */
1804             apic->highest_isr_cache == -1 ||
1805             /* Need EOI to update ioapic. */
1806             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1807                 /*
1808                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1809                  * so we need not do anything here.
1810                  */
1811                 return;
1812         }
1813
1814         pv_eoi_set_pending(apic->vcpu);
1815 }
1816
1817 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1818 {
1819         u32 data, tpr;
1820         int max_irr, max_isr;
1821         struct kvm_lapic *apic = vcpu->arch.apic;
1822
1823         apic_sync_pv_eoi_to_guest(vcpu, apic);
1824
1825         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1826                 return;
1827
1828         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1829         max_irr = apic_find_highest_irr(apic);
1830         if (max_irr < 0)
1831                 max_irr = 0;
1832         max_isr = apic_find_highest_isr(apic);
1833         if (max_isr < 0)
1834                 max_isr = 0;
1835         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1836
1837         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1838                                 sizeof(u32));
1839 }
1840
1841 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1842 {
1843         if (vapic_addr) {
1844                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1845                                         &vcpu->arch.apic->vapic_cache,
1846                                         vapic_addr, sizeof(u32)))
1847                         return -EINVAL;
1848                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1849         } else {
1850                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1851         }
1852
1853         vcpu->arch.apic->vapic_addr = vapic_addr;
1854         return 0;
1855 }
1856
1857 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858 {
1859         struct kvm_lapic *apic = vcpu->arch.apic;
1860         u32 reg = (msr - APIC_BASE_MSR) << 4;
1861
1862         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1863                 return 1;
1864
1865         /* if this is ICR write vector before command */
1866         if (msr == 0x830)
1867                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1868         return apic_reg_write(apic, reg, (u32)data);
1869 }
1870
1871 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1872 {
1873         struct kvm_lapic *apic = vcpu->arch.apic;
1874         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1875
1876         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1877                 return 1;
1878
1879         if (apic_reg_read(apic, reg, 4, &low))
1880                 return 1;
1881         if (msr == 0x830)
1882                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1883
1884         *data = (((u64)high) << 32) | low;
1885
1886         return 0;
1887 }
1888
1889 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1890 {
1891         struct kvm_lapic *apic = vcpu->arch.apic;
1892
1893         if (!kvm_vcpu_has_lapic(vcpu))
1894                 return 1;
1895
1896         /* if this is ICR write vector before command */
1897         if (reg == APIC_ICR)
1898                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1899         return apic_reg_write(apic, reg, (u32)data);
1900 }
1901
1902 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1903 {
1904         struct kvm_lapic *apic = vcpu->arch.apic;
1905         u32 low, high = 0;
1906
1907         if (!kvm_vcpu_has_lapic(vcpu))
1908                 return 1;
1909
1910         if (apic_reg_read(apic, reg, 4, &low))
1911                 return 1;
1912         if (reg == APIC_ICR)
1913                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1914
1915         *data = (((u64)high) << 32) | low;
1916
1917         return 0;
1918 }
1919
1920 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1921 {
1922         u64 addr = data & ~KVM_MSR_ENABLED;
1923         if (!IS_ALIGNED(addr, 4))
1924                 return 1;
1925
1926         vcpu->arch.pv_eoi.msr_val = data;
1927         if (!pv_eoi_enabled(vcpu))
1928                 return 0;
1929         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1930                                          addr, sizeof(u8));
1931 }
1932
1933 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1934 {
1935         struct kvm_lapic *apic = vcpu->arch.apic;
1936         unsigned int sipi_vector;
1937         unsigned long pe;
1938
1939         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1940                 return;
1941
1942         pe = xchg(&apic->pending_events, 0);
1943
1944         if (test_bit(KVM_APIC_INIT, &pe)) {
1945                 kvm_lapic_reset(vcpu);
1946                 kvm_vcpu_reset(vcpu);
1947                 if (kvm_vcpu_is_bsp(apic->vcpu))
1948                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1949                 else
1950                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1951         }
1952         if (test_bit(KVM_APIC_SIPI, &pe) &&
1953             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1954                 /* evaluate pending_events before reading the vector */
1955                 smp_rmb();
1956                 sipi_vector = apic->sipi_vector;
1957                 apic_debug("vcpu %d received sipi with vector # %x\n",
1958                          vcpu->vcpu_id, sipi_vector);
1959                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1960                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1961         }
1962 }
1963
1964 void kvm_lapic_init(void)
1965 {
1966         /* do not patch jump label more than once per second */
1967         jump_label_rate_limit(&apic_hw_disabled, HZ);
1968         jump_label_rate_limit(&apic_sw_disabled, HZ);
1969 }