arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         struct page *avic_logical_id_table_page;
 149         struct page *avic_physical_id_table_page;
 150         struct hlist_node hnode;
 151
 152         struct kvm_sev_info sev_info;
 153 };
 154
 155 struct kvm_vcpu;
 156
 157 struct nested_state {
 158         struct vmcb *hsave;
 159         u64 hsave_msr;
 160         u64 vm_cr_msr;
 161         u64 vmcb;
 162
 163         /* These are the merged vectors */
 164         u32 *msrpm;
 165
 166         /* gpa pointers to the real vectors */
 167         u64 vmcb_msrpm;
 168         u64 vmcb_iopm;
 169
 170         /* A VMEXIT is required but not yet emulated */
 171         bool exit_required;
 172
 173         /* cache for intercepts of the guest */
 174         u32 intercept_cr;
 175         u32 intercept_dr;
 176         u32 intercept_exceptions;
 177         u64 intercept;
 178
 179         /* Nested Paging related state */
 180         u64 nested_cr3;
 181 };
 182
 183 #define MSRPM_OFFSETS   16
 184 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 185
 186 /*
 187  * Set osvw_len to higher value when updated Revision Guides
 188  * are published and we know what the new status bits are
 189  */
 190 static uint64_t osvw_len = 4, osvw_status;
 191
 192 struct vcpu_svm {
 193         struct kvm_vcpu vcpu;
 194         struct vmcb *vmcb;
 195         unsigned long vmcb_pa;
 196         struct svm_cpu_data *svm_data;
 197         uint64_t asid_generation;
 198         uint64_t sysenter_esp;
 199         uint64_t sysenter_eip;
 200         uint64_t tsc_aux;
 201
 202         u64 msr_decfg;
 203
 204         u64 next_rip;
 205
 206         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 207         struct {
 208                 u16 fs;
 209                 u16 gs;
 210                 u16 ldt;
 211                 u64 gs_base;
 212         } host;
 213
 214         u64 spec_ctrl;
 215         /*
 216          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 217          * translated into the appropriate L2_CFG bits on the host to
 218          * perform speculative control.
 219          */
 220         u64 virt_spec_ctrl;
 221
 222         u32 *msrpm;
 223
 224         ulong nmi_iret_rip;
 225
 226         struct nested_state nested;
 227
 228         bool nmi_singlestep;
 229         u64 nmi_singlestep_guest_rflags;
 230
 231         unsigned int3_injected;
 232         unsigned long int3_rip;
 233
 234         /* cached guest cpuid flags for faster access */
 235         bool nrips_enabled      : 1;
 236
 237         u32 ldr_reg;
 238         u32 dfr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 266
 267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 271
 272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 274
 275 #define MSR_INVALID                     0xffffffffU
 276
 277 static const struct svm_direct_access_msrs {
 278         u32 index;   /* Index of the MSR */
 279         bool always; /* True if intercept is always on */
 280 } direct_access_msrs[] = {
 281         { .index = MSR_STAR,                            .always = true  },
 282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 283 #ifdef CONFIG_X86_64
 284         { .index = MSR_GS_BASE,                         .always = true  },
 285         { .index = MSR_FS_BASE,                         .always = true  },
 286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 287         { .index = MSR_LSTAR,                           .always = true  },
 288         { .index = MSR_CSTAR,                           .always = true  },
 289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 290 #endif
 291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 297         { .index = MSR_INVALID,                         .always = false },
 298 };
 299
 300 /* enable NPT for AMD64 and X86 with PAE */
 301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 302 static bool npt_enabled = true;
 303 #else
 304 static bool npt_enabled;
 305 #endif
 306
 307 /*
 308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 309  * pause_filter_count: On processors that support Pause filtering(indicated
 310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 311  *      count value. On VMRUN this value is loaded into an internal counter.
 312  *      Each time a pause instruction is executed, this counter is decremented
 313  *      until it reaches zero at which time a #VMEXIT is generated if pause
 314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 315  *      Intercept Filtering for more details.
 316  *      This also indicate if ple logic enabled.
 317  *
 318  * pause_filter_thresh: In addition, some processor families support advanced
 319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 320  *      the amount of time a guest is allowed to execute in a pause loop.
 321  *      In this mode, a 16-bit pause filter threshold field is added in the
 322  *      VMCB. The threshold value is a cycle count that is used to reset the
 323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 324  *      count value from VMCB into an internal counter. Then, on each pause
 325  *      instruction the hardware checks the elapsed number of cycles since
 326  *      the most recent pause instruction against the pause filter threshold.
 327  *      If the elapsed cycle count is greater than the pause filter threshold,
 328  *      then the internal pause count is reloaded from the VMCB and execution
 329  *      continues. If the elapsed cycle count is less than the pause filter
 330  *      threshold, then the internal pause count is decremented. If the count
 331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 332  *      triggered. If advanced pause filtering is supported and pause filter
 333  *      threshold field is set to zero, the filter will operate in the simpler,
 334  *      count only mode.
 335  */
 336
 337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 338 module_param(pause_filter_thresh, ushort, 0444);
 339
 340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 341 module_param(pause_filter_count, ushort, 0444);
 342
 343 /* Default doubles per-vcpu window every exit. */
 344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 345 module_param(pause_filter_count_grow, ushort, 0444);
 346
 347 /* Default resets per-vcpu window every exit to pause_filter_count. */
 348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 349 module_param(pause_filter_count_shrink, ushort, 0444);
 350
 351 /* Default is to compute the maximum so we can never overflow. */
 352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 353 module_param(pause_filter_count_max, ushort, 0444);
 354
 355 /* allow nested paging (virtualized MMU) for all guests */
 356 static int npt = true;
 357 module_param(npt, int, S_IRUGO);
 358
 359 /* allow nested virtualization in KVM/SVM */
 360 static int nested = true;
 361 module_param(nested, int, S_IRUGO);
 362
 363 /* enable / disable AVIC */
 364 static int avic;
 365 #ifdef CONFIG_X86_LOCAL_APIC
 366 module_param(avic, int, S_IRUGO);
 367 #endif
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 382
 383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 385 static void svm_complete_interrupts(struct vcpu_svm *svm);
 386
 387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 388 static int nested_svm_intercept(struct vcpu_svm *svm);
 389 static int nested_svm_vmexit(struct vcpu_svm *svm);
 390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 391                                       bool has_error_code, u32 error_code);
 392
 393 enum {
 394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 395                             pause filter count */
 396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 397         VMCB_ASID,       /* ASID */
 398         VMCB_INTR,       /* int_ctl, int_vector */
 399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 401         VMCB_DR,         /* DR6, DR7 */
 402         VMCB_DT,         /* GDT, IDT */
 403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 404         VMCB_CR2,        /* CR2 only */
 405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 407                           * AVIC PHYSICAL_TABLE pointer,
 408                           * AVIC LOGICAL_TABLE pointer
 409                           */
 410         VMCB_DIRTY_MAX,
 411 };
 412
 413 /* TPR and CR2 are always written before VMRUN */
 414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 415
 416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 417
 418 static unsigned int max_sev_asid;
 419 static unsigned int min_sev_asid;
 420 static unsigned long *sev_asid_bitmap;
 421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 422
 423 struct enc_region {
 424         struct list_head list;
 425         unsigned long npages;
 426         struct page **pages;
 427         unsigned long uaddr;
 428         unsigned long size;
 429 };
 430
 431
 432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 433 {
 434         return container_of(kvm, struct kvm_svm, kvm);
 435 }
 436
 437 static inline bool svm_sev_enabled(void)
 438 {
 439         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 440 }
 441
 442 static inline bool sev_guest(struct kvm *kvm)
 443 {
 444 #ifdef CONFIG_KVM_AMD_SEV
 445         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 446
 447         return sev->active;
 448 #else
 449         return false;
 450 #endif
 451 }
 452
 453 static inline int sev_get_asid(struct kvm *kvm)
 454 {
 455         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 456
 457         return sev->asid;
 458 }
 459
 460 static inline void mark_all_dirty(struct vmcb *vmcb)
 461 {
 462         vmcb->control.clean = 0;
 463 }
 464
 465 static inline void mark_all_clean(struct vmcb *vmcb)
 466 {
 467         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 468                                & ~VMCB_ALWAYS_DIRTY_MASK;
 469 }
 470
 471 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 472 {
 473         vmcb->control.clean &= ~(1 << bit);
 474 }
 475
 476 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 477 {
 478         return container_of(vcpu, struct vcpu_svm, vcpu);
 479 }
 480
 481 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 482 {
 483         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 484         mark_dirty(svm->vmcb, VMCB_AVIC);
 485 }
 486
 487 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 488 {
 489         struct vcpu_svm *svm = to_svm(vcpu);
 490         u64 *entry = svm->avic_physical_id_cache;
 491
 492         if (!entry)
 493                 return false;
 494
 495         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 496 }
 497
 498 static void recalc_intercepts(struct vcpu_svm *svm)
 499 {
 500         struct vmcb_control_area *c, *h;
 501         struct nested_state *g;
 502
 503         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 504
 505         if (!is_guest_mode(&svm->vcpu))
 506                 return;
 507
 508         c = &svm->vmcb->control;
 509         h = &svm->nested.hsave->control;
 510         g = &svm->nested;
 511
 512         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 513         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 514         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 515         c->intercept = h->intercept | g->intercept;
 516 }
 517
 518 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 519 {
 520         if (is_guest_mode(&svm->vcpu))
 521                 return svm->nested.hsave;
 522         else
 523                 return svm->vmcb;
 524 }
 525
 526 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 527 {
 528         struct vmcb *vmcb = get_host_vmcb(svm);
 529
 530         vmcb->control.intercept_cr |= (1U << bit);
 531
 532         recalc_intercepts(svm);
 533 }
 534
 535 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 536 {
 537         struct vmcb *vmcb = get_host_vmcb(svm);
 538
 539         vmcb->control.intercept_cr &= ~(1U << bit);
 540
 541         recalc_intercepts(svm);
 542 }
 543
 544 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 545 {
 546         struct vmcb *vmcb = get_host_vmcb(svm);
 547
 548         return vmcb->control.intercept_cr & (1U << bit);
 549 }
 550
 551 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 552 {
 553         struct vmcb *vmcb = get_host_vmcb(svm);
 554
 555         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 556                 | (1 << INTERCEPT_DR1_READ)
 557                 | (1 << INTERCEPT_DR2_READ)
 558                 | (1 << INTERCEPT_DR3_READ)
 559                 | (1 << INTERCEPT_DR4_READ)
 560                 | (1 << INTERCEPT_DR5_READ)
 561                 | (1 << INTERCEPT_DR6_READ)
 562                 | (1 << INTERCEPT_DR7_READ)
 563                 | (1 << INTERCEPT_DR0_WRITE)
 564                 | (1 << INTERCEPT_DR1_WRITE)
 565                 | (1 << INTERCEPT_DR2_WRITE)
 566                 | (1 << INTERCEPT_DR3_WRITE)
 567                 | (1 << INTERCEPT_DR4_WRITE)
 568                 | (1 << INTERCEPT_DR5_WRITE)
 569                 | (1 << INTERCEPT_DR6_WRITE)
 570                 | (1 << INTERCEPT_DR7_WRITE);
 571
 572         recalc_intercepts(svm);
 573 }
 574
 575 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 576 {
 577         struct vmcb *vmcb = get_host_vmcb(svm);
 578
 579         vmcb->control.intercept_dr = 0;
 580
 581         recalc_intercepts(svm);
 582 }
 583
 584 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 585 {
 586         struct vmcb *vmcb = get_host_vmcb(svm);
 587
 588         vmcb->control.intercept_exceptions |= (1U << bit);
 589
 590         recalc_intercepts(svm);
 591 }
 592
 593 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 594 {
 595         struct vmcb *vmcb = get_host_vmcb(svm);
 596
 597         vmcb->control.intercept_exceptions &= ~(1U << bit);
 598
 599         recalc_intercepts(svm);
 600 }
 601
 602 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 603 {
 604         struct vmcb *vmcb = get_host_vmcb(svm);
 605
 606         vmcb->control.intercept |= (1ULL << bit);
 607
 608         recalc_intercepts(svm);
 609 }
 610
 611 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 612 {
 613         struct vmcb *vmcb = get_host_vmcb(svm);
 614
 615         vmcb->control.intercept &= ~(1ULL << bit);
 616
 617         recalc_intercepts(svm);
 618 }
 619
 620 static inline bool vgif_enabled(struct vcpu_svm *svm)
 621 {
 622         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 623 }
 624
 625 static inline void enable_gif(struct vcpu_svm *svm)
 626 {
 627         if (vgif_enabled(svm))
 628                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 629         else
 630                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 631 }
 632
 633 static inline void disable_gif(struct vcpu_svm *svm)
 634 {
 635         if (vgif_enabled(svm))
 636                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 637         else
 638                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 639 }
 640
 641 static inline bool gif_set(struct vcpu_svm *svm)
 642 {
 643         if (vgif_enabled(svm))
 644                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 645         else
 646                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 647 }
 648
 649 static unsigned long iopm_base;
 650
 651 struct kvm_ldttss_desc {
 652         u16 limit0;
 653         u16 base0;
 654         unsigned base1:8, type:5, dpl:2, p:1;
 655         unsigned limit1:4, zero0:3, g:1, base2:8;
 656         u32 base3;
 657         u32 zero1;
 658 } __attribute__((packed));
 659
 660 struct svm_cpu_data {
 661         int cpu;
 662
 663         u64 asid_generation;
 664         u32 max_asid;
 665         u32 next_asid;
 666         u32 min_asid;
 667         struct kvm_ldttss_desc *tss_desc;
 668
 669         struct page *save_area;
 670         struct vmcb *current_vmcb;
 671
 672         /* index = sev_asid, value = vmcb pointer */
 673         struct vmcb **sev_vmcbs;
 674 };
 675
 676 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 677
 678 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 679
 680 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 681 #define MSRS_RANGE_SIZE 2048
 682 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 683
 684 static u32 svm_msrpm_offset(u32 msr)
 685 {
 686         u32 offset;
 687         int i;
 688
 689         for (i = 0; i < NUM_MSR_MAPS; i++) {
 690                 if (msr < msrpm_ranges[i] ||
 691                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 692                         continue;
 693
 694                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 695                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 696
 697                 /* Now we have the u8 offset - but need the u32 offset */
 698                 return offset / 4;
 699         }
 700
 701         /* MSR not in any range */
 702         return MSR_INVALID;
 703 }
 704
 705 #define MAX_INST_SIZE 15
 706
 707 static inline void clgi(void)
 708 {
 709         asm volatile (__ex("clgi"));
 710 }
 711
 712 static inline void stgi(void)
 713 {
 714         asm volatile (__ex("stgi"));
 715 }
 716
 717 static inline void invlpga(unsigned long addr, u32 asid)
 718 {
 719         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 720 }
 721
 722 static int get_npt_level(struct kvm_vcpu *vcpu)
 723 {
 724 #ifdef CONFIG_X86_64
 725         return PT64_ROOT_4LEVEL;
 726 #else
 727         return PT32E_ROOT_LEVEL;
 728 #endif
 729 }
 730
 731 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 732 {
 733         vcpu->arch.efer = efer;
 734         if (!npt_enabled && !(efer & EFER_LMA))
 735                 efer &= ~EFER_LME;
 736
 737         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 738         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 739 }
 740
 741 static int is_external_interrupt(u32 info)
 742 {
 743         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 744         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 745 }
 746
 747 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 748 {
 749         struct vcpu_svm *svm = to_svm(vcpu);
 750         u32 ret = 0;
 751
 752         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 753                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 754         return ret;
 755 }
 756
 757 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 758 {
 759         struct vcpu_svm *svm = to_svm(vcpu);
 760
 761         if (mask == 0)
 762                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 763         else
 764                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 765
 766 }
 767
 768 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 769 {
 770         struct vcpu_svm *svm = to_svm(vcpu);
 771
 772         if (svm->vmcb->control.next_rip != 0) {
 773                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 774                 svm->next_rip = svm->vmcb->control.next_rip;
 775         }
 776
 777         if (!svm->next_rip) {
 778                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 779                                 EMULATE_DONE)
 780                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 781                 return;
 782         }
 783         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 784                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 785                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 786
 787         kvm_rip_write(vcpu, svm->next_rip);
 788         svm_set_interrupt_shadow(vcpu, 0);
 789 }
 790
 791 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 792 {
 793         struct vcpu_svm *svm = to_svm(vcpu);
 794         unsigned nr = vcpu->arch.exception.nr;
 795         bool has_error_code = vcpu->arch.exception.has_error_code;
 796         bool reinject = vcpu->arch.exception.injected;
 797         u32 error_code = vcpu->arch.exception.error_code;
 798
 799         /*
 800          * If we are within a nested VM we'd better #VMEXIT and let the guest
 801          * handle the exception
 802          */
 803         if (!reinject &&
 804             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 805                 return;
 806
 807         kvm_deliver_exception_payload(&svm->vcpu);
 808
 809         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 810                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 811
 812                 /*
 813                  * For guest debugging where we have to reinject #BP if some
 814                  * INT3 is guest-owned:
 815                  * Emulate nRIP by moving RIP forward. Will fail if injection
 816                  * raises a fault that is not intercepted. Still better than
 817                  * failing in all cases.
 818                  */
 819                 skip_emulated_instruction(&svm->vcpu);
 820                 rip = kvm_rip_read(&svm->vcpu);
 821                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 822                 svm->int3_injected = rip - old_rip;
 823         }
 824
 825         svm->vmcb->control.event_inj = nr
 826                 | SVM_EVTINJ_VALID
 827                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 828                 | SVM_EVTINJ_TYPE_EXEPT;
 829         svm->vmcb->control.event_inj_err = error_code;
 830 }
 831
 832 static void svm_init_erratum_383(void)
 833 {
 834         u32 low, high;
 835         int err;
 836         u64 val;
 837
 838         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 839                 return;
 840
 841         /* Use _safe variants to not break nested virtualization */
 842         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 843         if (err)
 844                 return;
 845
 846         val |= (1ULL << 47);
 847
 848         low  = lower_32_bits(val);
 849         high = upper_32_bits(val);
 850
 851         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 852
 853         erratum_383_found = true;
 854 }
 855
 856 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 857 {
 858         /*
 859          * Guests should see errata 400 and 415 as fixed (assuming that
 860          * HLT and IO instructions are intercepted).
 861          */
 862         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 863         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 864
 865         /*
 866          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 867          * all osvw.status bits inside that length, including bit 0 (which is
 868          * reserved for erratum 298), are valid. However, if host processor's
 869          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 870          * be conservative here and therefore we tell the guest that erratum 298
 871          * is present (because we really don't know).
 872          */
 873         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 874                 vcpu->arch.osvw.status |= 1;
 875 }
 876
 877 static int has_svm(void)
 878 {
 879         const char *msg;
 880
 881         if (!cpu_has_svm(&msg)) {
 882                 printk(KERN_INFO "has_svm: %s\n", msg);
 883                 return 0;
 884         }
 885
 886         return 1;
 887 }
 888
 889 static void svm_hardware_disable(void)
 890 {
 891         /* Make sure we clean up behind us */
 892         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 893                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 894
 895         cpu_svm_disable();
 896
 897         amd_pmu_disable_virt();
 898 }
 899
 900 static int svm_hardware_enable(void)
 901 {
 902
 903         struct svm_cpu_data *sd;
 904         uint64_t efer;
 905         struct desc_struct *gdt;
 906         int me = raw_smp_processor_id();
 907
 908         rdmsrl(MSR_EFER, efer);
 909         if (efer & EFER_SVME)
 910                 return -EBUSY;
 911
 912         if (!has_svm()) {
 913                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 914                 return -EINVAL;
 915         }
 916         sd = per_cpu(svm_data, me);
 917         if (!sd) {
 918                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 919                 return -EINVAL;
 920         }
 921
 922         sd->asid_generation = 1;
 923         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 924         sd->next_asid = sd->max_asid + 1;
 925         sd->min_asid = max_sev_asid + 1;
 926
 927         gdt = get_current_gdt_rw();
 928         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 929
 930         wrmsrl(MSR_EFER, efer | EFER_SVME);
 931
 932         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 933
 934         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 935                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 936                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 937         }
 938
 939
 940         /*
 941          * Get OSVW bits.
 942          *
 943          * Note that it is possible to have a system with mixed processor
 944          * revisions and therefore different OSVW bits. If bits are not the same
 945          * on different processors then choose the worst case (i.e. if erratum
 946          * is present on one processor and not on another then assume that the
 947          * erratum is present everywhere).
 948          */
 949         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 950                 uint64_t len, status = 0;
 951                 int err;
 952
 953                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 954                 if (!err)
 955                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 956                                                       &err);
 957
 958                 if (err)
 959                         osvw_status = osvw_len = 0;
 960                 else {
 961                         if (len < osvw_len)
 962                                 osvw_len = len;
 963                         osvw_status |= status;
 964                         osvw_status &= (1ULL << osvw_len) - 1;
 965                 }
 966         } else
 967                 osvw_status = osvw_len = 0;
 968
 969         svm_init_erratum_383();
 970
 971         amd_pmu_enable_virt();
 972
 973         return 0;
 974 }
 975
 976 static void svm_cpu_uninit(int cpu)
 977 {
 978         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 979
 980         if (!sd)
 981                 return;
 982
 983         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 984         kfree(sd->sev_vmcbs);
 985         __free_page(sd->save_area);
 986         kfree(sd);
 987 }
 988
 989 static int svm_cpu_init(int cpu)
 990 {
 991         struct svm_cpu_data *sd;
 992         int r;
 993
 994         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 995         if (!sd)
 996                 return -ENOMEM;
 997         sd->cpu = cpu;
 998         r = -ENOMEM;
 999         sd->save_area = alloc_page(GFP_KERNEL);
1000         if (!sd->save_area)
1001                 goto err_1;
1002
1003         if (svm_sev_enabled()) {
1004                 r = -ENOMEM;
1005                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1006                                               sizeof(void *),
1007                                               GFP_KERNEL);
1008                 if (!sd->sev_vmcbs)
1009                         goto err_1;
1010         }
1011
1012         per_cpu(svm_data, cpu) = sd;
1013
1014         return 0;
1015
1016 err_1:
1017         kfree(sd);
1018         return r;
1019
1020 }
1021
1022 static bool valid_msr_intercept(u32 index)
1023 {
1024         int i;
1025
1026         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1027                 if (direct_access_msrs[i].index == index)
1028                         return true;
1029
1030         return false;
1031 }
1032
1033 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1034 {
1035         u8 bit_write;
1036         unsigned long tmp;
1037         u32 offset;
1038         u32 *msrpm;
1039
1040         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1041                                       to_svm(vcpu)->msrpm;
1042
1043         offset    = svm_msrpm_offset(msr);
1044         bit_write = 2 * (msr & 0x0f) + 1;
1045         tmp       = msrpm[offset];
1046
1047         BUG_ON(offset == MSR_INVALID);
1048
1049         return !!test_bit(bit_write,  &tmp);
1050 }
1051
1052 static void set_msr_interception(u32 *msrpm, unsigned msr,
1053                                  int read, int write)
1054 {
1055         u8 bit_read, bit_write;
1056         unsigned long tmp;
1057         u32 offset;
1058
1059         /*
1060          * If this warning triggers extend the direct_access_msrs list at the
1061          * beginning of the file
1062          */
1063         WARN_ON(!valid_msr_intercept(msr));
1064
1065         offset    = svm_msrpm_offset(msr);
1066         bit_read  = 2 * (msr & 0x0f);
1067         bit_write = 2 * (msr & 0x0f) + 1;
1068         tmp       = msrpm[offset];
1069
1070         BUG_ON(offset == MSR_INVALID);
1071
1072         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1073         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1074
1075         msrpm[offset] = tmp;
1076 }
1077
1078 static void svm_vcpu_init_msrpm(u32 *msrpm)
1079 {
1080         int i;
1081
1082         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1083
1084         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1085                 if (!direct_access_msrs[i].always)
1086                         continue;
1087
1088                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1089         }
1090 }
1091
1092 static void add_msr_offset(u32 offset)
1093 {
1094         int i;
1095
1096         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1097
1098                 /* Offset already in list? */
1099                 if (msrpm_offsets[i] == offset)
1100                         return;
1101
1102                 /* Slot used by another offset? */
1103                 if (msrpm_offsets[i] != MSR_INVALID)
1104                         continue;
1105
1106                 /* Add offset to list */
1107                 msrpm_offsets[i] = offset;
1108
1109                 return;
1110         }
1111
1112         /*
1113          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1114          * increase MSRPM_OFFSETS in this case.
1115          */
1116         BUG();
1117 }
1118
1119 static void init_msrpm_offsets(void)
1120 {
1121         int i;
1122
1123         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1124
1125         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1126                 u32 offset;
1127
1128                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1129                 BUG_ON(offset == MSR_INVALID);
1130
1131                 add_msr_offset(offset);
1132         }
1133 }
1134
1135 static void svm_enable_lbrv(struct vcpu_svm *svm)
1136 {
1137         u32 *msrpm = svm->msrpm;
1138
1139         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1140         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1141         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1142         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1143         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1144 }
1145
1146 static void svm_disable_lbrv(struct vcpu_svm *svm)
1147 {
1148         u32 *msrpm = svm->msrpm;
1149
1150         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1151         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1152         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1153         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1154         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1155 }
1156
1157 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1158 {
1159         svm->nmi_singlestep = false;
1160
1161         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1162                 /* Clear our flags if they were not set by the guest */
1163                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1164                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1165                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1166                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1167         }
1168 }
1169
1170 /* Note:
1171  * This hash table is used to map VM_ID to a struct kvm_svm,
1172  * when handling AMD IOMMU GALOG notification to schedule in
1173  * a particular vCPU.
1174  */
1175 #define SVM_VM_DATA_HASH_BITS   8
1176 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1177 static u32 next_vm_id = 0;
1178 static bool next_vm_id_wrapped = 0;
1179 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1180
1181 /* Note:
1182  * This function is called from IOMMU driver to notify
1183  * SVM to schedule in a particular vCPU of a particular VM.
1184  */
1185 static int avic_ga_log_notifier(u32 ga_tag)
1186 {
1187         unsigned long flags;
1188         struct kvm_svm *kvm_svm;
1189         struct kvm_vcpu *vcpu = NULL;
1190         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1191         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1192
1193         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1194
1195         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1196         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1197                 if (kvm_svm->avic_vm_id != vm_id)
1198                         continue;
1199                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1200                 break;
1201         }
1202         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1203
1204         /* Note:
1205          * At this point, the IOMMU should have already set the pending
1206          * bit in the vAPIC backing page. So, we just need to schedule
1207          * in the vcpu.
1208          */
1209         if (vcpu)
1210                 kvm_vcpu_wake_up(vcpu);
1211
1212         return 0;
1213 }
1214
1215 static __init int sev_hardware_setup(void)
1216 {
1217         struct sev_user_data_status *status;
1218         int rc;
1219
1220         /* Maximum number of encrypted guests supported simultaneously */
1221         max_sev_asid = cpuid_ecx(0x8000001F);
1222
1223         if (!max_sev_asid)
1224                 return 1;
1225
1226         /* Minimum ASID value that should be used for SEV guest */
1227         min_sev_asid = cpuid_edx(0x8000001F);
1228
1229         /* Initialize SEV ASID bitmap */
1230         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1231         if (!sev_asid_bitmap)
1232                 return 1;
1233
1234         status = kmalloc(sizeof(*status), GFP_KERNEL);
1235         if (!status)
1236                 return 1;
1237
1238         /*
1239          * Check SEV platform status.
1240          *
1241          * PLATFORM_STATUS can be called in any state, if we failed to query
1242          * the PLATFORM status then either PSP firmware does not support SEV
1243          * feature or SEV firmware is dead.
1244          */
1245         rc = sev_platform_status(status, NULL);
1246         if (rc)
1247                 goto err;
1248
1249         pr_info("SEV supported\n");
1250
1251 err:
1252         kfree(status);
1253         return rc;
1254 }
1255
1256 static void grow_ple_window(struct kvm_vcpu *vcpu)
1257 {
1258         struct vcpu_svm *svm = to_svm(vcpu);
1259         struct vmcb_control_area *control = &svm->vmcb->control;
1260         int old = control->pause_filter_count;
1261
1262         control->pause_filter_count = __grow_ple_window(old,
1263                                                         pause_filter_count,
1264                                                         pause_filter_count_grow,
1265                                                         pause_filter_count_max);
1266
1267         if (control->pause_filter_count != old)
1268                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1269
1270         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1271                                   control->pause_filter_count, old);
1272 }
1273
1274 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277         struct vmcb_control_area *control = &svm->vmcb->control;
1278         int old = control->pause_filter_count;
1279
1280         control->pause_filter_count =
1281                                 __shrink_ple_window(old,
1282                                                     pause_filter_count,
1283                                                     pause_filter_count_shrink,
1284                                                     pause_filter_count);
1285         if (control->pause_filter_count != old)
1286                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1287
1288         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1289                                     control->pause_filter_count, old);
1290 }
1291
1292 static __init int svm_hardware_setup(void)
1293 {
1294         int cpu;
1295         struct page *iopm_pages;
1296         void *iopm_va;
1297         int r;
1298
1299         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1300
1301         if (!iopm_pages)
1302                 return -ENOMEM;
1303
1304         iopm_va = page_address(iopm_pages);
1305         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1306         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1307
1308         init_msrpm_offsets();
1309
1310         if (boot_cpu_has(X86_FEATURE_NX))
1311                 kvm_enable_efer_bits(EFER_NX);
1312
1313         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1314                 kvm_enable_efer_bits(EFER_FFXSR);
1315
1316         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1317                 kvm_has_tsc_control = true;
1318                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1319                 kvm_tsc_scaling_ratio_frac_bits = 32;
1320         }
1321
1322         /* Check for pause filtering support */
1323         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1324                 pause_filter_count = 0;
1325                 pause_filter_thresh = 0;
1326         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1327                 pause_filter_thresh = 0;
1328         }
1329
1330         if (nested) {
1331                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1332                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1333         }
1334
1335         if (sev) {
1336                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1337                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1338                         r = sev_hardware_setup();
1339                         if (r)
1340                                 sev = false;
1341                 } else {
1342                         sev = false;
1343                 }
1344         }
1345
1346         for_each_possible_cpu(cpu) {
1347                 r = svm_cpu_init(cpu);
1348                 if (r)
1349                         goto err;
1350         }
1351
1352         if (!boot_cpu_has(X86_FEATURE_NPT))
1353                 npt_enabled = false;
1354
1355         if (npt_enabled && !npt) {
1356                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1357                 npt_enabled = false;
1358         }
1359
1360         if (npt_enabled) {
1361                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1362                 kvm_enable_tdp();
1363         } else
1364                 kvm_disable_tdp();
1365
1366         if (avic) {
1367                 if (!npt_enabled ||
1368                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1369                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1370                         avic = false;
1371                 } else {
1372                         pr_info("AVIC enabled\n");
1373
1374                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1375                 }
1376         }
1377
1378         if (vls) {
1379                 if (!npt_enabled ||
1380                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1381                     !IS_ENABLED(CONFIG_X86_64)) {
1382                         vls = false;
1383                 } else {
1384                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1385                 }
1386         }
1387
1388         if (vgif) {
1389                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1390                         vgif = false;
1391                 else
1392                         pr_info("Virtual GIF supported\n");
1393         }
1394
1395         return 0;
1396
1397 err:
1398         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1399         iopm_base = 0;
1400         return r;
1401 }
1402
1403 static __exit void svm_hardware_unsetup(void)
1404 {
1405         int cpu;
1406
1407         if (svm_sev_enabled())
1408                 bitmap_free(sev_asid_bitmap);
1409
1410         for_each_possible_cpu(cpu)
1411                 svm_cpu_uninit(cpu);
1412
1413         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1414         iopm_base = 0;
1415 }
1416
1417 static void init_seg(struct vmcb_seg *seg)
1418 {
1419         seg->selector = 0;
1420         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1421                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1422         seg->limit = 0xffff;
1423         seg->base = 0;
1424 }
1425
1426 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1427 {
1428         seg->selector = 0;
1429         seg->attrib = SVM_SELECTOR_P_MASK | type;
1430         seg->limit = 0xffff;
1431         seg->base = 0;
1432 }
1433
1434 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1435 {
1436         struct vcpu_svm *svm = to_svm(vcpu);
1437
1438         if (is_guest_mode(vcpu))
1439                 return svm->nested.hsave->control.tsc_offset;
1440
1441         return vcpu->arch.tsc_offset;
1442 }
1443
1444 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1445 {
1446         struct vcpu_svm *svm = to_svm(vcpu);
1447         u64 g_tsc_offset = 0;
1448
1449         if (is_guest_mode(vcpu)) {
1450                 /* Write L1's TSC offset.  */
1451                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1452                                svm->nested.hsave->control.tsc_offset;
1453                 svm->nested.hsave->control.tsc_offset = offset;
1454         }
1455
1456         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1457                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1458                                    offset);
1459
1460         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1461
1462         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1463         return svm->vmcb->control.tsc_offset;
1464 }
1465
1466 static void avic_init_vmcb(struct vcpu_svm *svm)
1467 {
1468         struct vmcb *vmcb = svm->vmcb;
1469         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1470         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1471         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1472         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1473
1474         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1475         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1476         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1477         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1478         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1479 }
1480
1481 static void init_vmcb(struct vcpu_svm *svm)
1482 {
1483         struct vmcb_control_area *control = &svm->vmcb->control;
1484         struct vmcb_save_area *save = &svm->vmcb->save;
1485
1486         svm->vcpu.arch.hflags = 0;
1487
1488         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1489         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1490         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1491         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1492         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1493         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1494         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1495                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1496
1497         set_dr_intercepts(svm);
1498
1499         set_exception_intercept(svm, PF_VECTOR);
1500         set_exception_intercept(svm, UD_VECTOR);
1501         set_exception_intercept(svm, MC_VECTOR);
1502         set_exception_intercept(svm, AC_VECTOR);
1503         set_exception_intercept(svm, DB_VECTOR);
1504         /*
1505          * Guest access to VMware backdoor ports could legitimately
1506          * trigger #GP because of TSS I/O permission bitmap.
1507          * We intercept those #GP and allow access to them anyway
1508          * as VMware does.
1509          */
1510         if (enable_vmware_backdoor)
1511                 set_exception_intercept(svm, GP_VECTOR);
1512
1513         set_intercept(svm, INTERCEPT_INTR);
1514         set_intercept(svm, INTERCEPT_NMI);
1515         set_intercept(svm, INTERCEPT_SMI);
1516         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1517         set_intercept(svm, INTERCEPT_RDPMC);
1518         set_intercept(svm, INTERCEPT_CPUID);
1519         set_intercept(svm, INTERCEPT_INVD);
1520         set_intercept(svm, INTERCEPT_INVLPG);
1521         set_intercept(svm, INTERCEPT_INVLPGA);
1522         set_intercept(svm, INTERCEPT_IOIO_PROT);
1523         set_intercept(svm, INTERCEPT_MSR_PROT);
1524         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1525         set_intercept(svm, INTERCEPT_SHUTDOWN);
1526         set_intercept(svm, INTERCEPT_VMRUN);
1527         set_intercept(svm, INTERCEPT_VMMCALL);
1528         set_intercept(svm, INTERCEPT_VMLOAD);
1529         set_intercept(svm, INTERCEPT_VMSAVE);
1530         set_intercept(svm, INTERCEPT_STGI);
1531         set_intercept(svm, INTERCEPT_CLGI);
1532         set_intercept(svm, INTERCEPT_SKINIT);
1533         set_intercept(svm, INTERCEPT_WBINVD);
1534         set_intercept(svm, INTERCEPT_XSETBV);
1535         set_intercept(svm, INTERCEPT_RSM);
1536
1537         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1538                 set_intercept(svm, INTERCEPT_MONITOR);
1539                 set_intercept(svm, INTERCEPT_MWAIT);
1540         }
1541
1542         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1543                 set_intercept(svm, INTERCEPT_HLT);
1544
1545         control->iopm_base_pa = __sme_set(iopm_base);
1546         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1547         control->int_ctl = V_INTR_MASKING_MASK;
1548
1549         init_seg(&save->es);
1550         init_seg(&save->ss);
1551         init_seg(&save->ds);
1552         init_seg(&save->fs);
1553         init_seg(&save->gs);
1554
1555         save->cs.selector = 0xf000;
1556         save->cs.base = 0xffff0000;
1557         /* Executable/Readable Code Segment */
1558         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1559                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1560         save->cs.limit = 0xffff;
1561
1562         save->gdtr.limit = 0xffff;
1563         save->idtr.limit = 0xffff;
1564
1565         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1566         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1567
1568         svm_set_efer(&svm->vcpu, 0);
1569         save->dr6 = 0xffff0ff0;
1570         kvm_set_rflags(&svm->vcpu, 2);
1571         save->rip = 0x0000fff0;
1572         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1573
1574         /*
1575          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1576          * It also updates the guest-visible cr0 value.
1577          */
1578         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1579         kvm_mmu_reset_context(&svm->vcpu);
1580
1581         save->cr4 = X86_CR4_PAE;
1582         /* rdx = ?? */
1583
1584         if (npt_enabled) {
1585                 /* Setup VMCB for Nested Paging */
1586                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1587                 clr_intercept(svm, INTERCEPT_INVLPG);
1588                 clr_exception_intercept(svm, PF_VECTOR);
1589                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1590                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1591                 save->g_pat = svm->vcpu.arch.pat;
1592                 save->cr3 = 0;
1593                 save->cr4 = 0;
1594         }
1595         svm->asid_generation = 0;
1596
1597         svm->nested.vmcb = 0;
1598         svm->vcpu.arch.hflags = 0;
1599
1600         if (pause_filter_count) {
1601                 control->pause_filter_count = pause_filter_count;
1602                 if (pause_filter_thresh)
1603                         control->pause_filter_thresh = pause_filter_thresh;
1604                 set_intercept(svm, INTERCEPT_PAUSE);
1605         } else {
1606                 clr_intercept(svm, INTERCEPT_PAUSE);
1607         }
1608
1609         if (kvm_vcpu_apicv_active(&svm->vcpu))
1610                 avic_init_vmcb(svm);
1611
1612         /*
1613          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1614          * in VMCB and clear intercepts to avoid #VMEXIT.
1615          */
1616         if (vls) {
1617                 clr_intercept(svm, INTERCEPT_VMLOAD);
1618                 clr_intercept(svm, INTERCEPT_VMSAVE);
1619                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1620         }
1621
1622         if (vgif) {
1623                 clr_intercept(svm, INTERCEPT_STGI);
1624                 clr_intercept(svm, INTERCEPT_CLGI);
1625                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1626         }
1627
1628         if (sev_guest(svm->vcpu.kvm)) {
1629                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1630                 clr_exception_intercept(svm, UD_VECTOR);
1631         }
1632
1633         mark_all_dirty(svm->vmcb);
1634
1635         enable_gif(svm);
1636
1637 }
1638
1639 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1640                                        unsigned int index)
1641 {
1642         u64 *avic_physical_id_table;
1643         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1644
1645         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1646                 return NULL;
1647
1648         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1649
1650         return &avic_physical_id_table[index];
1651 }
1652
1653 /**
1654  * Note:
1655  * AVIC hardware walks the nested page table to check permissions,
1656  * but does not use the SPA address specified in the leaf page
1657  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1658  * field of the VMCB. Therefore, we set up the
1659  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1660  */
1661 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1662 {
1663         struct kvm *kvm = vcpu->kvm;
1664         int ret = 0;
1665
1666         mutex_lock(&kvm->slots_lock);
1667         if (kvm->arch.apic_access_page_done)
1668                 goto out;
1669
1670         ret = __x86_set_memory_region(kvm,
1671                                       APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1672                                       APIC_DEFAULT_PHYS_BASE,
1673                                       PAGE_SIZE);
1674         if (ret)
1675                 goto out;
1676
1677         kvm->arch.apic_access_page_done = true;
1678 out:
1679         mutex_unlock(&kvm->slots_lock);
1680         return ret;
1681 }
1682
1683 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1684 {
1685         int ret;
1686         u64 *entry, new_entry;
1687         int id = vcpu->vcpu_id;
1688         struct vcpu_svm *svm = to_svm(vcpu);
1689
1690         ret = avic_init_access_page(vcpu);
1691         if (ret)
1692                 return ret;
1693
1694         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1695                 return -EINVAL;
1696
1697         if (!svm->vcpu.arch.apic->regs)
1698                 return -EINVAL;
1699
1700         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1701
1702         /* Setting AVIC backing page address in the phy APIC ID table */
1703         entry = avic_get_physical_id_entry(vcpu, id);
1704         if (!entry)
1705                 return -EINVAL;
1706
1707         new_entry = READ_ONCE(*entry);
1708         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1709                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1710                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1711         WRITE_ONCE(*entry, new_entry);
1712
1713         svm->avic_physical_id_cache = entry;
1714
1715         return 0;
1716 }
1717
1718 static void __sev_asid_free(int asid)
1719 {
1720         struct svm_cpu_data *sd;
1721         int cpu, pos;
1722
1723         pos = asid - 1;
1724         clear_bit(pos, sev_asid_bitmap);
1725
1726         for_each_possible_cpu(cpu) {
1727                 sd = per_cpu(svm_data, cpu);
1728                 sd->sev_vmcbs[pos] = NULL;
1729         }
1730 }
1731
1732 static void sev_asid_free(struct kvm *kvm)
1733 {
1734         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1735
1736         __sev_asid_free(sev->asid);
1737 }
1738
1739 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1740 {
1741         struct sev_data_decommission *decommission;
1742         struct sev_data_deactivate *data;
1743
1744         if (!handle)
1745                 return;
1746
1747         data = kzalloc(sizeof(*data), GFP_KERNEL);
1748         if (!data)
1749                 return;
1750
1751         /* deactivate handle */
1752         data->handle = handle;
1753         sev_guest_deactivate(data, NULL);
1754
1755         wbinvd_on_all_cpus();
1756         sev_guest_df_flush(NULL);
1757         kfree(data);
1758
1759         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1760         if (!decommission)
1761                 return;
1762
1763         /* decommission handle */
1764         decommission->handle = handle;
1765         sev_guest_decommission(decommission, NULL);
1766
1767         kfree(decommission);
1768 }
1769
1770 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1771                                     unsigned long ulen, unsigned long *n,
1772                                     int write)
1773 {
1774         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1775         unsigned long npages, npinned, size;
1776         unsigned long locked, lock_limit;
1777         struct page **pages;
1778         unsigned long first, last;
1779
1780         if (ulen == 0 || uaddr + ulen < uaddr)
1781                 return NULL;
1782
1783         /* Calculate number of pages. */
1784         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1785         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1786         npages = (last - first + 1);
1787
1788         locked = sev->pages_locked + npages;
1789         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1790         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1791                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1792                 return NULL;
1793         }
1794
1795         /* Avoid using vmalloc for smaller buffers. */
1796         size = npages * sizeof(struct page *);
1797         if (size > PAGE_SIZE)
1798                 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1799                                   PAGE_KERNEL);
1800         else
1801                 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1802
1803         if (!pages)
1804                 return NULL;
1805
1806         /* Pin the user virtual address. */
1807         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1808         if (npinned != npages) {
1809                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1810                 goto err;
1811         }
1812
1813         *n = npages;
1814         sev->pages_locked = locked;
1815
1816         return pages;
1817
1818 err:
1819         if (npinned > 0)
1820                 release_pages(pages, npinned);
1821
1822         kvfree(pages);
1823         return NULL;
1824 }
1825
1826 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1827                              unsigned long npages)
1828 {
1829         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1830
1831         release_pages(pages, npages);
1832         kvfree(pages);
1833         sev->pages_locked -= npages;
1834 }
1835
1836 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1837 {
1838         uint8_t *page_virtual;
1839         unsigned long i;
1840
1841         if (npages == 0 || pages == NULL)
1842                 return;
1843
1844         for (i = 0; i < npages; i++) {
1845                 page_virtual = kmap_atomic(pages[i]);
1846                 clflush_cache_range(page_virtual, PAGE_SIZE);
1847                 kunmap_atomic(page_virtual);
1848         }
1849 }
1850
1851 static void __unregister_enc_region_locked(struct kvm *kvm,
1852                                            struct enc_region *region)
1853 {
1854         /*
1855          * The guest may change the memory encryption attribute from C=0 -> C=1
1856          * or vice versa for this memory range. Lets make sure caches are
1857          * flushed to ensure that guest data gets written into memory with
1858          * correct C-bit.
1859          */
1860         sev_clflush_pages(region->pages, region->npages);
1861
1862         sev_unpin_memory(kvm, region->pages, region->npages);
1863         list_del(&region->list);
1864         kfree(region);
1865 }
1866
1867 static struct kvm *svm_vm_alloc(void)
1868 {
1869         struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1870                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1871                                             PAGE_KERNEL);
1872         return &kvm_svm->kvm;
1873 }
1874
1875 static void svm_vm_free(struct kvm *kvm)
1876 {
1877         vfree(to_kvm_svm(kvm));
1878 }
1879
1880 static void sev_vm_destroy(struct kvm *kvm)
1881 {
1882         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1883         struct list_head *head = &sev->regions_list;
1884         struct list_head *pos, *q;
1885
1886         if (!sev_guest(kvm))
1887                 return;
1888
1889         mutex_lock(&kvm->lock);
1890
1891         /*
1892          * if userspace was terminated before unregistering the memory regions
1893          * then lets unpin all the registered memory.
1894          */
1895         if (!list_empty(head)) {
1896                 list_for_each_safe(pos, q, head) {
1897                         __unregister_enc_region_locked(kvm,
1898                                 list_entry(pos, struct enc_region, list));
1899                 }
1900         }
1901
1902         mutex_unlock(&kvm->lock);
1903
1904         sev_unbind_asid(kvm, sev->handle);
1905         sev_asid_free(kvm);
1906 }
1907
1908 static void avic_vm_destroy(struct kvm *kvm)
1909 {
1910         unsigned long flags;
1911         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1912
1913         if (!avic)
1914                 return;
1915
1916         if (kvm_svm->avic_logical_id_table_page)
1917                 __free_page(kvm_svm->avic_logical_id_table_page);
1918         if (kvm_svm->avic_physical_id_table_page)
1919                 __free_page(kvm_svm->avic_physical_id_table_page);
1920
1921         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1922         hash_del(&kvm_svm->hnode);
1923         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1924 }
1925
1926 static void svm_vm_destroy(struct kvm *kvm)
1927 {
1928         avic_vm_destroy(kvm);
1929         sev_vm_destroy(kvm);
1930 }
1931
1932 static int avic_vm_init(struct kvm *kvm)
1933 {
1934         unsigned long flags;
1935         int err = -ENOMEM;
1936         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1937         struct kvm_svm *k2;
1938         struct page *p_page;
1939         struct page *l_page;
1940         u32 vm_id;
1941
1942         if (!avic)
1943                 return 0;
1944
1945         /* Allocating physical APIC ID table (4KB) */
1946         p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1947         if (!p_page)
1948                 goto free_avic;
1949
1950         kvm_svm->avic_physical_id_table_page = p_page;
1951         clear_page(page_address(p_page));
1952
1953         /* Allocating logical APIC ID table (4KB) */
1954         l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1955         if (!l_page)
1956                 goto free_avic;
1957
1958         kvm_svm->avic_logical_id_table_page = l_page;
1959         clear_page(page_address(l_page));
1960
1961         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1962  again:
1963         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1964         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1965                 next_vm_id_wrapped = 1;
1966                 goto again;
1967         }
1968         /* Is it still in use? Only possible if wrapped at least once */
1969         if (next_vm_id_wrapped) {
1970                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1971                         if (k2->avic_vm_id == vm_id)
1972                                 goto again;
1973                 }
1974         }
1975         kvm_svm->avic_vm_id = vm_id;
1976         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1977         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1978
1979         return 0;
1980
1981 free_avic:
1982         avic_vm_destroy(kvm);
1983         return err;
1984 }
1985
1986 static inline int
1987 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1988 {
1989         int ret = 0;
1990         unsigned long flags;
1991         struct amd_svm_iommu_ir *ir;
1992         struct vcpu_svm *svm = to_svm(vcpu);
1993
1994         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1995                 return 0;
1996
1997         /*
1998          * Here, we go through the per-vcpu ir_list to update all existing
1999          * interrupt remapping table entry targeting this vcpu.
2000          */
2001         spin_lock_irqsave(&svm->ir_list_lock, flags);
2002
2003         if (list_empty(&svm->ir_list))
2004                 goto out;
2005
2006         list_for_each_entry(ir, &svm->ir_list, node) {
2007                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2008                 if (ret)
2009                         break;
2010         }
2011 out:
2012         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2013         return ret;
2014 }
2015
2016 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2017 {
2018         u64 entry;
2019         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2020         int h_physical_id = kvm_cpu_get_apicid(cpu);
2021         struct vcpu_svm *svm = to_svm(vcpu);
2022
2023         if (!kvm_vcpu_apicv_active(vcpu))
2024                 return;
2025
2026         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2027                 return;
2028
2029         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2030         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2031
2032         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2033         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2034
2035         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2036         if (svm->avic_is_running)
2037                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2038
2039         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2040         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2041                                         svm->avic_is_running);
2042 }
2043
2044 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2045 {
2046         u64 entry;
2047         struct vcpu_svm *svm = to_svm(vcpu);
2048
2049         if (!kvm_vcpu_apicv_active(vcpu))
2050                 return;
2051
2052         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2053         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2054                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2055
2056         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2057         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2058 }
2059
2060 /**
2061  * This function is called during VCPU halt/unhalt.
2062  */
2063 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2064 {
2065         struct vcpu_svm *svm = to_svm(vcpu);
2066
2067         svm->avic_is_running = is_run;
2068         if (is_run)
2069                 avic_vcpu_load(vcpu, vcpu->cpu);
2070         else
2071                 avic_vcpu_put(vcpu);
2072 }
2073
2074 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2075 {
2076         struct vcpu_svm *svm = to_svm(vcpu);
2077         u32 dummy;
2078         u32 eax = 1;
2079
2080         vcpu->arch.microcode_version = 0x01000065;
2081         svm->spec_ctrl = 0;
2082         svm->virt_spec_ctrl = 0;
2083
2084         if (!init_event) {
2085                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2086                                            MSR_IA32_APICBASE_ENABLE;
2087                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2088                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2089         }
2090         init_vmcb(svm);
2091
2092         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2093         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2094
2095         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2096                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2097 }
2098
2099 static int avic_init_vcpu(struct vcpu_svm *svm)
2100 {
2101         int ret;
2102
2103         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2104                 return 0;
2105
2106         ret = avic_init_backing_page(&svm->vcpu);
2107         if (ret)
2108                 return ret;
2109
2110         INIT_LIST_HEAD(&svm->ir_list);
2111         spin_lock_init(&svm->ir_list_lock);
2112         svm->dfr_reg = APIC_DFR_FLAT;
2113
2114         return ret;
2115 }
2116
2117 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2118 {
2119         struct vcpu_svm *svm;
2120         struct page *page;
2121         struct page *msrpm_pages;
2122         struct page *hsave_page;
2123         struct page *nested_msrpm_pages;
2124         int err;
2125
2126         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2127         if (!svm) {
2128                 err = -ENOMEM;
2129                 goto out;
2130         }
2131
2132         svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2133                                                      GFP_KERNEL_ACCOUNT);
2134         if (!svm->vcpu.arch.guest_fpu) {
2135                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2136                 err = -ENOMEM;
2137                 goto free_partial_svm;
2138         }
2139
2140         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2141         if (err)
2142                 goto free_svm;
2143
2144         err = -ENOMEM;
2145         page = alloc_page(GFP_KERNEL_ACCOUNT);
2146         if (!page)
2147                 goto uninit;
2148
2149         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2150         if (!msrpm_pages)
2151                 goto free_page1;
2152
2153         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2154         if (!nested_msrpm_pages)
2155                 goto free_page2;
2156
2157         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2158         if (!hsave_page)
2159                 goto free_page3;
2160
2161         err = avic_init_vcpu(svm);
2162         if (err)
2163                 goto free_page4;
2164
2165         /* We initialize this flag to true to make sure that the is_running
2166          * bit would be set the first time the vcpu is loaded.
2167          */
2168         svm->avic_is_running = true;
2169
2170         svm->nested.hsave = page_address(hsave_page);
2171
2172         svm->msrpm = page_address(msrpm_pages);
2173         svm_vcpu_init_msrpm(svm->msrpm);
2174
2175         svm->nested.msrpm = page_address(nested_msrpm_pages);
2176         svm_vcpu_init_msrpm(svm->nested.msrpm);
2177
2178         svm->vmcb = page_address(page);
2179         clear_page(svm->vmcb);
2180         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2181         svm->asid_generation = 0;
2182         init_vmcb(svm);
2183
2184         svm_init_osvw(&svm->vcpu);
2185
2186         return &svm->vcpu;
2187
2188 free_page4:
2189         __free_page(hsave_page);
2190 free_page3:
2191         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2192 free_page2:
2193         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2194 free_page1:
2195         __free_page(page);
2196 uninit:
2197         kvm_vcpu_uninit(&svm->vcpu);
2198 free_svm:
2199         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2200 free_partial_svm:
2201         kmem_cache_free(kvm_vcpu_cache, svm);
2202 out:
2203         return ERR_PTR(err);
2204 }
2205
2206 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2207 {
2208         int i;
2209
2210         for_each_online_cpu(i)
2211                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2212 }
2213
2214 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2215 {
2216         struct vcpu_svm *svm = to_svm(vcpu);
2217
2218         /*
2219          * The vmcb page can be recycled, causing a false negative in
2220          * svm_vcpu_load(). So, ensure that no logical CPU has this
2221          * vmcb page recorded as its current vmcb.
2222          */
2223         svm_clear_current_vmcb(svm->vmcb);
2224
2225         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2226         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2227         __free_page(virt_to_page(svm->nested.hsave));
2228         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2229         kvm_vcpu_uninit(vcpu);
2230         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2231         kmem_cache_free(kvm_vcpu_cache, svm);
2232 }
2233
2234 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2235 {
2236         struct vcpu_svm *svm = to_svm(vcpu);
2237         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2238         int i;
2239
2240         if (unlikely(cpu != vcpu->cpu)) {
2241                 svm->asid_generation = 0;
2242                 mark_all_dirty(svm->vmcb);
2243         }
2244
2245 #ifdef CONFIG_X86_64
2246         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2247 #endif
2248         savesegment(fs, svm->host.fs);
2249         savesegment(gs, svm->host.gs);
2250         svm->host.ldt = kvm_read_ldt();
2251
2252         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2253                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2254
2255         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2256                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2257                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2258                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2259                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2260                 }
2261         }
2262         /* This assumes that the kernel never uses MSR_TSC_AUX */
2263         if (static_cpu_has(X86_FEATURE_RDTSCP))
2264                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2265
2266         if (sd->current_vmcb != svm->vmcb) {
2267                 sd->current_vmcb = svm->vmcb;
2268                 indirect_branch_prediction_barrier();
2269         }
2270         avic_vcpu_load(vcpu, cpu);
2271 }
2272
2273 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2274 {
2275         struct vcpu_svm *svm = to_svm(vcpu);
2276         int i;
2277
2278         avic_vcpu_put(vcpu);
2279
2280         ++vcpu->stat.host_state_reload;
2281         kvm_load_ldt(svm->host.ldt);
2282 #ifdef CONFIG_X86_64
2283         loadsegment(fs, svm->host.fs);
2284         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2285         load_gs_index(svm->host.gs);
2286 #else
2287 #ifdef CONFIG_X86_32_LAZY_GS
2288         loadsegment(gs, svm->host.gs);
2289 #endif
2290 #endif
2291         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2292                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2293 }
2294
2295 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2296 {
2297         avic_set_running(vcpu, false);
2298 }
2299
2300 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2301 {
2302         avic_set_running(vcpu, true);
2303 }
2304
2305 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2306 {
2307         struct vcpu_svm *svm = to_svm(vcpu);
2308         unsigned long rflags = svm->vmcb->save.rflags;
2309
2310         if (svm->nmi_singlestep) {
2311                 /* Hide our flags if they were not set by the guest */
2312                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2313                         rflags &= ~X86_EFLAGS_TF;
2314                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2315                         rflags &= ~X86_EFLAGS_RF;
2316         }
2317         return rflags;
2318 }
2319
2320 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2321 {
2322         if (to_svm(vcpu)->nmi_singlestep)
2323                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2324
2325        /*
2326         * Any change of EFLAGS.VM is accompanied by a reload of SS
2327         * (caused by either a task switch or an inter-privilege IRET),
2328         * so we do not need to update the CPL here.
2329         */
2330         to_svm(vcpu)->vmcb->save.rflags = rflags;
2331 }
2332
2333 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2334 {
2335         switch (reg) {
2336         case VCPU_EXREG_PDPTR:
2337                 BUG_ON(!npt_enabled);
2338                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2339                 break;
2340         default:
2341                 BUG();
2342         }
2343 }
2344
2345 static void svm_set_vintr(struct vcpu_svm *svm)
2346 {
2347         set_intercept(svm, INTERCEPT_VINTR);
2348 }
2349
2350 static void svm_clear_vintr(struct vcpu_svm *svm)
2351 {
2352         clr_intercept(svm, INTERCEPT_VINTR);
2353 }
2354
2355 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2356 {
2357         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2358
2359         switch (seg) {
2360         case VCPU_SREG_CS: return &save->cs;
2361         case VCPU_SREG_DS: return &save->ds;
2362         case VCPU_SREG_ES: return &save->es;
2363         case VCPU_SREG_FS: return &save->fs;
2364         case VCPU_SREG_GS: return &save->gs;
2365         case VCPU_SREG_SS: return &save->ss;
2366         case VCPU_SREG_TR: return &save->tr;
2367         case VCPU_SREG_LDTR: return &save->ldtr;
2368         }
2369         BUG();
2370         return NULL;
2371 }
2372
2373 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2374 {
2375         struct vmcb_seg *s = svm_seg(vcpu, seg);
2376
2377         return s->base;
2378 }
2379
2380 static void svm_get_segment(struct kvm_vcpu *vcpu,
2381                             struct kvm_segment *var, int seg)
2382 {
2383         struct vmcb_seg *s = svm_seg(vcpu, seg);
2384
2385         var->base = s->base;
2386         var->limit = s->limit;
2387         var->selector = s->selector;
2388         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2389         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2390         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2391         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2392         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2393         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2394         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2395
2396         /*
2397          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2398          * However, the SVM spec states that the G bit is not observed by the
2399          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2400          * So let's synthesize a legal G bit for all segments, this helps
2401          * running KVM nested. It also helps cross-vendor migration, because
2402          * Intel's vmentry has a check on the 'G' bit.
2403          */
2404         var->g = s->limit > 0xfffff;
2405
2406         /*
2407          * AMD's VMCB does not have an explicit unusable field, so emulate it
2408          * for cross vendor migration purposes by "not present"
2409          */
2410         var->unusable = !var->present;
2411
2412         switch (seg) {
2413         case VCPU_SREG_TR:
2414                 /*
2415                  * Work around a bug where the busy flag in the tr selector
2416                  * isn't exposed
2417                  */
2418                 var->type |= 0x2;
2419                 break;
2420         case VCPU_SREG_DS:
2421         case VCPU_SREG_ES:
2422         case VCPU_SREG_FS:
2423         case VCPU_SREG_GS:
2424                 /*
2425                  * The accessed bit must always be set in the segment
2426                  * descriptor cache, although it can be cleared in the
2427                  * descriptor, the cached bit always remains at 1. Since
2428                  * Intel has a check on this, set it here to support
2429                  * cross-vendor migration.
2430                  */
2431                 if (!var->unusable)
2432                         var->type |= 0x1;
2433                 break;
2434         case VCPU_SREG_SS:
2435                 /*
2436                  * On AMD CPUs sometimes the DB bit in the segment
2437                  * descriptor is left as 1, although the whole segment has
2438                  * been made unusable. Clear it here to pass an Intel VMX
2439                  * entry check when cross vendor migrating.
2440                  */
2441                 if (var->unusable)
2442                         var->db = 0;
2443                 /* This is symmetric with svm_set_segment() */
2444                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2445                 break;
2446         }
2447 }
2448
2449 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2450 {
2451         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2452
2453         return save->cpl;
2454 }
2455
2456 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2457 {
2458         struct vcpu_svm *svm = to_svm(vcpu);
2459
2460         dt->size = svm->vmcb->save.idtr.limit;
2461         dt->address = svm->vmcb->save.idtr.base;
2462 }
2463
2464 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2465 {
2466         struct vcpu_svm *svm = to_svm(vcpu);
2467
2468         svm->vmcb->save.idtr.limit = dt->size;
2469         svm->vmcb->save.idtr.base = dt->address ;
2470         mark_dirty(svm->vmcb, VMCB_DT);
2471 }
2472
2473 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2474 {
2475         struct vcpu_svm *svm = to_svm(vcpu);
2476
2477         dt->size = svm->vmcb->save.gdtr.limit;
2478         dt->address = svm->vmcb->save.gdtr.base;
2479 }
2480
2481 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2482 {
2483         struct vcpu_svm *svm = to_svm(vcpu);
2484
2485         svm->vmcb->save.gdtr.limit = dt->size;
2486         svm->vmcb->save.gdtr.base = dt->address ;
2487         mark_dirty(svm->vmcb, VMCB_DT);
2488 }
2489
2490 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2491 {
2492 }
2493
2494 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2495 {
2496 }
2497
2498 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2499 {
2500 }
2501
2502 static void update_cr0_intercept(struct vcpu_svm *svm)
2503 {
2504         ulong gcr0 = svm->vcpu.arch.cr0;
2505         u64 *hcr0 = &svm->vmcb->save.cr0;
2506
2507         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2508                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2509
2510         mark_dirty(svm->vmcb, VMCB_CR);
2511
2512         if (gcr0 == *hcr0) {
2513                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2514                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2515         } else {
2516                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2517                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2518         }
2519 }
2520
2521 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2522 {
2523         struct vcpu_svm *svm = to_svm(vcpu);
2524
2525 #ifdef CONFIG_X86_64
2526         if (vcpu->arch.efer & EFER_LME) {
2527                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2528                         vcpu->arch.efer |= EFER_LMA;
2529                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2530                 }
2531
2532                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2533                         vcpu->arch.efer &= ~EFER_LMA;
2534                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2535                 }
2536         }
2537 #endif
2538         vcpu->arch.cr0 = cr0;
2539
2540         if (!npt_enabled)
2541                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2542
2543         /*
2544          * re-enable caching here because the QEMU bios
2545          * does not do it - this results in some delay at
2546          * reboot
2547          */
2548         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2549                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2550         svm->vmcb->save.cr0 = cr0;
2551         mark_dirty(svm->vmcb, VMCB_CR);
2552         update_cr0_intercept(svm);
2553 }
2554
2555 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2556 {
2557         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2558         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2559
2560         if (cr4 & X86_CR4_VMXE)
2561                 return 1;
2562
2563         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2564                 svm_flush_tlb(vcpu, true);
2565
2566         vcpu->arch.cr4 = cr4;
2567         if (!npt_enabled)
2568                 cr4 |= X86_CR4_PAE;
2569         cr4 |= host_cr4_mce;
2570         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2571         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2572         return 0;
2573 }
2574
2575 static void svm_set_segment(struct kvm_vcpu *vcpu,
2576                             struct kvm_segment *var, int seg)
2577 {
2578         struct vcpu_svm *svm = to_svm(vcpu);
2579         struct vmcb_seg *s = svm_seg(vcpu, seg);
2580
2581         s->base = var->base;
2582         s->limit = var->limit;
2583         s->selector = var->selector;
2584         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2585         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2586         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2587         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2588         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2589         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2590         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2591         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2592
2593         /*
2594          * This is always accurate, except if SYSRET returned to a segment
2595          * with SS.DPL != 3.  Intel does not have this quirk, and always
2596          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2597          * would entail passing the CPL to userspace and back.
2598          */
2599         if (seg == VCPU_SREG_SS)
2600                 /* This is symmetric with svm_get_segment() */
2601                 svm->vmcb->save.cpl = (var->dpl & 3);
2602
2603         mark_dirty(svm->vmcb, VMCB_SEG);
2604 }
2605
2606 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2607 {
2608         struct vcpu_svm *svm = to_svm(vcpu);
2609
2610         clr_exception_intercept(svm, BP_VECTOR);
2611
2612         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2613                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2614                         set_exception_intercept(svm, BP_VECTOR);
2615         } else
2616                 vcpu->guest_debug = 0;
2617 }
2618
2619 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2620 {
2621         if (sd->next_asid > sd->max_asid) {
2622                 ++sd->asid_generation;
2623                 sd->next_asid = sd->min_asid;
2624                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2625         }
2626
2627         svm->asid_generation = sd->asid_generation;
2628         svm->vmcb->control.asid = sd->next_asid++;
2629
2630         mark_dirty(svm->vmcb, VMCB_ASID);
2631 }
2632
2633 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2634 {
2635         return to_svm(vcpu)->vmcb->save.dr6;
2636 }
2637
2638 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2639 {
2640         struct vcpu_svm *svm = to_svm(vcpu);
2641
2642         svm->vmcb->save.dr6 = value;
2643         mark_dirty(svm->vmcb, VMCB_DR);
2644 }
2645
2646 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2647 {
2648         struct vcpu_svm *svm = to_svm(vcpu);
2649
2650         get_debugreg(vcpu->arch.db[0], 0);
2651         get_debugreg(vcpu->arch.db[1], 1);
2652         get_debugreg(vcpu->arch.db[2], 2);
2653         get_debugreg(vcpu->arch.db[3], 3);
2654         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2655         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2656
2657         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2658         set_dr_intercepts(svm);
2659 }
2660
2661 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2662 {
2663         struct vcpu_svm *svm = to_svm(vcpu);
2664
2665         svm->vmcb->save.dr7 = value;
2666         mark_dirty(svm->vmcb, VMCB_DR);
2667 }
2668
2669 static int pf_interception(struct vcpu_svm *svm)
2670 {
2671         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2672         u64 error_code = svm->vmcb->control.exit_info_1;
2673
2674         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2675                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2676                         svm->vmcb->control.insn_bytes : NULL,
2677                         svm->vmcb->control.insn_len);
2678 }
2679
2680 static int npf_interception(struct vcpu_svm *svm)
2681 {
2682         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2683         u64 error_code = svm->vmcb->control.exit_info_1;
2684
2685         trace_kvm_page_fault(fault_address, error_code);
2686         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2687                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2688                         svm->vmcb->control.insn_bytes : NULL,
2689                         svm->vmcb->control.insn_len);
2690 }
2691
2692 static int db_interception(struct vcpu_svm *svm)
2693 {
2694         struct kvm_run *kvm_run = svm->vcpu.run;
2695
2696         if (!(svm->vcpu.guest_debug &
2697               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2698                 !svm->nmi_singlestep) {
2699                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2700                 return 1;
2701         }
2702
2703         if (svm->nmi_singlestep) {
2704                 disable_nmi_singlestep(svm);
2705         }
2706
2707         if (svm->vcpu.guest_debug &
2708             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2709                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2710                 kvm_run->debug.arch.pc =
2711                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2712                 kvm_run->debug.arch.exception = DB_VECTOR;
2713                 return 0;
2714         }
2715
2716         return 1;
2717 }
2718
2719 static int bp_interception(struct vcpu_svm *svm)
2720 {
2721         struct kvm_run *kvm_run = svm->vcpu.run;
2722
2723         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2724         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2725         kvm_run->debug.arch.exception = BP_VECTOR;
2726         return 0;
2727 }
2728
2729 static int ud_interception(struct vcpu_svm *svm)
2730 {
2731         return handle_ud(&svm->vcpu);
2732 }
2733
2734 static int ac_interception(struct vcpu_svm *svm)
2735 {
2736         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2737         return 1;
2738 }
2739
2740 static int gp_interception(struct vcpu_svm *svm)
2741 {
2742         struct kvm_vcpu *vcpu = &svm->vcpu;
2743         u32 error_code = svm->vmcb->control.exit_info_1;
2744         int er;
2745
2746         WARN_ON_ONCE(!enable_vmware_backdoor);
2747
2748         er = kvm_emulate_instruction(vcpu,
2749                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2750         if (er == EMULATE_USER_EXIT)
2751                 return 0;
2752         else if (er != EMULATE_DONE)
2753                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2754         return 1;
2755 }
2756
2757 static bool is_erratum_383(void)
2758 {
2759         int err, i;
2760         u64 value;
2761
2762         if (!erratum_383_found)
2763                 return false;
2764
2765         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2766         if (err)
2767                 return false;
2768
2769         /* Bit 62 may or may not be set for this mce */
2770         value &= ~(1ULL << 62);
2771
2772         if (value != 0xb600000000010015ULL)
2773                 return false;
2774
2775         /* Clear MCi_STATUS registers */
2776         for (i = 0; i < 6; ++i)
2777                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2778
2779         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2780         if (!err) {
2781                 u32 low, high;
2782
2783                 value &= ~(1ULL << 2);
2784                 low    = lower_32_bits(value);
2785                 high   = upper_32_bits(value);
2786
2787                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2788         }
2789
2790         /* Flush tlb to evict multi-match entries */
2791         __flush_tlb_all();
2792
2793         return true;
2794 }
2795
2796 static void svm_handle_mce(struct vcpu_svm *svm)
2797 {
2798         if (is_erratum_383()) {
2799                 /*
2800                  * Erratum 383 triggered. Guest state is corrupt so kill the
2801                  * guest.
2802                  */
2803                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2804
2805                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2806
2807                 return;
2808         }
2809
2810         /*
2811          * On an #MC intercept the MCE handler is not called automatically in
2812          * the host. So do it by hand here.
2813          */
2814         asm volatile (
2815                 "int $0x12\n");
2816         /* not sure if we ever come back to this point */
2817
2818         return;
2819 }
2820
2821 static int mc_interception(struct vcpu_svm *svm)
2822 {
2823         return 1;
2824 }
2825
2826 static int shutdown_interception(struct vcpu_svm *svm)
2827 {
2828         struct kvm_run *kvm_run = svm->vcpu.run;
2829
2830         /*
2831          * VMCB is undefined after a SHUTDOWN intercept
2832          * so reinitialize it.
2833          */
2834         clear_page(svm->vmcb);
2835         init_vmcb(svm);
2836
2837         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2838         return 0;
2839 }
2840
2841 static int io_interception(struct vcpu_svm *svm)
2842 {
2843         struct kvm_vcpu *vcpu = &svm->vcpu;
2844         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2845         int size, in, string;
2846         unsigned port;
2847
2848         ++svm->vcpu.stat.io_exits;
2849         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2850         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2851         if (string)
2852                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2853
2854         port = io_info >> 16;
2855         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2856         svm->next_rip = svm->vmcb->control.exit_info_2;
2857
2858         return kvm_fast_pio(&svm->vcpu, size, port, in);
2859 }
2860
2861 static int nmi_interception(struct vcpu_svm *svm)
2862 {
2863         return 1;
2864 }
2865
2866 static int intr_interception(struct vcpu_svm *svm)
2867 {
2868         ++svm->vcpu.stat.irq_exits;
2869         return 1;
2870 }
2871
2872 static int nop_on_interception(struct vcpu_svm *svm)
2873 {
2874         return 1;
2875 }
2876
2877 static int halt_interception(struct vcpu_svm *svm)
2878 {
2879         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2880         return kvm_emulate_halt(&svm->vcpu);
2881 }
2882
2883 static int vmmcall_interception(struct vcpu_svm *svm)
2884 {
2885         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2886         return kvm_emulate_hypercall(&svm->vcpu);
2887 }
2888
2889 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2890 {
2891         struct vcpu_svm *svm = to_svm(vcpu);
2892
2893         return svm->nested.nested_cr3;
2894 }
2895
2896 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2897 {
2898         struct vcpu_svm *svm = to_svm(vcpu);
2899         u64 cr3 = svm->nested.nested_cr3;
2900         u64 pdpte;
2901         int ret;
2902
2903         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2904                                        offset_in_page(cr3) + index * 8, 8);
2905         if (ret)
2906                 return 0;
2907         return pdpte;
2908 }
2909
2910 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2911                                    unsigned long root)
2912 {
2913         struct vcpu_svm *svm = to_svm(vcpu);
2914
2915         svm->vmcb->control.nested_cr3 = __sme_set(root);
2916         mark_dirty(svm->vmcb, VMCB_NPT);
2917 }
2918
2919 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2920                                        struct x86_exception *fault)
2921 {
2922         struct vcpu_svm *svm = to_svm(vcpu);
2923
2924         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2925                 /*
2926                  * TODO: track the cause of the nested page fault, and
2927                  * correctly fill in the high bits of exit_info_1.
2928                  */
2929                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2930                 svm->vmcb->control.exit_code_hi = 0;
2931                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2932                 svm->vmcb->control.exit_info_2 = fault->address;
2933         }
2934
2935         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2936         svm->vmcb->control.exit_info_1 |= fault->error_code;
2937
2938         /*
2939          * The present bit is always zero for page structure faults on real
2940          * hardware.
2941          */
2942         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2943                 svm->vmcb->control.exit_info_1 &= ~1;
2944
2945         nested_svm_vmexit(svm);
2946 }
2947
2948 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2949 {
2950         WARN_ON(mmu_is_nested(vcpu));
2951
2952         vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2953         kvm_init_shadow_mmu(vcpu);
2954         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2955         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2956         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2957         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2958         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2959         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2960         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2961 }
2962
2963 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2964 {
2965         vcpu->arch.mmu = &vcpu->arch.root_mmu;
2966         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2967 }
2968
2969 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2970 {
2971         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2972             !is_paging(&svm->vcpu)) {
2973                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2974                 return 1;
2975         }
2976
2977         if (svm->vmcb->save.cpl) {
2978                 kvm_inject_gp(&svm->vcpu, 0);
2979                 return 1;
2980         }
2981
2982         return 0;
2983 }
2984
2985 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2986                                       bool has_error_code, u32 error_code)
2987 {
2988         int vmexit;
2989
2990         if (!is_guest_mode(&svm->vcpu))
2991                 return 0;
2992
2993         vmexit = nested_svm_intercept(svm);
2994         if (vmexit != NESTED_EXIT_DONE)
2995                 return 0;
2996
2997         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2998         svm->vmcb->control.exit_code_hi = 0;
2999         svm->vmcb->control.exit_info_1 = error_code;
3000
3001         /*
3002          * EXITINFO2 is undefined for all exception intercepts other
3003          * than #PF.
3004          */
3005         if (svm->vcpu.arch.exception.nested_apf)
3006                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3007         else if (svm->vcpu.arch.exception.has_payload)
3008                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3009         else
3010                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3011
3012         svm->nested.exit_required = true;
3013         return vmexit;
3014 }
3015
3016 /* This function returns true if it is save to enable the irq window */
3017 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3018 {
3019         if (!is_guest_mode(&svm->vcpu))
3020                 return true;
3021
3022         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3023                 return true;
3024
3025         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3026                 return false;
3027
3028         /*
3029          * if vmexit was already requested (by intercepted exception
3030          * for instance) do not overwrite it with "external interrupt"
3031          * vmexit.
3032          */
3033         if (svm->nested.exit_required)
3034                 return false;
3035
3036         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3037         svm->vmcb->control.exit_info_1 = 0;
3038         svm->vmcb->control.exit_info_2 = 0;
3039
3040         if (svm->nested.intercept & 1ULL) {
3041                 /*
3042                  * The #vmexit can't be emulated here directly because this
3043                  * code path runs with irqs and preemption disabled. A
3044                  * #vmexit emulation might sleep. Only signal request for
3045                  * the #vmexit here.
3046                  */
3047                 svm->nested.exit_required = true;
3048                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3049                 return false;
3050         }
3051
3052         return true;
3053 }
3054
3055 /* This function returns true if it is save to enable the nmi window */
3056 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3057 {
3058         if (!is_guest_mode(&svm->vcpu))
3059                 return true;
3060
3061         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3062                 return true;
3063
3064         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3065         svm->nested.exit_required = true;
3066
3067         return false;
3068 }
3069
3070 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3071 {
3072         struct page *page;
3073
3074         might_sleep();
3075
3076         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3077         if (is_error_page(page))
3078                 goto error;
3079
3080         *_page = page;
3081
3082         return kmap(page);
3083
3084 error:
3085         kvm_inject_gp(&svm->vcpu, 0);
3086
3087         return NULL;
3088 }
3089
3090 static void nested_svm_unmap(struct page *page)
3091 {
3092         kunmap(page);
3093         kvm_release_page_dirty(page);
3094 }
3095
3096 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3097 {
3098         unsigned port, size, iopm_len;
3099         u16 val, mask;
3100         u8 start_bit;
3101         u64 gpa;
3102
3103         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3104                 return NESTED_EXIT_HOST;
3105
3106         port = svm->vmcb->control.exit_info_1 >> 16;
3107         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3108                 SVM_IOIO_SIZE_SHIFT;
3109         gpa  = svm->nested.vmcb_iopm + (port / 8);
3110         start_bit = port % 8;
3111         iopm_len = (start_bit + size > 8) ? 2 : 1;
3112         mask = (0xf >> (4 - size)) << start_bit;
3113         val = 0;
3114
3115         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3116                 return NESTED_EXIT_DONE;
3117
3118         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3119 }
3120
3121 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3122 {
3123         u32 offset, msr, value;
3124         int write, mask;
3125
3126         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3127                 return NESTED_EXIT_HOST;
3128
3129         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3130         offset = svm_msrpm_offset(msr);
3131         write  = svm->vmcb->control.exit_info_1 & 1;
3132         mask   = 1 << ((2 * (msr & 0xf)) + write);
3133
3134         if (offset == MSR_INVALID)
3135                 return NESTED_EXIT_DONE;
3136
3137         /* Offset is in 32 bit units but need in 8 bit units */
3138         offset *= 4;
3139
3140         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3141                 return NESTED_EXIT_DONE;
3142
3143         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3144 }
3145
3146 /* DB exceptions for our internal use must not cause vmexit */
3147 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3148 {
3149         unsigned long dr6;
3150
3151         /* if we're not singlestepping, it's not ours */
3152         if (!svm->nmi_singlestep)
3153                 return NESTED_EXIT_DONE;
3154
3155         /* if it's not a singlestep exception, it's not ours */
3156         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3157                 return NESTED_EXIT_DONE;
3158         if (!(dr6 & DR6_BS))
3159                 return NESTED_EXIT_DONE;
3160
3161         /* if the guest is singlestepping, it should get the vmexit */
3162         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3163                 disable_nmi_singlestep(svm);
3164                 return NESTED_EXIT_DONE;
3165         }
3166
3167         /* it's ours, the nested hypervisor must not see this one */
3168         return NESTED_EXIT_HOST;
3169 }
3170
3171 static int nested_svm_exit_special(struct vcpu_svm *svm)
3172 {
3173         u32 exit_code = svm->vmcb->control.exit_code;
3174
3175         switch (exit_code) {
3176         case SVM_EXIT_INTR:
3177         case SVM_EXIT_NMI:
3178         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3179                 return NESTED_EXIT_HOST;
3180         case SVM_EXIT_NPF:
3181                 /* For now we are always handling NPFs when using them */
3182                 if (npt_enabled)
3183                         return NESTED_EXIT_HOST;
3184                 break;
3185         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3186                 /* When we're shadowing, trap PFs, but not async PF */
3187                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3188                         return NESTED_EXIT_HOST;
3189                 break;
3190         default:
3191                 break;
3192         }
3193
3194         return NESTED_EXIT_CONTINUE;
3195 }
3196
3197 /*
3198  * If this function returns true, this #vmexit was already handled
3199  */
3200 static int nested_svm_intercept(struct vcpu_svm *svm)
3201 {
3202         u32 exit_code = svm->vmcb->control.exit_code;
3203         int vmexit = NESTED_EXIT_HOST;
3204
3205         switch (exit_code) {
3206         case SVM_EXIT_MSR:
3207                 vmexit = nested_svm_exit_handled_msr(svm);
3208                 break;
3209         case SVM_EXIT_IOIO:
3210                 vmexit = nested_svm_intercept_ioio(svm);
3211                 break;
3212         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3213                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3214                 if (svm->nested.intercept_cr & bit)
3215                         vmexit = NESTED_EXIT_DONE;
3216                 break;
3217         }
3218         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3219                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3220                 if (svm->nested.intercept_dr & bit)
3221                         vmexit = NESTED_EXIT_DONE;
3222                 break;
3223         }
3224         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3225                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3226                 if (svm->nested.intercept_exceptions & excp_bits) {
3227                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3228                                 vmexit = nested_svm_intercept_db(svm);
3229                         else
3230                                 vmexit = NESTED_EXIT_DONE;
3231                 }
3232                 /* async page fault always cause vmexit */
3233                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3234                          svm->vcpu.arch.exception.nested_apf != 0)
3235                         vmexit = NESTED_EXIT_DONE;
3236                 break;
3237         }
3238         case SVM_EXIT_ERR: {
3239                 vmexit = NESTED_EXIT_DONE;
3240                 break;
3241         }
3242         default: {
3243                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3244                 if (svm->nested.intercept & exit_bits)
3245                         vmexit = NESTED_EXIT_DONE;
3246         }
3247         }
3248
3249         return vmexit;
3250 }
3251
3252 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3253 {
3254         int vmexit;
3255
3256         vmexit = nested_svm_intercept(svm);
3257
3258         if (vmexit == NESTED_EXIT_DONE)
3259                 nested_svm_vmexit(svm);
3260
3261         return vmexit;
3262 }
3263
3264 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3265 {
3266         struct vmcb_control_area *dst  = &dst_vmcb->control;
3267         struct vmcb_control_area *from = &from_vmcb->control;
3268
3269         dst->intercept_cr         = from->intercept_cr;
3270         dst->intercept_dr         = from->intercept_dr;
3271         dst->intercept_exceptions = from->intercept_exceptions;
3272         dst->intercept            = from->intercept;
3273         dst->iopm_base_pa         = from->iopm_base_pa;
3274         dst->msrpm_base_pa        = from->msrpm_base_pa;
3275         dst->tsc_offset           = from->tsc_offset;
3276         dst->asid                 = from->asid;
3277         dst->tlb_ctl              = from->tlb_ctl;
3278         dst->int_ctl              = from->int_ctl;
3279         dst->int_vector           = from->int_vector;
3280         dst->int_state            = from->int_state;
3281         dst->exit_code            = from->exit_code;
3282         dst->exit_code_hi         = from->exit_code_hi;
3283         dst->exit_info_1          = from->exit_info_1;
3284         dst->exit_info_2          = from->exit_info_2;
3285         dst->exit_int_info        = from->exit_int_info;
3286         dst->exit_int_info_err    = from->exit_int_info_err;
3287         dst->nested_ctl           = from->nested_ctl;
3288         dst->event_inj            = from->event_inj;
3289         dst->event_inj_err        = from->event_inj_err;
3290         dst->nested_cr3           = from->nested_cr3;
3291         dst->virt_ext              = from->virt_ext;
3292         dst->pause_filter_count   = from->pause_filter_count;
3293         dst->pause_filter_thresh  = from->pause_filter_thresh;
3294 }
3295
3296 static int nested_svm_vmexit(struct vcpu_svm *svm)
3297 {
3298         struct vmcb *nested_vmcb;
3299         struct vmcb *hsave = svm->nested.hsave;
3300         struct vmcb *vmcb = svm->vmcb;
3301         struct page *page;
3302
3303         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3304                                        vmcb->control.exit_info_1,
3305                                        vmcb->control.exit_info_2,
3306                                        vmcb->control.exit_int_info,
3307                                        vmcb->control.exit_int_info_err,
3308                                        KVM_ISA_SVM);
3309
3310         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3311         if (!nested_vmcb)
3312                 return 1;
3313
3314         /* Exit Guest-Mode */
3315         leave_guest_mode(&svm->vcpu);
3316         svm->nested.vmcb = 0;
3317
3318         /* Give the current vmcb to the guest */
3319         disable_gif(svm);
3320
3321         nested_vmcb->save.es     = vmcb->save.es;
3322         nested_vmcb->save.cs     = vmcb->save.cs;
3323         nested_vmcb->save.ss     = vmcb->save.ss;
3324         nested_vmcb->save.ds     = vmcb->save.ds;
3325         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3326         nested_vmcb->save.idtr   = vmcb->save.idtr;
3327         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3328         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3329         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3330         nested_vmcb->save.cr2    = vmcb->save.cr2;
3331         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3332         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3333         nested_vmcb->save.rip    = vmcb->save.rip;
3334         nested_vmcb->save.rsp    = vmcb->save.rsp;
3335         nested_vmcb->save.rax    = vmcb->save.rax;
3336         nested_vmcb->save.dr7    = vmcb->save.dr7;
3337         nested_vmcb->save.dr6    = vmcb->save.dr6;
3338         nested_vmcb->save.cpl    = vmcb->save.cpl;
3339
3340         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3341         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3342         nested_vmcb->control.int_state         = vmcb->control.int_state;
3343         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3344         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3345         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3346         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3347         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3348         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3349
3350         if (svm->nrips_enabled)
3351                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3352
3353         /*
3354          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3355          * to make sure that we do not lose injected events. So check event_inj
3356          * here and copy it to exit_int_info if it is valid.
3357          * Exit_int_info and event_inj can't be both valid because the case
3358          * below only happens on a VMRUN instruction intercept which has
3359          * no valid exit_int_info set.
3360          */
3361         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3362                 struct vmcb_control_area *nc = &nested_vmcb->control;
3363
3364                 nc->exit_int_info     = vmcb->control.event_inj;
3365                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3366         }
3367
3368         nested_vmcb->control.tlb_ctl           = 0;
3369         nested_vmcb->control.event_inj         = 0;
3370         nested_vmcb->control.event_inj_err     = 0;
3371
3372         nested_vmcb->control.pause_filter_count =
3373                 svm->vmcb->control.pause_filter_count;
3374         nested_vmcb->control.pause_filter_thresh =
3375                 svm->vmcb->control.pause_filter_thresh;
3376
3377         /* We always set V_INTR_MASKING and remember the old value in hflags */
3378         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3379                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3380
3381         /* Restore the original control entries */
3382         copy_vmcb_control_area(vmcb, hsave);
3383
3384         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3385         kvm_clear_exception_queue(&svm->vcpu);
3386         kvm_clear_interrupt_queue(&svm->vcpu);
3387
3388         svm->nested.nested_cr3 = 0;
3389
3390         /* Restore selected save entries */
3391         svm->vmcb->save.es = hsave->save.es;
3392         svm->vmcb->save.cs = hsave->save.cs;
3393         svm->vmcb->save.ss = hsave->save.ss;
3394         svm->vmcb->save.ds = hsave->save.ds;
3395         svm->vmcb->save.gdtr = hsave->save.gdtr;
3396         svm->vmcb->save.idtr = hsave->save.idtr;
3397         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3398         svm_set_efer(&svm->vcpu, hsave->save.efer);
3399         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3400         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3401         if (npt_enabled) {
3402                 svm->vmcb->save.cr3 = hsave->save.cr3;
3403                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3404         } else {
3405                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3406         }
3407         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3408         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3409         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3410         svm->vmcb->save.dr7 = 0;
3411         svm->vmcb->save.cpl = 0;
3412         svm->vmcb->control.exit_int_info = 0;
3413
3414         mark_all_dirty(svm->vmcb);
3415
3416         nested_svm_unmap(page);
3417
3418         nested_svm_uninit_mmu_context(&svm->vcpu);
3419         kvm_mmu_reset_context(&svm->vcpu);
3420         kvm_mmu_load(&svm->vcpu);
3421
3422         /*
3423          * Drop what we picked up for L2 via svm_complete_interrupts() so it
3424          * doesn't end up in L1.
3425          */
3426         svm->vcpu.arch.nmi_injected = false;
3427         kvm_clear_exception_queue(&svm->vcpu);
3428         kvm_clear_interrupt_queue(&svm->vcpu);
3429
3430         return 0;
3431 }
3432
3433 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3434 {
3435         /*
3436          * This function merges the msr permission bitmaps of kvm and the
3437          * nested vmcb. It is optimized in that it only merges the parts where
3438          * the kvm msr permission bitmap may contain zero bits
3439          */
3440         int i;
3441
3442         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3443                 return true;
3444
3445         for (i = 0; i < MSRPM_OFFSETS; i++) {
3446                 u32 value, p;
3447                 u64 offset;
3448
3449                 if (msrpm_offsets[i] == 0xffffffff)
3450                         break;
3451
3452                 p      = msrpm_offsets[i];
3453                 offset = svm->nested.vmcb_msrpm + (p * 4);
3454
3455                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3456                         return false;
3457
3458                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3459         }
3460
3461         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3462
3463         return true;
3464 }
3465
3466 static bool nested_vmcb_checks(struct vmcb *vmcb)
3467 {
3468         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3469                 return false;
3470
3471         if (vmcb->control.asid == 0)
3472                 return false;
3473
3474         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3475             !npt_enabled)
3476                 return false;
3477
3478         return true;
3479 }
3480
3481 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3482                                  struct vmcb *nested_vmcb, struct page *page)
3483 {
3484         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3485                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3486         else
3487                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3488
3489         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3490                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3491                 nested_svm_init_mmu_context(&svm->vcpu);
3492         }
3493
3494         /* Load the nested guest state */
3495         svm->vmcb->save.es = nested_vmcb->save.es;
3496         svm->vmcb->save.cs = nested_vmcb->save.cs;
3497         svm->vmcb->save.ss = nested_vmcb->save.ss;
3498         svm->vmcb->save.ds = nested_vmcb->save.ds;
3499         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3500         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3501         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3502         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3503         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3504         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3505         if (npt_enabled) {
3506                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3507                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3508         } else
3509                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3510
3511         /* Guest paging mode is active - reset mmu */
3512         kvm_mmu_reset_context(&svm->vcpu);
3513
3514         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3515         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3516         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3517         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3518
3519         /* In case we don't even reach vcpu_run, the fields are not updated */
3520         svm->vmcb->save.rax = nested_vmcb->save.rax;
3521         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3522         svm->vmcb->save.rip = nested_vmcb->save.rip;
3523         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3524         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3525         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3526
3527         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3528         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3529
3530         /* cache intercepts */
3531         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3532         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3533         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3534         svm->nested.intercept            = nested_vmcb->control.intercept;
3535
3536         svm_flush_tlb(&svm->vcpu, true);
3537         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3538         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3539                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3540         else
3541                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3542
3543         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3544                 /* We only want the cr8 intercept bits of the guest */
3545                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3546                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3547         }
3548
3549         /* We don't want to see VMMCALLs from a nested guest */
3550         clr_intercept(svm, INTERCEPT_VMMCALL);
3551
3552         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3553         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3554
3555         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3556         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3557         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3558         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3559         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3560
3561         svm->vmcb->control.pause_filter_count =
3562                 nested_vmcb->control.pause_filter_count;
3563         svm->vmcb->control.pause_filter_thresh =
3564                 nested_vmcb->control.pause_filter_thresh;
3565
3566         nested_svm_unmap(page);
3567
3568         /* Enter Guest-Mode */
3569         enter_guest_mode(&svm->vcpu);
3570
3571         /*
3572          * Merge guest and host intercepts - must be called  with vcpu in
3573          * guest-mode to take affect here
3574          */
3575         recalc_intercepts(svm);
3576
3577         svm->nested.vmcb = vmcb_gpa;
3578
3579         enable_gif(svm);
3580
3581         mark_all_dirty(svm->vmcb);
3582 }
3583
3584 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3585 {
3586         struct vmcb *nested_vmcb;
3587         struct vmcb *hsave = svm->nested.hsave;
3588         struct vmcb *vmcb = svm->vmcb;
3589         struct page *page;
3590         u64 vmcb_gpa;
3591
3592         vmcb_gpa = svm->vmcb->save.rax;
3593
3594         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3595         if (!nested_vmcb)
3596                 return false;
3597
3598         if (!nested_vmcb_checks(nested_vmcb)) {
3599                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3600                 nested_vmcb->control.exit_code_hi = 0;
3601                 nested_vmcb->control.exit_info_1  = 0;
3602                 nested_vmcb->control.exit_info_2  = 0;
3603
3604                 nested_svm_unmap(page);
3605
3606                 return false;
3607         }
3608
3609         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3610                                nested_vmcb->save.rip,
3611                                nested_vmcb->control.int_ctl,
3612                                nested_vmcb->control.event_inj,
3613                                nested_vmcb->control.nested_ctl);
3614
3615         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3616                                     nested_vmcb->control.intercept_cr >> 16,
3617                                     nested_vmcb->control.intercept_exceptions,
3618                                     nested_vmcb->control.intercept);
3619
3620         /* Clear internal status */
3621         kvm_clear_exception_queue(&svm->vcpu);
3622         kvm_clear_interrupt_queue(&svm->vcpu);
3623
3624         /*
3625          * Save the old vmcb, so we don't need to pick what we save, but can
3626          * restore everything when a VMEXIT occurs
3627          */
3628         hsave->save.es     = vmcb->save.es;
3629         hsave->save.cs     = vmcb->save.cs;
3630         hsave->save.ss     = vmcb->save.ss;
3631         hsave->save.ds     = vmcb->save.ds;
3632         hsave->save.gdtr   = vmcb->save.gdtr;
3633         hsave->save.idtr   = vmcb->save.idtr;
3634         hsave->save.efer   = svm->vcpu.arch.efer;
3635         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3636         hsave->save.cr4    = svm->vcpu.arch.cr4;
3637         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3638         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3639         hsave->save.rsp    = vmcb->save.rsp;
3640         hsave->save.rax    = vmcb->save.rax;
3641         if (npt_enabled)
3642                 hsave->save.cr3    = vmcb->save.cr3;
3643         else
3644                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3645
3646         copy_vmcb_control_area(hsave, vmcb);
3647
3648         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3649
3650         return true;
3651 }
3652
3653 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3654 {
3655         to_vmcb->save.fs = from_vmcb->save.fs;
3656         to_vmcb->save.gs = from_vmcb->save.gs;
3657         to_vmcb->save.tr = from_vmcb->save.tr;
3658         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3659         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3660         to_vmcb->save.star = from_vmcb->save.star;
3661         to_vmcb->save.lstar = from_vmcb->save.lstar;
3662         to_vmcb->save.cstar = from_vmcb->save.cstar;
3663         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3664         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3665         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3666         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3667 }
3668
3669 static int vmload_interception(struct vcpu_svm *svm)
3670 {
3671         struct vmcb *nested_vmcb;
3672         struct page *page;
3673         int ret;
3674
3675         if (nested_svm_check_permissions(svm))
3676                 return 1;
3677
3678         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3679         if (!nested_vmcb)
3680                 return 1;
3681
3682         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3683         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3684
3685         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3686         nested_svm_unmap(page);
3687
3688         return ret;
3689 }
3690
3691 static int vmsave_interception(struct vcpu_svm *svm)
3692 {
3693         struct vmcb *nested_vmcb;
3694         struct page *page;
3695         int ret;
3696
3697         if (nested_svm_check_permissions(svm))
3698                 return 1;
3699
3700         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3701         if (!nested_vmcb)
3702                 return 1;
3703
3704         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3705         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3706
3707         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3708         nested_svm_unmap(page);
3709
3710         return ret;
3711 }
3712
3713 static int vmrun_interception(struct vcpu_svm *svm)
3714 {
3715         if (nested_svm_check_permissions(svm))
3716                 return 1;
3717
3718         /* Save rip after vmrun instruction */
3719         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3720
3721         if (!nested_svm_vmrun(svm))
3722                 return 1;
3723
3724         if (!nested_svm_vmrun_msrpm(svm))
3725                 goto failed;
3726
3727         return 1;
3728
3729 failed:
3730
3731         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3732         svm->vmcb->control.exit_code_hi = 0;
3733         svm->vmcb->control.exit_info_1  = 0;
3734         svm->vmcb->control.exit_info_2  = 0;
3735
3736         nested_svm_vmexit(svm);
3737
3738         return 1;
3739 }
3740
3741 static int stgi_interception(struct vcpu_svm *svm)
3742 {
3743         int ret;
3744
3745         if (nested_svm_check_permissions(svm))
3746                 return 1;
3747
3748         /*
3749          * If VGIF is enabled, the STGI intercept is only added to
3750          * detect the opening of the SMI/NMI window; remove it now.
3751          */
3752         if (vgif_enabled(svm))
3753                 clr_intercept(svm, INTERCEPT_STGI);
3754
3755         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3756         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3757         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3758
3759         enable_gif(svm);
3760
3761         return ret;
3762 }
3763
3764 static int clgi_interception(struct vcpu_svm *svm)
3765 {
3766         int ret;
3767
3768         if (nested_svm_check_permissions(svm))
3769                 return 1;
3770
3771         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3772         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3773
3774         disable_gif(svm);
3775
3776         /* After a CLGI no interrupts should come */
3777         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3778                 svm_clear_vintr(svm);
3779                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3780                 mark_dirty(svm->vmcb, VMCB_INTR);
3781         }
3782
3783         return ret;
3784 }
3785
3786 static int invlpga_interception(struct vcpu_svm *svm)
3787 {
3788         struct kvm_vcpu *vcpu = &svm->vcpu;
3789
3790         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3791                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3792
3793         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3794         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3795
3796         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3797         return kvm_skip_emulated_instruction(&svm->vcpu);
3798 }
3799
3800 static int skinit_interception(struct vcpu_svm *svm)
3801 {
3802         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3803
3804         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3805         return 1;
3806 }
3807
3808 static int wbinvd_interception(struct vcpu_svm *svm)
3809 {
3810         return kvm_emulate_wbinvd(&svm->vcpu);
3811 }
3812
3813 static int xsetbv_interception(struct vcpu_svm *svm)
3814 {
3815         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3816         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3817
3818         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3819                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3820                 return kvm_skip_emulated_instruction(&svm->vcpu);
3821         }
3822
3823         return 1;
3824 }
3825
3826 static int task_switch_interception(struct vcpu_svm *svm)
3827 {
3828         u16 tss_selector;
3829         int reason;
3830         int int_type = svm->vmcb->control.exit_int_info &
3831                 SVM_EXITINTINFO_TYPE_MASK;
3832         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3833         uint32_t type =
3834                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3835         uint32_t idt_v =
3836                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3837         bool has_error_code = false;
3838         u32 error_code = 0;
3839
3840         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3841
3842         if (svm->vmcb->control.exit_info_2 &
3843             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3844                 reason = TASK_SWITCH_IRET;
3845         else if (svm->vmcb->control.exit_info_2 &
3846                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3847                 reason = TASK_SWITCH_JMP;
3848         else if (idt_v)
3849                 reason = TASK_SWITCH_GATE;
3850         else
3851                 reason = TASK_SWITCH_CALL;
3852
3853         if (reason == TASK_SWITCH_GATE) {
3854                 switch (type) {
3855                 case SVM_EXITINTINFO_TYPE_NMI:
3856                         svm->vcpu.arch.nmi_injected = false;
3857                         break;
3858                 case SVM_EXITINTINFO_TYPE_EXEPT:
3859                         if (svm->vmcb->control.exit_info_2 &
3860                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3861                                 has_error_code = true;
3862                                 error_code =
3863                                         (u32)svm->vmcb->control.exit_info_2;
3864                         }
3865                         kvm_clear_exception_queue(&svm->vcpu);
3866                         break;
3867                 case SVM_EXITINTINFO_TYPE_INTR:
3868                         kvm_clear_interrupt_queue(&svm->vcpu);
3869                         break;
3870                 default:
3871                         break;
3872                 }
3873         }
3874
3875         if (reason != TASK_SWITCH_GATE ||
3876             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3877             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3878              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3879                 skip_emulated_instruction(&svm->vcpu);
3880
3881         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3882                 int_vec = -1;
3883
3884         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3885                                 has_error_code, error_code) == EMULATE_FAIL) {
3886                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3887                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3888                 svm->vcpu.run->internal.ndata = 0;
3889                 return 0;
3890         }
3891         return 1;
3892 }
3893
3894 static int cpuid_interception(struct vcpu_svm *svm)
3895 {
3896         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3897         return kvm_emulate_cpuid(&svm->vcpu);
3898 }
3899
3900 static int iret_interception(struct vcpu_svm *svm)
3901 {
3902         ++svm->vcpu.stat.nmi_window_exits;
3903         clr_intercept(svm, INTERCEPT_IRET);
3904         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3905         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3906         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3907         return 1;
3908 }
3909
3910 static int invlpg_interception(struct vcpu_svm *svm)
3911 {
3912         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3913                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3914
3915         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3916         return kvm_skip_emulated_instruction(&svm->vcpu);
3917 }
3918
3919 static int emulate_on_interception(struct vcpu_svm *svm)
3920 {
3921         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3922 }
3923
3924 static int rsm_interception(struct vcpu_svm *svm)
3925 {
3926         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3927                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3928 }
3929
3930 static int rdpmc_interception(struct vcpu_svm *svm)
3931 {
3932         int err;
3933
3934         if (!static_cpu_has(X86_FEATURE_NRIPS))
3935                 return emulate_on_interception(svm);
3936
3937         err = kvm_rdpmc(&svm->vcpu);
3938         return kvm_complete_insn_gp(&svm->vcpu, err);
3939 }
3940
3941 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3942                                             unsigned long val)
3943 {
3944         unsigned long cr0 = svm->vcpu.arch.cr0;
3945         bool ret = false;
3946         u64 intercept;
3947
3948         intercept = svm->nested.intercept;
3949
3950         if (!is_guest_mode(&svm->vcpu) ||
3951             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3952                 return false;
3953
3954         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3955         val &= ~SVM_CR0_SELECTIVE_MASK;
3956
3957         if (cr0 ^ val) {
3958                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3959                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3960         }
3961
3962         return ret;
3963 }
3964
3965 #define CR_VALID (1ULL << 63)
3966
3967 static int cr_interception(struct vcpu_svm *svm)
3968 {
3969         int reg, cr;
3970         unsigned long val;
3971         int err;
3972
3973         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3974                 return emulate_on_interception(svm);
3975
3976         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3977                 return emulate_on_interception(svm);
3978
3979         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3980         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3981                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3982         else
3983                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3984
3985         err = 0;
3986         if (cr >= 16) { /* mov to cr */
3987                 cr -= 16;
3988                 val = kvm_register_read(&svm->vcpu, reg);
3989                 switch (cr) {
3990                 case 0:
3991                         if (!check_selective_cr0_intercepted(svm, val))
3992                                 err = kvm_set_cr0(&svm->vcpu, val);
3993                         else
3994                                 return 1;
3995
3996                         break;
3997                 case 3:
3998                         err = kvm_set_cr3(&svm->vcpu, val);
3999                         break;
4000                 case 4:
4001                         err = kvm_set_cr4(&svm->vcpu, val);
4002                         break;
4003                 case 8:
4004                         err = kvm_set_cr8(&svm->vcpu, val);
4005                         break;
4006                 default:
4007                         WARN(1, "unhandled write to CR%d", cr);
4008                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4009                         return 1;
4010                 }
4011         } else { /* mov from cr */
4012                 switch (cr) {
4013                 case 0:
4014                         val = kvm_read_cr0(&svm->vcpu);
4015                         break;
4016                 case 2:
4017                         val = svm->vcpu.arch.cr2;
4018                         break;
4019                 case 3:
4020                         val = kvm_read_cr3(&svm->vcpu);
4021                         break;
4022                 case 4:
4023                         val = kvm_read_cr4(&svm->vcpu);
4024                         break;
4025                 case 8:
4026                         val = kvm_get_cr8(&svm->vcpu);
4027                         break;
4028                 default:
4029                         WARN(1, "unhandled read from CR%d", cr);
4030                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4031                         return 1;
4032                 }
4033                 kvm_register_write(&svm->vcpu, reg, val);
4034         }
4035         return kvm_complete_insn_gp(&svm->vcpu, err);
4036 }
4037
4038 static int dr_interception(struct vcpu_svm *svm)
4039 {
4040         int reg, dr;
4041         unsigned long val;
4042
4043         if (svm->vcpu.guest_debug == 0) {
4044                 /*
4045                  * No more DR vmexits; force a reload of the debug registers
4046                  * and reenter on this instruction.  The next vmexit will
4047                  * retrieve the full state of the debug registers.
4048                  */
4049                 clr_dr_intercepts(svm);
4050                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4051                 return 1;
4052         }
4053
4054         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4055                 return emulate_on_interception(svm);
4056
4057         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4058         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4059
4060         if (dr >= 16) { /* mov to DRn */
4061                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4062                         return 1;
4063                 val = kvm_register_read(&svm->vcpu, reg);
4064                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4065         } else {
4066                 if (!kvm_require_dr(&svm->vcpu, dr))
4067                         return 1;
4068                 kvm_get_dr(&svm->vcpu, dr, &val);
4069                 kvm_register_write(&svm->vcpu, reg, val);
4070         }
4071
4072         return kvm_skip_emulated_instruction(&svm->vcpu);
4073 }
4074
4075 static int cr8_write_interception(struct vcpu_svm *svm)
4076 {
4077         struct kvm_run *kvm_run = svm->vcpu.run;
4078         int r;
4079
4080         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4081         /* instruction emulation calls kvm_set_cr8() */
4082         r = cr_interception(svm);
4083         if (lapic_in_kernel(&svm->vcpu))
4084                 return r;
4085         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4086                 return r;
4087         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4088         return 0;
4089 }
4090
4091 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4092 {
4093         msr->data = 0;
4094
4095         switch (msr->index) {
4096         case MSR_F10H_DECFG:
4097                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4098                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4099                 break;
4100         default:
4101                 return 1;
4102         }
4103
4104         return 0;
4105 }
4106
4107 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4108 {
4109         struct vcpu_svm *svm = to_svm(vcpu);
4110
4111         switch (msr_info->index) {
4112         case MSR_STAR:
4113                 msr_info->data = svm->vmcb->save.star;
4114                 break;
4115 #ifdef CONFIG_X86_64
4116         case MSR_LSTAR:
4117                 msr_info->data = svm->vmcb->save.lstar;
4118                 break;
4119         case MSR_CSTAR:
4120                 msr_info->data = svm->vmcb->save.cstar;
4121                 break;
4122         case MSR_KERNEL_GS_BASE:
4123                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4124                 break;
4125         case MSR_SYSCALL_MASK:
4126                 msr_info->data = svm->vmcb->save.sfmask;
4127                 break;
4128 #endif
4129         case MSR_IA32_SYSENTER_CS:
4130                 msr_info->data = svm->vmcb->save.sysenter_cs;
4131                 break;
4132         case MSR_IA32_SYSENTER_EIP:
4133                 msr_info->data = svm->sysenter_eip;
4134                 break;
4135         case MSR_IA32_SYSENTER_ESP:
4136                 msr_info->data = svm->sysenter_esp;
4137                 break;
4138         case MSR_TSC_AUX:
4139                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4140                         return 1;
4141                 msr_info->data = svm->tsc_aux;
4142                 break;
4143         /*
4144          * Nobody will change the following 5 values in the VMCB so we can
4145          * safely return them on rdmsr. They will always be 0 until LBRV is
4146          * implemented.
4147          */
4148         case MSR_IA32_DEBUGCTLMSR:
4149                 msr_info->data = svm->vmcb->save.dbgctl;
4150                 break;
4151         case MSR_IA32_LASTBRANCHFROMIP:
4152                 msr_info->data = svm->vmcb->save.br_from;
4153                 break;
4154         case MSR_IA32_LASTBRANCHTOIP:
4155                 msr_info->data = svm->vmcb->save.br_to;
4156                 break;
4157         case MSR_IA32_LASTINTFROMIP:
4158                 msr_info->data = svm->vmcb->save.last_excp_from;
4159                 break;
4160         case MSR_IA32_LASTINTTOIP:
4161                 msr_info->data = svm->vmcb->save.last_excp_to;
4162                 break;
4163         case MSR_VM_HSAVE_PA:
4164                 msr_info->data = svm->nested.hsave_msr;
4165                 break;
4166         case MSR_VM_CR:
4167                 msr_info->data = svm->nested.vm_cr_msr;
4168                 break;
4169         case MSR_IA32_SPEC_CTRL:
4170                 if (!msr_info->host_initiated &&
4171                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4172                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4173                         return 1;
4174
4175                 msr_info->data = svm->spec_ctrl;
4176                 break;
4177         case MSR_AMD64_VIRT_SPEC_CTRL:
4178                 if (!msr_info->host_initiated &&
4179                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4180                         return 1;
4181
4182                 msr_info->data = svm->virt_spec_ctrl;
4183                 break;
4184         case MSR_F15H_IC_CFG: {
4185
4186                 int family, model;
4187
4188                 family = guest_cpuid_family(vcpu);
4189                 model  = guest_cpuid_model(vcpu);
4190
4191                 if (family < 0 || model < 0)
4192                         return kvm_get_msr_common(vcpu, msr_info);
4193
4194                 msr_info->data = 0;
4195
4196                 if (family == 0x15 &&
4197                     (model >= 0x2 && model < 0x20))
4198                         msr_info->data = 0x1E;
4199                 }
4200                 break;
4201         case MSR_F10H_DECFG:
4202                 msr_info->data = svm->msr_decfg;
4203                 break;
4204         default:
4205                 return kvm_get_msr_common(vcpu, msr_info);
4206         }
4207         return 0;
4208 }
4209
4210 static int rdmsr_interception(struct vcpu_svm *svm)
4211 {
4212         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4213         struct msr_data msr_info;
4214
4215         msr_info.index = ecx;
4216         msr_info.host_initiated = false;
4217         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4218                 trace_kvm_msr_read_ex(ecx);
4219                 kvm_inject_gp(&svm->vcpu, 0);
4220                 return 1;
4221         } else {
4222                 trace_kvm_msr_read(ecx, msr_info.data);
4223
4224                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4225                                    msr_info.data & 0xffffffff);
4226                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4227                                    msr_info.data >> 32);
4228                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4229                 return kvm_skip_emulated_instruction(&svm->vcpu);
4230         }
4231 }
4232
4233 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4234 {
4235         struct vcpu_svm *svm = to_svm(vcpu);
4236         int svm_dis, chg_mask;
4237
4238         if (data & ~SVM_VM_CR_VALID_MASK)
4239                 return 1;
4240
4241         chg_mask = SVM_VM_CR_VALID_MASK;
4242
4243         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4244                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4245
4246         svm->nested.vm_cr_msr &= ~chg_mask;
4247         svm->nested.vm_cr_msr |= (data & chg_mask);
4248
4249         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4250
4251         /* check for svm_disable while efer.svme is set */
4252         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4253                 return 1;
4254
4255         return 0;
4256 }
4257
4258 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4259 {
4260         struct vcpu_svm *svm = to_svm(vcpu);
4261
4262         u32 ecx = msr->index;
4263         u64 data = msr->data;
4264         switch (ecx) {
4265         case MSR_IA32_CR_PAT:
4266                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4267                         return 1;
4268                 vcpu->arch.pat = data;
4269                 svm->vmcb->save.g_pat = data;
4270                 mark_dirty(svm->vmcb, VMCB_NPT);
4271                 break;
4272         case MSR_IA32_SPEC_CTRL:
4273                 if (!msr->host_initiated &&
4274                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4275                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4276                         return 1;
4277
4278                 /* The STIBP bit doesn't fault even if it's not advertised */
4279                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4280                         return 1;
4281
4282                 svm->spec_ctrl = data;
4283
4284                 if (!data)
4285                         break;
4286
4287                 /*
4288                  * For non-nested:
4289                  * When it's written (to non-zero) for the first time, pass
4290                  * it through.
4291                  *
4292                  * For nested:
4293                  * The handling of the MSR bitmap for L2 guests is done in
4294                  * nested_svm_vmrun_msrpm.
4295                  * We update the L1 MSR bit as well since it will end up
4296                  * touching the MSR anyway now.
4297                  */
4298                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4299                 break;
4300         case MSR_IA32_PRED_CMD:
4301                 if (!msr->host_initiated &&
4302                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4303                         return 1;
4304
4305                 if (data & ~PRED_CMD_IBPB)
4306                         return 1;
4307
4308                 if (!data)
4309                         break;
4310
4311                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4312                 if (is_guest_mode(vcpu))
4313                         break;
4314                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4315                 break;
4316         case MSR_AMD64_VIRT_SPEC_CTRL:
4317                 if (!msr->host_initiated &&
4318                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4319                         return 1;
4320
4321                 if (data & ~SPEC_CTRL_SSBD)
4322                         return 1;
4323
4324                 svm->virt_spec_ctrl = data;
4325                 break;
4326         case MSR_STAR:
4327                 svm->vmcb->save.star = data;
4328                 break;
4329 #ifdef CONFIG_X86_64
4330         case MSR_LSTAR:
4331                 svm->vmcb->save.lstar = data;
4332                 break;
4333         case MSR_CSTAR:
4334                 svm->vmcb->save.cstar = data;
4335                 break;
4336         case MSR_KERNEL_GS_BASE:
4337                 svm->vmcb->save.kernel_gs_base = data;
4338                 break;
4339         case MSR_SYSCALL_MASK:
4340                 svm->vmcb->save.sfmask = data;
4341                 break;
4342 #endif
4343         case MSR_IA32_SYSENTER_CS:
4344                 svm->vmcb->save.sysenter_cs = data;
4345                 break;
4346         case MSR_IA32_SYSENTER_EIP:
4347                 svm->sysenter_eip = data;
4348                 svm->vmcb->save.sysenter_eip = data;
4349                 break;
4350         case MSR_IA32_SYSENTER_ESP:
4351                 svm->sysenter_esp = data;
4352                 svm->vmcb->save.sysenter_esp = data;
4353                 break;
4354         case MSR_TSC_AUX:
4355                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4356                         return 1;
4357
4358                 /*
4359                  * This is rare, so we update the MSR here instead of using
4360                  * direct_access_msrs.  Doing that would require a rdmsr in
4361                  * svm_vcpu_put.
4362                  */
4363                 svm->tsc_aux = data;
4364                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4365                 break;
4366         case MSR_IA32_DEBUGCTLMSR:
4367                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4368                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4369                                     __func__, data);
4370                         break;
4371                 }
4372                 if (data & DEBUGCTL_RESERVED_BITS)
4373                         return 1;
4374
4375                 svm->vmcb->save.dbgctl = data;
4376                 mark_dirty(svm->vmcb, VMCB_LBR);
4377                 if (data & (1ULL<<0))
4378                         svm_enable_lbrv(svm);
4379                 else
4380                         svm_disable_lbrv(svm);
4381                 break;
4382         case MSR_VM_HSAVE_PA:
4383                 svm->nested.hsave_msr = data;
4384                 break;
4385         case MSR_VM_CR:
4386                 return svm_set_vm_cr(vcpu, data);
4387         case MSR_VM_IGNNE:
4388                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4389                 break;
4390         case MSR_F10H_DECFG: {
4391                 struct kvm_msr_entry msr_entry;
4392
4393                 msr_entry.index = msr->index;
4394                 if (svm_get_msr_feature(&msr_entry))
4395                         return 1;
4396
4397                 /* Check the supported bits */
4398                 if (data & ~msr_entry.data)
4399                         return 1;
4400
4401                 /* Don't allow the guest to change a bit, #GP */
4402                 if (!msr->host_initiated && (data ^ msr_entry.data))
4403                         return 1;
4404
4405                 svm->msr_decfg = data;
4406                 break;
4407         }
4408         case MSR_IA32_APICBASE:
4409                 if (kvm_vcpu_apicv_active(vcpu))
4410                         avic_update_vapic_bar(to_svm(vcpu), data);
4411                 /* Fall through */
4412         default:
4413                 return kvm_set_msr_common(vcpu, msr);
4414         }
4415         return 0;
4416 }
4417
4418 static int wrmsr_interception(struct vcpu_svm *svm)
4419 {
4420         struct msr_data msr;
4421         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4422         u64 data = kvm_read_edx_eax(&svm->vcpu);
4423
4424         msr.data = data;
4425         msr.index = ecx;
4426         msr.host_initiated = false;
4427
4428         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4429         if (kvm_set_msr(&svm->vcpu, &msr)) {
4430                 trace_kvm_msr_write_ex(ecx, data);
4431                 kvm_inject_gp(&svm->vcpu, 0);
4432                 return 1;
4433         } else {
4434                 trace_kvm_msr_write(ecx, data);
4435                 return kvm_skip_emulated_instruction(&svm->vcpu);
4436         }
4437 }
4438
4439 static int msr_interception(struct vcpu_svm *svm)
4440 {
4441         if (svm->vmcb->control.exit_info_1)
4442                 return wrmsr_interception(svm);
4443         else
4444                 return rdmsr_interception(svm);
4445 }
4446
4447 static int interrupt_window_interception(struct vcpu_svm *svm)
4448 {
4449         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4450         svm_clear_vintr(svm);
4451         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4452         mark_dirty(svm->vmcb, VMCB_INTR);
4453         ++svm->vcpu.stat.irq_window_exits;
4454         return 1;
4455 }
4456
4457 static int pause_interception(struct vcpu_svm *svm)
4458 {
4459         struct kvm_vcpu *vcpu = &svm->vcpu;
4460         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4461
4462         if (pause_filter_thresh)
4463                 grow_ple_window(vcpu);
4464
4465         kvm_vcpu_on_spin(vcpu, in_kernel);
4466         return 1;
4467 }
4468
4469 static int nop_interception(struct vcpu_svm *svm)
4470 {
4471         return kvm_skip_emulated_instruction(&(svm->vcpu));
4472 }
4473
4474 static int monitor_interception(struct vcpu_svm *svm)
4475 {
4476         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4477         return nop_interception(svm);
4478 }
4479
4480 static int mwait_interception(struct vcpu_svm *svm)
4481 {
4482         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4483         return nop_interception(svm);
4484 }
4485
4486 enum avic_ipi_failure_cause {
4487         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4488         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4489         AVIC_IPI_FAILURE_INVALID_TARGET,
4490         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4491 };
4492
4493 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4494 {
4495         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4496         u32 icrl = svm->vmcb->control.exit_info_1;
4497         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4498         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4499         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4500
4501         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4502
4503         switch (id) {
4504         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4505                 /*
4506                  * AVIC hardware handles the generation of
4507                  * IPIs when the specified Message Type is Fixed
4508                  * (also known as fixed delivery mode) and
4509                  * the Trigger Mode is edge-triggered. The hardware
4510                  * also supports self and broadcast delivery modes
4511                  * specified via the Destination Shorthand(DSH)
4512                  * field of the ICRL. Logical and physical APIC ID
4513                  * formats are supported. All other IPI types cause
4514                  * a #VMEXIT, which needs to emulated.
4515                  */
4516                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4517                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4518                 break;
4519         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4520                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4521
4522                 /*
4523                  * Update ICR high and low, then emulate sending IPI,
4524                  * which is handled when writing APIC_ICR.
4525                  */
4526                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4527                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4528                 break;
4529         }
4530         case AVIC_IPI_FAILURE_INVALID_TARGET:
4531                 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4532                           index, svm->vcpu.vcpu_id, icrh, icrl);
4533                 break;
4534         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4535                 WARN_ONCE(1, "Invalid backing page\n");
4536                 break;
4537         default:
4538                 pr_err("Unknown IPI interception\n");
4539         }
4540
4541         return 1;
4542 }
4543
4544 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4545 {
4546         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4547         int index;
4548         u32 *logical_apic_id_table;
4549         int dlid = GET_APIC_LOGICAL_ID(ldr);
4550
4551         if (!dlid)
4552                 return NULL;
4553
4554         if (flat) { /* flat */
4555                 index = ffs(dlid) - 1;
4556                 if (index > 7)
4557                         return NULL;
4558         } else { /* cluster */
4559                 int cluster = (dlid & 0xf0) >> 4;
4560                 int apic = ffs(dlid & 0x0f) - 1;
4561
4562                 if ((apic < 0) || (apic > 7) ||
4563                     (cluster >= 0xf))
4564                         return NULL;
4565                 index = (cluster << 2) + apic;
4566         }
4567
4568         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4569
4570         return &logical_apic_id_table[index];
4571 }
4572
4573 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4574 {
4575         bool flat;
4576         u32 *entry, new_entry;
4577
4578         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4579         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4580         if (!entry)
4581                 return -EINVAL;
4582
4583         new_entry = READ_ONCE(*entry);
4584         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4585         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4586         new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4587         WRITE_ONCE(*entry, new_entry);
4588
4589         return 0;
4590 }
4591
4592 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4593 {
4594         struct vcpu_svm *svm = to_svm(vcpu);
4595         bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4596         u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4597
4598         if (entry)
4599                 WRITE_ONCE(*entry, (u32) ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK);
4600 }
4601
4602 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4603 {
4604         int ret = 0;
4605         struct vcpu_svm *svm = to_svm(vcpu);
4606         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4607
4608         if (ldr == svm->ldr_reg)
4609                 return 0;
4610
4611         avic_invalidate_logical_id_entry(vcpu);
4612
4613         if (ldr)
4614                 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4615
4616         if (!ret)
4617                 svm->ldr_reg = ldr;
4618
4619         return ret;
4620 }
4621
4622 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4623 {
4624         u64 *old, *new;
4625         struct vcpu_svm *svm = to_svm(vcpu);
4626         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4627         u32 id = (apic_id_reg >> 24) & 0xff;
4628
4629         if (vcpu->vcpu_id == id)
4630                 return 0;
4631
4632         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4633         new = avic_get_physical_id_entry(vcpu, id);
4634         if (!new || !old)
4635                 return 1;
4636
4637         /* We need to move physical_id_entry to new offset */
4638         *new = *old;
4639         *old = 0ULL;
4640         to_svm(vcpu)->avic_physical_id_cache = new;
4641
4642         /*
4643          * Also update the guest physical APIC ID in the logical
4644          * APIC ID table entry if already setup the LDR.
4645          */
4646         if (svm->ldr_reg)
4647                 avic_handle_ldr_update(vcpu);
4648
4649         return 0;
4650 }
4651
4652 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4653 {
4654         struct vcpu_svm *svm = to_svm(vcpu);
4655         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4656
4657         if (svm->dfr_reg == dfr)
4658                 return;
4659
4660         avic_invalidate_logical_id_entry(vcpu);
4661         svm->dfr_reg = dfr;
4662 }
4663
4664 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4665 {
4666         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4667         u32 offset = svm->vmcb->control.exit_info_1 &
4668                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4669
4670         switch (offset) {
4671         case APIC_ID:
4672                 if (avic_handle_apic_id_update(&svm->vcpu))
4673                         return 0;
4674                 break;
4675         case APIC_LDR:
4676                 if (avic_handle_ldr_update(&svm->vcpu))
4677                         return 0;
4678                 break;
4679         case APIC_DFR:
4680                 avic_handle_dfr_update(&svm->vcpu);
4681                 break;
4682         default:
4683                 break;
4684         }
4685
4686         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4687
4688         return 1;
4689 }
4690
4691 static bool is_avic_unaccelerated_access_trap(u32 offset)
4692 {
4693         bool ret = false;
4694
4695         switch (offset) {
4696         case APIC_ID:
4697         case APIC_EOI:
4698         case APIC_RRR:
4699         case APIC_LDR:
4700         case APIC_DFR:
4701         case APIC_SPIV:
4702         case APIC_ESR:
4703         case APIC_ICR:
4704         case APIC_LVTT:
4705         case APIC_LVTTHMR:
4706         case APIC_LVTPC:
4707         case APIC_LVT0:
4708         case APIC_LVT1:
4709         case APIC_LVTERR:
4710         case APIC_TMICT:
4711         case APIC_TDCR:
4712                 ret = true;
4713                 break;
4714         default:
4715                 break;
4716         }
4717         return ret;
4718 }
4719
4720 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4721 {
4722         int ret = 0;
4723         u32 offset = svm->vmcb->control.exit_info_1 &
4724                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4725         u32 vector = svm->vmcb->control.exit_info_2 &
4726                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4727         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4728                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4729         bool trap = is_avic_unaccelerated_access_trap(offset);
4730
4731         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4732                                             trap, write, vector);
4733         if (trap) {
4734                 /* Handling Trap */
4735                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4736                 ret = avic_unaccel_trap_write(svm);
4737         } else {
4738                 /* Handling Fault */
4739                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4740         }
4741
4742         return ret;
4743 }
4744
4745 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4746         [SVM_EXIT_READ_CR0]                     = cr_interception,
4747         [SVM_EXIT_READ_CR3]                     = cr_interception,
4748         [SVM_EXIT_READ_CR4]                     = cr_interception,
4749         [SVM_EXIT_READ_CR8]                     = cr_interception,
4750         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4751         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4752         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4753         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4754         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4755         [SVM_EXIT_READ_DR0]                     = dr_interception,
4756         [SVM_EXIT_READ_DR1]                     = dr_interception,
4757         [SVM_EXIT_READ_DR2]                     = dr_interception,
4758         [SVM_EXIT_READ_DR3]                     = dr_interception,
4759         [SVM_EXIT_READ_DR4]                     = dr_interception,
4760         [SVM_EXIT_READ_DR5]                     = dr_interception,
4761         [SVM_EXIT_READ_DR6]                     = dr_interception,
4762         [SVM_EXIT_READ_DR7]                     = dr_interception,
4763         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4764         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4765         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4766         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4767         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4768         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4769         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4770         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4771         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4772         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4773         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4774         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4775         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4776         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4777         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4778         [SVM_EXIT_INTR]                         = intr_interception,
4779         [SVM_EXIT_NMI]                          = nmi_interception,
4780         [SVM_EXIT_SMI]                          = nop_on_interception,
4781         [SVM_EXIT_INIT]                         = nop_on_interception,
4782         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4783         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4784         [SVM_EXIT_CPUID]                        = cpuid_interception,
4785         [SVM_EXIT_IRET]                         = iret_interception,
4786         [SVM_EXIT_INVD]                         = emulate_on_interception,
4787         [SVM_EXIT_PAUSE]                        = pause_interception,
4788         [SVM_EXIT_HLT]                          = halt_interception,
4789         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4790         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4791         [SVM_EXIT_IOIO]                         = io_interception,
4792         [SVM_EXIT_MSR]                          = msr_interception,
4793         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4794         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4795         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4796         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4797         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4798         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4799         [SVM_EXIT_STGI]                         = stgi_interception,
4800         [SVM_EXIT_CLGI]                         = clgi_interception,
4801         [SVM_EXIT_SKINIT]                       = skinit_interception,
4802         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4803         [SVM_EXIT_MONITOR]                      = monitor_interception,
4804         [SVM_EXIT_MWAIT]                        = mwait_interception,
4805         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4806         [SVM_EXIT_NPF]                          = npf_interception,
4807         [SVM_EXIT_RSM]                          = rsm_interception,
4808         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4809         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4810 };
4811
4812 static void dump_vmcb(struct kvm_vcpu *vcpu)
4813 {
4814         struct vcpu_svm *svm = to_svm(vcpu);
4815         struct vmcb_control_area *control = &svm->vmcb->control;
4816         struct vmcb_save_area *save = &svm->vmcb->save;
4817
4818         pr_err("VMCB Control Area:\n");
4819         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4820         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4821         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4822         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4823         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4824         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4825         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4826         pr_err("%-20s%d\n", "pause filter threshold:",
4827                control->pause_filter_thresh);
4828         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4829         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4830         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4831         pr_err("%-20s%d\n", "asid:", control->asid);
4832         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4833         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4834         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4835         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4836         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4837         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4838         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4839         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4840         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4841         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4842         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4843         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4844         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4845         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4846         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4847         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4848         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4849         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4850         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4851         pr_err("VMCB State Save Area:\n");
4852         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4853                "es:",
4854                save->es.selector, save->es.attrib,
4855                save->es.limit, save->es.base);
4856         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4857                "cs:",
4858                save->cs.selector, save->cs.attrib,
4859                save->cs.limit, save->cs.base);
4860         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4861                "ss:",
4862                save->ss.selector, save->ss.attrib,
4863                save->ss.limit, save->ss.base);
4864         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4865                "ds:",
4866                save->ds.selector, save->ds.attrib,
4867                save->ds.limit, save->ds.base);
4868         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4869                "fs:",
4870                save->fs.selector, save->fs.attrib,
4871                save->fs.limit, save->fs.base);
4872         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4873                "gs:",
4874                save->gs.selector, save->gs.attrib,
4875                save->gs.limit, save->gs.base);
4876         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4877                "gdtr:",
4878                save->gdtr.selector, save->gdtr.attrib,
4879                save->gdtr.limit, save->gdtr.base);
4880         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4881                "ldtr:",
4882                save->ldtr.selector, save->ldtr.attrib,
4883                save->ldtr.limit, save->ldtr.base);
4884         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4885                "idtr:",
4886                save->idtr.selector, save->idtr.attrib,
4887                save->idtr.limit, save->idtr.base);
4888         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4889                "tr:",
4890                save->tr.selector, save->tr.attrib,
4891                save->tr.limit, save->tr.base);
4892         pr_err("cpl:            %d                efer:         %016llx\n",
4893                 save->cpl, save->efer);
4894         pr_err("%-15s %016llx %-13s %016llx\n",
4895                "cr0:", save->cr0, "cr2:", save->cr2);
4896         pr_err("%-15s %016llx %-13s %016llx\n",
4897                "cr3:", save->cr3, "cr4:", save->cr4);
4898         pr_err("%-15s %016llx %-13s %016llx\n",
4899                "dr6:", save->dr6, "dr7:", save->dr7);
4900         pr_err("%-15s %016llx %-13s %016llx\n",
4901                "rip:", save->rip, "rflags:", save->rflags);
4902         pr_err("%-15s %016llx %-13s %016llx\n",
4903                "rsp:", save->rsp, "rax:", save->rax);
4904         pr_err("%-15s %016llx %-13s %016llx\n",
4905                "star:", save->star, "lstar:", save->lstar);
4906         pr_err("%-15s %016llx %-13s %016llx\n",
4907                "cstar:", save->cstar, "sfmask:", save->sfmask);
4908         pr_err("%-15s %016llx %-13s %016llx\n",
4909                "kernel_gs_base:", save->kernel_gs_base,
4910                "sysenter_cs:", save->sysenter_cs);
4911         pr_err("%-15s %016llx %-13s %016llx\n",
4912                "sysenter_esp:", save->sysenter_esp,
4913                "sysenter_eip:", save->sysenter_eip);
4914         pr_err("%-15s %016llx %-13s %016llx\n",
4915                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4916         pr_err("%-15s %016llx %-13s %016llx\n",
4917                "br_from:", save->br_from, "br_to:", save->br_to);
4918         pr_err("%-15s %016llx %-13s %016llx\n",
4919                "excp_from:", save->last_excp_from,
4920                "excp_to:", save->last_excp_to);
4921 }
4922
4923 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4924 {
4925         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4926
4927         *info1 = control->exit_info_1;
4928         *info2 = control->exit_info_2;
4929 }
4930
4931 static int handle_exit(struct kvm_vcpu *vcpu)
4932 {
4933         struct vcpu_svm *svm = to_svm(vcpu);
4934         struct kvm_run *kvm_run = vcpu->run;
4935         u32 exit_code = svm->vmcb->control.exit_code;
4936
4937         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4938
4939         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4940                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4941         if (npt_enabled)
4942                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4943
4944         if (unlikely(svm->nested.exit_required)) {
4945                 nested_svm_vmexit(svm);
4946                 svm->nested.exit_required = false;
4947
4948                 return 1;
4949         }
4950
4951         if (is_guest_mode(vcpu)) {
4952                 int vmexit;
4953
4954                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4955                                         svm->vmcb->control.exit_info_1,
4956                                         svm->vmcb->control.exit_info_2,
4957                                         svm->vmcb->control.exit_int_info,
4958                                         svm->vmcb->control.exit_int_info_err,
4959                                         KVM_ISA_SVM);
4960
4961                 vmexit = nested_svm_exit_special(svm);
4962
4963                 if (vmexit == NESTED_EXIT_CONTINUE)
4964                         vmexit = nested_svm_exit_handled(svm);
4965
4966                 if (vmexit == NESTED_EXIT_DONE)
4967                         return 1;
4968         }
4969
4970         svm_complete_interrupts(svm);
4971
4972         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4973                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4974                 kvm_run->fail_entry.hardware_entry_failure_reason
4975                         = svm->vmcb->control.exit_code;
4976                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4977                 dump_vmcb(vcpu);
4978                 return 0;
4979         }
4980
4981         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4982             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4983             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4984             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4985                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4986                        "exit_code 0x%x\n",
4987                        __func__, svm->vmcb->control.exit_int_info,
4988                        exit_code);
4989
4990         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4991             || !svm_exit_handlers[exit_code]) {
4992                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4993                 kvm_queue_exception(vcpu, UD_VECTOR);
4994                 return 1;
4995         }
4996
4997         return svm_exit_handlers[exit_code](svm);
4998 }
4999
5000 static void reload_tss(struct kvm_vcpu *vcpu)
5001 {
5002         int cpu = raw_smp_processor_id();
5003
5004         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5005         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5006         load_TR_desc();
5007 }
5008
5009 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5010 {
5011         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5012         int asid = sev_get_asid(svm->vcpu.kvm);
5013
5014         /* Assign the asid allocated with this SEV guest */
5015         svm->vmcb->control.asid = asid;
5016
5017         /*
5018          * Flush guest TLB:
5019          *
5020          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5021          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5022          */
5023         if (sd->sev_vmcbs[asid] == svm->vmcb &&
5024             svm->last_cpu == cpu)
5025                 return;
5026
5027         svm->last_cpu = cpu;
5028         sd->sev_vmcbs[asid] = svm->vmcb;
5029         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5030         mark_dirty(svm->vmcb, VMCB_ASID);
5031 }
5032
5033 static void pre_svm_run(struct vcpu_svm *svm)
5034 {
5035         int cpu = raw_smp_processor_id();
5036
5037         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5038
5039         if (sev_guest(svm->vcpu.kvm))
5040                 return pre_sev_run(svm, cpu);
5041
5042         /* FIXME: handle wraparound of asid_generation */
5043         if (svm->asid_generation != sd->asid_generation)
5044                 new_asid(svm, sd);
5045 }
5046
5047 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5048 {
5049         struct vcpu_svm *svm = to_svm(vcpu);
5050
5051         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5052         vcpu->arch.hflags |= HF_NMI_MASK;
5053         set_intercept(svm, INTERCEPT_IRET);
5054         ++vcpu->stat.nmi_injections;
5055 }
5056
5057 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5058 {
5059         struct vmcb_control_area *control;
5060
5061         /* The following fields are ignored when AVIC is enabled */
5062         control = &svm->vmcb->control;
5063         control->int_vector = irq;
5064         control->int_ctl &= ~V_INTR_PRIO_MASK;
5065         control->int_ctl |= V_IRQ_MASK |
5066                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5067         mark_dirty(svm->vmcb, VMCB_INTR);
5068 }
5069
5070 static void svm_set_irq(struct kvm_vcpu *vcpu)
5071 {
5072         struct vcpu_svm *svm = to_svm(vcpu);
5073
5074         BUG_ON(!(gif_set(svm)));
5075
5076         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5077         ++vcpu->stat.irq_injections;
5078
5079         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5080                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5081 }
5082
5083 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5084 {
5085         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5086 }
5087
5088 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5089 {
5090         struct vcpu_svm *svm = to_svm(vcpu);
5091
5092         if (svm_nested_virtualize_tpr(vcpu) ||
5093             kvm_vcpu_apicv_active(vcpu))
5094                 return;
5095
5096         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5097
5098         if (irr == -1)
5099                 return;
5100
5101         if (tpr >= irr)
5102                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5103 }
5104
5105 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5106 {
5107         return;
5108 }
5109
5110 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5111 {
5112         return avic && irqchip_split(vcpu->kvm);
5113 }
5114
5115 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5116 {
5117 }
5118
5119 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5120 {
5121 }
5122
5123 /* Note: Currently only used by Hyper-V. */
5124 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5125 {
5126         struct vcpu_svm *svm = to_svm(vcpu);
5127         struct vmcb *vmcb = svm->vmcb;
5128
5129         if (kvm_vcpu_apicv_active(vcpu))
5130                 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5131         else
5132                 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5133         mark_dirty(vmcb, VMCB_AVIC);
5134 }
5135
5136 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5137 {
5138         return;
5139 }
5140
5141 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5142 {
5143         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5144         smp_mb__after_atomic();
5145
5146         if (avic_vcpu_is_running(vcpu))
5147                 wrmsrl(SVM_AVIC_DOORBELL,
5148                        kvm_cpu_get_apicid(vcpu->cpu));
5149         else
5150                 kvm_vcpu_wake_up(vcpu);
5151 }
5152
5153 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5154 {
5155         unsigned long flags;
5156         struct amd_svm_iommu_ir *cur;
5157
5158         spin_lock_irqsave(&svm->ir_list_lock, flags);
5159         list_for_each_entry(cur, &svm->ir_list, node) {
5160                 if (cur->data != pi->ir_data)
5161                         continue;
5162                 list_del(&cur->node);
5163                 kfree(cur);
5164                 break;
5165         }
5166         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5167 }
5168
5169 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5170 {
5171         int ret = 0;
5172         unsigned long flags;
5173         struct amd_svm_iommu_ir *ir;
5174
5175         /**
5176          * In some cases, the existing irte is updaed and re-set,
5177          * so we need to check here if it's already been * added
5178          * to the ir_list.
5179          */
5180         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5181                 struct kvm *kvm = svm->vcpu.kvm;
5182                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5183                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5184                 struct vcpu_svm *prev_svm;
5185
5186                 if (!prev_vcpu) {
5187                         ret = -EINVAL;
5188                         goto out;
5189                 }
5190
5191                 prev_svm = to_svm(prev_vcpu);
5192                 svm_ir_list_del(prev_svm, pi);
5193         }
5194
5195         /**
5196          * Allocating new amd_iommu_pi_data, which will get
5197          * add to the per-vcpu ir_list.
5198          */
5199         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5200         if (!ir) {
5201                 ret = -ENOMEM;
5202                 goto out;
5203         }
5204         ir->data = pi->ir_data;
5205
5206         spin_lock_irqsave(&svm->ir_list_lock, flags);
5207         list_add(&ir->node, &svm->ir_list);
5208         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5209 out:
5210         return ret;
5211 }
5212
5213 /**
5214  * Note:
5215  * The HW cannot support posting multicast/broadcast
5216  * interrupts to a vCPU. So, we still use legacy interrupt
5217  * remapping for these kind of interrupts.
5218  *
5219  * For lowest-priority interrupts, we only support
5220  * those with single CPU as the destination, e.g. user
5221  * configures the interrupts via /proc/irq or uses
5222  * irqbalance to make the interrupts single-CPU.
5223  */
5224 static int
5225 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5226                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5227 {
5228         struct kvm_lapic_irq irq;
5229         struct kvm_vcpu *vcpu = NULL;
5230
5231         kvm_set_msi_irq(kvm, e, &irq);
5232
5233         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5234                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5235                          __func__, irq.vector);
5236                 return -1;
5237         }
5238
5239         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5240                  irq.vector);
5241         *svm = to_svm(vcpu);
5242         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5243         vcpu_info->vector = irq.vector;
5244
5245         return 0;
5246 }
5247
5248 /*
5249  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5250  *
5251  * @kvm: kvm
5252  * @host_irq: host irq of the interrupt
5253  * @guest_irq: gsi of the interrupt
5254  * @set: set or unset PI
5255  * returns 0 on success, < 0 on failure
5256  */
5257 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5258                               uint32_t guest_irq, bool set)
5259 {
5260         struct kvm_kernel_irq_routing_entry *e;
5261         struct kvm_irq_routing_table *irq_rt;
5262         int idx, ret = -EINVAL;
5263
5264         if (!kvm_arch_has_assigned_device(kvm) ||
5265             !irq_remapping_cap(IRQ_POSTING_CAP))
5266                 return 0;
5267
5268         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5269                  __func__, host_irq, guest_irq, set);
5270
5271         idx = srcu_read_lock(&kvm->irq_srcu);
5272         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5273         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5274
5275         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5276                 struct vcpu_data vcpu_info;
5277                 struct vcpu_svm *svm = NULL;
5278
5279                 if (e->type != KVM_IRQ_ROUTING_MSI)
5280                         continue;
5281
5282                 /**
5283                  * Here, we setup with legacy mode in the following cases:
5284                  * 1. When cannot target interrupt to a specific vcpu.
5285                  * 2. Unsetting posted interrupt.
5286                  * 3. APIC virtialization is disabled for the vcpu.
5287                  */
5288                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5289                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5290                         struct amd_iommu_pi_data pi;
5291
5292                         /* Try to enable guest_mode in IRTE */
5293                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5294                                             AVIC_HPA_MASK);
5295                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5296                                                      svm->vcpu.vcpu_id);
5297                         pi.is_guest_mode = true;
5298                         pi.vcpu_data = &vcpu_info;
5299                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5300
5301                         /**
5302                          * Here, we successfully setting up vcpu affinity in
5303                          * IOMMU guest mode. Now, we need to store the posted
5304                          * interrupt information in a per-vcpu ir_list so that
5305                          * we can reference to them directly when we update vcpu
5306                          * scheduling information in IOMMU irte.
5307                          */
5308                         if (!ret && pi.is_guest_mode)
5309                                 svm_ir_list_add(svm, &pi);
5310                 } else {
5311                         /* Use legacy mode in IRTE */
5312                         struct amd_iommu_pi_data pi;
5313
5314                         /**
5315                          * Here, pi is used to:
5316                          * - Tell IOMMU to use legacy mode for this interrupt.
5317                          * - Retrieve ga_tag of prior interrupt remapping data.
5318                          */
5319                         pi.is_guest_mode = false;
5320                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5321
5322                         /**
5323                          * Check if the posted interrupt was previously
5324                          * setup with the guest_mode by checking if the ga_tag
5325                          * was cached. If so, we need to clean up the per-vcpu
5326                          * ir_list.
5327                          */
5328                         if (!ret && pi.prev_ga_tag) {
5329                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5330                                 struct kvm_vcpu *vcpu;
5331
5332                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5333                                 if (vcpu)
5334                                         svm_ir_list_del(to_svm(vcpu), &pi);
5335                         }
5336                 }
5337
5338                 if (!ret && svm) {
5339                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5340                                                  e->gsi, vcpu_info.vector,
5341                                                  vcpu_info.pi_desc_addr, set);
5342                 }
5343
5344                 if (ret < 0) {
5345                         pr_err("%s: failed to update PI IRTE\n", __func__);
5346                         goto out;
5347                 }
5348         }
5349
5350         ret = 0;
5351 out:
5352         srcu_read_unlock(&kvm->irq_srcu, idx);
5353         return ret;
5354 }
5355
5356 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5357 {
5358         struct vcpu_svm *svm = to_svm(vcpu);
5359         struct vmcb *vmcb = svm->vmcb;
5360         int ret;
5361         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5362               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5363         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5364
5365         return ret;
5366 }
5367
5368 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5369 {
5370         struct vcpu_svm *svm = to_svm(vcpu);
5371
5372         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5373 }
5374
5375 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5376 {
5377         struct vcpu_svm *svm = to_svm(vcpu);
5378
5379         if (masked) {
5380                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5381                 set_intercept(svm, INTERCEPT_IRET);
5382         } else {
5383                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5384                 clr_intercept(svm, INTERCEPT_IRET);
5385         }
5386 }
5387
5388 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5389 {
5390         struct vcpu_svm *svm = to_svm(vcpu);
5391         struct vmcb *vmcb = svm->vmcb;
5392         int ret;
5393
5394         if (!gif_set(svm) ||
5395              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5396                 return 0;
5397
5398         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5399
5400         if (is_guest_mode(vcpu))
5401                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5402
5403         return ret;
5404 }
5405
5406 static void enable_irq_window(struct kvm_vcpu *vcpu)
5407 {
5408         struct vcpu_svm *svm = to_svm(vcpu);
5409
5410         if (kvm_vcpu_apicv_active(vcpu))
5411                 return;
5412
5413         /*
5414          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5415          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5416          * get that intercept, this function will be called again though and
5417          * we'll get the vintr intercept. However, if the vGIF feature is
5418          * enabled, the STGI interception will not occur. Enable the irq
5419          * window under the assumption that the hardware will set the GIF.
5420          */
5421         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5422                 svm_set_vintr(svm);
5423                 svm_inject_irq(svm, 0x0);
5424         }
5425 }
5426
5427 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5428 {
5429         struct vcpu_svm *svm = to_svm(vcpu);
5430
5431         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5432             == HF_NMI_MASK)
5433                 return; /* IRET will cause a vm exit */
5434
5435         if (!gif_set(svm)) {
5436                 if (vgif_enabled(svm))
5437                         set_intercept(svm, INTERCEPT_STGI);
5438                 return; /* STGI will cause a vm exit */
5439         }
5440
5441         if (svm->nested.exit_required)
5442                 return; /* we're not going to run the guest yet */
5443
5444         /*
5445          * Something prevents NMI from been injected. Single step over possible
5446          * problem (IRET or exception injection or interrupt shadow)
5447          */
5448         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5449         svm->nmi_singlestep = true;
5450         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5451 }
5452
5453 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5454 {
5455         return 0;
5456 }
5457
5458 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5459 {
5460         return 0;
5461 }
5462
5463 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5464 {
5465         struct vcpu_svm *svm = to_svm(vcpu);
5466
5467         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5468                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5469         else
5470                 svm->asid_generation--;
5471 }
5472
5473 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5474 {
5475         struct vcpu_svm *svm = to_svm(vcpu);
5476
5477         invlpga(gva, svm->vmcb->control.asid);
5478 }
5479
5480 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5481 {
5482 }
5483
5484 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5485 {
5486         struct vcpu_svm *svm = to_svm(vcpu);
5487
5488         if (svm_nested_virtualize_tpr(vcpu))
5489                 return;
5490
5491         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5492                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5493                 kvm_set_cr8(vcpu, cr8);
5494         }
5495 }
5496
5497 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5498 {
5499         struct vcpu_svm *svm = to_svm(vcpu);
5500         u64 cr8;
5501
5502         if (svm_nested_virtualize_tpr(vcpu) ||
5503             kvm_vcpu_apicv_active(vcpu))
5504                 return;
5505
5506         cr8 = kvm_get_cr8(vcpu);
5507         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5508         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5509 }
5510
5511 static void svm_complete_interrupts(struct vcpu_svm *svm)
5512 {
5513         u8 vector;
5514         int type;
5515         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5516         unsigned int3_injected = svm->int3_injected;
5517
5518         svm->int3_injected = 0;
5519
5520         /*
5521          * If we've made progress since setting HF_IRET_MASK, we've
5522          * executed an IRET and can allow NMI injection.
5523          */
5524         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5525             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5526                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5527                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5528         }
5529
5530         svm->vcpu.arch.nmi_injected = false;
5531         kvm_clear_exception_queue(&svm->vcpu);
5532         kvm_clear_interrupt_queue(&svm->vcpu);
5533
5534         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5535                 return;
5536
5537         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5538
5539         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5540         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5541
5542         switch (type) {
5543         case SVM_EXITINTINFO_TYPE_NMI:
5544                 svm->vcpu.arch.nmi_injected = true;
5545                 break;
5546         case SVM_EXITINTINFO_TYPE_EXEPT:
5547                 /*
5548                  * In case of software exceptions, do not reinject the vector,
5549                  * but re-execute the instruction instead. Rewind RIP first
5550                  * if we emulated INT3 before.
5551                  */
5552                 if (kvm_exception_is_soft(vector)) {
5553                         if (vector == BP_VECTOR && int3_injected &&
5554                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5555                                 kvm_rip_write(&svm->vcpu,
5556                                               kvm_rip_read(&svm->vcpu) -
5557                                               int3_injected);
5558                         break;
5559                 }
5560                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5561                         u32 err = svm->vmcb->control.exit_int_info_err;
5562                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5563
5564                 } else
5565                         kvm_requeue_exception(&svm->vcpu, vector);
5566                 break;
5567         case SVM_EXITINTINFO_TYPE_INTR:
5568                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5569                 break;
5570         default:
5571                 break;
5572         }
5573 }
5574
5575 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5576 {
5577         struct vcpu_svm *svm = to_svm(vcpu);
5578         struct vmcb_control_area *control = &svm->vmcb->control;
5579
5580         control->exit_int_info = control->event_inj;
5581         control->exit_int_info_err = control->event_inj_err;
5582         control->event_inj = 0;
5583         svm_complete_interrupts(svm);
5584 }
5585
5586 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5587 {
5588         struct vcpu_svm *svm = to_svm(vcpu);
5589
5590         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5591         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5592         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5593
5594         /*
5595          * A vmexit emulation is required before the vcpu can be executed
5596          * again.
5597          */
5598         if (unlikely(svm->nested.exit_required))
5599                 return;
5600
5601         /*
5602          * Disable singlestep if we're injecting an interrupt/exception.
5603          * We don't want our modified rflags to be pushed on the stack where
5604          * we might not be able to easily reset them if we disabled NMI
5605          * singlestep later.
5606          */
5607         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5608                 /*
5609                  * Event injection happens before external interrupts cause a
5610                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5611                  * is enough to force an immediate vmexit.
5612                  */
5613                 disable_nmi_singlestep(svm);
5614                 smp_send_reschedule(vcpu->cpu);
5615         }
5616
5617         pre_svm_run(svm);
5618
5619         sync_lapic_to_cr8(vcpu);
5620
5621         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5622
5623         clgi();
5624
5625         /*
5626          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5627          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5628          * is no need to worry about the conditional branch over the wrmsr
5629          * being speculatively taken.
5630          */
5631         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5632
5633         local_irq_enable();
5634
5635         asm volatile (
5636                 "push %%" _ASM_BP "; \n\t"
5637                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5638                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5639                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5640                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5641                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5642                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5643 #ifdef CONFIG_X86_64
5644                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5645                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5646                 "mov %c[r10](%[svm]), %%r10 \n\t"
5647                 "mov %c[r11](%[svm]), %%r11 \n\t"
5648                 "mov %c[r12](%[svm]), %%r12 \n\t"
5649                 "mov %c[r13](%[svm]), %%r13 \n\t"
5650                 "mov %c[r14](%[svm]), %%r14 \n\t"
5651                 "mov %c[r15](%[svm]), %%r15 \n\t"
5652 #endif
5653
5654                 /* Enter guest mode */
5655                 "push %%" _ASM_AX " \n\t"
5656                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5657                 __ex("vmload %%" _ASM_AX) "\n\t"
5658                 __ex("vmrun %%" _ASM_AX) "\n\t"
5659                 __ex("vmsave %%" _ASM_AX) "\n\t"
5660                 "pop %%" _ASM_AX " \n\t"
5661
5662                 /* Save guest registers, load host registers */
5663                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5664                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5665                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5666                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5667                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5668                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5669 #ifdef CONFIG_X86_64
5670                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5671                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5672                 "mov %%r10, %c[r10](%[svm]) \n\t"
5673                 "mov %%r11, %c[r11](%[svm]) \n\t"
5674                 "mov %%r12, %c[r12](%[svm]) \n\t"
5675                 "mov %%r13, %c[r13](%[svm]) \n\t"
5676                 "mov %%r14, %c[r14](%[svm]) \n\t"
5677                 "mov %%r15, %c[r15](%[svm]) \n\t"
5678                 /*
5679                 * Clear host registers marked as clobbered to prevent
5680                 * speculative use.
5681                 */
5682                 "xor %%r8d, %%r8d \n\t"
5683                 "xor %%r9d, %%r9d \n\t"
5684                 "xor %%r10d, %%r10d \n\t"
5685                 "xor %%r11d, %%r11d \n\t"
5686                 "xor %%r12d, %%r12d \n\t"
5687                 "xor %%r13d, %%r13d \n\t"
5688                 "xor %%r14d, %%r14d \n\t"
5689                 "xor %%r15d, %%r15d \n\t"
5690 #endif
5691                 "xor %%ebx, %%ebx \n\t"
5692                 "xor %%ecx, %%ecx \n\t"
5693                 "xor %%edx, %%edx \n\t"
5694                 "xor %%esi, %%esi \n\t"
5695                 "xor %%edi, %%edi \n\t"
5696                 "pop %%" _ASM_BP
5697                 :
5698                 : [svm]"a"(svm),
5699                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5700                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5701                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5702                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5703                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5704                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5705                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5706 #ifdef CONFIG_X86_64
5707                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5708                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5709                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5710                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5711                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5712                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5713                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5714                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5715 #endif
5716                 : "cc", "memory"
5717 #ifdef CONFIG_X86_64
5718                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5719                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5720 #else
5721                 , "ebx", "ecx", "edx", "esi", "edi"
5722 #endif
5723                 );
5724
5725         /* Eliminate branch target predictions from guest mode */
5726         vmexit_fill_RSB();
5727
5728 #ifdef CONFIG_X86_64
5729         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5730 #else
5731         loadsegment(fs, svm->host.fs);
5732 #ifndef CONFIG_X86_32_LAZY_GS
5733         loadsegment(gs, svm->host.gs);
5734 #endif
5735 #endif
5736
5737         /*
5738          * We do not use IBRS in the kernel. If this vCPU has used the
5739          * SPEC_CTRL MSR it may have left it on; save the value and
5740          * turn it off. This is much more efficient than blindly adding
5741          * it to the atomic save/restore list. Especially as the former
5742          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5743          *
5744          * For non-nested case:
5745          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5746          * save it.
5747          *
5748          * For nested case:
5749          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5750          * save it.
5751          */
5752         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5753                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5754
5755         reload_tss(vcpu);
5756
5757         local_irq_disable();
5758
5759         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5760
5761         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5762         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5763         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5764         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5765
5766         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5767                 kvm_before_interrupt(&svm->vcpu);
5768
5769         stgi();
5770
5771         /* Any pending NMI will happen here */
5772
5773         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5774                 kvm_after_interrupt(&svm->vcpu);
5775
5776         sync_cr8_to_lapic(vcpu);
5777
5778         svm->next_rip = 0;
5779
5780         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5781
5782         /* if exit due to PF check for async PF */
5783         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5784                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5785
5786         if (npt_enabled) {
5787                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5788                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5789         }
5790
5791         /*
5792          * We need to handle MC intercepts here before the vcpu has a chance to
5793          * change the physical cpu
5794          */
5795         if (unlikely(svm->vmcb->control.exit_code ==
5796                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5797                 svm_handle_mce(svm);
5798
5799         mark_all_clean(svm->vmcb);
5800 }
5801 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5802
5803 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5804 {
5805         struct vcpu_svm *svm = to_svm(vcpu);
5806
5807         svm->vmcb->save.cr3 = __sme_set(root);
5808         mark_dirty(svm->vmcb, VMCB_CR);
5809 }
5810
5811 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5812 {
5813         struct vcpu_svm *svm = to_svm(vcpu);
5814
5815         svm->vmcb->control.nested_cr3 = __sme_set(root);
5816         mark_dirty(svm->vmcb, VMCB_NPT);
5817
5818         /* Also sync guest cr3 here in case we live migrate */
5819         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5820         mark_dirty(svm->vmcb, VMCB_CR);
5821 }
5822
5823 static int is_disabled(void)
5824 {
5825         u64 vm_cr;
5826
5827         rdmsrl(MSR_VM_CR, vm_cr);
5828         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5829                 return 1;
5830
5831         return 0;
5832 }
5833
5834 static void
5835 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5836 {
5837         /*
5838          * Patch in the VMMCALL instruction:
5839          */
5840         hypercall[0] = 0x0f;
5841         hypercall[1] = 0x01;
5842         hypercall[2] = 0xd9;
5843 }
5844
5845 static void svm_check_processor_compat(void *rtn)
5846 {
5847         *(int *)rtn = 0;
5848 }
5849
5850 static bool svm_cpu_has_accelerated_tpr(void)
5851 {
5852         return false;
5853 }
5854
5855 static bool svm_has_emulated_msr(int index)
5856 {
5857         switch (index) {
5858         case MSR_IA32_MCG_EXT_CTL:
5859                 return false;
5860         default:
5861                 break;
5862         }
5863
5864         return true;
5865 }
5866
5867 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5868 {
5869         return 0;
5870 }
5871
5872 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5873 {
5874         struct vcpu_svm *svm = to_svm(vcpu);
5875
5876         /* Update nrips enabled cache */
5877         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5878
5879         if (!kvm_vcpu_apicv_active(vcpu))
5880                 return;
5881
5882         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5883 }
5884
5885 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5886 {
5887         switch (func) {
5888         case 0x1:
5889                 if (avic)
5890                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5891                 break;
5892         case 0x80000001:
5893                 if (nested)
5894                         entry->ecx |= (1 << 2); /* Set SVM bit */
5895                 break;
5896         case 0x8000000A:
5897                 entry->eax = 1; /* SVM revision 1 */
5898                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5899                                    ASID emulation to nested SVM */
5900                 entry->ecx = 0; /* Reserved */
5901                 entry->edx = 0; /* Per default do not support any
5902                                    additional features */
5903
5904                 /* Support next_rip if host supports it */
5905                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5906                         entry->edx |= SVM_FEATURE_NRIP;
5907
5908                 /* Support NPT for the guest if enabled */
5909                 if (npt_enabled)
5910                         entry->edx |= SVM_FEATURE_NPT;
5911
5912                 break;
5913         case 0x8000001F:
5914                 /* Support memory encryption cpuid if host supports it */
5915                 if (boot_cpu_has(X86_FEATURE_SEV))
5916                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5917                                 &entry->ecx, &entry->edx);
5918
5919         }
5920 }
5921
5922 static int svm_get_lpage_level(void)
5923 {
5924         return PT_PDPE_LEVEL;
5925 }
5926
5927 static bool svm_rdtscp_supported(void)
5928 {
5929         return boot_cpu_has(X86_FEATURE_RDTSCP);
5930 }
5931
5932 static bool svm_invpcid_supported(void)
5933 {
5934         return false;
5935 }
5936
5937 static bool svm_mpx_supported(void)
5938 {
5939         return false;
5940 }
5941
5942 static bool svm_xsaves_supported(void)
5943 {
5944         return false;
5945 }
5946
5947 static bool svm_umip_emulated(void)
5948 {
5949         return false;
5950 }
5951
5952 static bool svm_pt_supported(void)
5953 {
5954         return false;
5955 }
5956
5957 static bool svm_has_wbinvd_exit(void)
5958 {
5959         return true;
5960 }
5961
5962 #define PRE_EX(exit)  { .exit_code = (exit), \
5963                         .stage = X86_ICPT_PRE_EXCEPT, }
5964 #define POST_EX(exit) { .exit_code = (exit), \
5965                         .stage = X86_ICPT_POST_EXCEPT, }
5966 #define POST_MEM(exit) { .exit_code = (exit), \
5967                         .stage = X86_ICPT_POST_MEMACCESS, }
5968
5969 static const struct __x86_intercept {
5970         u32 exit_code;
5971         enum x86_intercept_stage stage;
5972 } x86_intercept_map[] = {
5973         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5974         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5975         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5976         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5977         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5978         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5979         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5980         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5981         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5982         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5983         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5984         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5985         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5986         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5987         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5988         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5989         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5990         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5991         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5992         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5993         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5994         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5995         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5996         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5997         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5998         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5999         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
6000         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
6001         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
6002         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
6003         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
6004         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
6005         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
6006         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
6007         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
6008         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
6009         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
6010         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
6011         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
6012         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
6013         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
6014         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
6015         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
6016         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
6017         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
6018         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
6019 };
6020
6021 #undef PRE_EX
6022 #undef POST_EX
6023 #undef POST_MEM
6024
6025 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6026                                struct x86_instruction_info *info,
6027                                enum x86_intercept_stage stage)
6028 {
6029         struct vcpu_svm *svm = to_svm(vcpu);
6030         int vmexit, ret = X86EMUL_CONTINUE;
6031         struct __x86_intercept icpt_info;
6032         struct vmcb *vmcb = svm->vmcb;
6033
6034         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6035                 goto out;
6036
6037         icpt_info = x86_intercept_map[info->intercept];
6038
6039         if (stage != icpt_info.stage)
6040                 goto out;
6041
6042         switch (icpt_info.exit_code) {
6043         case SVM_EXIT_READ_CR0:
6044                 if (info->intercept == x86_intercept_cr_read)
6045                         icpt_info.exit_code += info->modrm_reg;
6046                 break;
6047         case SVM_EXIT_WRITE_CR0: {
6048                 unsigned long cr0, val;
6049                 u64 intercept;
6050
6051                 if (info->intercept == x86_intercept_cr_write)
6052                         icpt_info.exit_code += info->modrm_reg;
6053
6054                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6055                     info->intercept == x86_intercept_clts)
6056                         break;
6057
6058                 intercept = svm->nested.intercept;
6059
6060                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6061                         break;
6062
6063                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6064                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6065
6066                 if (info->intercept == x86_intercept_lmsw) {
6067                         cr0 &= 0xfUL;
6068                         val &= 0xfUL;
6069                         /* lmsw can't clear PE - catch this here */
6070                         if (cr0 & X86_CR0_PE)
6071                                 val |= X86_CR0_PE;
6072                 }
6073
6074                 if (cr0 ^ val)
6075                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6076
6077                 break;
6078         }
6079         case SVM_EXIT_READ_DR0:
6080         case SVM_EXIT_WRITE_DR0:
6081                 icpt_info.exit_code += info->modrm_reg;
6082                 break;
6083         case SVM_EXIT_MSR:
6084                 if (info->intercept == x86_intercept_wrmsr)
6085                         vmcb->control.exit_info_1 = 1;
6086                 else
6087                         vmcb->control.exit_info_1 = 0;
6088                 break;
6089         case SVM_EXIT_PAUSE:
6090                 /*
6091                  * We get this for NOP only, but pause
6092                  * is rep not, check this here
6093                  */
6094                 if (info->rep_prefix != REPE_PREFIX)
6095                         goto out;
6096                 break;
6097         case SVM_EXIT_IOIO: {
6098                 u64 exit_info;
6099                 u32 bytes;
6100
6101                 if (info->intercept == x86_intercept_in ||
6102                     info->intercept == x86_intercept_ins) {
6103                         exit_info = ((info->src_val & 0xffff) << 16) |
6104                                 SVM_IOIO_TYPE_MASK;
6105                         bytes = info->dst_bytes;
6106                 } else {
6107                         exit_info = (info->dst_val & 0xffff) << 16;
6108                         bytes = info->src_bytes;
6109                 }
6110
6111                 if (info->intercept == x86_intercept_outs ||
6112                     info->intercept == x86_intercept_ins)
6113                         exit_info |= SVM_IOIO_STR_MASK;
6114
6115                 if (info->rep_prefix)
6116                         exit_info |= SVM_IOIO_REP_MASK;
6117
6118                 bytes = min(bytes, 4u);
6119
6120                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6121
6122                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6123
6124                 vmcb->control.exit_info_1 = exit_info;
6125                 vmcb->control.exit_info_2 = info->next_rip;
6126
6127                 break;
6128         }
6129         default:
6130                 break;
6131         }
6132
6133         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6134         if (static_cpu_has(X86_FEATURE_NRIPS))
6135                 vmcb->control.next_rip  = info->next_rip;
6136         vmcb->control.exit_code = icpt_info.exit_code;
6137         vmexit = nested_svm_exit_handled(svm);
6138
6139         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6140                                            : X86EMUL_CONTINUE;
6141
6142 out:
6143         return ret;
6144 }
6145
6146 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6147 {
6148         local_irq_enable();
6149         /*
6150          * We must have an instruction with interrupts enabled, so
6151          * the timer interrupt isn't delayed by the interrupt shadow.
6152          */
6153         asm("nop");
6154         local_irq_disable();
6155 }
6156
6157 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6158 {
6159         if (pause_filter_thresh)
6160                 shrink_ple_window(vcpu);
6161 }
6162
6163 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6164 {
6165         if (avic_handle_apic_id_update(vcpu) != 0)
6166                 return;
6167         avic_handle_dfr_update(vcpu);
6168         avic_handle_ldr_update(vcpu);
6169 }
6170
6171 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6172 {
6173         /* [63:9] are reserved. */
6174         vcpu->arch.mcg_cap &= 0x1ff;
6175 }
6176
6177 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6178 {
6179         struct vcpu_svm *svm = to_svm(vcpu);
6180
6181         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6182         if (!gif_set(svm))
6183                 return 0;
6184
6185         if (is_guest_mode(&svm->vcpu) &&
6186             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6187                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6188                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6189                 svm->nested.exit_required = true;
6190                 return 0;
6191         }
6192
6193         return 1;
6194 }
6195
6196 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6197 {
6198         struct vcpu_svm *svm = to_svm(vcpu);
6199         int ret;
6200
6201         if (is_guest_mode(vcpu)) {
6202                 /* FED8h - SVM Guest */
6203                 put_smstate(u64, smstate, 0x7ed8, 1);
6204                 /* FEE0h - SVM Guest VMCB Physical Address */
6205                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6206
6207                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6208                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6209                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6210
6211                 ret = nested_svm_vmexit(svm);
6212                 if (ret)
6213                         return ret;
6214         }
6215         return 0;
6216 }
6217
6218 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6219 {
6220         struct vcpu_svm *svm = to_svm(vcpu);
6221         struct vmcb *nested_vmcb;
6222         struct page *page;
6223         struct {
6224                 u64 guest;
6225                 u64 vmcb;
6226         } svm_state_save;
6227         int ret;
6228
6229         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6230                                   sizeof(svm_state_save));
6231         if (ret)
6232                 return ret;
6233
6234         if (svm_state_save.guest) {
6235                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6236                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6237                 if (nested_vmcb)
6238                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6239                 else
6240                         ret = 1;
6241                 vcpu->arch.hflags |= HF_SMM_MASK;
6242         }
6243         return ret;
6244 }
6245
6246 static int enable_smi_window(struct kvm_vcpu *vcpu)
6247 {
6248         struct vcpu_svm *svm = to_svm(vcpu);
6249
6250         if (!gif_set(svm)) {
6251                 if (vgif_enabled(svm))
6252                         set_intercept(svm, INTERCEPT_STGI);
6253                 /* STGI will cause a vm exit */
6254                 return 1;
6255         }
6256         return 0;
6257 }
6258
6259 static int sev_asid_new(void)
6260 {
6261         int pos;
6262
6263         /*
6264          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6265          */
6266         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6267         if (pos >= max_sev_asid)
6268                 return -EBUSY;
6269
6270         set_bit(pos, sev_asid_bitmap);
6271         return pos + 1;
6272 }
6273
6274 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6275 {
6276         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6277         int asid, ret;
6278
6279         ret = -EBUSY;
6280         if (unlikely(sev->active))
6281                 return ret;
6282
6283         asid = sev_asid_new();
6284         if (asid < 0)
6285                 return ret;
6286
6287         ret = sev_platform_init(&argp->error);
6288         if (ret)
6289                 goto e_free;
6290
6291         sev->active = true;
6292         sev->asid = asid;
6293         INIT_LIST_HEAD(&sev->regions_list);
6294
6295         return 0;
6296
6297 e_free:
6298         __sev_asid_free(asid);
6299         return ret;
6300 }
6301
6302 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6303 {
6304         struct sev_data_activate *data;
6305         int asid = sev_get_asid(kvm);
6306         int ret;
6307
6308         wbinvd_on_all_cpus();
6309
6310         ret = sev_guest_df_flush(error);
6311         if (ret)
6312                 return ret;
6313
6314         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6315         if (!data)
6316                 return -ENOMEM;
6317
6318         /* activate ASID on the given handle */
6319         data->handle = handle;
6320         data->asid   = asid;
6321         ret = sev_guest_activate(data, error);
6322         kfree(data);
6323
6324         return ret;
6325 }
6326
6327 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6328 {
6329         struct fd f;
6330         int ret;
6331
6332         f = fdget(fd);
6333         if (!f.file)
6334                 return -EBADF;
6335
6336         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6337
6338         fdput(f);
6339         return ret;
6340 }
6341
6342 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6343 {
6344         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6345
6346         return __sev_issue_cmd(sev->fd, id, data, error);
6347 }
6348
6349 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6350 {
6351         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6352         struct sev_data_launch_start *start;
6353         struct kvm_sev_launch_start params;
6354         void *dh_blob, *session_blob;
6355         int *error = &argp->error;
6356         int ret;
6357
6358         if (!sev_guest(kvm))
6359                 return -ENOTTY;
6360
6361         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6362                 return -EFAULT;
6363
6364         start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6365         if (!start)
6366                 return -ENOMEM;
6367
6368         dh_blob = NULL;
6369         if (params.dh_uaddr) {
6370                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6371                 if (IS_ERR(dh_blob)) {
6372                         ret = PTR_ERR(dh_blob);
6373                         goto e_free;
6374                 }
6375
6376                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6377                 start->dh_cert_len = params.dh_len;
6378         }
6379
6380         session_blob = NULL;
6381         if (params.session_uaddr) {
6382                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6383                 if (IS_ERR(session_blob)) {
6384                         ret = PTR_ERR(session_blob);
6385                         goto e_free_dh;
6386                 }
6387
6388                 start->session_address = __sme_set(__pa(session_blob));
6389                 start->session_len = params.session_len;
6390         }
6391
6392         start->handle = params.handle;
6393         start->policy = params.policy;
6394
6395         /* create memory encryption context */
6396         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6397         if (ret)
6398                 goto e_free_session;
6399
6400         /* Bind ASID to this guest */
6401         ret = sev_bind_asid(kvm, start->handle, error);
6402         if (ret)
6403                 goto e_free_session;
6404
6405         /* return handle to userspace */
6406         params.handle = start->handle;
6407         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6408                 sev_unbind_asid(kvm, start->handle);
6409                 ret = -EFAULT;
6410                 goto e_free_session;
6411         }
6412
6413         sev->handle = start->handle;
6414         sev->fd = argp->sev_fd;
6415
6416 e_free_session:
6417         kfree(session_blob);
6418 e_free_dh:
6419         kfree(dh_blob);
6420 e_free:
6421         kfree(start);
6422         return ret;
6423 }
6424
6425 static int get_num_contig_pages(int idx, struct page **inpages,
6426                                 unsigned long npages)
6427 {
6428         unsigned long paddr, next_paddr;
6429         int i = idx + 1, pages = 1;
6430
6431         /* find the number of contiguous pages starting from idx */
6432         paddr = __sme_page_pa(inpages[idx]);
6433         while (i < npages) {
6434                 next_paddr = __sme_page_pa(inpages[i++]);
6435                 if ((paddr + PAGE_SIZE) == next_paddr) {
6436                         pages++;
6437                         paddr = next_paddr;
6438                         continue;
6439                 }
6440                 break;
6441         }
6442
6443         return pages;
6444 }
6445
6446 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6447 {
6448         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6449         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6450         struct kvm_sev_launch_update_data params;
6451         struct sev_data_launch_update_data *data;
6452         struct page **inpages;
6453         int i, ret, pages;
6454
6455         if (!sev_guest(kvm))
6456                 return -ENOTTY;
6457
6458         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6459                 return -EFAULT;
6460
6461         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6462         if (!data)
6463                 return -ENOMEM;
6464
6465         vaddr = params.uaddr;
6466         size = params.len;
6467         vaddr_end = vaddr + size;
6468
6469         /* Lock the user memory. */
6470         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6471         if (!inpages) {
6472                 ret = -ENOMEM;
6473                 goto e_free;
6474         }
6475
6476         /*
6477          * The LAUNCH_UPDATE command will perform in-place encryption of the
6478          * memory content (i.e it will write the same memory region with C=1).
6479          * It's possible that the cache may contain the data with C=0, i.e.,
6480          * unencrypted so invalidate it first.
6481          */
6482         sev_clflush_pages(inpages, npages);
6483
6484         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6485                 int offset, len;
6486
6487                 /*
6488                  * If the user buffer is not page-aligned, calculate the offset
6489                  * within the page.
6490                  */
6491                 offset = vaddr & (PAGE_SIZE - 1);
6492
6493                 /* Calculate the number of pages that can be encrypted in one go. */
6494                 pages = get_num_contig_pages(i, inpages, npages);
6495
6496                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6497
6498                 data->handle = sev->handle;
6499                 data->len = len;
6500                 data->address = __sme_page_pa(inpages[i]) + offset;
6501                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6502                 if (ret)
6503                         goto e_unpin;
6504
6505                 size -= len;
6506                 next_vaddr = vaddr + len;
6507         }
6508
6509 e_unpin:
6510         /* content of memory is updated, mark pages dirty */
6511         for (i = 0; i < npages; i++) {
6512                 set_page_dirty_lock(inpages[i]);
6513                 mark_page_accessed(inpages[i]);
6514         }
6515         /* unlock the user pages */
6516         sev_unpin_memory(kvm, inpages, npages);
6517 e_free:
6518         kfree(data);
6519         return ret;
6520 }
6521
6522 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6523 {
6524         void __user *measure = (void __user *)(uintptr_t)argp->data;
6525         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6526         struct sev_data_launch_measure *data;
6527         struct kvm_sev_launch_measure params;
6528         void __user *p = NULL;
6529         void *blob = NULL;
6530         int ret;
6531
6532         if (!sev_guest(kvm))
6533                 return -ENOTTY;
6534
6535         if (copy_from_user(&params, measure, sizeof(params)))
6536                 return -EFAULT;
6537
6538         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6539         if (!data)
6540                 return -ENOMEM;
6541
6542         /* User wants to query the blob length */
6543         if (!params.len)
6544                 goto cmd;
6545
6546         p = (void __user *)(uintptr_t)params.uaddr;
6547         if (p) {
6548                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6549                         ret = -EINVAL;
6550                         goto e_free;
6551                 }
6552
6553                 ret = -ENOMEM;
6554                 blob = kmalloc(params.len, GFP_KERNEL);
6555                 if (!blob)
6556                         goto e_free;
6557
6558                 data->address = __psp_pa(blob);
6559                 data->len = params.len;
6560         }
6561
6562 cmd:
6563         data->handle = sev->handle;
6564         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6565
6566         /*
6567          * If we query the session length, FW responded with expected data.
6568          */
6569         if (!params.len)
6570                 goto done;
6571
6572         if (ret)
6573                 goto e_free_blob;
6574
6575         if (blob) {
6576                 if (copy_to_user(p, blob, params.len))
6577                         ret = -EFAULT;
6578         }
6579
6580 done:
6581         params.len = data->len;
6582         if (copy_to_user(measure, &params, sizeof(params)))
6583                 ret = -EFAULT;
6584 e_free_blob:
6585         kfree(blob);
6586 e_free:
6587         kfree(data);
6588         return ret;
6589 }
6590
6591 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6592 {
6593         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6594         struct sev_data_launch_finish *data;
6595         int ret;
6596
6597         if (!sev_guest(kvm))
6598                 return -ENOTTY;
6599
6600         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6601         if (!data)
6602                 return -ENOMEM;
6603
6604         data->handle = sev->handle;
6605         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6606
6607         kfree(data);
6608         return ret;
6609 }
6610
6611 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6612 {
6613         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6614         struct kvm_sev_guest_status params;
6615         struct sev_data_guest_status *data;
6616         int ret;
6617
6618         if (!sev_guest(kvm))
6619                 return -ENOTTY;
6620
6621         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6622         if (!data)
6623                 return -ENOMEM;
6624
6625         data->handle = sev->handle;
6626         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6627         if (ret)
6628                 goto e_free;
6629
6630         params.policy = data->policy;
6631         params.state = data->state;
6632         params.handle = data->handle;
6633
6634         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6635                 ret = -EFAULT;
6636 e_free:
6637         kfree(data);
6638         return ret;
6639 }
6640
6641 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6642                                unsigned long dst, int size,
6643                                int *error, bool enc)
6644 {
6645         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6646         struct sev_data_dbg *data;
6647         int ret;
6648
6649         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6650         if (!data)
6651                 return -ENOMEM;
6652
6653         data->handle = sev->handle;
6654         data->dst_addr = dst;
6655         data->src_addr = src;
6656         data->len = size;
6657
6658         ret = sev_issue_cmd(kvm,
6659                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6660                             data, error);
6661         kfree(data);
6662         return ret;
6663 }
6664
6665 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6666                              unsigned long dst_paddr, int sz, int *err)
6667 {
6668         int offset;
6669
6670         /*
6671          * Its safe to read more than we are asked, caller should ensure that
6672          * destination has enough space.
6673          */
6674         src_paddr = round_down(src_paddr, 16);
6675         offset = src_paddr & 15;
6676         sz = round_up(sz + offset, 16);
6677
6678         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6679 }
6680
6681 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6682                                   unsigned long __user dst_uaddr,
6683                                   unsigned long dst_paddr,
6684                                   int size, int *err)
6685 {
6686         struct page *tpage = NULL;
6687         int ret, offset;
6688
6689         /* if inputs are not 16-byte then use intermediate buffer */
6690         if (!IS_ALIGNED(dst_paddr, 16) ||
6691             !IS_ALIGNED(paddr,     16) ||
6692             !IS_ALIGNED(size,      16)) {
6693                 tpage = (void *)alloc_page(GFP_KERNEL);
6694                 if (!tpage)
6695                         return -ENOMEM;
6696
6697                 dst_paddr = __sme_page_pa(tpage);
6698         }
6699
6700         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6701         if (ret)
6702                 goto e_free;
6703
6704         if (tpage) {
6705                 offset = paddr & 15;
6706                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6707                                  page_address(tpage) + offset, size))
6708                         ret = -EFAULT;
6709         }
6710
6711 e_free:
6712         if (tpage)
6713                 __free_page(tpage);
6714
6715         return ret;
6716 }
6717
6718 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6719                                   unsigned long __user vaddr,
6720                                   unsigned long dst_paddr,
6721                                   unsigned long __user dst_vaddr,
6722                                   int size, int *error)
6723 {
6724         struct page *src_tpage = NULL;
6725         struct page *dst_tpage = NULL;
6726         int ret, len = size;
6727
6728         /* If source buffer is not aligned then use an intermediate buffer */
6729         if (!IS_ALIGNED(vaddr, 16)) {
6730                 src_tpage = alloc_page(GFP_KERNEL);
6731                 if (!src_tpage)
6732                         return -ENOMEM;
6733
6734                 if (copy_from_user(page_address(src_tpage),
6735                                 (void __user *)(uintptr_t)vaddr, size)) {
6736                         __free_page(src_tpage);
6737                         return -EFAULT;
6738                 }
6739
6740                 paddr = __sme_page_pa(src_tpage);
6741         }
6742
6743         /*
6744          *  If destination buffer or length is not aligned then do read-modify-write:
6745          *   - decrypt destination in an intermediate buffer
6746          *   - copy the source buffer in an intermediate buffer
6747          *   - use the intermediate buffer as source buffer
6748          */
6749         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6750                 int dst_offset;
6751
6752                 dst_tpage = alloc_page(GFP_KERNEL);
6753                 if (!dst_tpage) {
6754                         ret = -ENOMEM;
6755                         goto e_free;
6756                 }
6757
6758                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6759                                         __sme_page_pa(dst_tpage), size, error);
6760                 if (ret)
6761                         goto e_free;
6762
6763                 /*
6764                  *  If source is kernel buffer then use memcpy() otherwise
6765                  *  copy_from_user().
6766                  */
6767                 dst_offset = dst_paddr & 15;
6768
6769                 if (src_tpage)
6770                         memcpy(page_address(dst_tpage) + dst_offset,
6771                                page_address(src_tpage), size);
6772                 else {
6773                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6774                                            (void __user *)(uintptr_t)vaddr, size)) {
6775                                 ret = -EFAULT;
6776                                 goto e_free;
6777                         }
6778                 }
6779
6780                 paddr = __sme_page_pa(dst_tpage);
6781                 dst_paddr = round_down(dst_paddr, 16);
6782                 len = round_up(size, 16);
6783         }
6784
6785         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6786
6787 e_free:
6788         if (src_tpage)
6789                 __free_page(src_tpage);
6790         if (dst_tpage)
6791                 __free_page(dst_tpage);
6792         return ret;
6793 }
6794
6795 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6796 {
6797         unsigned long vaddr, vaddr_end, next_vaddr;
6798         unsigned long dst_vaddr;
6799         struct page **src_p, **dst_p;
6800         struct kvm_sev_dbg debug;
6801         unsigned long n;
6802         int ret, size;
6803
6804         if (!sev_guest(kvm))
6805                 return -ENOTTY;
6806
6807         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6808                 return -EFAULT;
6809
6810         vaddr = debug.src_uaddr;
6811         size = debug.len;
6812         vaddr_end = vaddr + size;
6813         dst_vaddr = debug.dst_uaddr;
6814
6815         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6816                 int len, s_off, d_off;
6817
6818                 /* lock userspace source and destination page */
6819                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6820                 if (!src_p)
6821                         return -EFAULT;
6822
6823                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6824                 if (!dst_p) {
6825                         sev_unpin_memory(kvm, src_p, n);
6826                         return -EFAULT;
6827                 }
6828
6829                 /*
6830                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6831                  * memory content (i.e it will write the same memory region with C=1).
6832                  * It's possible that the cache may contain the data with C=0, i.e.,
6833                  * unencrypted so invalidate it first.
6834                  */
6835                 sev_clflush_pages(src_p, 1);
6836                 sev_clflush_pages(dst_p, 1);
6837
6838                 /*
6839                  * Since user buffer may not be page aligned, calculate the
6840                  * offset within the page.
6841                  */
6842                 s_off = vaddr & ~PAGE_MASK;
6843                 d_off = dst_vaddr & ~PAGE_MASK;
6844                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6845
6846                 if (dec)
6847                         ret = __sev_dbg_decrypt_user(kvm,
6848                                                      __sme_page_pa(src_p[0]) + s_off,
6849                                                      dst_vaddr,
6850                                                      __sme_page_pa(dst_p[0]) + d_off,
6851                                                      len, &argp->error);
6852                 else
6853                         ret = __sev_dbg_encrypt_user(kvm,
6854                                                      __sme_page_pa(src_p[0]) + s_off,
6855                                                      vaddr,
6856                                                      __sme_page_pa(dst_p[0]) + d_off,
6857                                                      dst_vaddr,
6858                                                      len, &argp->error);
6859
6860                 sev_unpin_memory(kvm, src_p, 1);
6861                 sev_unpin_memory(kvm, dst_p, 1);
6862
6863                 if (ret)
6864                         goto err;
6865
6866                 next_vaddr = vaddr + len;
6867                 dst_vaddr = dst_vaddr + len;
6868                 size -= len;
6869         }
6870 err:
6871         return ret;
6872 }
6873
6874 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6875 {
6876         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6877         struct sev_data_launch_secret *data;
6878         struct kvm_sev_launch_secret params;
6879         struct page **pages;
6880         void *blob, *hdr;
6881         unsigned long n;
6882         int ret, offset;
6883
6884         if (!sev_guest(kvm))
6885                 return -ENOTTY;
6886
6887         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6888                 return -EFAULT;
6889
6890         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6891         if (!pages)
6892                 return -ENOMEM;
6893
6894         /*
6895          * The secret must be copied into contiguous memory region, lets verify
6896          * that userspace memory pages are contiguous before we issue command.
6897          */
6898         if (get_num_contig_pages(0, pages, n) != n) {
6899                 ret = -EINVAL;
6900                 goto e_unpin_memory;
6901         }
6902
6903         ret = -ENOMEM;
6904         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6905         if (!data)
6906                 goto e_unpin_memory;
6907
6908         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6909         data->guest_address = __sme_page_pa(pages[0]) + offset;
6910         data->guest_len = params.guest_len;
6911
6912         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6913         if (IS_ERR(blob)) {
6914                 ret = PTR_ERR(blob);
6915                 goto e_free;
6916         }
6917
6918         data->trans_address = __psp_pa(blob);
6919         data->trans_len = params.trans_len;
6920
6921         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6922         if (IS_ERR(hdr)) {
6923                 ret = PTR_ERR(hdr);
6924                 goto e_free_blob;
6925         }
6926         data->hdr_address = __psp_pa(hdr);
6927         data->hdr_len = params.hdr_len;
6928
6929         data->handle = sev->handle;
6930         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6931
6932         kfree(hdr);
6933
6934 e_free_blob:
6935         kfree(blob);
6936 e_free:
6937         kfree(data);
6938 e_unpin_memory:
6939         sev_unpin_memory(kvm, pages, n);
6940         return ret;
6941 }
6942
6943 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6944 {
6945         struct kvm_sev_cmd sev_cmd;
6946         int r;
6947
6948         if (!svm_sev_enabled())
6949                 return -ENOTTY;
6950
6951         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6952                 return -EFAULT;
6953
6954         mutex_lock(&kvm->lock);
6955
6956         switch (sev_cmd.id) {
6957         case KVM_SEV_INIT:
6958                 r = sev_guest_init(kvm, &sev_cmd);
6959                 break;
6960         case KVM_SEV_LAUNCH_START:
6961                 r = sev_launch_start(kvm, &sev_cmd);
6962                 break;
6963         case KVM_SEV_LAUNCH_UPDATE_DATA:
6964                 r = sev_launch_update_data(kvm, &sev_cmd);
6965                 break;
6966         case KVM_SEV_LAUNCH_MEASURE:
6967                 r = sev_launch_measure(kvm, &sev_cmd);
6968                 break;
6969         case KVM_SEV_LAUNCH_FINISH:
6970                 r = sev_launch_finish(kvm, &sev_cmd);
6971                 break;
6972         case KVM_SEV_GUEST_STATUS:
6973                 r = sev_guest_status(kvm, &sev_cmd);
6974                 break;
6975         case KVM_SEV_DBG_DECRYPT:
6976                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6977                 break;
6978         case KVM_SEV_DBG_ENCRYPT:
6979                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6980                 break;
6981         case KVM_SEV_LAUNCH_SECRET:
6982                 r = sev_launch_secret(kvm, &sev_cmd);
6983                 break;
6984         default:
6985                 r = -EINVAL;
6986                 goto out;
6987         }
6988
6989         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6990                 r = -EFAULT;
6991
6992 out:
6993         mutex_unlock(&kvm->lock);
6994         return r;
6995 }
6996
6997 static int svm_register_enc_region(struct kvm *kvm,
6998                                    struct kvm_enc_region *range)
6999 {
7000         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7001         struct enc_region *region;
7002         int ret = 0;
7003
7004         if (!sev_guest(kvm))
7005                 return -ENOTTY;
7006
7007         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7008                 return -EINVAL;
7009
7010         region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7011         if (!region)
7012                 return -ENOMEM;
7013
7014         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
7015         if (!region->pages) {
7016                 ret = -ENOMEM;
7017                 goto e_free;
7018         }
7019
7020         /*
7021          * The guest may change the memory encryption attribute from C=0 -> C=1
7022          * or vice versa for this memory range. Lets make sure caches are
7023          * flushed to ensure that guest data gets written into memory with
7024          * correct C-bit.
7025          */
7026         sev_clflush_pages(region->pages, region->npages);
7027
7028         region->uaddr = range->addr;
7029         region->size = range->size;
7030
7031         mutex_lock(&kvm->lock);
7032         list_add_tail(&region->list, &sev->regions_list);
7033         mutex_unlock(&kvm->lock);
7034
7035         return ret;
7036
7037 e_free:
7038         kfree(region);
7039         return ret;
7040 }
7041
7042 static struct enc_region *
7043 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7044 {
7045         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7046         struct list_head *head = &sev->regions_list;
7047         struct enc_region *i;
7048
7049         list_for_each_entry(i, head, list) {
7050                 if (i->uaddr == range->addr &&
7051                     i->size == range->size)
7052                         return i;
7053         }
7054
7055         return NULL;
7056 }
7057
7058
7059 static int svm_unregister_enc_region(struct kvm *kvm,
7060                                      struct kvm_enc_region *range)
7061 {
7062         struct enc_region *region;
7063         int ret;
7064
7065         mutex_lock(&kvm->lock);
7066
7067         if (!sev_guest(kvm)) {
7068                 ret = -ENOTTY;
7069                 goto failed;
7070         }
7071
7072         region = find_enc_region(kvm, range);
7073         if (!region) {
7074                 ret = -EINVAL;
7075                 goto failed;
7076         }
7077
7078         __unregister_enc_region_locked(kvm, region);
7079
7080         mutex_unlock(&kvm->lock);
7081         return 0;
7082
7083 failed:
7084         mutex_unlock(&kvm->lock);
7085         return ret;
7086 }
7087
7088 static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
7089 {
7090         /* Not supported */
7091         return 0;
7092 }
7093
7094 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7095                                    uint16_t *vmcs_version)
7096 {
7097         /* Intel-only feature */
7098         return -ENODEV;
7099 }
7100
7101 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7102 {
7103         bool is_user, smap;
7104
7105         is_user = svm_get_cpl(vcpu) == 3;
7106         smap = !kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
7107
7108         /*
7109          * Detect and workaround Errata 1096 Fam_17h_00_0Fh
7110          *
7111          * In non SEV guest, hypervisor will be able to read the guest
7112          * memory to decode the instruction pointer when insn_len is zero
7113          * so we return true to indicate that decoding is possible.
7114          *
7115          * But in the SEV guest, the guest memory is encrypted with the
7116          * guest specific key and hypervisor will not be able to decode the
7117          * instruction pointer so we will not able to workaround it. Lets
7118          * print the error and request to kill the guest.
7119          */
7120         if (is_user && smap) {
7121                 if (!sev_guest(vcpu->kvm))
7122                         return true;
7123
7124                 pr_err_ratelimited("KVM: Guest triggered AMD Erratum 1096\n");
7125                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7126         }
7127
7128         return false;
7129 }
7130
7131 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7132         .cpu_has_kvm_support = has_svm,
7133         .disabled_by_bios = is_disabled,
7134         .hardware_setup = svm_hardware_setup,
7135         .hardware_unsetup = svm_hardware_unsetup,
7136         .check_processor_compatibility = svm_check_processor_compat,
7137         .hardware_enable = svm_hardware_enable,
7138         .hardware_disable = svm_hardware_disable,
7139         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7140         .has_emulated_msr = svm_has_emulated_msr,
7141
7142         .vcpu_create = svm_create_vcpu,
7143         .vcpu_free = svm_free_vcpu,
7144         .vcpu_reset = svm_vcpu_reset,
7145
7146         .vm_alloc = svm_vm_alloc,
7147         .vm_free = svm_vm_free,
7148         .vm_init = avic_vm_init,
7149         .vm_destroy = svm_vm_destroy,
7150
7151         .prepare_guest_switch = svm_prepare_guest_switch,
7152         .vcpu_load = svm_vcpu_load,
7153         .vcpu_put = svm_vcpu_put,
7154         .vcpu_blocking = svm_vcpu_blocking,
7155         .vcpu_unblocking = svm_vcpu_unblocking,
7156
7157         .update_bp_intercept = update_bp_intercept,
7158         .get_msr_feature = svm_get_msr_feature,
7159         .get_msr = svm_get_msr,
7160         .set_msr = svm_set_msr,
7161         .get_segment_base = svm_get_segment_base,
7162         .get_segment = svm_get_segment,
7163         .set_segment = svm_set_segment,
7164         .get_cpl = svm_get_cpl,
7165         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7166         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7167         .decache_cr3 = svm_decache_cr3,
7168         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7169         .set_cr0 = svm_set_cr0,
7170         .set_cr3 = svm_set_cr3,
7171         .set_cr4 = svm_set_cr4,
7172         .set_efer = svm_set_efer,
7173         .get_idt = svm_get_idt,
7174         .set_idt = svm_set_idt,
7175         .get_gdt = svm_get_gdt,
7176         .set_gdt = svm_set_gdt,
7177         .get_dr6 = svm_get_dr6,
7178         .set_dr6 = svm_set_dr6,
7179         .set_dr7 = svm_set_dr7,
7180         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7181         .cache_reg = svm_cache_reg,
7182         .get_rflags = svm_get_rflags,
7183         .set_rflags = svm_set_rflags,
7184
7185         .tlb_flush = svm_flush_tlb,
7186         .tlb_flush_gva = svm_flush_tlb_gva,
7187
7188         .run = svm_vcpu_run,
7189         .handle_exit = handle_exit,
7190         .skip_emulated_instruction = skip_emulated_instruction,
7191         .set_interrupt_shadow = svm_set_interrupt_shadow,
7192         .get_interrupt_shadow = svm_get_interrupt_shadow,
7193         .patch_hypercall = svm_patch_hypercall,
7194         .set_irq = svm_set_irq,
7195         .set_nmi = svm_inject_nmi,
7196         .queue_exception = svm_queue_exception,
7197         .cancel_injection = svm_cancel_injection,
7198         .interrupt_allowed = svm_interrupt_allowed,
7199         .nmi_allowed = svm_nmi_allowed,
7200         .get_nmi_mask = svm_get_nmi_mask,
7201         .set_nmi_mask = svm_set_nmi_mask,
7202         .enable_nmi_window = enable_nmi_window,
7203         .enable_irq_window = enable_irq_window,
7204         .update_cr8_intercept = update_cr8_intercept,
7205         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7206         .get_enable_apicv = svm_get_enable_apicv,
7207         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7208         .load_eoi_exitmap = svm_load_eoi_exitmap,
7209         .hwapic_irr_update = svm_hwapic_irr_update,
7210         .hwapic_isr_update = svm_hwapic_isr_update,
7211         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7212         .apicv_post_state_restore = avic_post_state_restore,
7213
7214         .set_tss_addr = svm_set_tss_addr,
7215         .set_identity_map_addr = svm_set_identity_map_addr,
7216         .get_tdp_level = get_npt_level,
7217         .get_mt_mask = svm_get_mt_mask,
7218
7219         .get_exit_info = svm_get_exit_info,
7220
7221         .get_lpage_level = svm_get_lpage_level,
7222
7223         .cpuid_update = svm_cpuid_update,
7224
7225         .rdtscp_supported = svm_rdtscp_supported,
7226         .invpcid_supported = svm_invpcid_supported,
7227         .mpx_supported = svm_mpx_supported,
7228         .xsaves_supported = svm_xsaves_supported,
7229         .umip_emulated = svm_umip_emulated,
7230         .pt_supported = svm_pt_supported,
7231
7232         .set_supported_cpuid = svm_set_supported_cpuid,
7233
7234         .has_wbinvd_exit = svm_has_wbinvd_exit,
7235
7236         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7237         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7238
7239         .set_tdp_cr3 = set_tdp_cr3,
7240
7241         .check_intercept = svm_check_intercept,
7242         .handle_external_intr = svm_handle_external_intr,
7243
7244         .request_immediate_exit = __kvm_request_immediate_exit,
7245
7246         .sched_in = svm_sched_in,
7247
7248         .pmu_ops = &amd_pmu_ops,
7249         .deliver_posted_interrupt = svm_deliver_avic_intr,
7250         .update_pi_irte = svm_update_pi_irte,
7251         .setup_mce = svm_setup_mce,
7252
7253         .smi_allowed = svm_smi_allowed,
7254         .pre_enter_smm = svm_pre_enter_smm,
7255         .pre_leave_smm = svm_pre_leave_smm,
7256         .enable_smi_window = enable_smi_window,
7257
7258         .mem_enc_op = svm_mem_enc_op,
7259         .mem_enc_reg_region = svm_register_enc_region,
7260         .mem_enc_unreg_region = svm_unregister_enc_region,
7261
7262         .nested_enable_evmcs = nested_enable_evmcs,
7263         .nested_get_evmcs_version = nested_get_evmcs_version,
7264
7265         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7266 };
7267
7268 static int __init svm_init(void)
7269 {
7270         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7271                         __alignof__(struct vcpu_svm), THIS_MODULE);
7272 }
7273
7274 static void __exit svm_exit(void)
7275 {
7276         kvm_exit();
7277 }
7278
7279 module_init(svm_init)
7280 module_exit(svm_exit)