arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         struct page *avic_logical_id_table_page;
 149         struct page *avic_physical_id_table_page;
 150         struct hlist_node hnode;
 151
 152         struct kvm_sev_info sev_info;
 153 };
 154
 155 struct kvm_vcpu;
 156
 157 struct nested_state {
 158         struct vmcb *hsave;
 159         u64 hsave_msr;
 160         u64 vm_cr_msr;
 161         u64 vmcb;
 162
 163         /* These are the merged vectors */
 164         u32 *msrpm;
 165
 166         /* gpa pointers to the real vectors */
 167         u64 vmcb_msrpm;
 168         u64 vmcb_iopm;
 169
 170         /* A VMEXIT is required but not yet emulated */
 171         bool exit_required;
 172
 173         /* cache for intercepts of the guest */
 174         u32 intercept_cr;
 175         u32 intercept_dr;
 176         u32 intercept_exceptions;
 177         u64 intercept;
 178
 179         /* Nested Paging related state */
 180         u64 nested_cr3;
 181 };
 182
 183 #define MSRPM_OFFSETS   16
 184 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 185
 186 /*
 187  * Set osvw_len to higher value when updated Revision Guides
 188  * are published and we know what the new status bits are
 189  */
 190 static uint64_t osvw_len = 4, osvw_status;
 191
 192 struct vcpu_svm {
 193         struct kvm_vcpu vcpu;
 194         struct vmcb *vmcb;
 195         unsigned long vmcb_pa;
 196         struct svm_cpu_data *svm_data;
 197         uint64_t asid_generation;
 198         uint64_t sysenter_esp;
 199         uint64_t sysenter_eip;
 200         uint64_t tsc_aux;
 201
 202         u64 msr_decfg;
 203
 204         u64 next_rip;
 205
 206         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 207         struct {
 208                 u16 fs;
 209                 u16 gs;
 210                 u16 ldt;
 211                 u64 gs_base;
 212         } host;
 213
 214         u64 spec_ctrl;
 215         /*
 216          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 217          * translated into the appropriate L2_CFG bits on the host to
 218          * perform speculative control.
 219          */
 220         u64 virt_spec_ctrl;
 221
 222         u32 *msrpm;
 223
 224         ulong nmi_iret_rip;
 225
 226         struct nested_state nested;
 227
 228         bool nmi_singlestep;
 229         u64 nmi_singlestep_guest_rflags;
 230
 231         unsigned int3_injected;
 232         unsigned long int3_rip;
 233
 234         /* cached guest cpuid flags for faster access */
 235         bool nrips_enabled      : 1;
 236
 237         u32 ldr_reg;
 238         u32 dfr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT                 31
 266 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 267
 268 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 269 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 270 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 271 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 272
 273 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 274 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 275
 276 #define MSR_INVALID                     0xffffffffU
 277
 278 static const struct svm_direct_access_msrs {
 279         u32 index;   /* Index of the MSR */
 280         bool always; /* True if intercept is always on */
 281 } direct_access_msrs[] = {
 282         { .index = MSR_STAR,                            .always = true  },
 283         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 284 #ifdef CONFIG_X86_64
 285         { .index = MSR_GS_BASE,                         .always = true  },
 286         { .index = MSR_FS_BASE,                         .always = true  },
 287         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 288         { .index = MSR_LSTAR,                           .always = true  },
 289         { .index = MSR_CSTAR,                           .always = true  },
 290         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 291 #endif
 292         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 293         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 294         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 295         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 296         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 297         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 298         { .index = MSR_INVALID,                         .always = false },
 299 };
 300
 301 /* enable NPT for AMD64 and X86 with PAE */
 302 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 303 static bool npt_enabled = true;
 304 #else
 305 static bool npt_enabled;
 306 #endif
 307
 308 /*
 309  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 310  * pause_filter_count: On processors that support Pause filtering(indicated
 311  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 312  *      count value. On VMRUN this value is loaded into an internal counter.
 313  *      Each time a pause instruction is executed, this counter is decremented
 314  *      until it reaches zero at which time a #VMEXIT is generated if pause
 315  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 316  *      Intercept Filtering for more details.
 317  *      This also indicate if ple logic enabled.
 318  *
 319  * pause_filter_thresh: In addition, some processor families support advanced
 320  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 321  *      the amount of time a guest is allowed to execute in a pause loop.
 322  *      In this mode, a 16-bit pause filter threshold field is added in the
 323  *      VMCB. The threshold value is a cycle count that is used to reset the
 324  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 325  *      count value from VMCB into an internal counter. Then, on each pause
 326  *      instruction the hardware checks the elapsed number of cycles since
 327  *      the most recent pause instruction against the pause filter threshold.
 328  *      If the elapsed cycle count is greater than the pause filter threshold,
 329  *      then the internal pause count is reloaded from the VMCB and execution
 330  *      continues. If the elapsed cycle count is less than the pause filter
 331  *      threshold, then the internal pause count is decremented. If the count
 332  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 333  *      triggered. If advanced pause filtering is supported and pause filter
 334  *      threshold field is set to zero, the filter will operate in the simpler,
 335  *      count only mode.
 336  */
 337
 338 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 339 module_param(pause_filter_thresh, ushort, 0444);
 340
 341 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 342 module_param(pause_filter_count, ushort, 0444);
 343
 344 /* Default doubles per-vcpu window every exit. */
 345 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 346 module_param(pause_filter_count_grow, ushort, 0444);
 347
 348 /* Default resets per-vcpu window every exit to pause_filter_count. */
 349 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 350 module_param(pause_filter_count_shrink, ushort, 0444);
 351
 352 /* Default is to compute the maximum so we can never overflow. */
 353 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 354 module_param(pause_filter_count_max, ushort, 0444);
 355
 356 /* allow nested paging (virtualized MMU) for all guests */
 357 static int npt = true;
 358 module_param(npt, int, S_IRUGO);
 359
 360 /* allow nested virtualization in KVM/SVM */
 361 static int nested = true;
 362 module_param(nested, int, S_IRUGO);
 363
 364 /* enable / disable AVIC */
 365 static int avic;
 366 #ifdef CONFIG_X86_LOCAL_APIC
 367 module_param(avic, int, S_IRUGO);
 368 #endif
 369
 370 /* enable/disable Virtual VMLOAD VMSAVE */
 371 static int vls = true;
 372 module_param(vls, int, 0444);
 373
 374 /* enable/disable Virtual GIF */
 375 static int vgif = true;
 376 module_param(vgif, int, 0444);
 377
 378 /* enable/disable SEV support */
 379 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 380 module_param(sev, int, 0444);
 381
 382 static bool __read_mostly dump_invalid_vmcb = 0;
 383 module_param(dump_invalid_vmcb, bool, 0644);
 384
 385 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 386
 387 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 388 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 389 static void svm_complete_interrupts(struct vcpu_svm *svm);
 390
 391 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 392 static int nested_svm_intercept(struct vcpu_svm *svm);
 393 static int nested_svm_vmexit(struct vcpu_svm *svm);
 394 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 395                                       bool has_error_code, u32 error_code);
 396
 397 enum {
 398         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 399                             pause filter count */
 400         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 401         VMCB_ASID,       /* ASID */
 402         VMCB_INTR,       /* int_ctl, int_vector */
 403         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 404         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 405         VMCB_DR,         /* DR6, DR7 */
 406         VMCB_DT,         /* GDT, IDT */
 407         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 408         VMCB_CR2,        /* CR2 only */
 409         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 410         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 411                           * AVIC PHYSICAL_TABLE pointer,
 412                           * AVIC LOGICAL_TABLE pointer
 413                           */
 414         VMCB_DIRTY_MAX,
 415 };
 416
 417 /* TPR and CR2 are always written before VMRUN */
 418 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 419
 420 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 421
 422 static unsigned int max_sev_asid;
 423 static unsigned int min_sev_asid;
 424 static unsigned long *sev_asid_bitmap;
 425 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 426
 427 struct enc_region {
 428         struct list_head list;
 429         unsigned long npages;
 430         struct page **pages;
 431         unsigned long uaddr;
 432         unsigned long size;
 433 };
 434
 435
 436 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 437 {
 438         return container_of(kvm, struct kvm_svm, kvm);
 439 }
 440
 441 static inline bool svm_sev_enabled(void)
 442 {
 443         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 444 }
 445
 446 static inline bool sev_guest(struct kvm *kvm)
 447 {
 448 #ifdef CONFIG_KVM_AMD_SEV
 449         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 450
 451         return sev->active;
 452 #else
 453         return false;
 454 #endif
 455 }
 456
 457 static inline int sev_get_asid(struct kvm *kvm)
 458 {
 459         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 460
 461         return sev->asid;
 462 }
 463
 464 static inline void mark_all_dirty(struct vmcb *vmcb)
 465 {
 466         vmcb->control.clean = 0;
 467 }
 468
 469 static inline void mark_all_clean(struct vmcb *vmcb)
 470 {
 471         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 472                                & ~VMCB_ALWAYS_DIRTY_MASK;
 473 }
 474
 475 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 476 {
 477         vmcb->control.clean &= ~(1 << bit);
 478 }
 479
 480 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 481 {
 482         return container_of(vcpu, struct vcpu_svm, vcpu);
 483 }
 484
 485 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 486 {
 487         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 488         mark_dirty(svm->vmcb, VMCB_AVIC);
 489 }
 490
 491 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 492 {
 493         struct vcpu_svm *svm = to_svm(vcpu);
 494         u64 *entry = svm->avic_physical_id_cache;
 495
 496         if (!entry)
 497                 return false;
 498
 499         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 500 }
 501
 502 static void recalc_intercepts(struct vcpu_svm *svm)
 503 {
 504         struct vmcb_control_area *c, *h;
 505         struct nested_state *g;
 506
 507         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 508
 509         if (!is_guest_mode(&svm->vcpu))
 510                 return;
 511
 512         c = &svm->vmcb->control;
 513         h = &svm->nested.hsave->control;
 514         g = &svm->nested;
 515
 516         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 517         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 518         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 519         c->intercept = h->intercept | g->intercept;
 520 }
 521
 522 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 523 {
 524         if (is_guest_mode(&svm->vcpu))
 525                 return svm->nested.hsave;
 526         else
 527                 return svm->vmcb;
 528 }
 529
 530 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 531 {
 532         struct vmcb *vmcb = get_host_vmcb(svm);
 533
 534         vmcb->control.intercept_cr |= (1U << bit);
 535
 536         recalc_intercepts(svm);
 537 }
 538
 539 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 540 {
 541         struct vmcb *vmcb = get_host_vmcb(svm);
 542
 543         vmcb->control.intercept_cr &= ~(1U << bit);
 544
 545         recalc_intercepts(svm);
 546 }
 547
 548 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 549 {
 550         struct vmcb *vmcb = get_host_vmcb(svm);
 551
 552         return vmcb->control.intercept_cr & (1U << bit);
 553 }
 554
 555 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 556 {
 557         struct vmcb *vmcb = get_host_vmcb(svm);
 558
 559         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 560                 | (1 << INTERCEPT_DR1_READ)
 561                 | (1 << INTERCEPT_DR2_READ)
 562                 | (1 << INTERCEPT_DR3_READ)
 563                 | (1 << INTERCEPT_DR4_READ)
 564                 | (1 << INTERCEPT_DR5_READ)
 565                 | (1 << INTERCEPT_DR6_READ)
 566                 | (1 << INTERCEPT_DR7_READ)
 567                 | (1 << INTERCEPT_DR0_WRITE)
 568                 | (1 << INTERCEPT_DR1_WRITE)
 569                 | (1 << INTERCEPT_DR2_WRITE)
 570                 | (1 << INTERCEPT_DR3_WRITE)
 571                 | (1 << INTERCEPT_DR4_WRITE)
 572                 | (1 << INTERCEPT_DR5_WRITE)
 573                 | (1 << INTERCEPT_DR6_WRITE)
 574                 | (1 << INTERCEPT_DR7_WRITE);
 575
 576         recalc_intercepts(svm);
 577 }
 578
 579 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 580 {
 581         struct vmcb *vmcb = get_host_vmcb(svm);
 582
 583         vmcb->control.intercept_dr = 0;
 584
 585         recalc_intercepts(svm);
 586 }
 587
 588 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 589 {
 590         struct vmcb *vmcb = get_host_vmcb(svm);
 591
 592         vmcb->control.intercept_exceptions |= (1U << bit);
 593
 594         recalc_intercepts(svm);
 595 }
 596
 597 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 598 {
 599         struct vmcb *vmcb = get_host_vmcb(svm);
 600
 601         vmcb->control.intercept_exceptions &= ~(1U << bit);
 602
 603         recalc_intercepts(svm);
 604 }
 605
 606 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 607 {
 608         struct vmcb *vmcb = get_host_vmcb(svm);
 609
 610         vmcb->control.intercept |= (1ULL << bit);
 611
 612         recalc_intercepts(svm);
 613 }
 614
 615 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 616 {
 617         struct vmcb *vmcb = get_host_vmcb(svm);
 618
 619         vmcb->control.intercept &= ~(1ULL << bit);
 620
 621         recalc_intercepts(svm);
 622 }
 623
 624 static inline bool vgif_enabled(struct vcpu_svm *svm)
 625 {
 626         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 627 }
 628
 629 static inline void enable_gif(struct vcpu_svm *svm)
 630 {
 631         if (vgif_enabled(svm))
 632                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 633         else
 634                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 635 }
 636
 637 static inline void disable_gif(struct vcpu_svm *svm)
 638 {
 639         if (vgif_enabled(svm))
 640                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 641         else
 642                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 643 }
 644
 645 static inline bool gif_set(struct vcpu_svm *svm)
 646 {
 647         if (vgif_enabled(svm))
 648                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 649         else
 650                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 651 }
 652
 653 static unsigned long iopm_base;
 654
 655 struct kvm_ldttss_desc {
 656         u16 limit0;
 657         u16 base0;
 658         unsigned base1:8, type:5, dpl:2, p:1;
 659         unsigned limit1:4, zero0:3, g:1, base2:8;
 660         u32 base3;
 661         u32 zero1;
 662 } __attribute__((packed));
 663
 664 struct svm_cpu_data {
 665         int cpu;
 666
 667         u64 asid_generation;
 668         u32 max_asid;
 669         u32 next_asid;
 670         u32 min_asid;
 671         struct kvm_ldttss_desc *tss_desc;
 672
 673         struct page *save_area;
 674         struct vmcb *current_vmcb;
 675
 676         /* index = sev_asid, value = vmcb pointer */
 677         struct vmcb **sev_vmcbs;
 678 };
 679
 680 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 681
 682 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 683
 684 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 685 #define MSRS_RANGE_SIZE 2048
 686 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 687
 688 static u32 svm_msrpm_offset(u32 msr)
 689 {
 690         u32 offset;
 691         int i;
 692
 693         for (i = 0; i < NUM_MSR_MAPS; i++) {
 694                 if (msr < msrpm_ranges[i] ||
 695                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 696                         continue;
 697
 698                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 699                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 700
 701                 /* Now we have the u8 offset - but need the u32 offset */
 702                 return offset / 4;
 703         }
 704
 705         /* MSR not in any range */
 706         return MSR_INVALID;
 707 }
 708
 709 #define MAX_INST_SIZE 15
 710
 711 static inline void clgi(void)
 712 {
 713         asm volatile (__ex("clgi"));
 714 }
 715
 716 static inline void stgi(void)
 717 {
 718         asm volatile (__ex("stgi"));
 719 }
 720
 721 static inline void invlpga(unsigned long addr, u32 asid)
 722 {
 723         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 724 }
 725
 726 static int get_npt_level(struct kvm_vcpu *vcpu)
 727 {
 728 #ifdef CONFIG_X86_64
 729         return PT64_ROOT_4LEVEL;
 730 #else
 731         return PT32E_ROOT_LEVEL;
 732 #endif
 733 }
 734
 735 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 736 {
 737         vcpu->arch.efer = efer;
 738         if (!npt_enabled && !(efer & EFER_LMA))
 739                 efer &= ~EFER_LME;
 740
 741         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 742         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 743 }
 744
 745 static int is_external_interrupt(u32 info)
 746 {
 747         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 748         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 749 }
 750
 751 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 752 {
 753         struct vcpu_svm *svm = to_svm(vcpu);
 754         u32 ret = 0;
 755
 756         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 757                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 758         return ret;
 759 }
 760
 761 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764
 765         if (mask == 0)
 766                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 767         else
 768                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 769
 770 }
 771
 772 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 773 {
 774         struct vcpu_svm *svm = to_svm(vcpu);
 775
 776         if (svm->vmcb->control.next_rip != 0) {
 777                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 778                 svm->next_rip = svm->vmcb->control.next_rip;
 779         }
 780
 781         if (!svm->next_rip) {
 782                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 783                                 EMULATE_DONE)
 784                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 785                 return;
 786         }
 787         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 788                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 789                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 790
 791         kvm_rip_write(vcpu, svm->next_rip);
 792         svm_set_interrupt_shadow(vcpu, 0);
 793 }
 794
 795 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 796 {
 797         struct vcpu_svm *svm = to_svm(vcpu);
 798         unsigned nr = vcpu->arch.exception.nr;
 799         bool has_error_code = vcpu->arch.exception.has_error_code;
 800         bool reinject = vcpu->arch.exception.injected;
 801         u32 error_code = vcpu->arch.exception.error_code;
 802
 803         /*
 804          * If we are within a nested VM we'd better #VMEXIT and let the guest
 805          * handle the exception
 806          */
 807         if (!reinject &&
 808             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 809                 return;
 810
 811         kvm_deliver_exception_payload(&svm->vcpu);
 812
 813         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 814                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 815
 816                 /*
 817                  * For guest debugging where we have to reinject #BP if some
 818                  * INT3 is guest-owned:
 819                  * Emulate nRIP by moving RIP forward. Will fail if injection
 820                  * raises a fault that is not intercepted. Still better than
 821                  * failing in all cases.
 822                  */
 823                 skip_emulated_instruction(&svm->vcpu);
 824                 rip = kvm_rip_read(&svm->vcpu);
 825                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 826                 svm->int3_injected = rip - old_rip;
 827         }
 828
 829         svm->vmcb->control.event_inj = nr
 830                 | SVM_EVTINJ_VALID
 831                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 832                 | SVM_EVTINJ_TYPE_EXEPT;
 833         svm->vmcb->control.event_inj_err = error_code;
 834 }
 835
 836 static void svm_init_erratum_383(void)
 837 {
 838         u32 low, high;
 839         int err;
 840         u64 val;
 841
 842         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 843                 return;
 844
 845         /* Use _safe variants to not break nested virtualization */
 846         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 847         if (err)
 848                 return;
 849
 850         val |= (1ULL << 47);
 851
 852         low  = lower_32_bits(val);
 853         high = upper_32_bits(val);
 854
 855         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 856
 857         erratum_383_found = true;
 858 }
 859
 860 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 861 {
 862         /*
 863          * Guests should see errata 400 and 415 as fixed (assuming that
 864          * HLT and IO instructions are intercepted).
 865          */
 866         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 867         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 868
 869         /*
 870          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 871          * all osvw.status bits inside that length, including bit 0 (which is
 872          * reserved for erratum 298), are valid. However, if host processor's
 873          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 874          * be conservative here and therefore we tell the guest that erratum 298
 875          * is present (because we really don't know).
 876          */
 877         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 878                 vcpu->arch.osvw.status |= 1;
 879 }
 880
 881 static int has_svm(void)
 882 {
 883         const char *msg;
 884
 885         if (!cpu_has_svm(&msg)) {
 886                 printk(KERN_INFO "has_svm: %s\n", msg);
 887                 return 0;
 888         }
 889
 890         return 1;
 891 }
 892
 893 static void svm_hardware_disable(void)
 894 {
 895         /* Make sure we clean up behind us */
 896         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 897                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 898
 899         cpu_svm_disable();
 900
 901         amd_pmu_disable_virt();
 902 }
 903
 904 static int svm_hardware_enable(void)
 905 {
 906
 907         struct svm_cpu_data *sd;
 908         uint64_t efer;
 909         struct desc_struct *gdt;
 910         int me = raw_smp_processor_id();
 911
 912         rdmsrl(MSR_EFER, efer);
 913         if (efer & EFER_SVME)
 914                 return -EBUSY;
 915
 916         if (!has_svm()) {
 917                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 918                 return -EINVAL;
 919         }
 920         sd = per_cpu(svm_data, me);
 921         if (!sd) {
 922                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 923                 return -EINVAL;
 924         }
 925
 926         sd->asid_generation = 1;
 927         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 928         sd->next_asid = sd->max_asid + 1;
 929         sd->min_asid = max_sev_asid + 1;
 930
 931         gdt = get_current_gdt_rw();
 932         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 933
 934         wrmsrl(MSR_EFER, efer | EFER_SVME);
 935
 936         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 937
 938         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 939                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 940                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 941         }
 942
 943
 944         /*
 945          * Get OSVW bits.
 946          *
 947          * Note that it is possible to have a system with mixed processor
 948          * revisions and therefore different OSVW bits. If bits are not the same
 949          * on different processors then choose the worst case (i.e. if erratum
 950          * is present on one processor and not on another then assume that the
 951          * erratum is present everywhere).
 952          */
 953         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 954                 uint64_t len, status = 0;
 955                 int err;
 956
 957                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 958                 if (!err)
 959                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 960                                                       &err);
 961
 962                 if (err)
 963                         osvw_status = osvw_len = 0;
 964                 else {
 965                         if (len < osvw_len)
 966                                 osvw_len = len;
 967                         osvw_status |= status;
 968                         osvw_status &= (1ULL << osvw_len) - 1;
 969                 }
 970         } else
 971                 osvw_status = osvw_len = 0;
 972
 973         svm_init_erratum_383();
 974
 975         amd_pmu_enable_virt();
 976
 977         return 0;
 978 }
 979
 980 static void svm_cpu_uninit(int cpu)
 981 {
 982         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 983
 984         if (!sd)
 985                 return;
 986
 987         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 988         kfree(sd->sev_vmcbs);
 989         __free_page(sd->save_area);
 990         kfree(sd);
 991 }
 992
 993 static int svm_cpu_init(int cpu)
 994 {
 995         struct svm_cpu_data *sd;
 996         int r;
 997
 998         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 999         if (!sd)
1000                 return -ENOMEM;
1001         sd->cpu = cpu;
1002         r = -ENOMEM;
1003         sd->save_area = alloc_page(GFP_KERNEL);
1004         if (!sd->save_area)
1005                 goto err_1;
1006
1007         if (svm_sev_enabled()) {
1008                 r = -ENOMEM;
1009                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1010                                               sizeof(void *),
1011                                               GFP_KERNEL);
1012                 if (!sd->sev_vmcbs)
1013                         goto err_1;
1014         }
1015
1016         per_cpu(svm_data, cpu) = sd;
1017
1018         return 0;
1019
1020 err_1:
1021         kfree(sd);
1022         return r;
1023
1024 }
1025
1026 static bool valid_msr_intercept(u32 index)
1027 {
1028         int i;
1029
1030         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1031                 if (direct_access_msrs[i].index == index)
1032                         return true;
1033
1034         return false;
1035 }
1036
1037 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1038 {
1039         u8 bit_write;
1040         unsigned long tmp;
1041         u32 offset;
1042         u32 *msrpm;
1043
1044         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1045                                       to_svm(vcpu)->msrpm;
1046
1047         offset    = svm_msrpm_offset(msr);
1048         bit_write = 2 * (msr & 0x0f) + 1;
1049         tmp       = msrpm[offset];
1050
1051         BUG_ON(offset == MSR_INVALID);
1052
1053         return !!test_bit(bit_write,  &tmp);
1054 }
1055
1056 static void set_msr_interception(u32 *msrpm, unsigned msr,
1057                                  int read, int write)
1058 {
1059         u8 bit_read, bit_write;
1060         unsigned long tmp;
1061         u32 offset;
1062
1063         /*
1064          * If this warning triggers extend the direct_access_msrs list at the
1065          * beginning of the file
1066          */
1067         WARN_ON(!valid_msr_intercept(msr));
1068
1069         offset    = svm_msrpm_offset(msr);
1070         bit_read  = 2 * (msr & 0x0f);
1071         bit_write = 2 * (msr & 0x0f) + 1;
1072         tmp       = msrpm[offset];
1073
1074         BUG_ON(offset == MSR_INVALID);
1075
1076         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1077         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1078
1079         msrpm[offset] = tmp;
1080 }
1081
1082 static void svm_vcpu_init_msrpm(u32 *msrpm)
1083 {
1084         int i;
1085
1086         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1087
1088         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1089                 if (!direct_access_msrs[i].always)
1090                         continue;
1091
1092                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1093         }
1094 }
1095
1096 static void add_msr_offset(u32 offset)
1097 {
1098         int i;
1099
1100         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1101
1102                 /* Offset already in list? */
1103                 if (msrpm_offsets[i] == offset)
1104                         return;
1105
1106                 /* Slot used by another offset? */
1107                 if (msrpm_offsets[i] != MSR_INVALID)
1108                         continue;
1109
1110                 /* Add offset to list */
1111                 msrpm_offsets[i] = offset;
1112
1113                 return;
1114         }
1115
1116         /*
1117          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1118          * increase MSRPM_OFFSETS in this case.
1119          */
1120         BUG();
1121 }
1122
1123 static void init_msrpm_offsets(void)
1124 {
1125         int i;
1126
1127         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1128
1129         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1130                 u32 offset;
1131
1132                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1133                 BUG_ON(offset == MSR_INVALID);
1134
1135                 add_msr_offset(offset);
1136         }
1137 }
1138
1139 static void svm_enable_lbrv(struct vcpu_svm *svm)
1140 {
1141         u32 *msrpm = svm->msrpm;
1142
1143         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1144         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1145         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1146         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1147         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1148 }
1149
1150 static void svm_disable_lbrv(struct vcpu_svm *svm)
1151 {
1152         u32 *msrpm = svm->msrpm;
1153
1154         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1155         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1156         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1157         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1158         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1159 }
1160
1161 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1162 {
1163         svm->nmi_singlestep = false;
1164
1165         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1166                 /* Clear our flags if they were not set by the guest */
1167                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1168                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1169                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1170                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1171         }
1172 }
1173
1174 /* Note:
1175  * This hash table is used to map VM_ID to a struct kvm_svm,
1176  * when handling AMD IOMMU GALOG notification to schedule in
1177  * a particular vCPU.
1178  */
1179 #define SVM_VM_DATA_HASH_BITS   8
1180 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1181 static u32 next_vm_id = 0;
1182 static bool next_vm_id_wrapped = 0;
1183 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1184
1185 /* Note:
1186  * This function is called from IOMMU driver to notify
1187  * SVM to schedule in a particular vCPU of a particular VM.
1188  */
1189 static int avic_ga_log_notifier(u32 ga_tag)
1190 {
1191         unsigned long flags;
1192         struct kvm_svm *kvm_svm;
1193         struct kvm_vcpu *vcpu = NULL;
1194         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1195         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1196
1197         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1198
1199         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1200         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1201                 if (kvm_svm->avic_vm_id != vm_id)
1202                         continue;
1203                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1204                 break;
1205         }
1206         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1207
1208         /* Note:
1209          * At this point, the IOMMU should have already set the pending
1210          * bit in the vAPIC backing page. So, we just need to schedule
1211          * in the vcpu.
1212          */
1213         if (vcpu)
1214                 kvm_vcpu_wake_up(vcpu);
1215
1216         return 0;
1217 }
1218
1219 static __init int sev_hardware_setup(void)
1220 {
1221         struct sev_user_data_status *status;
1222         int rc;
1223
1224         /* Maximum number of encrypted guests supported simultaneously */
1225         max_sev_asid = cpuid_ecx(0x8000001F);
1226
1227         if (!max_sev_asid)
1228                 return 1;
1229
1230         /* Minimum ASID value that should be used for SEV guest */
1231         min_sev_asid = cpuid_edx(0x8000001F);
1232
1233         /* Initialize SEV ASID bitmap */
1234         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1235         if (!sev_asid_bitmap)
1236                 return 1;
1237
1238         status = kmalloc(sizeof(*status), GFP_KERNEL);
1239         if (!status)
1240                 return 1;
1241
1242         /*
1243          * Check SEV platform status.
1244          *
1245          * PLATFORM_STATUS can be called in any state, if we failed to query
1246          * the PLATFORM status then either PSP firmware does not support SEV
1247          * feature or SEV firmware is dead.
1248          */
1249         rc = sev_platform_status(status, NULL);
1250         if (rc)
1251                 goto err;
1252
1253         pr_info("SEV supported\n");
1254
1255 err:
1256         kfree(status);
1257         return rc;
1258 }
1259
1260 static void grow_ple_window(struct kvm_vcpu *vcpu)
1261 {
1262         struct vcpu_svm *svm = to_svm(vcpu);
1263         struct vmcb_control_area *control = &svm->vmcb->control;
1264         int old = control->pause_filter_count;
1265
1266         control->pause_filter_count = __grow_ple_window(old,
1267                                                         pause_filter_count,
1268                                                         pause_filter_count_grow,
1269                                                         pause_filter_count_max);
1270
1271         if (control->pause_filter_count != old)
1272                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1273
1274         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1275                                   control->pause_filter_count, old);
1276 }
1277
1278 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1279 {
1280         struct vcpu_svm *svm = to_svm(vcpu);
1281         struct vmcb_control_area *control = &svm->vmcb->control;
1282         int old = control->pause_filter_count;
1283
1284         control->pause_filter_count =
1285                                 __shrink_ple_window(old,
1286                                                     pause_filter_count,
1287                                                     pause_filter_count_shrink,
1288                                                     pause_filter_count);
1289         if (control->pause_filter_count != old)
1290                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1291
1292         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1293                                     control->pause_filter_count, old);
1294 }
1295
1296 static __init int svm_hardware_setup(void)
1297 {
1298         int cpu;
1299         struct page *iopm_pages;
1300         void *iopm_va;
1301         int r;
1302
1303         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1304
1305         if (!iopm_pages)
1306                 return -ENOMEM;
1307
1308         iopm_va = page_address(iopm_pages);
1309         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1310         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1311
1312         init_msrpm_offsets();
1313
1314         if (boot_cpu_has(X86_FEATURE_NX))
1315                 kvm_enable_efer_bits(EFER_NX);
1316
1317         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1318                 kvm_enable_efer_bits(EFER_FFXSR);
1319
1320         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1321                 kvm_has_tsc_control = true;
1322                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1323                 kvm_tsc_scaling_ratio_frac_bits = 32;
1324         }
1325
1326         /* Check for pause filtering support */
1327         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1328                 pause_filter_count = 0;
1329                 pause_filter_thresh = 0;
1330         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1331                 pause_filter_thresh = 0;
1332         }
1333
1334         if (nested) {
1335                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1336                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1337         }
1338
1339         if (sev) {
1340                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1341                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1342                         r = sev_hardware_setup();
1343                         if (r)
1344                                 sev = false;
1345                 } else {
1346                         sev = false;
1347                 }
1348         }
1349
1350         for_each_possible_cpu(cpu) {
1351                 r = svm_cpu_init(cpu);
1352                 if (r)
1353                         goto err;
1354         }
1355
1356         if (!boot_cpu_has(X86_FEATURE_NPT))
1357                 npt_enabled = false;
1358
1359         if (npt_enabled && !npt) {
1360                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1361                 npt_enabled = false;
1362         }
1363
1364         if (npt_enabled) {
1365                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1366                 kvm_enable_tdp();
1367         } else
1368                 kvm_disable_tdp();
1369
1370         if (avic) {
1371                 if (!npt_enabled ||
1372                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1373                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1374                         avic = false;
1375                 } else {
1376                         pr_info("AVIC enabled\n");
1377
1378                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1379                 }
1380         }
1381
1382         if (vls) {
1383                 if (!npt_enabled ||
1384                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1385                     !IS_ENABLED(CONFIG_X86_64)) {
1386                         vls = false;
1387                 } else {
1388                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1389                 }
1390         }
1391
1392         if (vgif) {
1393                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1394                         vgif = false;
1395                 else
1396                         pr_info("Virtual GIF supported\n");
1397         }
1398
1399         return 0;
1400
1401 err:
1402         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1403         iopm_base = 0;
1404         return r;
1405 }
1406
1407 static __exit void svm_hardware_unsetup(void)
1408 {
1409         int cpu;
1410
1411         if (svm_sev_enabled())
1412                 bitmap_free(sev_asid_bitmap);
1413
1414         for_each_possible_cpu(cpu)
1415                 svm_cpu_uninit(cpu);
1416
1417         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1418         iopm_base = 0;
1419 }
1420
1421 static void init_seg(struct vmcb_seg *seg)
1422 {
1423         seg->selector = 0;
1424         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1425                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1426         seg->limit = 0xffff;
1427         seg->base = 0;
1428 }
1429
1430 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1431 {
1432         seg->selector = 0;
1433         seg->attrib = SVM_SELECTOR_P_MASK | type;
1434         seg->limit = 0xffff;
1435         seg->base = 0;
1436 }
1437
1438 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1439 {
1440         struct vcpu_svm *svm = to_svm(vcpu);
1441
1442         if (is_guest_mode(vcpu))
1443                 return svm->nested.hsave->control.tsc_offset;
1444
1445         return vcpu->arch.tsc_offset;
1446 }
1447
1448 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1449 {
1450         struct vcpu_svm *svm = to_svm(vcpu);
1451         u64 g_tsc_offset = 0;
1452
1453         if (is_guest_mode(vcpu)) {
1454                 /* Write L1's TSC offset.  */
1455                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1456                                svm->nested.hsave->control.tsc_offset;
1457                 svm->nested.hsave->control.tsc_offset = offset;
1458         }
1459
1460         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1461                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1462                                    offset);
1463
1464         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1465
1466         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1467         return svm->vmcb->control.tsc_offset;
1468 }
1469
1470 static void avic_init_vmcb(struct vcpu_svm *svm)
1471 {
1472         struct vmcb *vmcb = svm->vmcb;
1473         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1474         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1475         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1476         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1477
1478         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1479         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1480         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1481         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1482         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1483 }
1484
1485 static void init_vmcb(struct vcpu_svm *svm)
1486 {
1487         struct vmcb_control_area *control = &svm->vmcb->control;
1488         struct vmcb_save_area *save = &svm->vmcb->save;
1489
1490         svm->vcpu.arch.hflags = 0;
1491
1492         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1493         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1494         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1495         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1496         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1497         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1498         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1499                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1500
1501         set_dr_intercepts(svm);
1502
1503         set_exception_intercept(svm, PF_VECTOR);
1504         set_exception_intercept(svm, UD_VECTOR);
1505         set_exception_intercept(svm, MC_VECTOR);
1506         set_exception_intercept(svm, AC_VECTOR);
1507         set_exception_intercept(svm, DB_VECTOR);
1508         /*
1509          * Guest access to VMware backdoor ports could legitimately
1510          * trigger #GP because of TSS I/O permission bitmap.
1511          * We intercept those #GP and allow access to them anyway
1512          * as VMware does.
1513          */
1514         if (enable_vmware_backdoor)
1515                 set_exception_intercept(svm, GP_VECTOR);
1516
1517         set_intercept(svm, INTERCEPT_INTR);
1518         set_intercept(svm, INTERCEPT_NMI);
1519         set_intercept(svm, INTERCEPT_SMI);
1520         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1521         set_intercept(svm, INTERCEPT_RDPMC);
1522         set_intercept(svm, INTERCEPT_CPUID);
1523         set_intercept(svm, INTERCEPT_INVD);
1524         set_intercept(svm, INTERCEPT_INVLPG);
1525         set_intercept(svm, INTERCEPT_INVLPGA);
1526         set_intercept(svm, INTERCEPT_IOIO_PROT);
1527         set_intercept(svm, INTERCEPT_MSR_PROT);
1528         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1529         set_intercept(svm, INTERCEPT_SHUTDOWN);
1530         set_intercept(svm, INTERCEPT_VMRUN);
1531         set_intercept(svm, INTERCEPT_VMMCALL);
1532         set_intercept(svm, INTERCEPT_VMLOAD);
1533         set_intercept(svm, INTERCEPT_VMSAVE);
1534         set_intercept(svm, INTERCEPT_STGI);
1535         set_intercept(svm, INTERCEPT_CLGI);
1536         set_intercept(svm, INTERCEPT_SKINIT);
1537         set_intercept(svm, INTERCEPT_WBINVD);
1538         set_intercept(svm, INTERCEPT_XSETBV);
1539         set_intercept(svm, INTERCEPT_RSM);
1540
1541         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1542                 set_intercept(svm, INTERCEPT_MONITOR);
1543                 set_intercept(svm, INTERCEPT_MWAIT);
1544         }
1545
1546         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1547                 set_intercept(svm, INTERCEPT_HLT);
1548
1549         control->iopm_base_pa = __sme_set(iopm_base);
1550         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1551         control->int_ctl = V_INTR_MASKING_MASK;
1552
1553         init_seg(&save->es);
1554         init_seg(&save->ss);
1555         init_seg(&save->ds);
1556         init_seg(&save->fs);
1557         init_seg(&save->gs);
1558
1559         save->cs.selector = 0xf000;
1560         save->cs.base = 0xffff0000;
1561         /* Executable/Readable Code Segment */
1562         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1563                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1564         save->cs.limit = 0xffff;
1565
1566         save->gdtr.limit = 0xffff;
1567         save->idtr.limit = 0xffff;
1568
1569         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1570         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1571
1572         svm_set_efer(&svm->vcpu, 0);
1573         save->dr6 = 0xffff0ff0;
1574         kvm_set_rflags(&svm->vcpu, 2);
1575         save->rip = 0x0000fff0;
1576         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1577
1578         /*
1579          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1580          * It also updates the guest-visible cr0 value.
1581          */
1582         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1583         kvm_mmu_reset_context(&svm->vcpu);
1584
1585         save->cr4 = X86_CR4_PAE;
1586         /* rdx = ?? */
1587
1588         if (npt_enabled) {
1589                 /* Setup VMCB for Nested Paging */
1590                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1591                 clr_intercept(svm, INTERCEPT_INVLPG);
1592                 clr_exception_intercept(svm, PF_VECTOR);
1593                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1594                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1595                 save->g_pat = svm->vcpu.arch.pat;
1596                 save->cr3 = 0;
1597                 save->cr4 = 0;
1598         }
1599         svm->asid_generation = 0;
1600
1601         svm->nested.vmcb = 0;
1602         svm->vcpu.arch.hflags = 0;
1603
1604         if (pause_filter_count) {
1605                 control->pause_filter_count = pause_filter_count;
1606                 if (pause_filter_thresh)
1607                         control->pause_filter_thresh = pause_filter_thresh;
1608                 set_intercept(svm, INTERCEPT_PAUSE);
1609         } else {
1610                 clr_intercept(svm, INTERCEPT_PAUSE);
1611         }
1612
1613         if (kvm_vcpu_apicv_active(&svm->vcpu))
1614                 avic_init_vmcb(svm);
1615
1616         /*
1617          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1618          * in VMCB and clear intercepts to avoid #VMEXIT.
1619          */
1620         if (vls) {
1621                 clr_intercept(svm, INTERCEPT_VMLOAD);
1622                 clr_intercept(svm, INTERCEPT_VMSAVE);
1623                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1624         }
1625
1626         if (vgif) {
1627                 clr_intercept(svm, INTERCEPT_STGI);
1628                 clr_intercept(svm, INTERCEPT_CLGI);
1629                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1630         }
1631
1632         if (sev_guest(svm->vcpu.kvm)) {
1633                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1634                 clr_exception_intercept(svm, UD_VECTOR);
1635         }
1636
1637         mark_all_dirty(svm->vmcb);
1638
1639         enable_gif(svm);
1640
1641 }
1642
1643 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1644                                        unsigned int index)
1645 {
1646         u64 *avic_physical_id_table;
1647         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1648
1649         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1650                 return NULL;
1651
1652         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1653
1654         return &avic_physical_id_table[index];
1655 }
1656
1657 /**
1658  * Note:
1659  * AVIC hardware walks the nested page table to check permissions,
1660  * but does not use the SPA address specified in the leaf page
1661  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1662  * field of the VMCB. Therefore, we set up the
1663  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1664  */
1665 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1666 {
1667         struct kvm *kvm = vcpu->kvm;
1668         int ret = 0;
1669
1670         mutex_lock(&kvm->slots_lock);
1671         if (kvm->arch.apic_access_page_done)
1672                 goto out;
1673
1674         ret = __x86_set_memory_region(kvm,
1675                                       APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1676                                       APIC_DEFAULT_PHYS_BASE,
1677                                       PAGE_SIZE);
1678         if (ret)
1679                 goto out;
1680
1681         kvm->arch.apic_access_page_done = true;
1682 out:
1683         mutex_unlock(&kvm->slots_lock);
1684         return ret;
1685 }
1686
1687 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1688 {
1689         int ret;
1690         u64 *entry, new_entry;
1691         int id = vcpu->vcpu_id;
1692         struct vcpu_svm *svm = to_svm(vcpu);
1693
1694         ret = avic_init_access_page(vcpu);
1695         if (ret)
1696                 return ret;
1697
1698         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1699                 return -EINVAL;
1700
1701         if (!svm->vcpu.arch.apic->regs)
1702                 return -EINVAL;
1703
1704         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1705
1706         /* Setting AVIC backing page address in the phy APIC ID table */
1707         entry = avic_get_physical_id_entry(vcpu, id);
1708         if (!entry)
1709                 return -EINVAL;
1710
1711         new_entry = READ_ONCE(*entry);
1712         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1713                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1714                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1715         WRITE_ONCE(*entry, new_entry);
1716
1717         svm->avic_physical_id_cache = entry;
1718
1719         return 0;
1720 }
1721
1722 static void __sev_asid_free(int asid)
1723 {
1724         struct svm_cpu_data *sd;
1725         int cpu, pos;
1726
1727         pos = asid - 1;
1728         clear_bit(pos, sev_asid_bitmap);
1729
1730         for_each_possible_cpu(cpu) {
1731                 sd = per_cpu(svm_data, cpu);
1732                 sd->sev_vmcbs[pos] = NULL;
1733         }
1734 }
1735
1736 static void sev_asid_free(struct kvm *kvm)
1737 {
1738         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1739
1740         __sev_asid_free(sev->asid);
1741 }
1742
1743 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1744 {
1745         struct sev_data_decommission *decommission;
1746         struct sev_data_deactivate *data;
1747
1748         if (!handle)
1749                 return;
1750
1751         data = kzalloc(sizeof(*data), GFP_KERNEL);
1752         if (!data)
1753                 return;
1754
1755         /* deactivate handle */
1756         data->handle = handle;
1757         sev_guest_deactivate(data, NULL);
1758
1759         wbinvd_on_all_cpus();
1760         sev_guest_df_flush(NULL);
1761         kfree(data);
1762
1763         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1764         if (!decommission)
1765                 return;
1766
1767         /* decommission handle */
1768         decommission->handle = handle;
1769         sev_guest_decommission(decommission, NULL);
1770
1771         kfree(decommission);
1772 }
1773
1774 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1775                                     unsigned long ulen, unsigned long *n,
1776                                     int write)
1777 {
1778         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1779         unsigned long npages, npinned, size;
1780         unsigned long locked, lock_limit;
1781         struct page **pages;
1782         unsigned long first, last;
1783
1784         if (ulen == 0 || uaddr + ulen < uaddr)
1785                 return NULL;
1786
1787         /* Calculate number of pages. */
1788         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1789         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1790         npages = (last - first + 1);
1791
1792         locked = sev->pages_locked + npages;
1793         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1794         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1795                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1796                 return NULL;
1797         }
1798
1799         /* Avoid using vmalloc for smaller buffers. */
1800         size = npages * sizeof(struct page *);
1801         if (size > PAGE_SIZE)
1802                 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1803                                   PAGE_KERNEL);
1804         else
1805                 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1806
1807         if (!pages)
1808                 return NULL;
1809
1810         /* Pin the user virtual address. */
1811         npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1812         if (npinned != npages) {
1813                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1814                 goto err;
1815         }
1816
1817         *n = npages;
1818         sev->pages_locked = locked;
1819
1820         return pages;
1821
1822 err:
1823         if (npinned > 0)
1824                 release_pages(pages, npinned);
1825
1826         kvfree(pages);
1827         return NULL;
1828 }
1829
1830 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1831                              unsigned long npages)
1832 {
1833         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1834
1835         release_pages(pages, npages);
1836         kvfree(pages);
1837         sev->pages_locked -= npages;
1838 }
1839
1840 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1841 {
1842         uint8_t *page_virtual;
1843         unsigned long i;
1844
1845         if (npages == 0 || pages == NULL)
1846                 return;
1847
1848         for (i = 0; i < npages; i++) {
1849                 page_virtual = kmap_atomic(pages[i]);
1850                 clflush_cache_range(page_virtual, PAGE_SIZE);
1851                 kunmap_atomic(page_virtual);
1852         }
1853 }
1854
1855 static void __unregister_enc_region_locked(struct kvm *kvm,
1856                                            struct enc_region *region)
1857 {
1858         /*
1859          * The guest may change the memory encryption attribute from C=0 -> C=1
1860          * or vice versa for this memory range. Lets make sure caches are
1861          * flushed to ensure that guest data gets written into memory with
1862          * correct C-bit.
1863          */
1864         sev_clflush_pages(region->pages, region->npages);
1865
1866         sev_unpin_memory(kvm, region->pages, region->npages);
1867         list_del(&region->list);
1868         kfree(region);
1869 }
1870
1871 static struct kvm *svm_vm_alloc(void)
1872 {
1873         struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1874                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1875                                             PAGE_KERNEL);
1876         return &kvm_svm->kvm;
1877 }
1878
1879 static void svm_vm_free(struct kvm *kvm)
1880 {
1881         vfree(to_kvm_svm(kvm));
1882 }
1883
1884 static void sev_vm_destroy(struct kvm *kvm)
1885 {
1886         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1887         struct list_head *head = &sev->regions_list;
1888         struct list_head *pos, *q;
1889
1890         if (!sev_guest(kvm))
1891                 return;
1892
1893         mutex_lock(&kvm->lock);
1894
1895         /*
1896          * if userspace was terminated before unregistering the memory regions
1897          * then lets unpin all the registered memory.
1898          */
1899         if (!list_empty(head)) {
1900                 list_for_each_safe(pos, q, head) {
1901                         __unregister_enc_region_locked(kvm,
1902                                 list_entry(pos, struct enc_region, list));
1903                 }
1904         }
1905
1906         mutex_unlock(&kvm->lock);
1907
1908         sev_unbind_asid(kvm, sev->handle);
1909         sev_asid_free(kvm);
1910 }
1911
1912 static void avic_vm_destroy(struct kvm *kvm)
1913 {
1914         unsigned long flags;
1915         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1916
1917         if (!avic)
1918                 return;
1919
1920         if (kvm_svm->avic_logical_id_table_page)
1921                 __free_page(kvm_svm->avic_logical_id_table_page);
1922         if (kvm_svm->avic_physical_id_table_page)
1923                 __free_page(kvm_svm->avic_physical_id_table_page);
1924
1925         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1926         hash_del(&kvm_svm->hnode);
1927         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1928 }
1929
1930 static void svm_vm_destroy(struct kvm *kvm)
1931 {
1932         avic_vm_destroy(kvm);
1933         sev_vm_destroy(kvm);
1934 }
1935
1936 static int avic_vm_init(struct kvm *kvm)
1937 {
1938         unsigned long flags;
1939         int err = -ENOMEM;
1940         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1941         struct kvm_svm *k2;
1942         struct page *p_page;
1943         struct page *l_page;
1944         u32 vm_id;
1945
1946         if (!avic)
1947                 return 0;
1948
1949         /* Allocating physical APIC ID table (4KB) */
1950         p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1951         if (!p_page)
1952                 goto free_avic;
1953
1954         kvm_svm->avic_physical_id_table_page = p_page;
1955         clear_page(page_address(p_page));
1956
1957         /* Allocating logical APIC ID table (4KB) */
1958         l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1959         if (!l_page)
1960                 goto free_avic;
1961
1962         kvm_svm->avic_logical_id_table_page = l_page;
1963         clear_page(page_address(l_page));
1964
1965         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1966  again:
1967         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1968         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1969                 next_vm_id_wrapped = 1;
1970                 goto again;
1971         }
1972         /* Is it still in use? Only possible if wrapped at least once */
1973         if (next_vm_id_wrapped) {
1974                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1975                         if (k2->avic_vm_id == vm_id)
1976                                 goto again;
1977                 }
1978         }
1979         kvm_svm->avic_vm_id = vm_id;
1980         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1981         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1982
1983         return 0;
1984
1985 free_avic:
1986         avic_vm_destroy(kvm);
1987         return err;
1988 }
1989
1990 static inline int
1991 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1992 {
1993         int ret = 0;
1994         unsigned long flags;
1995         struct amd_svm_iommu_ir *ir;
1996         struct vcpu_svm *svm = to_svm(vcpu);
1997
1998         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1999                 return 0;
2000
2001         /*
2002          * Here, we go through the per-vcpu ir_list to update all existing
2003          * interrupt remapping table entry targeting this vcpu.
2004          */
2005         spin_lock_irqsave(&svm->ir_list_lock, flags);
2006
2007         if (list_empty(&svm->ir_list))
2008                 goto out;
2009
2010         list_for_each_entry(ir, &svm->ir_list, node) {
2011                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2012                 if (ret)
2013                         break;
2014         }
2015 out:
2016         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2017         return ret;
2018 }
2019
2020 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2021 {
2022         u64 entry;
2023         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2024         int h_physical_id = kvm_cpu_get_apicid(cpu);
2025         struct vcpu_svm *svm = to_svm(vcpu);
2026
2027         if (!kvm_vcpu_apicv_active(vcpu))
2028                 return;
2029
2030         /*
2031          * Since the host physical APIC id is 8 bits,
2032          * we can support host APIC ID upto 255.
2033          */
2034         if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2035                 return;
2036
2037         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2038         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2039
2040         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2041         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2042
2043         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2044         if (svm->avic_is_running)
2045                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2046
2047         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2048         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2049                                         svm->avic_is_running);
2050 }
2051
2052 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2053 {
2054         u64 entry;
2055         struct vcpu_svm *svm = to_svm(vcpu);
2056
2057         if (!kvm_vcpu_apicv_active(vcpu))
2058                 return;
2059
2060         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2061         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2062                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2063
2064         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2065         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2066 }
2067
2068 /**
2069  * This function is called during VCPU halt/unhalt.
2070  */
2071 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2072 {
2073         struct vcpu_svm *svm = to_svm(vcpu);
2074
2075         svm->avic_is_running = is_run;
2076         if (is_run)
2077                 avic_vcpu_load(vcpu, vcpu->cpu);
2078         else
2079                 avic_vcpu_put(vcpu);
2080 }
2081
2082 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2083 {
2084         struct vcpu_svm *svm = to_svm(vcpu);
2085         u32 dummy;
2086         u32 eax = 1;
2087
2088         vcpu->arch.microcode_version = 0x01000065;
2089         svm->spec_ctrl = 0;
2090         svm->virt_spec_ctrl = 0;
2091
2092         if (!init_event) {
2093                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2094                                            MSR_IA32_APICBASE_ENABLE;
2095                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2096                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2097         }
2098         init_vmcb(svm);
2099
2100         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2101         kvm_rdx_write(vcpu, eax);
2102
2103         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2104                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2105 }
2106
2107 static int avic_init_vcpu(struct vcpu_svm *svm)
2108 {
2109         int ret;
2110
2111         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2112                 return 0;
2113
2114         ret = avic_init_backing_page(&svm->vcpu);
2115         if (ret)
2116                 return ret;
2117
2118         INIT_LIST_HEAD(&svm->ir_list);
2119         spin_lock_init(&svm->ir_list_lock);
2120         svm->dfr_reg = APIC_DFR_FLAT;
2121
2122         return ret;
2123 }
2124
2125 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2126 {
2127         struct vcpu_svm *svm;
2128         struct page *page;
2129         struct page *msrpm_pages;
2130         struct page *hsave_page;
2131         struct page *nested_msrpm_pages;
2132         int err;
2133
2134         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2135         if (!svm) {
2136                 err = -ENOMEM;
2137                 goto out;
2138         }
2139
2140         svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2141                                                      GFP_KERNEL_ACCOUNT);
2142         if (!svm->vcpu.arch.guest_fpu) {
2143                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2144                 err = -ENOMEM;
2145                 goto free_partial_svm;
2146         }
2147
2148         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2149         if (err)
2150                 goto free_svm;
2151
2152         err = -ENOMEM;
2153         page = alloc_page(GFP_KERNEL_ACCOUNT);
2154         if (!page)
2155                 goto uninit;
2156
2157         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2158         if (!msrpm_pages)
2159                 goto free_page1;
2160
2161         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2162         if (!nested_msrpm_pages)
2163                 goto free_page2;
2164
2165         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2166         if (!hsave_page)
2167                 goto free_page3;
2168
2169         err = avic_init_vcpu(svm);
2170         if (err)
2171                 goto free_page4;
2172
2173         /* We initialize this flag to true to make sure that the is_running
2174          * bit would be set the first time the vcpu is loaded.
2175          */
2176         svm->avic_is_running = true;
2177
2178         svm->nested.hsave = page_address(hsave_page);
2179
2180         svm->msrpm = page_address(msrpm_pages);
2181         svm_vcpu_init_msrpm(svm->msrpm);
2182
2183         svm->nested.msrpm = page_address(nested_msrpm_pages);
2184         svm_vcpu_init_msrpm(svm->nested.msrpm);
2185
2186         svm->vmcb = page_address(page);
2187         clear_page(svm->vmcb);
2188         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2189         svm->asid_generation = 0;
2190         init_vmcb(svm);
2191
2192         svm_init_osvw(&svm->vcpu);
2193
2194         return &svm->vcpu;
2195
2196 free_page4:
2197         __free_page(hsave_page);
2198 free_page3:
2199         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2200 free_page2:
2201         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2202 free_page1:
2203         __free_page(page);
2204 uninit:
2205         kvm_vcpu_uninit(&svm->vcpu);
2206 free_svm:
2207         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2208 free_partial_svm:
2209         kmem_cache_free(kvm_vcpu_cache, svm);
2210 out:
2211         return ERR_PTR(err);
2212 }
2213
2214 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2215 {
2216         int i;
2217
2218         for_each_online_cpu(i)
2219                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2220 }
2221
2222 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2223 {
2224         struct vcpu_svm *svm = to_svm(vcpu);
2225
2226         /*
2227          * The vmcb page can be recycled, causing a false negative in
2228          * svm_vcpu_load(). So, ensure that no logical CPU has this
2229          * vmcb page recorded as its current vmcb.
2230          */
2231         svm_clear_current_vmcb(svm->vmcb);
2232
2233         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2234         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2235         __free_page(virt_to_page(svm->nested.hsave));
2236         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2237         kvm_vcpu_uninit(vcpu);
2238         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2239         kmem_cache_free(kvm_vcpu_cache, svm);
2240 }
2241
2242 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2243 {
2244         struct vcpu_svm *svm = to_svm(vcpu);
2245         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2246         int i;
2247
2248         if (unlikely(cpu != vcpu->cpu)) {
2249                 svm->asid_generation = 0;
2250                 mark_all_dirty(svm->vmcb);
2251         }
2252
2253 #ifdef CONFIG_X86_64
2254         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2255 #endif
2256         savesegment(fs, svm->host.fs);
2257         savesegment(gs, svm->host.gs);
2258         svm->host.ldt = kvm_read_ldt();
2259
2260         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2261                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2262
2263         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2264                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2265                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2266                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2267                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2268                 }
2269         }
2270         /* This assumes that the kernel never uses MSR_TSC_AUX */
2271         if (static_cpu_has(X86_FEATURE_RDTSCP))
2272                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2273
2274         if (sd->current_vmcb != svm->vmcb) {
2275                 sd->current_vmcb = svm->vmcb;
2276                 indirect_branch_prediction_barrier();
2277         }
2278         avic_vcpu_load(vcpu, cpu);
2279 }
2280
2281 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2282 {
2283         struct vcpu_svm *svm = to_svm(vcpu);
2284         int i;
2285
2286         avic_vcpu_put(vcpu);
2287
2288         ++vcpu->stat.host_state_reload;
2289         kvm_load_ldt(svm->host.ldt);
2290 #ifdef CONFIG_X86_64
2291         loadsegment(fs, svm->host.fs);
2292         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2293         load_gs_index(svm->host.gs);
2294 #else
2295 #ifdef CONFIG_X86_32_LAZY_GS
2296         loadsegment(gs, svm->host.gs);
2297 #endif
2298 #endif
2299         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2300                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2301 }
2302
2303 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2304 {
2305         avic_set_running(vcpu, false);
2306 }
2307
2308 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2309 {
2310         avic_set_running(vcpu, true);
2311 }
2312
2313 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2314 {
2315         struct vcpu_svm *svm = to_svm(vcpu);
2316         unsigned long rflags = svm->vmcb->save.rflags;
2317
2318         if (svm->nmi_singlestep) {
2319                 /* Hide our flags if they were not set by the guest */
2320                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2321                         rflags &= ~X86_EFLAGS_TF;
2322                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2323                         rflags &= ~X86_EFLAGS_RF;
2324         }
2325         return rflags;
2326 }
2327
2328 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2329 {
2330         if (to_svm(vcpu)->nmi_singlestep)
2331                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2332
2333        /*
2334         * Any change of EFLAGS.VM is accompanied by a reload of SS
2335         * (caused by either a task switch or an inter-privilege IRET),
2336         * so we do not need to update the CPL here.
2337         */
2338         to_svm(vcpu)->vmcb->save.rflags = rflags;
2339 }
2340
2341 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2342 {
2343         switch (reg) {
2344         case VCPU_EXREG_PDPTR:
2345                 BUG_ON(!npt_enabled);
2346                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2347                 break;
2348         default:
2349                 BUG();
2350         }
2351 }
2352
2353 static void svm_set_vintr(struct vcpu_svm *svm)
2354 {
2355         set_intercept(svm, INTERCEPT_VINTR);
2356 }
2357
2358 static void svm_clear_vintr(struct vcpu_svm *svm)
2359 {
2360         clr_intercept(svm, INTERCEPT_VINTR);
2361 }
2362
2363 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2364 {
2365         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2366
2367         switch (seg) {
2368         case VCPU_SREG_CS: return &save->cs;
2369         case VCPU_SREG_DS: return &save->ds;
2370         case VCPU_SREG_ES: return &save->es;
2371         case VCPU_SREG_FS: return &save->fs;
2372         case VCPU_SREG_GS: return &save->gs;
2373         case VCPU_SREG_SS: return &save->ss;
2374         case VCPU_SREG_TR: return &save->tr;
2375         case VCPU_SREG_LDTR: return &save->ldtr;
2376         }
2377         BUG();
2378         return NULL;
2379 }
2380
2381 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2382 {
2383         struct vmcb_seg *s = svm_seg(vcpu, seg);
2384
2385         return s->base;
2386 }
2387
2388 static void svm_get_segment(struct kvm_vcpu *vcpu,
2389                             struct kvm_segment *var, int seg)
2390 {
2391         struct vmcb_seg *s = svm_seg(vcpu, seg);
2392
2393         var->base = s->base;
2394         var->limit = s->limit;
2395         var->selector = s->selector;
2396         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2397         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2398         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2399         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2400         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2401         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2402         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2403
2404         /*
2405          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2406          * However, the SVM spec states that the G bit is not observed by the
2407          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2408          * So let's synthesize a legal G bit for all segments, this helps
2409          * running KVM nested. It also helps cross-vendor migration, because
2410          * Intel's vmentry has a check on the 'G' bit.
2411          */
2412         var->g = s->limit > 0xfffff;
2413
2414         /*
2415          * AMD's VMCB does not have an explicit unusable field, so emulate it
2416          * for cross vendor migration purposes by "not present"
2417          */
2418         var->unusable = !var->present;
2419
2420         switch (seg) {
2421         case VCPU_SREG_TR:
2422                 /*
2423                  * Work around a bug where the busy flag in the tr selector
2424                  * isn't exposed
2425                  */
2426                 var->type |= 0x2;
2427                 break;
2428         case VCPU_SREG_DS:
2429         case VCPU_SREG_ES:
2430         case VCPU_SREG_FS:
2431         case VCPU_SREG_GS:
2432                 /*
2433                  * The accessed bit must always be set in the segment
2434                  * descriptor cache, although it can be cleared in the
2435                  * descriptor, the cached bit always remains at 1. Since
2436                  * Intel has a check on this, set it here to support
2437                  * cross-vendor migration.
2438                  */
2439                 if (!var->unusable)
2440                         var->type |= 0x1;
2441                 break;
2442         case VCPU_SREG_SS:
2443                 /*
2444                  * On AMD CPUs sometimes the DB bit in the segment
2445                  * descriptor is left as 1, although the whole segment has
2446                  * been made unusable. Clear it here to pass an Intel VMX
2447                  * entry check when cross vendor migrating.
2448                  */
2449                 if (var->unusable)
2450                         var->db = 0;
2451                 /* This is symmetric with svm_set_segment() */
2452                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2453                 break;
2454         }
2455 }
2456
2457 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2458 {
2459         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2460
2461         return save->cpl;
2462 }
2463
2464 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2465 {
2466         struct vcpu_svm *svm = to_svm(vcpu);
2467
2468         dt->size = svm->vmcb->save.idtr.limit;
2469         dt->address = svm->vmcb->save.idtr.base;
2470 }
2471
2472 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2473 {
2474         struct vcpu_svm *svm = to_svm(vcpu);
2475
2476         svm->vmcb->save.idtr.limit = dt->size;
2477         svm->vmcb->save.idtr.base = dt->address ;
2478         mark_dirty(svm->vmcb, VMCB_DT);
2479 }
2480
2481 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2482 {
2483         struct vcpu_svm *svm = to_svm(vcpu);
2484
2485         dt->size = svm->vmcb->save.gdtr.limit;
2486         dt->address = svm->vmcb->save.gdtr.base;
2487 }
2488
2489 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2490 {
2491         struct vcpu_svm *svm = to_svm(vcpu);
2492
2493         svm->vmcb->save.gdtr.limit = dt->size;
2494         svm->vmcb->save.gdtr.base = dt->address ;
2495         mark_dirty(svm->vmcb, VMCB_DT);
2496 }
2497
2498 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2499 {
2500 }
2501
2502 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2503 {
2504 }
2505
2506 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2507 {
2508 }
2509
2510 static void update_cr0_intercept(struct vcpu_svm *svm)
2511 {
2512         ulong gcr0 = svm->vcpu.arch.cr0;
2513         u64 *hcr0 = &svm->vmcb->save.cr0;
2514
2515         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2516                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2517
2518         mark_dirty(svm->vmcb, VMCB_CR);
2519
2520         if (gcr0 == *hcr0) {
2521                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2522                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2523         } else {
2524                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2525                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2526         }
2527 }
2528
2529 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2530 {
2531         struct vcpu_svm *svm = to_svm(vcpu);
2532
2533 #ifdef CONFIG_X86_64
2534         if (vcpu->arch.efer & EFER_LME) {
2535                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2536                         vcpu->arch.efer |= EFER_LMA;
2537                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2538                 }
2539
2540                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2541                         vcpu->arch.efer &= ~EFER_LMA;
2542                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2543                 }
2544         }
2545 #endif
2546         vcpu->arch.cr0 = cr0;
2547
2548         if (!npt_enabled)
2549                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2550
2551         /*
2552          * re-enable caching here because the QEMU bios
2553          * does not do it - this results in some delay at
2554          * reboot
2555          */
2556         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2557                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2558         svm->vmcb->save.cr0 = cr0;
2559         mark_dirty(svm->vmcb, VMCB_CR);
2560         update_cr0_intercept(svm);
2561 }
2562
2563 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2564 {
2565         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2566         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2567
2568         if (cr4 & X86_CR4_VMXE)
2569                 return 1;
2570
2571         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2572                 svm_flush_tlb(vcpu, true);
2573
2574         vcpu->arch.cr4 = cr4;
2575         if (!npt_enabled)
2576                 cr4 |= X86_CR4_PAE;
2577         cr4 |= host_cr4_mce;
2578         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2579         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2580         return 0;
2581 }
2582
2583 static void svm_set_segment(struct kvm_vcpu *vcpu,
2584                             struct kvm_segment *var, int seg)
2585 {
2586         struct vcpu_svm *svm = to_svm(vcpu);
2587         struct vmcb_seg *s = svm_seg(vcpu, seg);
2588
2589         s->base = var->base;
2590         s->limit = var->limit;
2591         s->selector = var->selector;
2592         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2593         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2594         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2595         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2596         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2597         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2598         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2599         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2600
2601         /*
2602          * This is always accurate, except if SYSRET returned to a segment
2603          * with SS.DPL != 3.  Intel does not have this quirk, and always
2604          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2605          * would entail passing the CPL to userspace and back.
2606          */
2607         if (seg == VCPU_SREG_SS)
2608                 /* This is symmetric with svm_get_segment() */
2609                 svm->vmcb->save.cpl = (var->dpl & 3);
2610
2611         mark_dirty(svm->vmcb, VMCB_SEG);
2612 }
2613
2614 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2615 {
2616         struct vcpu_svm *svm = to_svm(vcpu);
2617
2618         clr_exception_intercept(svm, BP_VECTOR);
2619
2620         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2621                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2622                         set_exception_intercept(svm, BP_VECTOR);
2623         } else
2624                 vcpu->guest_debug = 0;
2625 }
2626
2627 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2628 {
2629         if (sd->next_asid > sd->max_asid) {
2630                 ++sd->asid_generation;
2631                 sd->next_asid = sd->min_asid;
2632                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2633         }
2634
2635         svm->asid_generation = sd->asid_generation;
2636         svm->vmcb->control.asid = sd->next_asid++;
2637
2638         mark_dirty(svm->vmcb, VMCB_ASID);
2639 }
2640
2641 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2642 {
2643         return to_svm(vcpu)->vmcb->save.dr6;
2644 }
2645
2646 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2647 {
2648         struct vcpu_svm *svm = to_svm(vcpu);
2649
2650         svm->vmcb->save.dr6 = value;
2651         mark_dirty(svm->vmcb, VMCB_DR);
2652 }
2653
2654 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2655 {
2656         struct vcpu_svm *svm = to_svm(vcpu);
2657
2658         get_debugreg(vcpu->arch.db[0], 0);
2659         get_debugreg(vcpu->arch.db[1], 1);
2660         get_debugreg(vcpu->arch.db[2], 2);
2661         get_debugreg(vcpu->arch.db[3], 3);
2662         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2663         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2664
2665         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2666         set_dr_intercepts(svm);
2667 }
2668
2669 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2670 {
2671         struct vcpu_svm *svm = to_svm(vcpu);
2672
2673         svm->vmcb->save.dr7 = value;
2674         mark_dirty(svm->vmcb, VMCB_DR);
2675 }
2676
2677 static int pf_interception(struct vcpu_svm *svm)
2678 {
2679         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2680         u64 error_code = svm->vmcb->control.exit_info_1;
2681
2682         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2683                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2684                         svm->vmcb->control.insn_bytes : NULL,
2685                         svm->vmcb->control.insn_len);
2686 }
2687
2688 static int npf_interception(struct vcpu_svm *svm)
2689 {
2690         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2691         u64 error_code = svm->vmcb->control.exit_info_1;
2692
2693         trace_kvm_page_fault(fault_address, error_code);
2694         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2695                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2696                         svm->vmcb->control.insn_bytes : NULL,
2697                         svm->vmcb->control.insn_len);
2698 }
2699
2700 static int db_interception(struct vcpu_svm *svm)
2701 {
2702         struct kvm_run *kvm_run = svm->vcpu.run;
2703         struct kvm_vcpu *vcpu = &svm->vcpu;
2704
2705         if (!(svm->vcpu.guest_debug &
2706               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2707                 !svm->nmi_singlestep) {
2708                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2709                 return 1;
2710         }
2711
2712         if (svm->nmi_singlestep) {
2713                 disable_nmi_singlestep(svm);
2714                 /* Make sure we check for pending NMIs upon entry */
2715                 kvm_make_request(KVM_REQ_EVENT, vcpu);
2716         }
2717
2718         if (svm->vcpu.guest_debug &
2719             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2720                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2721                 kvm_run->debug.arch.pc =
2722                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2723                 kvm_run->debug.arch.exception = DB_VECTOR;
2724                 return 0;
2725         }
2726
2727         return 1;
2728 }
2729
2730 static int bp_interception(struct vcpu_svm *svm)
2731 {
2732         struct kvm_run *kvm_run = svm->vcpu.run;
2733
2734         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2735         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2736         kvm_run->debug.arch.exception = BP_VECTOR;
2737         return 0;
2738 }
2739
2740 static int ud_interception(struct vcpu_svm *svm)
2741 {
2742         return handle_ud(&svm->vcpu);
2743 }
2744
2745 static int ac_interception(struct vcpu_svm *svm)
2746 {
2747         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2748         return 1;
2749 }
2750
2751 static int gp_interception(struct vcpu_svm *svm)
2752 {
2753         struct kvm_vcpu *vcpu = &svm->vcpu;
2754         u32 error_code = svm->vmcb->control.exit_info_1;
2755         int er;
2756
2757         WARN_ON_ONCE(!enable_vmware_backdoor);
2758
2759         er = kvm_emulate_instruction(vcpu,
2760                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2761         if (er == EMULATE_USER_EXIT)
2762                 return 0;
2763         else if (er != EMULATE_DONE)
2764                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2765         return 1;
2766 }
2767
2768 static bool is_erratum_383(void)
2769 {
2770         int err, i;
2771         u64 value;
2772
2773         if (!erratum_383_found)
2774                 return false;
2775
2776         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2777         if (err)
2778                 return false;
2779
2780         /* Bit 62 may or may not be set for this mce */
2781         value &= ~(1ULL << 62);
2782
2783         if (value != 0xb600000000010015ULL)
2784                 return false;
2785
2786         /* Clear MCi_STATUS registers */
2787         for (i = 0; i < 6; ++i)
2788                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2789
2790         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2791         if (!err) {
2792                 u32 low, high;
2793
2794                 value &= ~(1ULL << 2);
2795                 low    = lower_32_bits(value);
2796                 high   = upper_32_bits(value);
2797
2798                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2799         }
2800
2801         /* Flush tlb to evict multi-match entries */
2802         __flush_tlb_all();
2803
2804         return true;
2805 }
2806
2807 static void svm_handle_mce(struct vcpu_svm *svm)
2808 {
2809         if (is_erratum_383()) {
2810                 /*
2811                  * Erratum 383 triggered. Guest state is corrupt so kill the
2812                  * guest.
2813                  */
2814                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2815
2816                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2817
2818                 return;
2819         }
2820
2821         /*
2822          * On an #MC intercept the MCE handler is not called automatically in
2823          * the host. So do it by hand here.
2824          */
2825         asm volatile (
2826                 "int $0x12\n");
2827         /* not sure if we ever come back to this point */
2828
2829         return;
2830 }
2831
2832 static int mc_interception(struct vcpu_svm *svm)
2833 {
2834         return 1;
2835 }
2836
2837 static int shutdown_interception(struct vcpu_svm *svm)
2838 {
2839         struct kvm_run *kvm_run = svm->vcpu.run;
2840
2841         /*
2842          * VMCB is undefined after a SHUTDOWN intercept
2843          * so reinitialize it.
2844          */
2845         clear_page(svm->vmcb);
2846         init_vmcb(svm);
2847
2848         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2849         return 0;
2850 }
2851
2852 static int io_interception(struct vcpu_svm *svm)
2853 {
2854         struct kvm_vcpu *vcpu = &svm->vcpu;
2855         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2856         int size, in, string;
2857         unsigned port;
2858
2859         ++svm->vcpu.stat.io_exits;
2860         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2861         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2862         if (string)
2863                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2864
2865         port = io_info >> 16;
2866         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2867         svm->next_rip = svm->vmcb->control.exit_info_2;
2868
2869         return kvm_fast_pio(&svm->vcpu, size, port, in);
2870 }
2871
2872 static int nmi_interception(struct vcpu_svm *svm)
2873 {
2874         return 1;
2875 }
2876
2877 static int intr_interception(struct vcpu_svm *svm)
2878 {
2879         ++svm->vcpu.stat.irq_exits;
2880         return 1;
2881 }
2882
2883 static int nop_on_interception(struct vcpu_svm *svm)
2884 {
2885         return 1;
2886 }
2887
2888 static int halt_interception(struct vcpu_svm *svm)
2889 {
2890         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2891         return kvm_emulate_halt(&svm->vcpu);
2892 }
2893
2894 static int vmmcall_interception(struct vcpu_svm *svm)
2895 {
2896         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2897         return kvm_emulate_hypercall(&svm->vcpu);
2898 }
2899
2900 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2901 {
2902         struct vcpu_svm *svm = to_svm(vcpu);
2903
2904         return svm->nested.nested_cr3;
2905 }
2906
2907 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2908 {
2909         struct vcpu_svm *svm = to_svm(vcpu);
2910         u64 cr3 = svm->nested.nested_cr3;
2911         u64 pdpte;
2912         int ret;
2913
2914         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2915                                        offset_in_page(cr3) + index * 8, 8);
2916         if (ret)
2917                 return 0;
2918         return pdpte;
2919 }
2920
2921 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2922                                    unsigned long root)
2923 {
2924         struct vcpu_svm *svm = to_svm(vcpu);
2925
2926         svm->vmcb->control.nested_cr3 = __sme_set(root);
2927         mark_dirty(svm->vmcb, VMCB_NPT);
2928 }
2929
2930 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2931                                        struct x86_exception *fault)
2932 {
2933         struct vcpu_svm *svm = to_svm(vcpu);
2934
2935         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2936                 /*
2937                  * TODO: track the cause of the nested page fault, and
2938                  * correctly fill in the high bits of exit_info_1.
2939                  */
2940                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2941                 svm->vmcb->control.exit_code_hi = 0;
2942                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2943                 svm->vmcb->control.exit_info_2 = fault->address;
2944         }
2945
2946         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2947         svm->vmcb->control.exit_info_1 |= fault->error_code;
2948
2949         /*
2950          * The present bit is always zero for page structure faults on real
2951          * hardware.
2952          */
2953         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2954                 svm->vmcb->control.exit_info_1 &= ~1;
2955
2956         nested_svm_vmexit(svm);
2957 }
2958
2959 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2960 {
2961         WARN_ON(mmu_is_nested(vcpu));
2962
2963         vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2964         kvm_init_shadow_mmu(vcpu);
2965         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2966         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2967         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2968         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2969         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2970         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2971         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2972 }
2973
2974 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2975 {
2976         vcpu->arch.mmu = &vcpu->arch.root_mmu;
2977         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2978 }
2979
2980 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2981 {
2982         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2983             !is_paging(&svm->vcpu)) {
2984                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2985                 return 1;
2986         }
2987
2988         if (svm->vmcb->save.cpl) {
2989                 kvm_inject_gp(&svm->vcpu, 0);
2990                 return 1;
2991         }
2992
2993         return 0;
2994 }
2995
2996 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2997                                       bool has_error_code, u32 error_code)
2998 {
2999         int vmexit;
3000
3001         if (!is_guest_mode(&svm->vcpu))
3002                 return 0;
3003
3004         vmexit = nested_svm_intercept(svm);
3005         if (vmexit != NESTED_EXIT_DONE)
3006                 return 0;
3007
3008         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3009         svm->vmcb->control.exit_code_hi = 0;
3010         svm->vmcb->control.exit_info_1 = error_code;
3011
3012         /*
3013          * EXITINFO2 is undefined for all exception intercepts other
3014          * than #PF.
3015          */
3016         if (svm->vcpu.arch.exception.nested_apf)
3017                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3018         else if (svm->vcpu.arch.exception.has_payload)
3019                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3020         else
3021                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3022
3023         svm->nested.exit_required = true;
3024         return vmexit;
3025 }
3026
3027 /* This function returns true if it is save to enable the irq window */
3028 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3029 {
3030         if (!is_guest_mode(&svm->vcpu))
3031                 return true;
3032
3033         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3034                 return true;
3035
3036         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3037                 return false;
3038
3039         /*
3040          * if vmexit was already requested (by intercepted exception
3041          * for instance) do not overwrite it with "external interrupt"
3042          * vmexit.
3043          */
3044         if (svm->nested.exit_required)
3045                 return false;
3046
3047         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3048         svm->vmcb->control.exit_info_1 = 0;
3049         svm->vmcb->control.exit_info_2 = 0;
3050
3051         if (svm->nested.intercept & 1ULL) {
3052                 /*
3053                  * The #vmexit can't be emulated here directly because this
3054                  * code path runs with irqs and preemption disabled. A
3055                  * #vmexit emulation might sleep. Only signal request for
3056                  * the #vmexit here.
3057                  */
3058                 svm->nested.exit_required = true;
3059                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3060                 return false;
3061         }
3062
3063         return true;
3064 }
3065
3066 /* This function returns true if it is save to enable the nmi window */
3067 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3068 {
3069         if (!is_guest_mode(&svm->vcpu))
3070                 return true;
3071
3072         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3073                 return true;
3074
3075         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3076         svm->nested.exit_required = true;
3077
3078         return false;
3079 }
3080
3081 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3082 {
3083         unsigned port, size, iopm_len;
3084         u16 val, mask;
3085         u8 start_bit;
3086         u64 gpa;
3087
3088         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3089                 return NESTED_EXIT_HOST;
3090
3091         port = svm->vmcb->control.exit_info_1 >> 16;
3092         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3093                 SVM_IOIO_SIZE_SHIFT;
3094         gpa  = svm->nested.vmcb_iopm + (port / 8);
3095         start_bit = port % 8;
3096         iopm_len = (start_bit + size > 8) ? 2 : 1;
3097         mask = (0xf >> (4 - size)) << start_bit;
3098         val = 0;
3099
3100         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3101                 return NESTED_EXIT_DONE;
3102
3103         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3104 }
3105
3106 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3107 {
3108         u32 offset, msr, value;
3109         int write, mask;
3110
3111         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3112                 return NESTED_EXIT_HOST;
3113
3114         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3115         offset = svm_msrpm_offset(msr);
3116         write  = svm->vmcb->control.exit_info_1 & 1;
3117         mask   = 1 << ((2 * (msr & 0xf)) + write);
3118
3119         if (offset == MSR_INVALID)
3120                 return NESTED_EXIT_DONE;
3121
3122         /* Offset is in 32 bit units but need in 8 bit units */
3123         offset *= 4;
3124
3125         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3126                 return NESTED_EXIT_DONE;
3127
3128         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3129 }
3130
3131 /* DB exceptions for our internal use must not cause vmexit */
3132 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3133 {
3134         unsigned long dr6;
3135
3136         /* if we're not singlestepping, it's not ours */
3137         if (!svm->nmi_singlestep)
3138                 return NESTED_EXIT_DONE;
3139
3140         /* if it's not a singlestep exception, it's not ours */
3141         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3142                 return NESTED_EXIT_DONE;
3143         if (!(dr6 & DR6_BS))
3144                 return NESTED_EXIT_DONE;
3145
3146         /* if the guest is singlestepping, it should get the vmexit */
3147         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3148                 disable_nmi_singlestep(svm);
3149                 return NESTED_EXIT_DONE;
3150         }
3151
3152         /* it's ours, the nested hypervisor must not see this one */
3153         return NESTED_EXIT_HOST;
3154 }
3155
3156 static int nested_svm_exit_special(struct vcpu_svm *svm)
3157 {
3158         u32 exit_code = svm->vmcb->control.exit_code;
3159
3160         switch (exit_code) {
3161         case SVM_EXIT_INTR:
3162         case SVM_EXIT_NMI:
3163         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3164                 return NESTED_EXIT_HOST;
3165         case SVM_EXIT_NPF:
3166                 /* For now we are always handling NPFs when using them */
3167                 if (npt_enabled)
3168                         return NESTED_EXIT_HOST;
3169                 break;
3170         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3171                 /* When we're shadowing, trap PFs, but not async PF */
3172                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3173                         return NESTED_EXIT_HOST;
3174                 break;
3175         default:
3176                 break;
3177         }
3178
3179         return NESTED_EXIT_CONTINUE;
3180 }
3181
3182 /*
3183  * If this function returns true, this #vmexit was already handled
3184  */
3185 static int nested_svm_intercept(struct vcpu_svm *svm)
3186 {
3187         u32 exit_code = svm->vmcb->control.exit_code;
3188         int vmexit = NESTED_EXIT_HOST;
3189
3190         switch (exit_code) {
3191         case SVM_EXIT_MSR:
3192                 vmexit = nested_svm_exit_handled_msr(svm);
3193                 break;
3194         case SVM_EXIT_IOIO:
3195                 vmexit = nested_svm_intercept_ioio(svm);
3196                 break;
3197         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3198                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3199                 if (svm->nested.intercept_cr & bit)
3200                         vmexit = NESTED_EXIT_DONE;
3201                 break;
3202         }
3203         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3204                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3205                 if (svm->nested.intercept_dr & bit)
3206                         vmexit = NESTED_EXIT_DONE;
3207                 break;
3208         }
3209         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3210                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3211                 if (svm->nested.intercept_exceptions & excp_bits) {
3212                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3213                                 vmexit = nested_svm_intercept_db(svm);
3214                         else
3215                                 vmexit = NESTED_EXIT_DONE;
3216                 }
3217                 /* async page fault always cause vmexit */
3218                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3219                          svm->vcpu.arch.exception.nested_apf != 0)
3220                         vmexit = NESTED_EXIT_DONE;
3221                 break;
3222         }
3223         case SVM_EXIT_ERR: {
3224                 vmexit = NESTED_EXIT_DONE;
3225                 break;
3226         }
3227         default: {
3228                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3229                 if (svm->nested.intercept & exit_bits)
3230                         vmexit = NESTED_EXIT_DONE;
3231         }
3232         }
3233
3234         return vmexit;
3235 }
3236
3237 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3238 {
3239         int vmexit;
3240
3241         vmexit = nested_svm_intercept(svm);
3242
3243         if (vmexit == NESTED_EXIT_DONE)
3244                 nested_svm_vmexit(svm);
3245
3246         return vmexit;
3247 }
3248
3249 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3250 {
3251         struct vmcb_control_area *dst  = &dst_vmcb->control;
3252         struct vmcb_control_area *from = &from_vmcb->control;
3253
3254         dst->intercept_cr         = from->intercept_cr;
3255         dst->intercept_dr         = from->intercept_dr;
3256         dst->intercept_exceptions = from->intercept_exceptions;
3257         dst->intercept            = from->intercept;
3258         dst->iopm_base_pa         = from->iopm_base_pa;
3259         dst->msrpm_base_pa        = from->msrpm_base_pa;
3260         dst->tsc_offset           = from->tsc_offset;
3261         dst->asid                 = from->asid;
3262         dst->tlb_ctl              = from->tlb_ctl;
3263         dst->int_ctl              = from->int_ctl;
3264         dst->int_vector           = from->int_vector;
3265         dst->int_state            = from->int_state;
3266         dst->exit_code            = from->exit_code;
3267         dst->exit_code_hi         = from->exit_code_hi;
3268         dst->exit_info_1          = from->exit_info_1;
3269         dst->exit_info_2          = from->exit_info_2;
3270         dst->exit_int_info        = from->exit_int_info;
3271         dst->exit_int_info_err    = from->exit_int_info_err;
3272         dst->nested_ctl           = from->nested_ctl;
3273         dst->event_inj            = from->event_inj;
3274         dst->event_inj_err        = from->event_inj_err;
3275         dst->nested_cr3           = from->nested_cr3;
3276         dst->virt_ext              = from->virt_ext;
3277         dst->pause_filter_count   = from->pause_filter_count;
3278         dst->pause_filter_thresh  = from->pause_filter_thresh;
3279 }
3280
3281 static int nested_svm_vmexit(struct vcpu_svm *svm)
3282 {
3283         int rc;
3284         struct vmcb *nested_vmcb;
3285         struct vmcb *hsave = svm->nested.hsave;
3286         struct vmcb *vmcb = svm->vmcb;
3287         struct kvm_host_map map;
3288
3289         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3290                                        vmcb->control.exit_info_1,
3291                                        vmcb->control.exit_info_2,
3292                                        vmcb->control.exit_int_info,
3293                                        vmcb->control.exit_int_info_err,
3294                                        KVM_ISA_SVM);
3295
3296         rc = kvm_vcpu_map(&svm->vcpu, gfn_to_gpa(svm->nested.vmcb), &map);
3297         if (rc) {
3298                 if (rc == -EINVAL)
3299                         kvm_inject_gp(&svm->vcpu, 0);
3300                 return 1;
3301         }
3302
3303         nested_vmcb = map.hva;
3304
3305         /* Exit Guest-Mode */
3306         leave_guest_mode(&svm->vcpu);
3307         svm->nested.vmcb = 0;
3308
3309         /* Give the current vmcb to the guest */
3310         disable_gif(svm);
3311
3312         nested_vmcb->save.es     = vmcb->save.es;
3313         nested_vmcb->save.cs     = vmcb->save.cs;
3314         nested_vmcb->save.ss     = vmcb->save.ss;
3315         nested_vmcb->save.ds     = vmcb->save.ds;
3316         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3317         nested_vmcb->save.idtr   = vmcb->save.idtr;
3318         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3319         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3320         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3321         nested_vmcb->save.cr2    = vmcb->save.cr2;
3322         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3323         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3324         nested_vmcb->save.rip    = vmcb->save.rip;
3325         nested_vmcb->save.rsp    = vmcb->save.rsp;
3326         nested_vmcb->save.rax    = vmcb->save.rax;
3327         nested_vmcb->save.dr7    = vmcb->save.dr7;
3328         nested_vmcb->save.dr6    = vmcb->save.dr6;
3329         nested_vmcb->save.cpl    = vmcb->save.cpl;
3330
3331         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3332         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3333         nested_vmcb->control.int_state         = vmcb->control.int_state;
3334         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3335         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3336         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3337         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3338         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3339         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3340
3341         if (svm->nrips_enabled)
3342                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3343
3344         /*
3345          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3346          * to make sure that we do not lose injected events. So check event_inj
3347          * here and copy it to exit_int_info if it is valid.
3348          * Exit_int_info and event_inj can't be both valid because the case
3349          * below only happens on a VMRUN instruction intercept which has
3350          * no valid exit_int_info set.
3351          */
3352         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3353                 struct vmcb_control_area *nc = &nested_vmcb->control;
3354
3355                 nc->exit_int_info     = vmcb->control.event_inj;
3356                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3357         }
3358
3359         nested_vmcb->control.tlb_ctl           = 0;
3360         nested_vmcb->control.event_inj         = 0;
3361         nested_vmcb->control.event_inj_err     = 0;
3362
3363         nested_vmcb->control.pause_filter_count =
3364                 svm->vmcb->control.pause_filter_count;
3365         nested_vmcb->control.pause_filter_thresh =
3366                 svm->vmcb->control.pause_filter_thresh;
3367
3368         /* We always set V_INTR_MASKING and remember the old value in hflags */
3369         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3370                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3371
3372         /* Restore the original control entries */
3373         copy_vmcb_control_area(vmcb, hsave);
3374
3375         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3376         kvm_clear_exception_queue(&svm->vcpu);
3377         kvm_clear_interrupt_queue(&svm->vcpu);
3378
3379         svm->nested.nested_cr3 = 0;
3380
3381         /* Restore selected save entries */
3382         svm->vmcb->save.es = hsave->save.es;
3383         svm->vmcb->save.cs = hsave->save.cs;
3384         svm->vmcb->save.ss = hsave->save.ss;
3385         svm->vmcb->save.ds = hsave->save.ds;
3386         svm->vmcb->save.gdtr = hsave->save.gdtr;
3387         svm->vmcb->save.idtr = hsave->save.idtr;
3388         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3389         svm_set_efer(&svm->vcpu, hsave->save.efer);
3390         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3391         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3392         if (npt_enabled) {
3393                 svm->vmcb->save.cr3 = hsave->save.cr3;
3394                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3395         } else {
3396                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3397         }
3398         kvm_rax_write(&svm->vcpu, hsave->save.rax);
3399         kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3400         kvm_rip_write(&svm->vcpu, hsave->save.rip);
3401         svm->vmcb->save.dr7 = 0;
3402         svm->vmcb->save.cpl = 0;
3403         svm->vmcb->control.exit_int_info = 0;
3404
3405         mark_all_dirty(svm->vmcb);
3406
3407         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3408
3409         nested_svm_uninit_mmu_context(&svm->vcpu);
3410         kvm_mmu_reset_context(&svm->vcpu);
3411         kvm_mmu_load(&svm->vcpu);
3412
3413         /*
3414          * Drop what we picked up for L2 via svm_complete_interrupts() so it
3415          * doesn't end up in L1.
3416          */
3417         svm->vcpu.arch.nmi_injected = false;
3418         kvm_clear_exception_queue(&svm->vcpu);
3419         kvm_clear_interrupt_queue(&svm->vcpu);
3420
3421         return 0;
3422 }
3423
3424 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3425 {
3426         /*
3427          * This function merges the msr permission bitmaps of kvm and the
3428          * nested vmcb. It is optimized in that it only merges the parts where
3429          * the kvm msr permission bitmap may contain zero bits
3430          */
3431         int i;
3432
3433         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3434                 return true;
3435
3436         for (i = 0; i < MSRPM_OFFSETS; i++) {
3437                 u32 value, p;
3438                 u64 offset;
3439
3440                 if (msrpm_offsets[i] == 0xffffffff)
3441                         break;
3442
3443                 p      = msrpm_offsets[i];
3444                 offset = svm->nested.vmcb_msrpm + (p * 4);
3445
3446                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3447                         return false;
3448
3449                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3450         }
3451
3452         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3453
3454         return true;
3455 }
3456
3457 static bool nested_vmcb_checks(struct vmcb *vmcb)
3458 {
3459         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3460                 return false;
3461
3462         if (vmcb->control.asid == 0)
3463                 return false;
3464
3465         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3466             !npt_enabled)
3467                 return false;
3468
3469         return true;
3470 }
3471
3472 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3473                                  struct vmcb *nested_vmcb, struct kvm_host_map *map)
3474 {
3475         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3476                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3477         else
3478                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3479
3480         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3481                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3482                 nested_svm_init_mmu_context(&svm->vcpu);
3483         }
3484
3485         /* Load the nested guest state */
3486         svm->vmcb->save.es = nested_vmcb->save.es;
3487         svm->vmcb->save.cs = nested_vmcb->save.cs;
3488         svm->vmcb->save.ss = nested_vmcb->save.ss;
3489         svm->vmcb->save.ds = nested_vmcb->save.ds;
3490         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3491         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3492         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3493         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3494         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3495         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3496         if (npt_enabled) {
3497                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3498                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3499         } else
3500                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3501
3502         /* Guest paging mode is active - reset mmu */
3503         kvm_mmu_reset_context(&svm->vcpu);
3504
3505         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3506         kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3507         kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3508         kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3509
3510         /* In case we don't even reach vcpu_run, the fields are not updated */
3511         svm->vmcb->save.rax = nested_vmcb->save.rax;
3512         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3513         svm->vmcb->save.rip = nested_vmcb->save.rip;
3514         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3515         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3516         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3517
3518         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3519         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3520
3521         /* cache intercepts */
3522         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3523         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3524         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3525         svm->nested.intercept            = nested_vmcb->control.intercept;
3526
3527         svm_flush_tlb(&svm->vcpu, true);
3528         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3529         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3530                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3531         else
3532                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3533
3534         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3535                 /* We only want the cr8 intercept bits of the guest */
3536                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3537                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3538         }
3539
3540         /* We don't want to see VMMCALLs from a nested guest */
3541         clr_intercept(svm, INTERCEPT_VMMCALL);
3542
3543         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3544         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3545
3546         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3547         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3548         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3549         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3550         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3551
3552         svm->vmcb->control.pause_filter_count =
3553                 nested_vmcb->control.pause_filter_count;
3554         svm->vmcb->control.pause_filter_thresh =
3555                 nested_vmcb->control.pause_filter_thresh;
3556
3557         kvm_vcpu_unmap(&svm->vcpu, map, true);
3558
3559         /* Enter Guest-Mode */
3560         enter_guest_mode(&svm->vcpu);
3561
3562         /*
3563          * Merge guest and host intercepts - must be called  with vcpu in
3564          * guest-mode to take affect here
3565          */
3566         recalc_intercepts(svm);
3567
3568         svm->nested.vmcb = vmcb_gpa;
3569
3570         enable_gif(svm);
3571
3572         mark_all_dirty(svm->vmcb);
3573 }
3574
3575 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3576 {
3577         int rc;
3578         struct vmcb *nested_vmcb;
3579         struct vmcb *hsave = svm->nested.hsave;
3580         struct vmcb *vmcb = svm->vmcb;
3581         struct kvm_host_map map;
3582         u64 vmcb_gpa;
3583
3584         vmcb_gpa = svm->vmcb->save.rax;
3585
3586         rc = kvm_vcpu_map(&svm->vcpu, gfn_to_gpa(vmcb_gpa), &map);
3587         if (rc) {
3588                 if (rc == -EINVAL)
3589                         kvm_inject_gp(&svm->vcpu, 0);
3590                 return false;
3591         }
3592
3593         nested_vmcb = map.hva;
3594
3595         if (!nested_vmcb_checks(nested_vmcb)) {
3596                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3597                 nested_vmcb->control.exit_code_hi = 0;
3598                 nested_vmcb->control.exit_info_1  = 0;
3599                 nested_vmcb->control.exit_info_2  = 0;
3600
3601                 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3602
3603                 return false;
3604         }
3605
3606         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3607                                nested_vmcb->save.rip,
3608                                nested_vmcb->control.int_ctl,
3609                                nested_vmcb->control.event_inj,
3610                                nested_vmcb->control.nested_ctl);
3611
3612         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3613                                     nested_vmcb->control.intercept_cr >> 16,
3614                                     nested_vmcb->control.intercept_exceptions,
3615                                     nested_vmcb->control.intercept);
3616
3617         /* Clear internal status */
3618         kvm_clear_exception_queue(&svm->vcpu);
3619         kvm_clear_interrupt_queue(&svm->vcpu);
3620
3621         /*
3622          * Save the old vmcb, so we don't need to pick what we save, but can
3623          * restore everything when a VMEXIT occurs
3624          */
3625         hsave->save.es     = vmcb->save.es;
3626         hsave->save.cs     = vmcb->save.cs;
3627         hsave->save.ss     = vmcb->save.ss;
3628         hsave->save.ds     = vmcb->save.ds;
3629         hsave->save.gdtr   = vmcb->save.gdtr;
3630         hsave->save.idtr   = vmcb->save.idtr;
3631         hsave->save.efer   = svm->vcpu.arch.efer;
3632         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3633         hsave->save.cr4    = svm->vcpu.arch.cr4;
3634         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3635         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3636         hsave->save.rsp    = vmcb->save.rsp;
3637         hsave->save.rax    = vmcb->save.rax;
3638         if (npt_enabled)
3639                 hsave->save.cr3    = vmcb->save.cr3;
3640         else
3641                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3642
3643         copy_vmcb_control_area(hsave, vmcb);
3644
3645         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3646
3647         return true;
3648 }
3649
3650 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3651 {
3652         to_vmcb->save.fs = from_vmcb->save.fs;
3653         to_vmcb->save.gs = from_vmcb->save.gs;
3654         to_vmcb->save.tr = from_vmcb->save.tr;
3655         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3656         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3657         to_vmcb->save.star = from_vmcb->save.star;
3658         to_vmcb->save.lstar = from_vmcb->save.lstar;
3659         to_vmcb->save.cstar = from_vmcb->save.cstar;
3660         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3661         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3662         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3663         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3664 }
3665
3666 static int vmload_interception(struct vcpu_svm *svm)
3667 {
3668         struct vmcb *nested_vmcb;
3669         struct kvm_host_map map;
3670         int ret;
3671
3672         if (nested_svm_check_permissions(svm))
3673                 return 1;
3674
3675         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3676         if (ret) {
3677                 if (ret == -EINVAL)
3678                         kvm_inject_gp(&svm->vcpu, 0);
3679                 return 1;
3680         }
3681
3682         nested_vmcb = map.hva;
3683
3684         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3685         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3686
3687         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3688         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3689
3690         return ret;
3691 }
3692
3693 static int vmsave_interception(struct vcpu_svm *svm)
3694 {
3695         struct vmcb *nested_vmcb;
3696         struct kvm_host_map map;
3697         int ret;
3698
3699         if (nested_svm_check_permissions(svm))
3700                 return 1;
3701
3702         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3703         if (ret) {
3704                 if (ret == -EINVAL)
3705                         kvm_inject_gp(&svm->vcpu, 0);
3706                 return 1;
3707         }
3708
3709         nested_vmcb = map.hva;
3710
3711         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3712         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3713
3714         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3715         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3716
3717         return ret;
3718 }
3719
3720 static int vmrun_interception(struct vcpu_svm *svm)
3721 {
3722         if (nested_svm_check_permissions(svm))
3723                 return 1;
3724
3725         /* Save rip after vmrun instruction */
3726         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3727
3728         if (!nested_svm_vmrun(svm))
3729                 return 1;
3730
3731         if (!nested_svm_vmrun_msrpm(svm))
3732                 goto failed;
3733
3734         return 1;
3735
3736 failed:
3737
3738         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3739         svm->vmcb->control.exit_code_hi = 0;
3740         svm->vmcb->control.exit_info_1  = 0;
3741         svm->vmcb->control.exit_info_2  = 0;
3742
3743         nested_svm_vmexit(svm);
3744
3745         return 1;
3746 }
3747
3748 static int stgi_interception(struct vcpu_svm *svm)
3749 {
3750         int ret;
3751
3752         if (nested_svm_check_permissions(svm))
3753                 return 1;
3754
3755         /*
3756          * If VGIF is enabled, the STGI intercept is only added to
3757          * detect the opening of the SMI/NMI window; remove it now.
3758          */
3759         if (vgif_enabled(svm))
3760                 clr_intercept(svm, INTERCEPT_STGI);
3761
3762         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3763         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3764         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3765
3766         enable_gif(svm);
3767
3768         return ret;
3769 }
3770
3771 static int clgi_interception(struct vcpu_svm *svm)
3772 {
3773         int ret;
3774
3775         if (nested_svm_check_permissions(svm))
3776                 return 1;
3777
3778         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3779         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3780
3781         disable_gif(svm);
3782
3783         /* After a CLGI no interrupts should come */
3784         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3785                 svm_clear_vintr(svm);
3786                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3787                 mark_dirty(svm->vmcb, VMCB_INTR);
3788         }
3789
3790         return ret;
3791 }
3792
3793 static int invlpga_interception(struct vcpu_svm *svm)
3794 {
3795         struct kvm_vcpu *vcpu = &svm->vcpu;
3796
3797         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3798                           kvm_rax_read(&svm->vcpu));
3799
3800         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3801         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3802
3803         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3804         return kvm_skip_emulated_instruction(&svm->vcpu);
3805 }
3806
3807 static int skinit_interception(struct vcpu_svm *svm)
3808 {
3809         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3810
3811         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3812         return 1;
3813 }
3814
3815 static int wbinvd_interception(struct vcpu_svm *svm)
3816 {
3817         return kvm_emulate_wbinvd(&svm->vcpu);
3818 }
3819
3820 static int xsetbv_interception(struct vcpu_svm *svm)
3821 {
3822         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3823         u32 index = kvm_rcx_read(&svm->vcpu);
3824
3825         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3826                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3827                 return kvm_skip_emulated_instruction(&svm->vcpu);
3828         }
3829
3830         return 1;
3831 }
3832
3833 static int task_switch_interception(struct vcpu_svm *svm)
3834 {
3835         u16 tss_selector;
3836         int reason;
3837         int int_type = svm->vmcb->control.exit_int_info &
3838                 SVM_EXITINTINFO_TYPE_MASK;
3839         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3840         uint32_t type =
3841                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3842         uint32_t idt_v =
3843                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3844         bool has_error_code = false;
3845         u32 error_code = 0;
3846
3847         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3848
3849         if (svm->vmcb->control.exit_info_2 &
3850             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3851                 reason = TASK_SWITCH_IRET;
3852         else if (svm->vmcb->control.exit_info_2 &
3853                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3854                 reason = TASK_SWITCH_JMP;
3855         else if (idt_v)
3856                 reason = TASK_SWITCH_GATE;
3857         else
3858                 reason = TASK_SWITCH_CALL;
3859
3860         if (reason == TASK_SWITCH_GATE) {
3861                 switch (type) {
3862                 case SVM_EXITINTINFO_TYPE_NMI:
3863                         svm->vcpu.arch.nmi_injected = false;
3864                         break;
3865                 case SVM_EXITINTINFO_TYPE_EXEPT:
3866                         if (svm->vmcb->control.exit_info_2 &
3867                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3868                                 has_error_code = true;
3869                                 error_code =
3870                                         (u32)svm->vmcb->control.exit_info_2;
3871                         }
3872                         kvm_clear_exception_queue(&svm->vcpu);
3873                         break;
3874                 case SVM_EXITINTINFO_TYPE_INTR:
3875                         kvm_clear_interrupt_queue(&svm->vcpu);
3876                         break;
3877                 default:
3878                         break;
3879                 }
3880         }
3881
3882         if (reason != TASK_SWITCH_GATE ||
3883             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3884             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3885              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3886                 skip_emulated_instruction(&svm->vcpu);
3887
3888         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3889                 int_vec = -1;
3890
3891         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3892                                 has_error_code, error_code) == EMULATE_FAIL) {
3893                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3894                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3895                 svm->vcpu.run->internal.ndata = 0;
3896                 return 0;
3897         }
3898         return 1;
3899 }
3900
3901 static int cpuid_interception(struct vcpu_svm *svm)
3902 {
3903         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3904         return kvm_emulate_cpuid(&svm->vcpu);
3905 }
3906
3907 static int iret_interception(struct vcpu_svm *svm)
3908 {
3909         ++svm->vcpu.stat.nmi_window_exits;
3910         clr_intercept(svm, INTERCEPT_IRET);
3911         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3912         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3913         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3914         return 1;
3915 }
3916
3917 static int invlpg_interception(struct vcpu_svm *svm)
3918 {
3919         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3920                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3921
3922         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3923         return kvm_skip_emulated_instruction(&svm->vcpu);
3924 }
3925
3926 static int emulate_on_interception(struct vcpu_svm *svm)
3927 {
3928         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3929 }
3930
3931 static int rsm_interception(struct vcpu_svm *svm)
3932 {
3933         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3934                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3935 }
3936
3937 static int rdpmc_interception(struct vcpu_svm *svm)
3938 {
3939         int err;
3940
3941         if (!static_cpu_has(X86_FEATURE_NRIPS))
3942                 return emulate_on_interception(svm);
3943
3944         err = kvm_rdpmc(&svm->vcpu);
3945         return kvm_complete_insn_gp(&svm->vcpu, err);
3946 }
3947
3948 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3949                                             unsigned long val)
3950 {
3951         unsigned long cr0 = svm->vcpu.arch.cr0;
3952         bool ret = false;
3953         u64 intercept;
3954
3955         intercept = svm->nested.intercept;
3956
3957         if (!is_guest_mode(&svm->vcpu) ||
3958             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3959                 return false;
3960
3961         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3962         val &= ~SVM_CR0_SELECTIVE_MASK;
3963
3964         if (cr0 ^ val) {
3965                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3966                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3967         }
3968
3969         return ret;
3970 }
3971
3972 #define CR_VALID (1ULL << 63)
3973
3974 static int cr_interception(struct vcpu_svm *svm)
3975 {
3976         int reg, cr;
3977         unsigned long val;
3978         int err;
3979
3980         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3981                 return emulate_on_interception(svm);
3982
3983         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3984                 return emulate_on_interception(svm);
3985
3986         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3987         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3988                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3989         else
3990                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3991
3992         err = 0;
3993         if (cr >= 16) { /* mov to cr */
3994                 cr -= 16;
3995                 val = kvm_register_read(&svm->vcpu, reg);
3996                 switch (cr) {
3997                 case 0:
3998                         if (!check_selective_cr0_intercepted(svm, val))
3999                                 err = kvm_set_cr0(&svm->vcpu, val);
4000                         else
4001                                 return 1;
4002
4003                         break;
4004                 case 3:
4005                         err = kvm_set_cr3(&svm->vcpu, val);
4006                         break;
4007                 case 4:
4008                         err = kvm_set_cr4(&svm->vcpu, val);
4009                         break;
4010                 case 8:
4011                         err = kvm_set_cr8(&svm->vcpu, val);
4012                         break;
4013                 default:
4014                         WARN(1, "unhandled write to CR%d", cr);
4015                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4016                         return 1;
4017                 }
4018         } else { /* mov from cr */
4019                 switch (cr) {
4020                 case 0:
4021                         val = kvm_read_cr0(&svm->vcpu);
4022                         break;
4023                 case 2:
4024                         val = svm->vcpu.arch.cr2;
4025                         break;
4026                 case 3:
4027                         val = kvm_read_cr3(&svm->vcpu);
4028                         break;
4029                 case 4:
4030                         val = kvm_read_cr4(&svm->vcpu);
4031                         break;
4032                 case 8:
4033                         val = kvm_get_cr8(&svm->vcpu);
4034                         break;
4035                 default:
4036                         WARN(1, "unhandled read from CR%d", cr);
4037                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4038                         return 1;
4039                 }
4040                 kvm_register_write(&svm->vcpu, reg, val);
4041         }
4042         return kvm_complete_insn_gp(&svm->vcpu, err);
4043 }
4044
4045 static int dr_interception(struct vcpu_svm *svm)
4046 {
4047         int reg, dr;
4048         unsigned long val;
4049
4050         if (svm->vcpu.guest_debug == 0) {
4051                 /*
4052                  * No more DR vmexits; force a reload of the debug registers
4053                  * and reenter on this instruction.  The next vmexit will
4054                  * retrieve the full state of the debug registers.
4055                  */
4056                 clr_dr_intercepts(svm);
4057                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4058                 return 1;
4059         }
4060
4061         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4062                 return emulate_on_interception(svm);
4063
4064         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4065         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4066
4067         if (dr >= 16) { /* mov to DRn */
4068                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4069                         return 1;
4070                 val = kvm_register_read(&svm->vcpu, reg);
4071                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4072         } else {
4073                 if (!kvm_require_dr(&svm->vcpu, dr))
4074                         return 1;
4075                 kvm_get_dr(&svm->vcpu, dr, &val);
4076                 kvm_register_write(&svm->vcpu, reg, val);
4077         }
4078
4079         return kvm_skip_emulated_instruction(&svm->vcpu);
4080 }
4081
4082 static int cr8_write_interception(struct vcpu_svm *svm)
4083 {
4084         struct kvm_run *kvm_run = svm->vcpu.run;
4085         int r;
4086
4087         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4088         /* instruction emulation calls kvm_set_cr8() */
4089         r = cr_interception(svm);
4090         if (lapic_in_kernel(&svm->vcpu))
4091                 return r;
4092         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4093                 return r;
4094         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4095         return 0;
4096 }
4097
4098 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4099 {
4100         msr->data = 0;
4101
4102         switch (msr->index) {
4103         case MSR_F10H_DECFG:
4104                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4105                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4106                 break;
4107         default:
4108                 return 1;
4109         }
4110
4111         return 0;
4112 }
4113
4114 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4115 {
4116         struct vcpu_svm *svm = to_svm(vcpu);
4117
4118         switch (msr_info->index) {
4119         case MSR_STAR:
4120                 msr_info->data = svm->vmcb->save.star;
4121                 break;
4122 #ifdef CONFIG_X86_64
4123         case MSR_LSTAR:
4124                 msr_info->data = svm->vmcb->save.lstar;
4125                 break;
4126         case MSR_CSTAR:
4127                 msr_info->data = svm->vmcb->save.cstar;
4128                 break;
4129         case MSR_KERNEL_GS_BASE:
4130                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4131                 break;
4132         case MSR_SYSCALL_MASK:
4133                 msr_info->data = svm->vmcb->save.sfmask;
4134                 break;
4135 #endif
4136         case MSR_IA32_SYSENTER_CS:
4137                 msr_info->data = svm->vmcb->save.sysenter_cs;
4138                 break;
4139         case MSR_IA32_SYSENTER_EIP:
4140                 msr_info->data = svm->sysenter_eip;
4141                 break;
4142         case MSR_IA32_SYSENTER_ESP:
4143                 msr_info->data = svm->sysenter_esp;
4144                 break;
4145         case MSR_TSC_AUX:
4146                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4147                         return 1;
4148                 msr_info->data = svm->tsc_aux;
4149                 break;
4150         /*
4151          * Nobody will change the following 5 values in the VMCB so we can
4152          * safely return them on rdmsr. They will always be 0 until LBRV is
4153          * implemented.
4154          */
4155         case MSR_IA32_DEBUGCTLMSR:
4156                 msr_info->data = svm->vmcb->save.dbgctl;
4157                 break;
4158         case MSR_IA32_LASTBRANCHFROMIP:
4159                 msr_info->data = svm->vmcb->save.br_from;
4160                 break;
4161         case MSR_IA32_LASTBRANCHTOIP:
4162                 msr_info->data = svm->vmcb->save.br_to;
4163                 break;
4164         case MSR_IA32_LASTINTFROMIP:
4165                 msr_info->data = svm->vmcb->save.last_excp_from;
4166                 break;
4167         case MSR_IA32_LASTINTTOIP:
4168                 msr_info->data = svm->vmcb->save.last_excp_to;
4169                 break;
4170         case MSR_VM_HSAVE_PA:
4171                 msr_info->data = svm->nested.hsave_msr;
4172                 break;
4173         case MSR_VM_CR:
4174                 msr_info->data = svm->nested.vm_cr_msr;
4175                 break;
4176         case MSR_IA32_SPEC_CTRL:
4177                 if (!msr_info->host_initiated &&
4178                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4179                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4180                         return 1;
4181
4182                 msr_info->data = svm->spec_ctrl;
4183                 break;
4184         case MSR_AMD64_VIRT_SPEC_CTRL:
4185                 if (!msr_info->host_initiated &&
4186                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4187                         return 1;
4188
4189                 msr_info->data = svm->virt_spec_ctrl;
4190                 break;
4191         case MSR_F15H_IC_CFG: {
4192
4193                 int family, model;
4194
4195                 family = guest_cpuid_family(vcpu);
4196                 model  = guest_cpuid_model(vcpu);
4197
4198                 if (family < 0 || model < 0)
4199                         return kvm_get_msr_common(vcpu, msr_info);
4200
4201                 msr_info->data = 0;
4202
4203                 if (family == 0x15 &&
4204                     (model >= 0x2 && model < 0x20))
4205                         msr_info->data = 0x1E;
4206                 }
4207                 break;
4208         case MSR_F10H_DECFG:
4209                 msr_info->data = svm->msr_decfg;
4210                 break;
4211         default:
4212                 return kvm_get_msr_common(vcpu, msr_info);
4213         }
4214         return 0;
4215 }
4216
4217 static int rdmsr_interception(struct vcpu_svm *svm)
4218 {
4219         u32 ecx = kvm_rcx_read(&svm->vcpu);
4220         struct msr_data msr_info;
4221
4222         msr_info.index = ecx;
4223         msr_info.host_initiated = false;
4224         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4225                 trace_kvm_msr_read_ex(ecx);
4226                 kvm_inject_gp(&svm->vcpu, 0);
4227                 return 1;
4228         } else {
4229                 trace_kvm_msr_read(ecx, msr_info.data);
4230
4231                 kvm_rax_write(&svm->vcpu, msr_info.data & 0xffffffff);
4232                 kvm_rdx_write(&svm->vcpu, msr_info.data >> 32);
4233                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4234                 return kvm_skip_emulated_instruction(&svm->vcpu);
4235         }
4236 }
4237
4238 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4239 {
4240         struct vcpu_svm *svm = to_svm(vcpu);
4241         int svm_dis, chg_mask;
4242
4243         if (data & ~SVM_VM_CR_VALID_MASK)
4244                 return 1;
4245
4246         chg_mask = SVM_VM_CR_VALID_MASK;
4247
4248         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4249                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4250
4251         svm->nested.vm_cr_msr &= ~chg_mask;
4252         svm->nested.vm_cr_msr |= (data & chg_mask);
4253
4254         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4255
4256         /* check for svm_disable while efer.svme is set */
4257         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4258                 return 1;
4259
4260         return 0;
4261 }
4262
4263 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4264 {
4265         struct vcpu_svm *svm = to_svm(vcpu);
4266
4267         u32 ecx = msr->index;
4268         u64 data = msr->data;
4269         switch (ecx) {
4270         case MSR_IA32_CR_PAT:
4271                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4272                         return 1;
4273                 vcpu->arch.pat = data;
4274                 svm->vmcb->save.g_pat = data;
4275                 mark_dirty(svm->vmcb, VMCB_NPT);
4276                 break;
4277         case MSR_IA32_SPEC_CTRL:
4278                 if (!msr->host_initiated &&
4279                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4280                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4281                         return 1;
4282
4283                 /* The STIBP bit doesn't fault even if it's not advertised */
4284                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4285                         return 1;
4286
4287                 svm->spec_ctrl = data;
4288
4289                 if (!data)
4290                         break;
4291
4292                 /*
4293                  * For non-nested:
4294                  * When it's written (to non-zero) for the first time, pass
4295                  * it through.
4296                  *
4297                  * For nested:
4298                  * The handling of the MSR bitmap for L2 guests is done in
4299                  * nested_svm_vmrun_msrpm.
4300                  * We update the L1 MSR bit as well since it will end up
4301                  * touching the MSR anyway now.
4302                  */
4303                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4304                 break;
4305         case MSR_IA32_PRED_CMD:
4306                 if (!msr->host_initiated &&
4307                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4308                         return 1;
4309
4310                 if (data & ~PRED_CMD_IBPB)
4311                         return 1;
4312
4313                 if (!data)
4314                         break;
4315
4316                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4317                 if (is_guest_mode(vcpu))
4318                         break;
4319                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4320                 break;
4321         case MSR_AMD64_VIRT_SPEC_CTRL:
4322                 if (!msr->host_initiated &&
4323                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4324                         return 1;
4325
4326                 if (data & ~SPEC_CTRL_SSBD)
4327                         return 1;
4328
4329                 svm->virt_spec_ctrl = data;
4330                 break;
4331         case MSR_STAR:
4332                 svm->vmcb->save.star = data;
4333                 break;
4334 #ifdef CONFIG_X86_64
4335         case MSR_LSTAR:
4336                 svm->vmcb->save.lstar = data;
4337                 break;
4338         case MSR_CSTAR:
4339                 svm->vmcb->save.cstar = data;
4340                 break;
4341         case MSR_KERNEL_GS_BASE:
4342                 svm->vmcb->save.kernel_gs_base = data;
4343                 break;
4344         case MSR_SYSCALL_MASK:
4345                 svm->vmcb->save.sfmask = data;
4346                 break;
4347 #endif
4348         case MSR_IA32_SYSENTER_CS:
4349                 svm->vmcb->save.sysenter_cs = data;
4350                 break;
4351         case MSR_IA32_SYSENTER_EIP:
4352                 svm->sysenter_eip = data;
4353                 svm->vmcb->save.sysenter_eip = data;
4354                 break;
4355         case MSR_IA32_SYSENTER_ESP:
4356                 svm->sysenter_esp = data;
4357                 svm->vmcb->save.sysenter_esp = data;
4358                 break;
4359         case MSR_TSC_AUX:
4360                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4361                         return 1;
4362
4363                 /*
4364                  * This is rare, so we update the MSR here instead of using
4365                  * direct_access_msrs.  Doing that would require a rdmsr in
4366                  * svm_vcpu_put.
4367                  */
4368                 svm->tsc_aux = data;
4369                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4370                 break;
4371         case MSR_IA32_DEBUGCTLMSR:
4372                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4373                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4374                                     __func__, data);
4375                         break;
4376                 }
4377                 if (data & DEBUGCTL_RESERVED_BITS)
4378                         return 1;
4379
4380                 svm->vmcb->save.dbgctl = data;
4381                 mark_dirty(svm->vmcb, VMCB_LBR);
4382                 if (data & (1ULL<<0))
4383                         svm_enable_lbrv(svm);
4384                 else
4385                         svm_disable_lbrv(svm);
4386                 break;
4387         case MSR_VM_HSAVE_PA:
4388                 svm->nested.hsave_msr = data;
4389                 break;
4390         case MSR_VM_CR:
4391                 return svm_set_vm_cr(vcpu, data);
4392         case MSR_VM_IGNNE:
4393                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4394                 break;
4395         case MSR_F10H_DECFG: {
4396                 struct kvm_msr_entry msr_entry;
4397
4398                 msr_entry.index = msr->index;
4399                 if (svm_get_msr_feature(&msr_entry))
4400                         return 1;
4401
4402                 /* Check the supported bits */
4403                 if (data & ~msr_entry.data)
4404                         return 1;
4405
4406                 /* Don't allow the guest to change a bit, #GP */
4407                 if (!msr->host_initiated && (data ^ msr_entry.data))
4408                         return 1;
4409
4410                 svm->msr_decfg = data;
4411                 break;
4412         }
4413         case MSR_IA32_APICBASE:
4414                 if (kvm_vcpu_apicv_active(vcpu))
4415                         avic_update_vapic_bar(to_svm(vcpu), data);
4416                 /* Fall through */
4417         default:
4418                 return kvm_set_msr_common(vcpu, msr);
4419         }
4420         return 0;
4421 }
4422
4423 static int wrmsr_interception(struct vcpu_svm *svm)
4424 {
4425         struct msr_data msr;
4426         u32 ecx = kvm_rcx_read(&svm->vcpu);
4427         u64 data = kvm_read_edx_eax(&svm->vcpu);
4428
4429         msr.data = data;
4430         msr.index = ecx;
4431         msr.host_initiated = false;
4432
4433         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4434         if (kvm_set_msr(&svm->vcpu, &msr)) {
4435                 trace_kvm_msr_write_ex(ecx, data);
4436                 kvm_inject_gp(&svm->vcpu, 0);
4437                 return 1;
4438         } else {
4439                 trace_kvm_msr_write(ecx, data);
4440                 return kvm_skip_emulated_instruction(&svm->vcpu);
4441         }
4442 }
4443
4444 static int msr_interception(struct vcpu_svm *svm)
4445 {
4446         if (svm->vmcb->control.exit_info_1)
4447                 return wrmsr_interception(svm);
4448         else
4449                 return rdmsr_interception(svm);
4450 }
4451
4452 static int interrupt_window_interception(struct vcpu_svm *svm)
4453 {
4454         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4455         svm_clear_vintr(svm);
4456         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4457         mark_dirty(svm->vmcb, VMCB_INTR);
4458         ++svm->vcpu.stat.irq_window_exits;
4459         return 1;
4460 }
4461
4462 static int pause_interception(struct vcpu_svm *svm)
4463 {
4464         struct kvm_vcpu *vcpu = &svm->vcpu;
4465         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4466
4467         if (pause_filter_thresh)
4468                 grow_ple_window(vcpu);
4469
4470         kvm_vcpu_on_spin(vcpu, in_kernel);
4471         return 1;
4472 }
4473
4474 static int nop_interception(struct vcpu_svm *svm)
4475 {
4476         return kvm_skip_emulated_instruction(&(svm->vcpu));
4477 }
4478
4479 static int monitor_interception(struct vcpu_svm *svm)
4480 {
4481         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4482         return nop_interception(svm);
4483 }
4484
4485 static int mwait_interception(struct vcpu_svm *svm)
4486 {
4487         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4488         return nop_interception(svm);
4489 }
4490
4491 enum avic_ipi_failure_cause {
4492         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4493         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4494         AVIC_IPI_FAILURE_INVALID_TARGET,
4495         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4496 };
4497
4498 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4499 {
4500         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4501         u32 icrl = svm->vmcb->control.exit_info_1;
4502         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4503         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4504         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4505
4506         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4507
4508         switch (id) {
4509         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4510                 /*
4511                  * AVIC hardware handles the generation of
4512                  * IPIs when the specified Message Type is Fixed
4513                  * (also known as fixed delivery mode) and
4514                  * the Trigger Mode is edge-triggered. The hardware
4515                  * also supports self and broadcast delivery modes
4516                  * specified via the Destination Shorthand(DSH)
4517                  * field of the ICRL. Logical and physical APIC ID
4518                  * formats are supported. All other IPI types cause
4519                  * a #VMEXIT, which needs to emulated.
4520                  */
4521                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4522                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4523                 break;
4524         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4525                 int i;
4526                 struct kvm_vcpu *vcpu;
4527                 struct kvm *kvm = svm->vcpu.kvm;
4528                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4529
4530                 /*
4531                  * At this point, we expect that the AVIC HW has already
4532                  * set the appropriate IRR bits on the valid target
4533                  * vcpus. So, we just need to kick the appropriate vcpu.
4534                  */
4535                 kvm_for_each_vcpu(i, vcpu, kvm) {
4536                         bool m = kvm_apic_match_dest(vcpu, apic,
4537                                                      icrl & KVM_APIC_SHORT_MASK,
4538                                                      GET_APIC_DEST_FIELD(icrh),
4539                                                      icrl & KVM_APIC_DEST_MASK);
4540
4541                         if (m && !avic_vcpu_is_running(vcpu))
4542                                 kvm_vcpu_wake_up(vcpu);
4543                 }
4544                 break;
4545         }
4546         case AVIC_IPI_FAILURE_INVALID_TARGET:
4547                 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4548                           index, svm->vcpu.vcpu_id, icrh, icrl);
4549                 break;
4550         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4551                 WARN_ONCE(1, "Invalid backing page\n");
4552                 break;
4553         default:
4554                 pr_err("Unknown IPI interception\n");
4555         }
4556
4557         return 1;
4558 }
4559
4560 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4561 {
4562         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4563         int index;
4564         u32 *logical_apic_id_table;
4565         int dlid = GET_APIC_LOGICAL_ID(ldr);
4566
4567         if (!dlid)
4568                 return NULL;
4569
4570         if (flat) { /* flat */
4571                 index = ffs(dlid) - 1;
4572                 if (index > 7)
4573                         return NULL;
4574         } else { /* cluster */
4575                 int cluster = (dlid & 0xf0) >> 4;
4576                 int apic = ffs(dlid & 0x0f) - 1;
4577
4578                 if ((apic < 0) || (apic > 7) ||
4579                     (cluster >= 0xf))
4580                         return NULL;
4581                 index = (cluster << 2) + apic;
4582         }
4583
4584         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4585
4586         return &logical_apic_id_table[index];
4587 }
4588
4589 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4590 {
4591         bool flat;
4592         u32 *entry, new_entry;
4593
4594         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4595         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4596         if (!entry)
4597                 return -EINVAL;
4598
4599         new_entry = READ_ONCE(*entry);
4600         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4601         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4602         new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4603         WRITE_ONCE(*entry, new_entry);
4604
4605         return 0;
4606 }
4607
4608 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4609 {
4610         struct vcpu_svm *svm = to_svm(vcpu);
4611         bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4612         u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4613
4614         if (entry)
4615                 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4616 }
4617
4618 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4619 {
4620         int ret = 0;
4621         struct vcpu_svm *svm = to_svm(vcpu);
4622         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4623
4624         if (ldr == svm->ldr_reg)
4625                 return 0;
4626
4627         avic_invalidate_logical_id_entry(vcpu);
4628
4629         if (ldr)
4630                 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4631
4632         if (!ret)
4633                 svm->ldr_reg = ldr;
4634
4635         return ret;
4636 }
4637
4638 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4639 {
4640         u64 *old, *new;
4641         struct vcpu_svm *svm = to_svm(vcpu);
4642         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4643         u32 id = (apic_id_reg >> 24) & 0xff;
4644
4645         if (vcpu->vcpu_id == id)
4646                 return 0;
4647
4648         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4649         new = avic_get_physical_id_entry(vcpu, id);
4650         if (!new || !old)
4651                 return 1;
4652
4653         /* We need to move physical_id_entry to new offset */
4654         *new = *old;
4655         *old = 0ULL;
4656         to_svm(vcpu)->avic_physical_id_cache = new;
4657
4658         /*
4659          * Also update the guest physical APIC ID in the logical
4660          * APIC ID table entry if already setup the LDR.
4661          */
4662         if (svm->ldr_reg)
4663                 avic_handle_ldr_update(vcpu);
4664
4665         return 0;
4666 }
4667
4668 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4669 {
4670         struct vcpu_svm *svm = to_svm(vcpu);
4671         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4672
4673         if (svm->dfr_reg == dfr)
4674                 return;
4675
4676         avic_invalidate_logical_id_entry(vcpu);
4677         svm->dfr_reg = dfr;
4678 }
4679
4680 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4681 {
4682         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4683         u32 offset = svm->vmcb->control.exit_info_1 &
4684                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4685
4686         switch (offset) {
4687         case APIC_ID:
4688                 if (avic_handle_apic_id_update(&svm->vcpu))
4689                         return 0;
4690                 break;
4691         case APIC_LDR:
4692                 if (avic_handle_ldr_update(&svm->vcpu))
4693                         return 0;
4694                 break;
4695         case APIC_DFR:
4696                 avic_handle_dfr_update(&svm->vcpu);
4697                 break;
4698         default:
4699                 break;
4700         }
4701
4702         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4703
4704         return 1;
4705 }
4706
4707 static bool is_avic_unaccelerated_access_trap(u32 offset)
4708 {
4709         bool ret = false;
4710
4711         switch (offset) {
4712         case APIC_ID:
4713         case APIC_EOI:
4714         case APIC_RRR:
4715         case APIC_LDR:
4716         case APIC_DFR:
4717         case APIC_SPIV:
4718         case APIC_ESR:
4719         case APIC_ICR:
4720         case APIC_LVTT:
4721         case APIC_LVTTHMR:
4722         case APIC_LVTPC:
4723         case APIC_LVT0:
4724         case APIC_LVT1:
4725         case APIC_LVTERR:
4726         case APIC_TMICT:
4727         case APIC_TDCR:
4728                 ret = true;
4729                 break;
4730         default:
4731                 break;
4732         }
4733         return ret;
4734 }
4735
4736 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4737 {
4738         int ret = 0;
4739         u32 offset = svm->vmcb->control.exit_info_1 &
4740                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4741         u32 vector = svm->vmcb->control.exit_info_2 &
4742                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4743         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4744                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4745         bool trap = is_avic_unaccelerated_access_trap(offset);
4746
4747         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4748                                             trap, write, vector);
4749         if (trap) {
4750                 /* Handling Trap */
4751                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4752                 ret = avic_unaccel_trap_write(svm);
4753         } else {
4754                 /* Handling Fault */
4755                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4756         }
4757
4758         return ret;
4759 }
4760
4761 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4762         [SVM_EXIT_READ_CR0]                     = cr_interception,
4763         [SVM_EXIT_READ_CR3]                     = cr_interception,
4764         [SVM_EXIT_READ_CR4]                     = cr_interception,
4765         [SVM_EXIT_READ_CR8]                     = cr_interception,
4766         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4767         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4768         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4769         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4770         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4771         [SVM_EXIT_READ_DR0]                     = dr_interception,
4772         [SVM_EXIT_READ_DR1]                     = dr_interception,
4773         [SVM_EXIT_READ_DR2]                     = dr_interception,
4774         [SVM_EXIT_READ_DR3]                     = dr_interception,
4775         [SVM_EXIT_READ_DR4]                     = dr_interception,
4776         [SVM_EXIT_READ_DR5]                     = dr_interception,
4777         [SVM_EXIT_READ_DR6]                     = dr_interception,
4778         [SVM_EXIT_READ_DR7]                     = dr_interception,
4779         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4780         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4781         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4782         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4783         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4784         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4785         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4786         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4787         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4788         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4789         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4790         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4791         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4792         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4793         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4794         [SVM_EXIT_INTR]                         = intr_interception,
4795         [SVM_EXIT_NMI]                          = nmi_interception,
4796         [SVM_EXIT_SMI]                          = nop_on_interception,
4797         [SVM_EXIT_INIT]                         = nop_on_interception,
4798         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4799         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4800         [SVM_EXIT_CPUID]                        = cpuid_interception,
4801         [SVM_EXIT_IRET]                         = iret_interception,
4802         [SVM_EXIT_INVD]                         = emulate_on_interception,
4803         [SVM_EXIT_PAUSE]                        = pause_interception,
4804         [SVM_EXIT_HLT]                          = halt_interception,
4805         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4806         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4807         [SVM_EXIT_IOIO]                         = io_interception,
4808         [SVM_EXIT_MSR]                          = msr_interception,
4809         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4810         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4811         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4812         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4813         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4814         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4815         [SVM_EXIT_STGI]                         = stgi_interception,
4816         [SVM_EXIT_CLGI]                         = clgi_interception,
4817         [SVM_EXIT_SKINIT]                       = skinit_interception,
4818         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4819         [SVM_EXIT_MONITOR]                      = monitor_interception,
4820         [SVM_EXIT_MWAIT]                        = mwait_interception,
4821         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4822         [SVM_EXIT_NPF]                          = npf_interception,
4823         [SVM_EXIT_RSM]                          = rsm_interception,
4824         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4825         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4826 };
4827
4828 static void dump_vmcb(struct kvm_vcpu *vcpu)
4829 {
4830         struct vcpu_svm *svm = to_svm(vcpu);
4831         struct vmcb_control_area *control = &svm->vmcb->control;
4832         struct vmcb_save_area *save = &svm->vmcb->save;
4833
4834         if (!dump_invalid_vmcb) {
4835                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4836                 return;
4837         }
4838
4839         pr_err("VMCB Control Area:\n");
4840         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4841         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4842         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4843         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4844         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4845         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4846         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4847         pr_err("%-20s%d\n", "pause filter threshold:",
4848                control->pause_filter_thresh);
4849         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4850         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4851         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4852         pr_err("%-20s%d\n", "asid:", control->asid);
4853         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4854         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4855         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4856         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4857         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4858         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4859         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4860         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4861         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4862         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4863         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4864         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4865         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4866         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4867         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4868         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4869         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4870         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4871         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4872         pr_err("VMCB State Save Area:\n");
4873         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4874                "es:",
4875                save->es.selector, save->es.attrib,
4876                save->es.limit, save->es.base);
4877         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4878                "cs:",
4879                save->cs.selector, save->cs.attrib,
4880                save->cs.limit, save->cs.base);
4881         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4882                "ss:",
4883                save->ss.selector, save->ss.attrib,
4884                save->ss.limit, save->ss.base);
4885         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4886                "ds:",
4887                save->ds.selector, save->ds.attrib,
4888                save->ds.limit, save->ds.base);
4889         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4890                "fs:",
4891                save->fs.selector, save->fs.attrib,
4892                save->fs.limit, save->fs.base);
4893         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4894                "gs:",
4895                save->gs.selector, save->gs.attrib,
4896                save->gs.limit, save->gs.base);
4897         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4898                "gdtr:",
4899                save->gdtr.selector, save->gdtr.attrib,
4900                save->gdtr.limit, save->gdtr.base);
4901         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4902                "ldtr:",
4903                save->ldtr.selector, save->ldtr.attrib,
4904                save->ldtr.limit, save->ldtr.base);
4905         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4906                "idtr:",
4907                save->idtr.selector, save->idtr.attrib,
4908                save->idtr.limit, save->idtr.base);
4909         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4910                "tr:",
4911                save->tr.selector, save->tr.attrib,
4912                save->tr.limit, save->tr.base);
4913         pr_err("cpl:            %d                efer:         %016llx\n",
4914                 save->cpl, save->efer);
4915         pr_err("%-15s %016llx %-13s %016llx\n",
4916                "cr0:", save->cr0, "cr2:", save->cr2);
4917         pr_err("%-15s %016llx %-13s %016llx\n",
4918                "cr3:", save->cr3, "cr4:", save->cr4);
4919         pr_err("%-15s %016llx %-13s %016llx\n",
4920                "dr6:", save->dr6, "dr7:", save->dr7);
4921         pr_err("%-15s %016llx %-13s %016llx\n",
4922                "rip:", save->rip, "rflags:", save->rflags);
4923         pr_err("%-15s %016llx %-13s %016llx\n",
4924                "rsp:", save->rsp, "rax:", save->rax);
4925         pr_err("%-15s %016llx %-13s %016llx\n",
4926                "star:", save->star, "lstar:", save->lstar);
4927         pr_err("%-15s %016llx %-13s %016llx\n",
4928                "cstar:", save->cstar, "sfmask:", save->sfmask);
4929         pr_err("%-15s %016llx %-13s %016llx\n",
4930                "kernel_gs_base:", save->kernel_gs_base,
4931                "sysenter_cs:", save->sysenter_cs);
4932         pr_err("%-15s %016llx %-13s %016llx\n",
4933                "sysenter_esp:", save->sysenter_esp,
4934                "sysenter_eip:", save->sysenter_eip);
4935         pr_err("%-15s %016llx %-13s %016llx\n",
4936                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4937         pr_err("%-15s %016llx %-13s %016llx\n",
4938                "br_from:", save->br_from, "br_to:", save->br_to);
4939         pr_err("%-15s %016llx %-13s %016llx\n",
4940                "excp_from:", save->last_excp_from,
4941                "excp_to:", save->last_excp_to);
4942 }
4943
4944 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4945 {
4946         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4947
4948         *info1 = control->exit_info_1;
4949         *info2 = control->exit_info_2;
4950 }
4951
4952 static int handle_exit(struct kvm_vcpu *vcpu)
4953 {
4954         struct vcpu_svm *svm = to_svm(vcpu);
4955         struct kvm_run *kvm_run = vcpu->run;
4956         u32 exit_code = svm->vmcb->control.exit_code;
4957
4958         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4959
4960         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4961                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4962         if (npt_enabled)
4963                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4964
4965         if (unlikely(svm->nested.exit_required)) {
4966                 nested_svm_vmexit(svm);
4967                 svm->nested.exit_required = false;
4968
4969                 return 1;
4970         }
4971
4972         if (is_guest_mode(vcpu)) {
4973                 int vmexit;
4974
4975                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4976                                         svm->vmcb->control.exit_info_1,
4977                                         svm->vmcb->control.exit_info_2,
4978                                         svm->vmcb->control.exit_int_info,
4979                                         svm->vmcb->control.exit_int_info_err,
4980                                         KVM_ISA_SVM);
4981
4982                 vmexit = nested_svm_exit_special(svm);
4983
4984                 if (vmexit == NESTED_EXIT_CONTINUE)
4985                         vmexit = nested_svm_exit_handled(svm);
4986
4987                 if (vmexit == NESTED_EXIT_DONE)
4988                         return 1;
4989         }
4990
4991         svm_complete_interrupts(svm);
4992
4993         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4994                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4995                 kvm_run->fail_entry.hardware_entry_failure_reason
4996                         = svm->vmcb->control.exit_code;
4997                 dump_vmcb(vcpu);
4998                 return 0;
4999         }
5000
5001         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
5002             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
5003             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
5004             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
5005                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
5006                        "exit_code 0x%x\n",
5007                        __func__, svm->vmcb->control.exit_int_info,
5008                        exit_code);
5009
5010         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5011             || !svm_exit_handlers[exit_code]) {
5012                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
5013                 kvm_queue_exception(vcpu, UD_VECTOR);
5014                 return 1;
5015         }
5016
5017         return svm_exit_handlers[exit_code](svm);
5018 }
5019
5020 static void reload_tss(struct kvm_vcpu *vcpu)
5021 {
5022         int cpu = raw_smp_processor_id();
5023
5024         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5025         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5026         load_TR_desc();
5027 }
5028
5029 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5030 {
5031         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5032         int asid = sev_get_asid(svm->vcpu.kvm);
5033
5034         /* Assign the asid allocated with this SEV guest */
5035         svm->vmcb->control.asid = asid;
5036
5037         /*
5038          * Flush guest TLB:
5039          *
5040          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5041          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5042          */
5043         if (sd->sev_vmcbs[asid] == svm->vmcb &&
5044             svm->last_cpu == cpu)
5045                 return;
5046
5047         svm->last_cpu = cpu;
5048         sd->sev_vmcbs[asid] = svm->vmcb;
5049         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5050         mark_dirty(svm->vmcb, VMCB_ASID);
5051 }
5052
5053 static void pre_svm_run(struct vcpu_svm *svm)
5054 {
5055         int cpu = raw_smp_processor_id();
5056
5057         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5058
5059         if (sev_guest(svm->vcpu.kvm))
5060                 return pre_sev_run(svm, cpu);
5061
5062         /* FIXME: handle wraparound of asid_generation */
5063         if (svm->asid_generation != sd->asid_generation)
5064                 new_asid(svm, sd);
5065 }
5066
5067 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5068 {
5069         struct vcpu_svm *svm = to_svm(vcpu);
5070
5071         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5072         vcpu->arch.hflags |= HF_NMI_MASK;
5073         set_intercept(svm, INTERCEPT_IRET);
5074         ++vcpu->stat.nmi_injections;
5075 }
5076
5077 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5078 {
5079         struct vmcb_control_area *control;
5080
5081         /* The following fields are ignored when AVIC is enabled */
5082         control = &svm->vmcb->control;
5083         control->int_vector = irq;
5084         control->int_ctl &= ~V_INTR_PRIO_MASK;
5085         control->int_ctl |= V_IRQ_MASK |
5086                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5087         mark_dirty(svm->vmcb, VMCB_INTR);
5088 }
5089
5090 static void svm_set_irq(struct kvm_vcpu *vcpu)
5091 {
5092         struct vcpu_svm *svm = to_svm(vcpu);
5093
5094         BUG_ON(!(gif_set(svm)));
5095
5096         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5097         ++vcpu->stat.irq_injections;
5098
5099         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5100                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5101 }
5102
5103 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5104 {
5105         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5106 }
5107
5108 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5109 {
5110         struct vcpu_svm *svm = to_svm(vcpu);
5111
5112         if (svm_nested_virtualize_tpr(vcpu) ||
5113             kvm_vcpu_apicv_active(vcpu))
5114                 return;
5115
5116         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5117
5118         if (irr == -1)
5119                 return;
5120
5121         if (tpr >= irr)
5122                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5123 }
5124
5125 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5126 {
5127         return;
5128 }
5129
5130 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5131 {
5132         return avic && irqchip_split(vcpu->kvm);
5133 }
5134
5135 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5136 {
5137 }
5138
5139 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5140 {
5141 }
5142
5143 /* Note: Currently only used by Hyper-V. */
5144 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5145 {
5146         struct vcpu_svm *svm = to_svm(vcpu);
5147         struct vmcb *vmcb = svm->vmcb;
5148
5149         if (kvm_vcpu_apicv_active(vcpu))
5150                 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5151         else
5152                 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5153         mark_dirty(vmcb, VMCB_AVIC);
5154 }
5155
5156 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5157 {
5158         return;
5159 }
5160
5161 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5162 {
5163         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5164         smp_mb__after_atomic();
5165
5166         if (avic_vcpu_is_running(vcpu))
5167                 wrmsrl(SVM_AVIC_DOORBELL,
5168                        kvm_cpu_get_apicid(vcpu->cpu));
5169         else
5170                 kvm_vcpu_wake_up(vcpu);
5171 }
5172
5173 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5174 {
5175         unsigned long flags;
5176         struct amd_svm_iommu_ir *cur;
5177
5178         spin_lock_irqsave(&svm->ir_list_lock, flags);
5179         list_for_each_entry(cur, &svm->ir_list, node) {
5180                 if (cur->data != pi->ir_data)
5181                         continue;
5182                 list_del(&cur->node);
5183                 kfree(cur);
5184                 break;
5185         }
5186         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5187 }
5188
5189 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5190 {
5191         int ret = 0;
5192         unsigned long flags;
5193         struct amd_svm_iommu_ir *ir;
5194
5195         /**
5196          * In some cases, the existing irte is updaed and re-set,
5197          * so we need to check here if it's already been * added
5198          * to the ir_list.
5199          */
5200         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5201                 struct kvm *kvm = svm->vcpu.kvm;
5202                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5203                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5204                 struct vcpu_svm *prev_svm;
5205
5206                 if (!prev_vcpu) {
5207                         ret = -EINVAL;
5208                         goto out;
5209                 }
5210
5211                 prev_svm = to_svm(prev_vcpu);
5212                 svm_ir_list_del(prev_svm, pi);
5213         }
5214
5215         /**
5216          * Allocating new amd_iommu_pi_data, which will get
5217          * add to the per-vcpu ir_list.
5218          */
5219         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5220         if (!ir) {
5221                 ret = -ENOMEM;
5222                 goto out;
5223         }
5224         ir->data = pi->ir_data;
5225
5226         spin_lock_irqsave(&svm->ir_list_lock, flags);
5227         list_add(&ir->node, &svm->ir_list);
5228         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5229 out:
5230         return ret;
5231 }
5232
5233 /**
5234  * Note:
5235  * The HW cannot support posting multicast/broadcast
5236  * interrupts to a vCPU. So, we still use legacy interrupt
5237  * remapping for these kind of interrupts.
5238  *
5239  * For lowest-priority interrupts, we only support
5240  * those with single CPU as the destination, e.g. user
5241  * configures the interrupts via /proc/irq or uses
5242  * irqbalance to make the interrupts single-CPU.
5243  */
5244 static int
5245 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5246                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5247 {
5248         struct kvm_lapic_irq irq;
5249         struct kvm_vcpu *vcpu = NULL;
5250
5251         kvm_set_msi_irq(kvm, e, &irq);
5252
5253         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5254                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5255                          __func__, irq.vector);
5256                 return -1;
5257         }
5258
5259         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5260                  irq.vector);
5261         *svm = to_svm(vcpu);
5262         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5263         vcpu_info->vector = irq.vector;
5264
5265         return 0;
5266 }
5267
5268 /*
5269  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5270  *
5271  * @kvm: kvm
5272  * @host_irq: host irq of the interrupt
5273  * @guest_irq: gsi of the interrupt
5274  * @set: set or unset PI
5275  * returns 0 on success, < 0 on failure
5276  */
5277 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5278                               uint32_t guest_irq, bool set)
5279 {
5280         struct kvm_kernel_irq_routing_entry *e;
5281         struct kvm_irq_routing_table *irq_rt;
5282         int idx, ret = -EINVAL;
5283
5284         if (!kvm_arch_has_assigned_device(kvm) ||
5285             !irq_remapping_cap(IRQ_POSTING_CAP))
5286                 return 0;
5287
5288         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5289                  __func__, host_irq, guest_irq, set);
5290
5291         idx = srcu_read_lock(&kvm->irq_srcu);
5292         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5293         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5294
5295         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5296                 struct vcpu_data vcpu_info;
5297                 struct vcpu_svm *svm = NULL;
5298
5299                 if (e->type != KVM_IRQ_ROUTING_MSI)
5300                         continue;
5301
5302                 /**
5303                  * Here, we setup with legacy mode in the following cases:
5304                  * 1. When cannot target interrupt to a specific vcpu.
5305                  * 2. Unsetting posted interrupt.
5306                  * 3. APIC virtialization is disabled for the vcpu.
5307                  */
5308                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5309                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5310                         struct amd_iommu_pi_data pi;
5311
5312                         /* Try to enable guest_mode in IRTE */
5313                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5314                                             AVIC_HPA_MASK);
5315                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5316                                                      svm->vcpu.vcpu_id);
5317                         pi.is_guest_mode = true;
5318                         pi.vcpu_data = &vcpu_info;
5319                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5320
5321                         /**
5322                          * Here, we successfully setting up vcpu affinity in
5323                          * IOMMU guest mode. Now, we need to store the posted
5324                          * interrupt information in a per-vcpu ir_list so that
5325                          * we can reference to them directly when we update vcpu
5326                          * scheduling information in IOMMU irte.
5327                          */
5328                         if (!ret && pi.is_guest_mode)
5329                                 svm_ir_list_add(svm, &pi);
5330                 } else {
5331                         /* Use legacy mode in IRTE */
5332                         struct amd_iommu_pi_data pi;
5333
5334                         /**
5335                          * Here, pi is used to:
5336                          * - Tell IOMMU to use legacy mode for this interrupt.
5337                          * - Retrieve ga_tag of prior interrupt remapping data.
5338                          */
5339                         pi.is_guest_mode = false;
5340                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5341
5342                         /**
5343                          * Check if the posted interrupt was previously
5344                          * setup with the guest_mode by checking if the ga_tag
5345                          * was cached. If so, we need to clean up the per-vcpu
5346                          * ir_list.
5347                          */
5348                         if (!ret && pi.prev_ga_tag) {
5349                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5350                                 struct kvm_vcpu *vcpu;
5351
5352                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5353                                 if (vcpu)
5354                                         svm_ir_list_del(to_svm(vcpu), &pi);
5355                         }
5356                 }
5357
5358                 if (!ret && svm) {
5359                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5360                                                  e->gsi, vcpu_info.vector,
5361                                                  vcpu_info.pi_desc_addr, set);
5362                 }
5363
5364                 if (ret < 0) {
5365                         pr_err("%s: failed to update PI IRTE\n", __func__);
5366                         goto out;
5367                 }
5368         }
5369
5370         ret = 0;
5371 out:
5372         srcu_read_unlock(&kvm->irq_srcu, idx);
5373         return ret;
5374 }
5375
5376 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5377 {
5378         struct vcpu_svm *svm = to_svm(vcpu);
5379         struct vmcb *vmcb = svm->vmcb;
5380         int ret;
5381         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5382               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5383         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5384
5385         return ret;
5386 }
5387
5388 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5389 {
5390         struct vcpu_svm *svm = to_svm(vcpu);
5391
5392         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5393 }
5394
5395 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5396 {
5397         struct vcpu_svm *svm = to_svm(vcpu);
5398
5399         if (masked) {
5400                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5401                 set_intercept(svm, INTERCEPT_IRET);
5402         } else {
5403                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5404                 clr_intercept(svm, INTERCEPT_IRET);
5405         }
5406 }
5407
5408 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5409 {
5410         struct vcpu_svm *svm = to_svm(vcpu);
5411         struct vmcb *vmcb = svm->vmcb;
5412         int ret;
5413
5414         if (!gif_set(svm) ||
5415              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5416                 return 0;
5417
5418         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5419
5420         if (is_guest_mode(vcpu))
5421                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5422
5423         return ret;
5424 }
5425
5426 static void enable_irq_window(struct kvm_vcpu *vcpu)
5427 {
5428         struct vcpu_svm *svm = to_svm(vcpu);
5429
5430         if (kvm_vcpu_apicv_active(vcpu))
5431                 return;
5432
5433         /*
5434          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5435          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5436          * get that intercept, this function will be called again though and
5437          * we'll get the vintr intercept. However, if the vGIF feature is
5438          * enabled, the STGI interception will not occur. Enable the irq
5439          * window under the assumption that the hardware will set the GIF.
5440          */
5441         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5442                 svm_set_vintr(svm);
5443                 svm_inject_irq(svm, 0x0);
5444         }
5445 }
5446
5447 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5448 {
5449         struct vcpu_svm *svm = to_svm(vcpu);
5450
5451         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5452             == HF_NMI_MASK)
5453                 return; /* IRET will cause a vm exit */
5454
5455         if (!gif_set(svm)) {
5456                 if (vgif_enabled(svm))
5457                         set_intercept(svm, INTERCEPT_STGI);
5458                 return; /* STGI will cause a vm exit */
5459         }
5460
5461         if (svm->nested.exit_required)
5462                 return; /* we're not going to run the guest yet */
5463
5464         /*
5465          * Something prevents NMI from been injected. Single step over possible
5466          * problem (IRET or exception injection or interrupt shadow)
5467          */
5468         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5469         svm->nmi_singlestep = true;
5470         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5471 }
5472
5473 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5474 {
5475         return 0;
5476 }
5477
5478 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5479 {
5480         return 0;
5481 }
5482
5483 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5484 {
5485         struct vcpu_svm *svm = to_svm(vcpu);
5486
5487         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5488                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5489         else
5490                 svm->asid_generation--;
5491 }
5492
5493 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5494 {
5495         struct vcpu_svm *svm = to_svm(vcpu);
5496
5497         invlpga(gva, svm->vmcb->control.asid);
5498 }
5499
5500 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5501 {
5502 }
5503
5504 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5505 {
5506         struct vcpu_svm *svm = to_svm(vcpu);
5507
5508         if (svm_nested_virtualize_tpr(vcpu))
5509                 return;
5510
5511         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5512                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5513                 kvm_set_cr8(vcpu, cr8);
5514         }
5515 }
5516
5517 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5518 {
5519         struct vcpu_svm *svm = to_svm(vcpu);
5520         u64 cr8;
5521
5522         if (svm_nested_virtualize_tpr(vcpu) ||
5523             kvm_vcpu_apicv_active(vcpu))
5524                 return;
5525
5526         cr8 = kvm_get_cr8(vcpu);
5527         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5528         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5529 }
5530
5531 static void svm_complete_interrupts(struct vcpu_svm *svm)
5532 {
5533         u8 vector;
5534         int type;
5535         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5536         unsigned int3_injected = svm->int3_injected;
5537
5538         svm->int3_injected = 0;
5539
5540         /*
5541          * If we've made progress since setting HF_IRET_MASK, we've
5542          * executed an IRET and can allow NMI injection.
5543          */
5544         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5545             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5546                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5547                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5548         }
5549
5550         svm->vcpu.arch.nmi_injected = false;
5551         kvm_clear_exception_queue(&svm->vcpu);
5552         kvm_clear_interrupt_queue(&svm->vcpu);
5553
5554         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5555                 return;
5556
5557         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5558
5559         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5560         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5561
5562         switch (type) {
5563         case SVM_EXITINTINFO_TYPE_NMI:
5564                 svm->vcpu.arch.nmi_injected = true;
5565                 break;
5566         case SVM_EXITINTINFO_TYPE_EXEPT:
5567                 /*
5568                  * In case of software exceptions, do not reinject the vector,
5569                  * but re-execute the instruction instead. Rewind RIP first
5570                  * if we emulated INT3 before.
5571                  */
5572                 if (kvm_exception_is_soft(vector)) {
5573                         if (vector == BP_VECTOR && int3_injected &&
5574                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5575                                 kvm_rip_write(&svm->vcpu,
5576                                               kvm_rip_read(&svm->vcpu) -
5577                                               int3_injected);
5578                         break;
5579                 }
5580                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5581                         u32 err = svm->vmcb->control.exit_int_info_err;
5582                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5583
5584                 } else
5585                         kvm_requeue_exception(&svm->vcpu, vector);
5586                 break;
5587         case SVM_EXITINTINFO_TYPE_INTR:
5588                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5589                 break;
5590         default:
5591                 break;
5592         }
5593 }
5594
5595 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5596 {
5597         struct vcpu_svm *svm = to_svm(vcpu);
5598         struct vmcb_control_area *control = &svm->vmcb->control;
5599
5600         control->exit_int_info = control->event_inj;
5601         control->exit_int_info_err = control->event_inj_err;
5602         control->event_inj = 0;
5603         svm_complete_interrupts(svm);
5604 }
5605
5606 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5607 {
5608         struct vcpu_svm *svm = to_svm(vcpu);
5609
5610         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5611         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5612         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5613
5614         /*
5615          * A vmexit emulation is required before the vcpu can be executed
5616          * again.
5617          */
5618         if (unlikely(svm->nested.exit_required))
5619                 return;
5620
5621         /*
5622          * Disable singlestep if we're injecting an interrupt/exception.
5623          * We don't want our modified rflags to be pushed on the stack where
5624          * we might not be able to easily reset them if we disabled NMI
5625          * singlestep later.
5626          */
5627         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5628                 /*
5629                  * Event injection happens before external interrupts cause a
5630                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5631                  * is enough to force an immediate vmexit.
5632                  */
5633                 disable_nmi_singlestep(svm);
5634                 smp_send_reschedule(vcpu->cpu);
5635         }
5636
5637         pre_svm_run(svm);
5638
5639         sync_lapic_to_cr8(vcpu);
5640
5641         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5642
5643         clgi();
5644         kvm_load_guest_xcr0(vcpu);
5645
5646         /*
5647          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5648          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5649          * is no need to worry about the conditional branch over the wrmsr
5650          * being speculatively taken.
5651          */
5652         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5653
5654         local_irq_enable();
5655
5656         asm volatile (
5657                 "push %%" _ASM_BP "; \n\t"
5658                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5659                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5660                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5661                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5662                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5663                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5664 #ifdef CONFIG_X86_64
5665                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5666                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5667                 "mov %c[r10](%[svm]), %%r10 \n\t"
5668                 "mov %c[r11](%[svm]), %%r11 \n\t"
5669                 "mov %c[r12](%[svm]), %%r12 \n\t"
5670                 "mov %c[r13](%[svm]), %%r13 \n\t"
5671                 "mov %c[r14](%[svm]), %%r14 \n\t"
5672                 "mov %c[r15](%[svm]), %%r15 \n\t"
5673 #endif
5674
5675                 /* Enter guest mode */
5676                 "push %%" _ASM_AX " \n\t"
5677                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5678                 __ex("vmload %%" _ASM_AX) "\n\t"
5679                 __ex("vmrun %%" _ASM_AX) "\n\t"
5680                 __ex("vmsave %%" _ASM_AX) "\n\t"
5681                 "pop %%" _ASM_AX " \n\t"
5682
5683                 /* Save guest registers, load host registers */
5684                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5685                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5686                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5687                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5688                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5689                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5690 #ifdef CONFIG_X86_64
5691                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5692                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5693                 "mov %%r10, %c[r10](%[svm]) \n\t"
5694                 "mov %%r11, %c[r11](%[svm]) \n\t"
5695                 "mov %%r12, %c[r12](%[svm]) \n\t"
5696                 "mov %%r13, %c[r13](%[svm]) \n\t"
5697                 "mov %%r14, %c[r14](%[svm]) \n\t"
5698                 "mov %%r15, %c[r15](%[svm]) \n\t"
5699                 /*
5700                 * Clear host registers marked as clobbered to prevent
5701                 * speculative use.
5702                 */
5703                 "xor %%r8d, %%r8d \n\t"
5704                 "xor %%r9d, %%r9d \n\t"
5705                 "xor %%r10d, %%r10d \n\t"
5706                 "xor %%r11d, %%r11d \n\t"
5707                 "xor %%r12d, %%r12d \n\t"
5708                 "xor %%r13d, %%r13d \n\t"
5709                 "xor %%r14d, %%r14d \n\t"
5710                 "xor %%r15d, %%r15d \n\t"
5711 #endif
5712                 "xor %%ebx, %%ebx \n\t"
5713                 "xor %%ecx, %%ecx \n\t"
5714                 "xor %%edx, %%edx \n\t"
5715                 "xor %%esi, %%esi \n\t"
5716                 "xor %%edi, %%edi \n\t"
5717                 "pop %%" _ASM_BP
5718                 :
5719                 : [svm]"a"(svm),
5720                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5721                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5722                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5723                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5724                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5725                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5726                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5727 #ifdef CONFIG_X86_64
5728                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5729                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5730                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5731                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5732                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5733                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5734                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5735                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5736 #endif
5737                 : "cc", "memory"
5738 #ifdef CONFIG_X86_64
5739                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5740                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5741 #else
5742                 , "ebx", "ecx", "edx", "esi", "edi"
5743 #endif
5744                 );
5745
5746         /* Eliminate branch target predictions from guest mode */
5747         vmexit_fill_RSB();
5748
5749 #ifdef CONFIG_X86_64
5750         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5751 #else
5752         loadsegment(fs, svm->host.fs);
5753 #ifndef CONFIG_X86_32_LAZY_GS
5754         loadsegment(gs, svm->host.gs);
5755 #endif
5756 #endif
5757
5758         /*
5759          * We do not use IBRS in the kernel. If this vCPU has used the
5760          * SPEC_CTRL MSR it may have left it on; save the value and
5761          * turn it off. This is much more efficient than blindly adding
5762          * it to the atomic save/restore list. Especially as the former
5763          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5764          *
5765          * For non-nested case:
5766          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5767          * save it.
5768          *
5769          * For nested case:
5770          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5771          * save it.
5772          */
5773         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5774                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5775
5776         reload_tss(vcpu);
5777
5778         local_irq_disable();
5779
5780         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5781
5782         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5783         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5784         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5785         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5786
5787         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5788                 kvm_before_interrupt(&svm->vcpu);
5789
5790         kvm_put_guest_xcr0(vcpu);
5791         stgi();
5792
5793         /* Any pending NMI will happen here */
5794
5795         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5796                 kvm_after_interrupt(&svm->vcpu);
5797
5798         sync_cr8_to_lapic(vcpu);
5799
5800         svm->next_rip = 0;
5801
5802         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5803
5804         /* if exit due to PF check for async PF */
5805         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5806                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5807
5808         if (npt_enabled) {
5809                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5810                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5811         }
5812
5813         /*
5814          * We need to handle MC intercepts here before the vcpu has a chance to
5815          * change the physical cpu
5816          */
5817         if (unlikely(svm->vmcb->control.exit_code ==
5818                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5819                 svm_handle_mce(svm);
5820
5821         mark_all_clean(svm->vmcb);
5822 }
5823 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5824
5825 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5826 {
5827         struct vcpu_svm *svm = to_svm(vcpu);
5828
5829         svm->vmcb->save.cr3 = __sme_set(root);
5830         mark_dirty(svm->vmcb, VMCB_CR);
5831 }
5832
5833 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5834 {
5835         struct vcpu_svm *svm = to_svm(vcpu);
5836
5837         svm->vmcb->control.nested_cr3 = __sme_set(root);
5838         mark_dirty(svm->vmcb, VMCB_NPT);
5839
5840         /* Also sync guest cr3 here in case we live migrate */
5841         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5842         mark_dirty(svm->vmcb, VMCB_CR);
5843 }
5844
5845 static int is_disabled(void)
5846 {
5847         u64 vm_cr;
5848
5849         rdmsrl(MSR_VM_CR, vm_cr);
5850         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5851                 return 1;
5852
5853         return 0;
5854 }
5855
5856 static void
5857 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5858 {
5859         /*
5860          * Patch in the VMMCALL instruction:
5861          */
5862         hypercall[0] = 0x0f;
5863         hypercall[1] = 0x01;
5864         hypercall[2] = 0xd9;
5865 }
5866
5867 static void svm_check_processor_compat(void *rtn)
5868 {
5869         *(int *)rtn = 0;
5870 }
5871
5872 static bool svm_cpu_has_accelerated_tpr(void)
5873 {
5874         return false;
5875 }
5876
5877 static bool svm_has_emulated_msr(int index)
5878 {
5879         switch (index) {
5880         case MSR_IA32_MCG_EXT_CTL:
5881                 return false;
5882         default:
5883                 break;
5884         }
5885
5886         return true;
5887 }
5888
5889 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5890 {
5891         return 0;
5892 }
5893
5894 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5895 {
5896         struct vcpu_svm *svm = to_svm(vcpu);
5897
5898         /* Update nrips enabled cache */
5899         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5900
5901         if (!kvm_vcpu_apicv_active(vcpu))
5902                 return;
5903
5904         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5905 }
5906
5907 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5908 {
5909         switch (func) {
5910         case 0x1:
5911                 if (avic)
5912                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5913                 break;
5914         case 0x80000001:
5915                 if (nested)
5916                         entry->ecx |= (1 << 2); /* Set SVM bit */
5917                 break;
5918         case 0x8000000A:
5919                 entry->eax = 1; /* SVM revision 1 */
5920                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5921                                    ASID emulation to nested SVM */
5922                 entry->ecx = 0; /* Reserved */
5923                 entry->edx = 0; /* Per default do not support any
5924                                    additional features */
5925
5926                 /* Support next_rip if host supports it */
5927                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5928                         entry->edx |= SVM_FEATURE_NRIP;
5929
5930                 /* Support NPT for the guest if enabled */
5931                 if (npt_enabled)
5932                         entry->edx |= SVM_FEATURE_NPT;
5933
5934                 break;
5935         case 0x8000001F:
5936                 /* Support memory encryption cpuid if host supports it */
5937                 if (boot_cpu_has(X86_FEATURE_SEV))
5938                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5939                                 &entry->ecx, &entry->edx);
5940
5941         }
5942 }
5943
5944 static int svm_get_lpage_level(void)
5945 {
5946         return PT_PDPE_LEVEL;
5947 }
5948
5949 static bool svm_rdtscp_supported(void)
5950 {
5951         return boot_cpu_has(X86_FEATURE_RDTSCP);
5952 }
5953
5954 static bool svm_invpcid_supported(void)
5955 {
5956         return false;
5957 }
5958
5959 static bool svm_mpx_supported(void)
5960 {
5961         return false;
5962 }
5963
5964 static bool svm_xsaves_supported(void)
5965 {
5966         return false;
5967 }
5968
5969 static bool svm_umip_emulated(void)
5970 {
5971         return false;
5972 }
5973
5974 static bool svm_pt_supported(void)
5975 {
5976         return false;
5977 }
5978
5979 static bool svm_has_wbinvd_exit(void)
5980 {
5981         return true;
5982 }
5983
5984 #define PRE_EX(exit)  { .exit_code = (exit), \
5985                         .stage = X86_ICPT_PRE_EXCEPT, }
5986 #define POST_EX(exit) { .exit_code = (exit), \
5987                         .stage = X86_ICPT_POST_EXCEPT, }
5988 #define POST_MEM(exit) { .exit_code = (exit), \
5989                         .stage = X86_ICPT_POST_MEMACCESS, }
5990
5991 static const struct __x86_intercept {
5992         u32 exit_code;
5993         enum x86_intercept_stage stage;
5994 } x86_intercept_map[] = {
5995         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5996         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5997         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5998         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5999         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
6000         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
6001         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
6002         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
6003         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
6004         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
6005         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
6006         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
6007         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
6008         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
6009         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
6010         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
6011         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
6012         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
6013         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
6014         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
6015         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
6016         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
6017         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
6018         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
6019         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
6020         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
6021         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
6022         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
6023         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
6024         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
6025         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
6026         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
6027         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
6028         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
6029         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
6030         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
6031         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
6032         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
6033         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
6034         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
6035         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
6036         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
6037         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
6038         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
6039         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
6040         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
6041 };
6042
6043 #undef PRE_EX
6044 #undef POST_EX
6045 #undef POST_MEM
6046
6047 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6048                                struct x86_instruction_info *info,
6049                                enum x86_intercept_stage stage)
6050 {
6051         struct vcpu_svm *svm = to_svm(vcpu);
6052         int vmexit, ret = X86EMUL_CONTINUE;
6053         struct __x86_intercept icpt_info;
6054         struct vmcb *vmcb = svm->vmcb;
6055
6056         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6057                 goto out;
6058
6059         icpt_info = x86_intercept_map[info->intercept];
6060
6061         if (stage != icpt_info.stage)
6062                 goto out;
6063
6064         switch (icpt_info.exit_code) {
6065         case SVM_EXIT_READ_CR0:
6066                 if (info->intercept == x86_intercept_cr_read)
6067                         icpt_info.exit_code += info->modrm_reg;
6068                 break;
6069         case SVM_EXIT_WRITE_CR0: {
6070                 unsigned long cr0, val;
6071                 u64 intercept;
6072
6073                 if (info->intercept == x86_intercept_cr_write)
6074                         icpt_info.exit_code += info->modrm_reg;
6075
6076                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6077                     info->intercept == x86_intercept_clts)
6078                         break;
6079
6080                 intercept = svm->nested.intercept;
6081
6082                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6083                         break;
6084
6085                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6086                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6087
6088                 if (info->intercept == x86_intercept_lmsw) {
6089                         cr0 &= 0xfUL;
6090                         val &= 0xfUL;
6091                         /* lmsw can't clear PE - catch this here */
6092                         if (cr0 & X86_CR0_PE)
6093                                 val |= X86_CR0_PE;
6094                 }
6095
6096                 if (cr0 ^ val)
6097                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6098
6099                 break;
6100         }
6101         case SVM_EXIT_READ_DR0:
6102         case SVM_EXIT_WRITE_DR0:
6103                 icpt_info.exit_code += info->modrm_reg;
6104                 break;
6105         case SVM_EXIT_MSR:
6106                 if (info->intercept == x86_intercept_wrmsr)
6107                         vmcb->control.exit_info_1 = 1;
6108                 else
6109                         vmcb->control.exit_info_1 = 0;
6110                 break;
6111         case SVM_EXIT_PAUSE:
6112                 /*
6113                  * We get this for NOP only, but pause
6114                  * is rep not, check this here
6115                  */
6116                 if (info->rep_prefix != REPE_PREFIX)
6117                         goto out;
6118                 break;
6119         case SVM_EXIT_IOIO: {
6120                 u64 exit_info;
6121                 u32 bytes;
6122
6123                 if (info->intercept == x86_intercept_in ||
6124                     info->intercept == x86_intercept_ins) {
6125                         exit_info = ((info->src_val & 0xffff) << 16) |
6126                                 SVM_IOIO_TYPE_MASK;
6127                         bytes = info->dst_bytes;
6128                 } else {
6129                         exit_info = (info->dst_val & 0xffff) << 16;
6130                         bytes = info->src_bytes;
6131                 }
6132
6133                 if (info->intercept == x86_intercept_outs ||
6134                     info->intercept == x86_intercept_ins)
6135                         exit_info |= SVM_IOIO_STR_MASK;
6136
6137                 if (info->rep_prefix)
6138                         exit_info |= SVM_IOIO_REP_MASK;
6139
6140                 bytes = min(bytes, 4u);
6141
6142                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6143
6144                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6145
6146                 vmcb->control.exit_info_1 = exit_info;
6147                 vmcb->control.exit_info_2 = info->next_rip;
6148
6149                 break;
6150         }
6151         default:
6152                 break;
6153         }
6154
6155         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6156         if (static_cpu_has(X86_FEATURE_NRIPS))
6157                 vmcb->control.next_rip  = info->next_rip;
6158         vmcb->control.exit_code = icpt_info.exit_code;
6159         vmexit = nested_svm_exit_handled(svm);
6160
6161         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6162                                            : X86EMUL_CONTINUE;
6163
6164 out:
6165         return ret;
6166 }
6167
6168 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6169 {
6170         local_irq_enable();
6171         /*
6172          * We must have an instruction with interrupts enabled, so
6173          * the timer interrupt isn't delayed by the interrupt shadow.
6174          */
6175         asm("nop");
6176         local_irq_disable();
6177 }
6178
6179 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6180 {
6181         if (pause_filter_thresh)
6182                 shrink_ple_window(vcpu);
6183 }
6184
6185 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6186 {
6187         if (avic_handle_apic_id_update(vcpu) != 0)
6188                 return;
6189         avic_handle_dfr_update(vcpu);
6190         avic_handle_ldr_update(vcpu);
6191 }
6192
6193 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6194 {
6195         /* [63:9] are reserved. */
6196         vcpu->arch.mcg_cap &= 0x1ff;
6197 }
6198
6199 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6200 {
6201         struct vcpu_svm *svm = to_svm(vcpu);
6202
6203         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6204         if (!gif_set(svm))
6205                 return 0;
6206
6207         if (is_guest_mode(&svm->vcpu) &&
6208             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6209                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6210                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6211                 svm->nested.exit_required = true;
6212                 return 0;
6213         }
6214
6215         return 1;
6216 }
6217
6218 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6219 {
6220         struct vcpu_svm *svm = to_svm(vcpu);
6221         int ret;
6222
6223         if (is_guest_mode(vcpu)) {
6224                 /* FED8h - SVM Guest */
6225                 put_smstate(u64, smstate, 0x7ed8, 1);
6226                 /* FEE0h - SVM Guest VMCB Physical Address */
6227                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6228
6229                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6230                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6231                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6232
6233                 ret = nested_svm_vmexit(svm);
6234                 if (ret)
6235                         return ret;
6236         }
6237         return 0;
6238 }
6239
6240 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6241 {
6242         struct vcpu_svm *svm = to_svm(vcpu);
6243         struct vmcb *nested_vmcb;
6244         struct kvm_host_map map;
6245         u64 guest;
6246         u64 vmcb;
6247
6248         guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6249         vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6250
6251         if (guest) {
6252                 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6253                         return 1;
6254                 nested_vmcb = map.hva;
6255                 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6256         }
6257         return 0;
6258 }
6259
6260 static int enable_smi_window(struct kvm_vcpu *vcpu)
6261 {
6262         struct vcpu_svm *svm = to_svm(vcpu);
6263
6264         if (!gif_set(svm)) {
6265                 if (vgif_enabled(svm))
6266                         set_intercept(svm, INTERCEPT_STGI);
6267                 /* STGI will cause a vm exit */
6268                 return 1;
6269         }
6270         return 0;
6271 }
6272
6273 static int sev_asid_new(void)
6274 {
6275         int pos;
6276
6277         /*
6278          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6279          */
6280         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6281         if (pos >= max_sev_asid)
6282                 return -EBUSY;
6283
6284         set_bit(pos, sev_asid_bitmap);
6285         return pos + 1;
6286 }
6287
6288 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6289 {
6290         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6291         int asid, ret;
6292
6293         ret = -EBUSY;
6294         if (unlikely(sev->active))
6295                 return ret;
6296
6297         asid = sev_asid_new();
6298         if (asid < 0)
6299                 return ret;
6300
6301         ret = sev_platform_init(&argp->error);
6302         if (ret)
6303                 goto e_free;
6304
6305         sev->active = true;
6306         sev->asid = asid;
6307         INIT_LIST_HEAD(&sev->regions_list);
6308
6309         return 0;
6310
6311 e_free:
6312         __sev_asid_free(asid);
6313         return ret;
6314 }
6315
6316 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6317 {
6318         struct sev_data_activate *data;
6319         int asid = sev_get_asid(kvm);
6320         int ret;
6321
6322         wbinvd_on_all_cpus();
6323
6324         ret = sev_guest_df_flush(error);
6325         if (ret)
6326                 return ret;
6327
6328         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6329         if (!data)
6330                 return -ENOMEM;
6331
6332         /* activate ASID on the given handle */
6333         data->handle = handle;
6334         data->asid   = asid;
6335         ret = sev_guest_activate(data, error);
6336         kfree(data);
6337
6338         return ret;
6339 }
6340
6341 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6342 {
6343         struct fd f;
6344         int ret;
6345
6346         f = fdget(fd);
6347         if (!f.file)
6348                 return -EBADF;
6349
6350         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6351
6352         fdput(f);
6353         return ret;
6354 }
6355
6356 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6357 {
6358         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6359
6360         return __sev_issue_cmd(sev->fd, id, data, error);
6361 }
6362
6363 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6364 {
6365         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6366         struct sev_data_launch_start *start;
6367         struct kvm_sev_launch_start params;
6368         void *dh_blob, *session_blob;
6369         int *error = &argp->error;
6370         int ret;
6371
6372         if (!sev_guest(kvm))
6373                 return -ENOTTY;
6374
6375         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6376                 return -EFAULT;
6377
6378         start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6379         if (!start)
6380                 return -ENOMEM;
6381
6382         dh_blob = NULL;
6383         if (params.dh_uaddr) {
6384                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6385                 if (IS_ERR(dh_blob)) {
6386                         ret = PTR_ERR(dh_blob);
6387                         goto e_free;
6388                 }
6389
6390                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6391                 start->dh_cert_len = params.dh_len;
6392         }
6393
6394         session_blob = NULL;
6395         if (params.session_uaddr) {
6396                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6397                 if (IS_ERR(session_blob)) {
6398                         ret = PTR_ERR(session_blob);
6399                         goto e_free_dh;
6400                 }
6401
6402                 start->session_address = __sme_set(__pa(session_blob));
6403                 start->session_len = params.session_len;
6404         }
6405
6406         start->handle = params.handle;
6407         start->policy = params.policy;
6408
6409         /* create memory encryption context */
6410         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6411         if (ret)
6412                 goto e_free_session;
6413
6414         /* Bind ASID to this guest */
6415         ret = sev_bind_asid(kvm, start->handle, error);
6416         if (ret)
6417                 goto e_free_session;
6418
6419         /* return handle to userspace */
6420         params.handle = start->handle;
6421         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6422                 sev_unbind_asid(kvm, start->handle);
6423                 ret = -EFAULT;
6424                 goto e_free_session;
6425         }
6426
6427         sev->handle = start->handle;
6428         sev->fd = argp->sev_fd;
6429
6430 e_free_session:
6431         kfree(session_blob);
6432 e_free_dh:
6433         kfree(dh_blob);
6434 e_free:
6435         kfree(start);
6436         return ret;
6437 }
6438
6439 static unsigned long get_num_contig_pages(unsigned long idx,
6440                                 struct page **inpages, unsigned long npages)
6441 {
6442         unsigned long paddr, next_paddr;
6443         unsigned long i = idx + 1, pages = 1;
6444
6445         /* find the number of contiguous pages starting from idx */
6446         paddr = __sme_page_pa(inpages[idx]);
6447         while (i < npages) {
6448                 next_paddr = __sme_page_pa(inpages[i++]);
6449                 if ((paddr + PAGE_SIZE) == next_paddr) {
6450                         pages++;
6451                         paddr = next_paddr;
6452                         continue;
6453                 }
6454                 break;
6455         }
6456
6457         return pages;
6458 }
6459
6460 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6461 {
6462         unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6463         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6464         struct kvm_sev_launch_update_data params;
6465         struct sev_data_launch_update_data *data;
6466         struct page **inpages;
6467         int ret;
6468
6469         if (!sev_guest(kvm))
6470                 return -ENOTTY;
6471
6472         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6473                 return -EFAULT;
6474
6475         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6476         if (!data)
6477                 return -ENOMEM;
6478
6479         vaddr = params.uaddr;
6480         size = params.len;
6481         vaddr_end = vaddr + size;
6482
6483         /* Lock the user memory. */
6484         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6485         if (!inpages) {
6486                 ret = -ENOMEM;
6487                 goto e_free;
6488         }
6489
6490         /*
6491          * The LAUNCH_UPDATE command will perform in-place encryption of the
6492          * memory content (i.e it will write the same memory region with C=1).
6493          * It's possible that the cache may contain the data with C=0, i.e.,
6494          * unencrypted so invalidate it first.
6495          */
6496         sev_clflush_pages(inpages, npages);
6497
6498         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6499                 int offset, len;
6500
6501                 /*
6502                  * If the user buffer is not page-aligned, calculate the offset
6503                  * within the page.
6504                  */
6505                 offset = vaddr & (PAGE_SIZE - 1);
6506
6507                 /* Calculate the number of pages that can be encrypted in one go. */
6508                 pages = get_num_contig_pages(i, inpages, npages);
6509
6510                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6511
6512                 data->handle = sev->handle;
6513                 data->len = len;
6514                 data->address = __sme_page_pa(inpages[i]) + offset;
6515                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6516                 if (ret)
6517                         goto e_unpin;
6518
6519                 size -= len;
6520                 next_vaddr = vaddr + len;
6521         }
6522
6523 e_unpin:
6524         /* content of memory is updated, mark pages dirty */
6525         for (i = 0; i < npages; i++) {
6526                 set_page_dirty_lock(inpages[i]);
6527                 mark_page_accessed(inpages[i]);
6528         }
6529         /* unlock the user pages */
6530         sev_unpin_memory(kvm, inpages, npages);
6531 e_free:
6532         kfree(data);
6533         return ret;
6534 }
6535
6536 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6537 {
6538         void __user *measure = (void __user *)(uintptr_t)argp->data;
6539         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6540         struct sev_data_launch_measure *data;
6541         struct kvm_sev_launch_measure params;
6542         void __user *p = NULL;
6543         void *blob = NULL;
6544         int ret;
6545
6546         if (!sev_guest(kvm))
6547                 return -ENOTTY;
6548
6549         if (copy_from_user(&params, measure, sizeof(params)))
6550                 return -EFAULT;
6551
6552         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6553         if (!data)
6554                 return -ENOMEM;
6555
6556         /* User wants to query the blob length */
6557         if (!params.len)
6558                 goto cmd;
6559
6560         p = (void __user *)(uintptr_t)params.uaddr;
6561         if (p) {
6562                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6563                         ret = -EINVAL;
6564                         goto e_free;
6565                 }
6566
6567                 ret = -ENOMEM;
6568                 blob = kmalloc(params.len, GFP_KERNEL);
6569                 if (!blob)
6570                         goto e_free;
6571
6572                 data->address = __psp_pa(blob);
6573                 data->len = params.len;
6574         }
6575
6576 cmd:
6577         data->handle = sev->handle;
6578         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6579
6580         /*
6581          * If we query the session length, FW responded with expected data.
6582          */
6583         if (!params.len)
6584                 goto done;
6585
6586         if (ret)
6587                 goto e_free_blob;
6588
6589         if (blob) {
6590                 if (copy_to_user(p, blob, params.len))
6591                         ret = -EFAULT;
6592         }
6593
6594 done:
6595         params.len = data->len;
6596         if (copy_to_user(measure, &params, sizeof(params)))
6597                 ret = -EFAULT;
6598 e_free_blob:
6599         kfree(blob);
6600 e_free:
6601         kfree(data);
6602         return ret;
6603 }
6604
6605 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6606 {
6607         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6608         struct sev_data_launch_finish *data;
6609         int ret;
6610
6611         if (!sev_guest(kvm))
6612                 return -ENOTTY;
6613
6614         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6615         if (!data)
6616                 return -ENOMEM;
6617
6618         data->handle = sev->handle;
6619         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6620
6621         kfree(data);
6622         return ret;
6623 }
6624
6625 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6626 {
6627         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6628         struct kvm_sev_guest_status params;
6629         struct sev_data_guest_status *data;
6630         int ret;
6631
6632         if (!sev_guest(kvm))
6633                 return -ENOTTY;
6634
6635         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6636         if (!data)
6637                 return -ENOMEM;
6638
6639         data->handle = sev->handle;
6640         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6641         if (ret)
6642                 goto e_free;
6643
6644         params.policy = data->policy;
6645         params.state = data->state;
6646         params.handle = data->handle;
6647
6648         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6649                 ret = -EFAULT;
6650 e_free:
6651         kfree(data);
6652         return ret;
6653 }
6654
6655 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6656                                unsigned long dst, int size,
6657                                int *error, bool enc)
6658 {
6659         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6660         struct sev_data_dbg *data;
6661         int ret;
6662
6663         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6664         if (!data)
6665                 return -ENOMEM;
6666
6667         data->handle = sev->handle;
6668         data->dst_addr = dst;
6669         data->src_addr = src;
6670         data->len = size;
6671
6672         ret = sev_issue_cmd(kvm,
6673                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6674                             data, error);
6675         kfree(data);
6676         return ret;
6677 }
6678
6679 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6680                              unsigned long dst_paddr, int sz, int *err)
6681 {
6682         int offset;
6683
6684         /*
6685          * Its safe to read more than we are asked, caller should ensure that
6686          * destination has enough space.
6687          */
6688         src_paddr = round_down(src_paddr, 16);
6689         offset = src_paddr & 15;
6690         sz = round_up(sz + offset, 16);
6691
6692         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6693 }
6694
6695 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6696                                   unsigned long __user dst_uaddr,
6697                                   unsigned long dst_paddr,
6698                                   int size, int *err)
6699 {
6700         struct page *tpage = NULL;
6701         int ret, offset;
6702
6703         /* if inputs are not 16-byte then use intermediate buffer */
6704         if (!IS_ALIGNED(dst_paddr, 16) ||
6705             !IS_ALIGNED(paddr,     16) ||
6706             !IS_ALIGNED(size,      16)) {
6707                 tpage = (void *)alloc_page(GFP_KERNEL);
6708                 if (!tpage)
6709                         return -ENOMEM;
6710
6711                 dst_paddr = __sme_page_pa(tpage);
6712         }
6713
6714         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6715         if (ret)
6716                 goto e_free;
6717
6718         if (tpage) {
6719                 offset = paddr & 15;
6720                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6721                                  page_address(tpage) + offset, size))
6722                         ret = -EFAULT;
6723         }
6724
6725 e_free:
6726         if (tpage)
6727                 __free_page(tpage);
6728
6729         return ret;
6730 }
6731
6732 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6733                                   unsigned long __user vaddr,
6734                                   unsigned long dst_paddr,
6735                                   unsigned long __user dst_vaddr,
6736                                   int size, int *error)
6737 {
6738         struct page *src_tpage = NULL;
6739         struct page *dst_tpage = NULL;
6740         int ret, len = size;
6741
6742         /* If source buffer is not aligned then use an intermediate buffer */
6743         if (!IS_ALIGNED(vaddr, 16)) {
6744                 src_tpage = alloc_page(GFP_KERNEL);
6745                 if (!src_tpage)
6746                         return -ENOMEM;
6747
6748                 if (copy_from_user(page_address(src_tpage),
6749                                 (void __user *)(uintptr_t)vaddr, size)) {
6750                         __free_page(src_tpage);
6751                         return -EFAULT;
6752                 }
6753
6754                 paddr = __sme_page_pa(src_tpage);
6755         }
6756
6757         /*
6758          *  If destination buffer or length is not aligned then do read-modify-write:
6759          *   - decrypt destination in an intermediate buffer
6760          *   - copy the source buffer in an intermediate buffer
6761          *   - use the intermediate buffer as source buffer
6762          */
6763         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6764                 int dst_offset;
6765
6766                 dst_tpage = alloc_page(GFP_KERNEL);
6767                 if (!dst_tpage) {
6768                         ret = -ENOMEM;
6769                         goto e_free;
6770                 }
6771
6772                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6773                                         __sme_page_pa(dst_tpage), size, error);
6774                 if (ret)
6775                         goto e_free;
6776
6777                 /*
6778                  *  If source is kernel buffer then use memcpy() otherwise
6779                  *  copy_from_user().
6780                  */
6781                 dst_offset = dst_paddr & 15;
6782
6783                 if (src_tpage)
6784                         memcpy(page_address(dst_tpage) + dst_offset,
6785                                page_address(src_tpage), size);
6786                 else {
6787                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6788                                            (void __user *)(uintptr_t)vaddr, size)) {
6789                                 ret = -EFAULT;
6790                                 goto e_free;
6791                         }
6792                 }
6793
6794                 paddr = __sme_page_pa(dst_tpage);
6795                 dst_paddr = round_down(dst_paddr, 16);
6796                 len = round_up(size, 16);
6797         }
6798
6799         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6800
6801 e_free:
6802         if (src_tpage)
6803                 __free_page(src_tpage);
6804         if (dst_tpage)
6805                 __free_page(dst_tpage);
6806         return ret;
6807 }
6808
6809 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6810 {
6811         unsigned long vaddr, vaddr_end, next_vaddr;
6812         unsigned long dst_vaddr;
6813         struct page **src_p, **dst_p;
6814         struct kvm_sev_dbg debug;
6815         unsigned long n;
6816         unsigned int size;
6817         int ret;
6818
6819         if (!sev_guest(kvm))
6820                 return -ENOTTY;
6821
6822         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6823                 return -EFAULT;
6824
6825         if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6826                 return -EINVAL;
6827         if (!debug.dst_uaddr)
6828                 return -EINVAL;
6829
6830         vaddr = debug.src_uaddr;
6831         size = debug.len;
6832         vaddr_end = vaddr + size;
6833         dst_vaddr = debug.dst_uaddr;
6834
6835         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6836                 int len, s_off, d_off;
6837
6838                 /* lock userspace source and destination page */
6839                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6840                 if (!src_p)
6841                         return -EFAULT;
6842
6843                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6844                 if (!dst_p) {
6845                         sev_unpin_memory(kvm, src_p, n);
6846                         return -EFAULT;
6847                 }
6848
6849                 /*
6850                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6851                  * memory content (i.e it will write the same memory region with C=1).
6852                  * It's possible that the cache may contain the data with C=0, i.e.,
6853                  * unencrypted so invalidate it first.
6854                  */
6855                 sev_clflush_pages(src_p, 1);
6856                 sev_clflush_pages(dst_p, 1);
6857
6858                 /*
6859                  * Since user buffer may not be page aligned, calculate the
6860                  * offset within the page.
6861                  */
6862                 s_off = vaddr & ~PAGE_MASK;
6863                 d_off = dst_vaddr & ~PAGE_MASK;
6864                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6865
6866                 if (dec)
6867                         ret = __sev_dbg_decrypt_user(kvm,
6868                                                      __sme_page_pa(src_p[0]) + s_off,
6869                                                      dst_vaddr,
6870                                                      __sme_page_pa(dst_p[0]) + d_off,
6871                                                      len, &argp->error);
6872                 else
6873                         ret = __sev_dbg_encrypt_user(kvm,
6874                                                      __sme_page_pa(src_p[0]) + s_off,
6875                                                      vaddr,
6876                                                      __sme_page_pa(dst_p[0]) + d_off,
6877                                                      dst_vaddr,
6878                                                      len, &argp->error);
6879
6880                 sev_unpin_memory(kvm, src_p, n);
6881                 sev_unpin_memory(kvm, dst_p, n);
6882
6883                 if (ret)
6884                         goto err;
6885
6886                 next_vaddr = vaddr + len;
6887                 dst_vaddr = dst_vaddr + len;
6888                 size -= len;
6889         }
6890 err:
6891         return ret;
6892 }
6893
6894 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6895 {
6896         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6897         struct sev_data_launch_secret *data;
6898         struct kvm_sev_launch_secret params;
6899         struct page **pages;
6900         void *blob, *hdr;
6901         unsigned long n;
6902         int ret, offset;
6903
6904         if (!sev_guest(kvm))
6905                 return -ENOTTY;
6906
6907         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6908                 return -EFAULT;
6909
6910         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6911         if (!pages)
6912                 return -ENOMEM;
6913
6914         /*
6915          * The secret must be copied into contiguous memory region, lets verify
6916          * that userspace memory pages are contiguous before we issue command.
6917          */
6918         if (get_num_contig_pages(0, pages, n) != n) {
6919                 ret = -EINVAL;
6920                 goto e_unpin_memory;
6921         }
6922
6923         ret = -ENOMEM;
6924         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6925         if (!data)
6926                 goto e_unpin_memory;
6927
6928         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6929         data->guest_address = __sme_page_pa(pages[0]) + offset;
6930         data->guest_len = params.guest_len;
6931
6932         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6933         if (IS_ERR(blob)) {
6934                 ret = PTR_ERR(blob);
6935                 goto e_free;
6936         }
6937
6938         data->trans_address = __psp_pa(blob);
6939         data->trans_len = params.trans_len;
6940
6941         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6942         if (IS_ERR(hdr)) {
6943                 ret = PTR_ERR(hdr);
6944                 goto e_free_blob;
6945         }
6946         data->hdr_address = __psp_pa(hdr);
6947         data->hdr_len = params.hdr_len;
6948
6949         data->handle = sev->handle;
6950         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6951
6952         kfree(hdr);
6953
6954 e_free_blob:
6955         kfree(blob);
6956 e_free:
6957         kfree(data);
6958 e_unpin_memory:
6959         sev_unpin_memory(kvm, pages, n);
6960         return ret;
6961 }
6962
6963 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6964 {
6965         struct kvm_sev_cmd sev_cmd;
6966         int r;
6967
6968         if (!svm_sev_enabled())
6969                 return -ENOTTY;
6970
6971         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6972                 return -EFAULT;
6973
6974         mutex_lock(&kvm->lock);
6975
6976         switch (sev_cmd.id) {
6977         case KVM_SEV_INIT:
6978                 r = sev_guest_init(kvm, &sev_cmd);
6979                 break;
6980         case KVM_SEV_LAUNCH_START:
6981                 r = sev_launch_start(kvm, &sev_cmd);
6982                 break;
6983         case KVM_SEV_LAUNCH_UPDATE_DATA:
6984                 r = sev_launch_update_data(kvm, &sev_cmd);
6985                 break;
6986         case KVM_SEV_LAUNCH_MEASURE:
6987                 r = sev_launch_measure(kvm, &sev_cmd);
6988                 break;
6989         case KVM_SEV_LAUNCH_FINISH:
6990                 r = sev_launch_finish(kvm, &sev_cmd);
6991                 break;
6992         case KVM_SEV_GUEST_STATUS:
6993                 r = sev_guest_status(kvm, &sev_cmd);
6994                 break;
6995         case KVM_SEV_DBG_DECRYPT:
6996                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6997                 break;
6998         case KVM_SEV_DBG_ENCRYPT:
6999                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7000                 break;
7001         case KVM_SEV_LAUNCH_SECRET:
7002                 r = sev_launch_secret(kvm, &sev_cmd);
7003                 break;
7004         default:
7005                 r = -EINVAL;
7006                 goto out;
7007         }
7008
7009         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7010                 r = -EFAULT;
7011
7012 out:
7013         mutex_unlock(&kvm->lock);
7014         return r;
7015 }
7016
7017 static int svm_register_enc_region(struct kvm *kvm,
7018                                    struct kvm_enc_region *range)
7019 {
7020         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7021         struct enc_region *region;
7022         int ret = 0;
7023
7024         if (!sev_guest(kvm))
7025                 return -ENOTTY;
7026
7027         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7028                 return -EINVAL;
7029
7030         region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7031         if (!region)
7032                 return -ENOMEM;
7033
7034         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
7035         if (!region->pages) {
7036                 ret = -ENOMEM;
7037                 goto e_free;
7038         }
7039
7040         /*
7041          * The guest may change the memory encryption attribute from C=0 -> C=1
7042          * or vice versa for this memory range. Lets make sure caches are
7043          * flushed to ensure that guest data gets written into memory with
7044          * correct C-bit.
7045          */
7046         sev_clflush_pages(region->pages, region->npages);
7047
7048         region->uaddr = range->addr;
7049         region->size = range->size;
7050
7051         mutex_lock(&kvm->lock);
7052         list_add_tail(&region->list, &sev->regions_list);
7053         mutex_unlock(&kvm->lock);
7054
7055         return ret;
7056
7057 e_free:
7058         kfree(region);
7059         return ret;
7060 }
7061
7062 static struct enc_region *
7063 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7064 {
7065         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7066         struct list_head *head = &sev->regions_list;
7067         struct enc_region *i;
7068
7069         list_for_each_entry(i, head, list) {
7070                 if (i->uaddr == range->addr &&
7071                     i->size == range->size)
7072                         return i;
7073         }
7074
7075         return NULL;
7076 }
7077
7078
7079 static int svm_unregister_enc_region(struct kvm *kvm,
7080                                      struct kvm_enc_region *range)
7081 {
7082         struct enc_region *region;
7083         int ret;
7084
7085         mutex_lock(&kvm->lock);
7086
7087         if (!sev_guest(kvm)) {
7088                 ret = -ENOTTY;
7089                 goto failed;
7090         }
7091
7092         region = find_enc_region(kvm, range);
7093         if (!region) {
7094                 ret = -EINVAL;
7095                 goto failed;
7096         }
7097
7098         __unregister_enc_region_locked(kvm, region);
7099
7100         mutex_unlock(&kvm->lock);
7101         return 0;
7102
7103 failed:
7104         mutex_unlock(&kvm->lock);
7105         return ret;
7106 }
7107
7108 static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
7109 {
7110         /* Not supported */
7111         return 0;
7112 }
7113
7114 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7115                                    uint16_t *vmcs_version)
7116 {
7117         /* Intel-only feature */
7118         return -ENODEV;
7119 }
7120
7121 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7122 {
7123         bool is_user, smap;
7124
7125         is_user = svm_get_cpl(vcpu) == 3;
7126         smap = !kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
7127
7128         /*
7129          * Detect and workaround Errata 1096 Fam_17h_00_0Fh
7130          *
7131          * In non SEV guest, hypervisor will be able to read the guest
7132          * memory to decode the instruction pointer when insn_len is zero
7133          * so we return true to indicate that decoding is possible.
7134          *
7135          * But in the SEV guest, the guest memory is encrypted with the
7136          * guest specific key and hypervisor will not be able to decode the
7137          * instruction pointer so we will not able to workaround it. Lets
7138          * print the error and request to kill the guest.
7139          */
7140         if (is_user && smap) {
7141                 if (!sev_guest(vcpu->kvm))
7142                         return true;
7143
7144                 pr_err_ratelimited("KVM: Guest triggered AMD Erratum 1096\n");
7145                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7146         }
7147
7148         return false;
7149 }
7150
7151 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7152         .cpu_has_kvm_support = has_svm,
7153         .disabled_by_bios = is_disabled,
7154         .hardware_setup = svm_hardware_setup,
7155         .hardware_unsetup = svm_hardware_unsetup,
7156         .check_processor_compatibility = svm_check_processor_compat,
7157         .hardware_enable = svm_hardware_enable,
7158         .hardware_disable = svm_hardware_disable,
7159         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7160         .has_emulated_msr = svm_has_emulated_msr,
7161
7162         .vcpu_create = svm_create_vcpu,
7163         .vcpu_free = svm_free_vcpu,
7164         .vcpu_reset = svm_vcpu_reset,
7165
7166         .vm_alloc = svm_vm_alloc,
7167         .vm_free = svm_vm_free,
7168         .vm_init = avic_vm_init,
7169         .vm_destroy = svm_vm_destroy,
7170
7171         .prepare_guest_switch = svm_prepare_guest_switch,
7172         .vcpu_load = svm_vcpu_load,
7173         .vcpu_put = svm_vcpu_put,
7174         .vcpu_blocking = svm_vcpu_blocking,
7175         .vcpu_unblocking = svm_vcpu_unblocking,
7176
7177         .update_bp_intercept = update_bp_intercept,
7178         .get_msr_feature = svm_get_msr_feature,
7179         .get_msr = svm_get_msr,
7180         .set_msr = svm_set_msr,
7181         .get_segment_base = svm_get_segment_base,
7182         .get_segment = svm_get_segment,
7183         .set_segment = svm_set_segment,
7184         .get_cpl = svm_get_cpl,
7185         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7186         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7187         .decache_cr3 = svm_decache_cr3,
7188         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7189         .set_cr0 = svm_set_cr0,
7190         .set_cr3 = svm_set_cr3,
7191         .set_cr4 = svm_set_cr4,
7192         .set_efer = svm_set_efer,
7193         .get_idt = svm_get_idt,
7194         .set_idt = svm_set_idt,
7195         .get_gdt = svm_get_gdt,
7196         .set_gdt = svm_set_gdt,
7197         .get_dr6 = svm_get_dr6,
7198         .set_dr6 = svm_set_dr6,
7199         .set_dr7 = svm_set_dr7,
7200         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7201         .cache_reg = svm_cache_reg,
7202         .get_rflags = svm_get_rflags,
7203         .set_rflags = svm_set_rflags,
7204
7205         .tlb_flush = svm_flush_tlb,
7206         .tlb_flush_gva = svm_flush_tlb_gva,
7207
7208         .run = svm_vcpu_run,
7209         .handle_exit = handle_exit,
7210         .skip_emulated_instruction = skip_emulated_instruction,
7211         .set_interrupt_shadow = svm_set_interrupt_shadow,
7212         .get_interrupt_shadow = svm_get_interrupt_shadow,
7213         .patch_hypercall = svm_patch_hypercall,
7214         .set_irq = svm_set_irq,
7215         .set_nmi = svm_inject_nmi,
7216         .queue_exception = svm_queue_exception,
7217         .cancel_injection = svm_cancel_injection,
7218         .interrupt_allowed = svm_interrupt_allowed,
7219         .nmi_allowed = svm_nmi_allowed,
7220         .get_nmi_mask = svm_get_nmi_mask,
7221         .set_nmi_mask = svm_set_nmi_mask,
7222         .enable_nmi_window = enable_nmi_window,
7223         .enable_irq_window = enable_irq_window,
7224         .update_cr8_intercept = update_cr8_intercept,
7225         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7226         .get_enable_apicv = svm_get_enable_apicv,
7227         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7228         .load_eoi_exitmap = svm_load_eoi_exitmap,
7229         .hwapic_irr_update = svm_hwapic_irr_update,
7230         .hwapic_isr_update = svm_hwapic_isr_update,
7231         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7232         .apicv_post_state_restore = avic_post_state_restore,
7233
7234         .set_tss_addr = svm_set_tss_addr,
7235         .set_identity_map_addr = svm_set_identity_map_addr,
7236         .get_tdp_level = get_npt_level,
7237         .get_mt_mask = svm_get_mt_mask,
7238
7239         .get_exit_info = svm_get_exit_info,
7240
7241         .get_lpage_level = svm_get_lpage_level,
7242
7243         .cpuid_update = svm_cpuid_update,
7244
7245         .rdtscp_supported = svm_rdtscp_supported,
7246         .invpcid_supported = svm_invpcid_supported,
7247         .mpx_supported = svm_mpx_supported,
7248         .xsaves_supported = svm_xsaves_supported,
7249         .umip_emulated = svm_umip_emulated,
7250         .pt_supported = svm_pt_supported,
7251
7252         .set_supported_cpuid = svm_set_supported_cpuid,
7253
7254         .has_wbinvd_exit = svm_has_wbinvd_exit,
7255
7256         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7257         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7258
7259         .set_tdp_cr3 = set_tdp_cr3,
7260
7261         .check_intercept = svm_check_intercept,
7262         .handle_external_intr = svm_handle_external_intr,
7263
7264         .request_immediate_exit = __kvm_request_immediate_exit,
7265
7266         .sched_in = svm_sched_in,
7267
7268         .pmu_ops = &amd_pmu_ops,
7269         .deliver_posted_interrupt = svm_deliver_avic_intr,
7270         .update_pi_irte = svm_update_pi_irte,
7271         .setup_mce = svm_setup_mce,
7272
7273         .smi_allowed = svm_smi_allowed,
7274         .pre_enter_smm = svm_pre_enter_smm,
7275         .pre_leave_smm = svm_pre_leave_smm,
7276         .enable_smi_window = enable_smi_window,
7277
7278         .mem_enc_op = svm_mem_enc_op,
7279         .mem_enc_reg_region = svm_register_enc_region,
7280         .mem_enc_unreg_region = svm_unregister_enc_region,
7281
7282         .nested_enable_evmcs = nested_enable_evmcs,
7283         .nested_get_evmcs_version = nested_get_evmcs_version,
7284
7285         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7286 };
7287
7288 static int __init svm_init(void)
7289 {
7290         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7291                         __alignof__(struct vcpu_svm), THIS_MODULE);
7292 }
7293
7294 static void __exit svm_exit(void)
7295 {
7296         kvm_exit();
7297 }
7298
7299 module_init(svm_init)
7300 module_exit(svm_exit)