arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv_reg_vid;
  88
  89 /*
  90  * If nested=1, nested virtualization is supported, i.e., guests may use
  91  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  92  * use VMX instructions.
  93  */
  94 static bool __read_mostly nested = 0;
  95 module_param(nested, bool, S_IRUGO);
  96
  97 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
  98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
  99 #define KVM_VM_CR0_ALWAYS_ON                                            \
 100         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 101 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 102         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 103          | X86_CR4_OSXMMEXCPT)
 104
 105 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 106 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 107
 108 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 109
 110 /*
 111  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 112  * ple_gap:    upper bound on the amount of time between two successive
 113  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 114  *             According to test, this time is usually smaller than 128 cycles.
 115  * ple_window: upper bound on the amount of time a guest is allowed to execute
 116  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 117  *             less than 2^12 cycles
 118  * Time is measured based on a counter that runs at the same rate as the TSC,
 119  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 120  */
 121 #define KVM_VMX_DEFAULT_PLE_GAP    128
 122 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 123 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 124 module_param(ple_gap, int, S_IRUGO);
 125
 126 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 127 module_param(ple_window, int, S_IRUGO);
 128
 129 extern const ulong vmx_return;
 130
 131 #define NR_AUTOLOAD_MSRS 8
 132 #define VMCS02_POOL_SIZE 1
 133
 134 struct vmcs {
 135         u32 revision_id;
 136         u32 abort;
 137         char data[0];
 138 };
 139
 140 /*
 141  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 142  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 143  * loaded on this CPU (so we can clear them if the CPU goes down).
 144  */
 145 struct loaded_vmcs {
 146         struct vmcs *vmcs;
 147         int cpu;
 148         int launched;
 149         struct list_head loaded_vmcss_on_cpu_link;
 150 };
 151
 152 struct shared_msr_entry {
 153         unsigned index;
 154         u64 data;
 155         u64 mask;
 156 };
 157
 158 /*
 159  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 160  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 161  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 162  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 163  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 164  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 165  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 166  * underlying hardware which will be used to run L2.
 167  * This structure is packed to ensure that its layout is identical across
 168  * machines (necessary for live migration).
 169  * If there are changes in this struct, VMCS12_REVISION must be changed.
 170  */
 171 typedef u64 natural_width;
 172 struct __packed vmcs12 {
 173         /* According to the Intel spec, a VMCS region must start with the
 174          * following two fields. Then follow implementation-specific data.
 175          */
 176         u32 revision_id;
 177         u32 abort;
 178
 179         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 180         u32 padding[7]; /* room for future expansion */
 181
 182         u64 io_bitmap_a;
 183         u64 io_bitmap_b;
 184         u64 msr_bitmap;
 185         u64 vm_exit_msr_store_addr;
 186         u64 vm_exit_msr_load_addr;
 187         u64 vm_entry_msr_load_addr;
 188         u64 tsc_offset;
 189         u64 virtual_apic_page_addr;
 190         u64 apic_access_addr;
 191         u64 ept_pointer;
 192         u64 guest_physical_address;
 193         u64 vmcs_link_pointer;
 194         u64 guest_ia32_debugctl;
 195         u64 guest_ia32_pat;
 196         u64 guest_ia32_efer;
 197         u64 guest_ia32_perf_global_ctrl;
 198         u64 guest_pdptr0;
 199         u64 guest_pdptr1;
 200         u64 guest_pdptr2;
 201         u64 guest_pdptr3;
 202         u64 host_ia32_pat;
 203         u64 host_ia32_efer;
 204         u64 host_ia32_perf_global_ctrl;
 205         u64 padding64[8]; /* room for future expansion */
 206         /*
 207          * To allow migration of L1 (complete with its L2 guests) between
 208          * machines of different natural widths (32 or 64 bit), we cannot have
 209          * unsigned long fields with no explict size. We use u64 (aliased
 210          * natural_width) instead. Luckily, x86 is little-endian.
 211          */
 212         natural_width cr0_guest_host_mask;
 213         natural_width cr4_guest_host_mask;
 214         natural_width cr0_read_shadow;
 215         natural_width cr4_read_shadow;
 216         natural_width cr3_target_value0;
 217         natural_width cr3_target_value1;
 218         natural_width cr3_target_value2;
 219         natural_width cr3_target_value3;
 220         natural_width exit_qualification;
 221         natural_width guest_linear_address;
 222         natural_width guest_cr0;
 223         natural_width guest_cr3;
 224         natural_width guest_cr4;
 225         natural_width guest_es_base;
 226         natural_width guest_cs_base;
 227         natural_width guest_ss_base;
 228         natural_width guest_ds_base;
 229         natural_width guest_fs_base;
 230         natural_width guest_gs_base;
 231         natural_width guest_ldtr_base;
 232         natural_width guest_tr_base;
 233         natural_width guest_gdtr_base;
 234         natural_width guest_idtr_base;
 235         natural_width guest_dr7;
 236         natural_width guest_rsp;
 237         natural_width guest_rip;
 238         natural_width guest_rflags;
 239         natural_width guest_pending_dbg_exceptions;
 240         natural_width guest_sysenter_esp;
 241         natural_width guest_sysenter_eip;
 242         natural_width host_cr0;
 243         natural_width host_cr3;
 244         natural_width host_cr4;
 245         natural_width host_fs_base;
 246         natural_width host_gs_base;
 247         natural_width host_tr_base;
 248         natural_width host_gdtr_base;
 249         natural_width host_idtr_base;
 250         natural_width host_ia32_sysenter_esp;
 251         natural_width host_ia32_sysenter_eip;
 252         natural_width host_rsp;
 253         natural_width host_rip;
 254         natural_width paddingl[8]; /* room for future expansion */
 255         u32 pin_based_vm_exec_control;
 256         u32 cpu_based_vm_exec_control;
 257         u32 exception_bitmap;
 258         u32 page_fault_error_code_mask;
 259         u32 page_fault_error_code_match;
 260         u32 cr3_target_count;
 261         u32 vm_exit_controls;
 262         u32 vm_exit_msr_store_count;
 263         u32 vm_exit_msr_load_count;
 264         u32 vm_entry_controls;
 265         u32 vm_entry_msr_load_count;
 266         u32 vm_entry_intr_info_field;
 267         u32 vm_entry_exception_error_code;
 268         u32 vm_entry_instruction_len;
 269         u32 tpr_threshold;
 270         u32 secondary_vm_exec_control;
 271         u32 vm_instruction_error;
 272         u32 vm_exit_reason;
 273         u32 vm_exit_intr_info;
 274         u32 vm_exit_intr_error_code;
 275         u32 idt_vectoring_info_field;
 276         u32 idt_vectoring_error_code;
 277         u32 vm_exit_instruction_len;
 278         u32 vmx_instruction_info;
 279         u32 guest_es_limit;
 280         u32 guest_cs_limit;
 281         u32 guest_ss_limit;
 282         u32 guest_ds_limit;
 283         u32 guest_fs_limit;
 284         u32 guest_gs_limit;
 285         u32 guest_ldtr_limit;
 286         u32 guest_tr_limit;
 287         u32 guest_gdtr_limit;
 288         u32 guest_idtr_limit;
 289         u32 guest_es_ar_bytes;
 290         u32 guest_cs_ar_bytes;
 291         u32 guest_ss_ar_bytes;
 292         u32 guest_ds_ar_bytes;
 293         u32 guest_fs_ar_bytes;
 294         u32 guest_gs_ar_bytes;
 295         u32 guest_ldtr_ar_bytes;
 296         u32 guest_tr_ar_bytes;
 297         u32 guest_interruptibility_info;
 298         u32 guest_activity_state;
 299         u32 guest_sysenter_cs;
 300         u32 host_ia32_sysenter_cs;
 301         u32 vmx_preemption_timer_value;
 302         u32 padding32[7]; /* room for future expansion */
 303         u16 virtual_processor_id;
 304         u16 guest_es_selector;
 305         u16 guest_cs_selector;
 306         u16 guest_ss_selector;
 307         u16 guest_ds_selector;
 308         u16 guest_fs_selector;
 309         u16 guest_gs_selector;
 310         u16 guest_ldtr_selector;
 311         u16 guest_tr_selector;
 312         u16 host_es_selector;
 313         u16 host_cs_selector;
 314         u16 host_ss_selector;
 315         u16 host_ds_selector;
 316         u16 host_fs_selector;
 317         u16 host_gs_selector;
 318         u16 host_tr_selector;
 319 };
 320
 321 /*
 322  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 323  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 324  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 325  */
 326 #define VMCS12_REVISION 0x11e57ed0
 327
 328 /*
 329  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 330  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 331  * current implementation, 4K are reserved to avoid future complications.
 332  */
 333 #define VMCS12_SIZE 0x1000
 334
 335 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 336 struct vmcs02_list {
 337         struct list_head list;
 338         gpa_t vmptr;
 339         struct loaded_vmcs vmcs02;
 340 };
 341
 342 /*
 343  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 344  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 345  */
 346 struct nested_vmx {
 347         /* Has the level1 guest done vmxon? */
 348         bool vmxon;
 349
 350         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 351         gpa_t current_vmptr;
 352         /* The host-usable pointer to the above */
 353         struct page *current_vmcs12_page;
 354         struct vmcs12 *current_vmcs12;
 355
 356         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 357         struct list_head vmcs02_pool;
 358         int vmcs02_num;
 359         u64 vmcs01_tsc_offset;
 360         /* L2 must run next, and mustn't decide to exit to L1. */
 361         bool nested_run_pending;
 362         /*
 363          * Guest pages referred to in vmcs02 with host-physical pointers, so
 364          * we must keep them pinned while L2 runs.
 365          */
 366         struct page *apic_access_page;
 367 };
 368
 369 struct vcpu_vmx {
 370         struct kvm_vcpu       vcpu;
 371         unsigned long         host_rsp;
 372         u8                    fail;
 373         u8                    cpl;
 374         bool                  nmi_known_unmasked;
 375         u32                   exit_intr_info;
 376         u32                   idt_vectoring_info;
 377         ulong                 rflags;
 378         struct shared_msr_entry *guest_msrs;
 379         int                   nmsrs;
 380         int                   save_nmsrs;
 381 #ifdef CONFIG_X86_64
 382         u64                   msr_host_kernel_gs_base;
 383         u64                   msr_guest_kernel_gs_base;
 384 #endif
 385         /*
 386          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 387          * non-nested (L1) guest, it always points to vmcs01. For a nested
 388          * guest (L2), it points to a different VMCS.
 389          */
 390         struct loaded_vmcs    vmcs01;
 391         struct loaded_vmcs   *loaded_vmcs;
 392         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 393         struct msr_autoload {
 394                 unsigned nr;
 395                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 396                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 397         } msr_autoload;
 398         struct {
 399                 int           loaded;
 400                 u16           fs_sel, gs_sel, ldt_sel;
 401 #ifdef CONFIG_X86_64
 402                 u16           ds_sel, es_sel;
 403 #endif
 404                 int           gs_ldt_reload_needed;
 405                 int           fs_reload_needed;
 406         } host_state;
 407         struct {
 408                 int vm86_active;
 409                 ulong save_rflags;
 410                 struct kvm_segment segs[8];
 411         } rmode;
 412         struct {
 413                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 414                 struct kvm_save_segment {
 415                         u16 selector;
 416                         unsigned long base;
 417                         u32 limit;
 418                         u32 ar;
 419                 } seg[8];
 420         } segment_cache;
 421         int vpid;
 422         bool emulation_required;
 423
 424         /* Support for vnmi-less CPUs */
 425         int soft_vnmi_blocked;
 426         ktime_t entry_time;
 427         s64 vnmi_blocked_time;
 428         u32 exit_reason;
 429
 430         bool rdtscp_enabled;
 431
 432         /* Support for a guest hypervisor (nested VMX) */
 433         struct nested_vmx nested;
 434 };
 435
 436 enum segment_cache_field {
 437         SEG_FIELD_SEL = 0,
 438         SEG_FIELD_BASE = 1,
 439         SEG_FIELD_LIMIT = 2,
 440         SEG_FIELD_AR = 3,
 441
 442         SEG_FIELD_NR = 4
 443 };
 444
 445 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 446 {
 447         return container_of(vcpu, struct vcpu_vmx, vcpu);
 448 }
 449
 450 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 451 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 452 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 453                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 454
 455 static const unsigned short vmcs_field_to_offset_table[] = {
 456         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 457         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 458         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 459         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 460         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 461         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 462         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 463         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 464         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 465         FIELD(HOST_ES_SELECTOR, host_es_selector),
 466         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 467         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 468         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 469         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 470         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 471         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 472         FIELD64(IO_BITMAP_A, io_bitmap_a),
 473         FIELD64(IO_BITMAP_B, io_bitmap_b),
 474         FIELD64(MSR_BITMAP, msr_bitmap),
 475         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 476         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 477         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 478         FIELD64(TSC_OFFSET, tsc_offset),
 479         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 480         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 481         FIELD64(EPT_POINTER, ept_pointer),
 482         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 483         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 484         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 485         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 486         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 487         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 488         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 489         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 490         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 491         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 492         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 493         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 494         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 495         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 496         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 497         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 498         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 499         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 500         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 501         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 502         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 503         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 504         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 505         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 506         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 507         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 508         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 509         FIELD(TPR_THRESHOLD, tpr_threshold),
 510         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 511         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 512         FIELD(VM_EXIT_REASON, vm_exit_reason),
 513         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 514         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 515         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 516         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 517         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 518         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 519         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 520         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 521         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 522         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 523         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 524         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 525         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 526         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 527         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 528         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 529         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 530         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 531         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 532         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 533         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 534         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 535         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 536         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 537         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 538         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 539         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 540         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 541         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 542         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 543         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 544         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 545         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 546         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 547         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 548         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 549         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 550         FIELD(EXIT_QUALIFICATION, exit_qualification),
 551         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 552         FIELD(GUEST_CR0, guest_cr0),
 553         FIELD(GUEST_CR3, guest_cr3),
 554         FIELD(GUEST_CR4, guest_cr4),
 555         FIELD(GUEST_ES_BASE, guest_es_base),
 556         FIELD(GUEST_CS_BASE, guest_cs_base),
 557         FIELD(GUEST_SS_BASE, guest_ss_base),
 558         FIELD(GUEST_DS_BASE, guest_ds_base),
 559         FIELD(GUEST_FS_BASE, guest_fs_base),
 560         FIELD(GUEST_GS_BASE, guest_gs_base),
 561         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 562         FIELD(GUEST_TR_BASE, guest_tr_base),
 563         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 564         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 565         FIELD(GUEST_DR7, guest_dr7),
 566         FIELD(GUEST_RSP, guest_rsp),
 567         FIELD(GUEST_RIP, guest_rip),
 568         FIELD(GUEST_RFLAGS, guest_rflags),
 569         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 570         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 571         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 572         FIELD(HOST_CR0, host_cr0),
 573         FIELD(HOST_CR3, host_cr3),
 574         FIELD(HOST_CR4, host_cr4),
 575         FIELD(HOST_FS_BASE, host_fs_base),
 576         FIELD(HOST_GS_BASE, host_gs_base),
 577         FIELD(HOST_TR_BASE, host_tr_base),
 578         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 579         FIELD(HOST_IDTR_BASE, host_idtr_base),
 580         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 581         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 582         FIELD(HOST_RSP, host_rsp),
 583         FIELD(HOST_RIP, host_rip),
 584 };
 585 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 586
 587 static inline short vmcs_field_to_offset(unsigned long field)
 588 {
 589         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 590                 return -1;
 591         return vmcs_field_to_offset_table[field];
 592 }
 593
 594 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 595 {
 596         return to_vmx(vcpu)->nested.current_vmcs12;
 597 }
 598
 599 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 600 {
 601         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 602         if (is_error_page(page))
 603                 return NULL;
 604
 605         return page;
 606 }
 607
 608 static void nested_release_page(struct page *page)
 609 {
 610         kvm_release_page_dirty(page);
 611 }
 612
 613 static void nested_release_page_clean(struct page *page)
 614 {
 615         kvm_release_page_clean(page);
 616 }
 617
 618 static u64 construct_eptp(unsigned long root_hpa);
 619 static void kvm_cpu_vmxon(u64 addr);
 620 static void kvm_cpu_vmxoff(void);
 621 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 622 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 623 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 624                             struct kvm_segment *var, int seg);
 625 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 626                             struct kvm_segment *var, int seg);
 627 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 628 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 629
 630 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 631 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 632 /*
 633  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 634  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 635  */
 636 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 637 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 638
 639 static unsigned long *vmx_io_bitmap_a;
 640 static unsigned long *vmx_io_bitmap_b;
 641 static unsigned long *vmx_msr_bitmap_legacy;
 642 static unsigned long *vmx_msr_bitmap_longmode;
 643 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 644 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 645
 646 static bool cpu_has_load_ia32_efer;
 647 static bool cpu_has_load_perf_global_ctrl;
 648
 649 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 650 static DEFINE_SPINLOCK(vmx_vpid_lock);
 651
 652 static struct vmcs_config {
 653         int size;
 654         int order;
 655         u32 revision_id;
 656         u32 pin_based_exec_ctrl;
 657         u32 cpu_based_exec_ctrl;
 658         u32 cpu_based_2nd_exec_ctrl;
 659         u32 vmexit_ctrl;
 660         u32 vmentry_ctrl;
 661 } vmcs_config;
 662
 663 static struct vmx_capability {
 664         u32 ept;
 665         u32 vpid;
 666 } vmx_capability;
 667
 668 #define VMX_SEGMENT_FIELD(seg)                                  \
 669         [VCPU_SREG_##seg] = {                                   \
 670                 .selector = GUEST_##seg##_SELECTOR,             \
 671                 .base = GUEST_##seg##_BASE,                     \
 672                 .limit = GUEST_##seg##_LIMIT,                   \
 673                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 674         }
 675
 676 static const struct kvm_vmx_segment_field {
 677         unsigned selector;
 678         unsigned base;
 679         unsigned limit;
 680         unsigned ar_bytes;
 681 } kvm_vmx_segment_fields[] = {
 682         VMX_SEGMENT_FIELD(CS),
 683         VMX_SEGMENT_FIELD(DS),
 684         VMX_SEGMENT_FIELD(ES),
 685         VMX_SEGMENT_FIELD(FS),
 686         VMX_SEGMENT_FIELD(GS),
 687         VMX_SEGMENT_FIELD(SS),
 688         VMX_SEGMENT_FIELD(TR),
 689         VMX_SEGMENT_FIELD(LDTR),
 690 };
 691
 692 static u64 host_efer;
 693
 694 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 695
 696 /*
 697  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 698  * away by decrementing the array size.
 699  */
 700 static const u32 vmx_msr_index[] = {
 701 #ifdef CONFIG_X86_64
 702         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 703 #endif
 704         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 705 };
 706 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 707
 708 static inline bool is_page_fault(u32 intr_info)
 709 {
 710         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 711                              INTR_INFO_VALID_MASK)) ==
 712                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 713 }
 714
 715 static inline bool is_no_device(u32 intr_info)
 716 {
 717         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 718                              INTR_INFO_VALID_MASK)) ==
 719                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 720 }
 721
 722 static inline bool is_invalid_opcode(u32 intr_info)
 723 {
 724         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 725                              INTR_INFO_VALID_MASK)) ==
 726                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 727 }
 728
 729 static inline bool is_external_interrupt(u32 intr_info)
 730 {
 731         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 732                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 733 }
 734
 735 static inline bool is_machine_check(u32 intr_info)
 736 {
 737         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 738                              INTR_INFO_VALID_MASK)) ==
 739                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 740 }
 741
 742 static inline bool cpu_has_vmx_msr_bitmap(void)
 743 {
 744         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 745 }
 746
 747 static inline bool cpu_has_vmx_tpr_shadow(void)
 748 {
 749         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 750 }
 751
 752 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 753 {
 754         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 755 }
 756
 757 static inline bool cpu_has_secondary_exec_ctrls(void)
 758 {
 759         return vmcs_config.cpu_based_exec_ctrl &
 760                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 761 }
 762
 763 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 764 {
 765         return vmcs_config.cpu_based_2nd_exec_ctrl &
 766                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 767 }
 768
 769 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 770 {
 771         return vmcs_config.cpu_based_2nd_exec_ctrl &
 772                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 773 }
 774
 775 static inline bool cpu_has_vmx_apic_register_virt(void)
 776 {
 777         return vmcs_config.cpu_based_2nd_exec_ctrl &
 778                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 779 }
 780
 781 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 782 {
 783         return vmcs_config.cpu_based_2nd_exec_ctrl &
 784                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 785 }
 786
 787 static inline bool cpu_has_vmx_flexpriority(void)
 788 {
 789         return cpu_has_vmx_tpr_shadow() &&
 790                 cpu_has_vmx_virtualize_apic_accesses();
 791 }
 792
 793 static inline bool cpu_has_vmx_ept_execute_only(void)
 794 {
 795         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 796 }
 797
 798 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 799 {
 800         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 801 }
 802
 803 static inline bool cpu_has_vmx_eptp_writeback(void)
 804 {
 805         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 806 }
 807
 808 static inline bool cpu_has_vmx_ept_2m_page(void)
 809 {
 810         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 811 }
 812
 813 static inline bool cpu_has_vmx_ept_1g_page(void)
 814 {
 815         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 816 }
 817
 818 static inline bool cpu_has_vmx_ept_4levels(void)
 819 {
 820         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 821 }
 822
 823 static inline bool cpu_has_vmx_ept_ad_bits(void)
 824 {
 825         return vmx_capability.ept & VMX_EPT_AD_BIT;
 826 }
 827
 828 static inline bool cpu_has_vmx_invept_context(void)
 829 {
 830         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 831 }
 832
 833 static inline bool cpu_has_vmx_invept_global(void)
 834 {
 835         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 836 }
 837
 838 static inline bool cpu_has_vmx_invvpid_single(void)
 839 {
 840         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 841 }
 842
 843 static inline bool cpu_has_vmx_invvpid_global(void)
 844 {
 845         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 846 }
 847
 848 static inline bool cpu_has_vmx_ept(void)
 849 {
 850         return vmcs_config.cpu_based_2nd_exec_ctrl &
 851                 SECONDARY_EXEC_ENABLE_EPT;
 852 }
 853
 854 static inline bool cpu_has_vmx_unrestricted_guest(void)
 855 {
 856         return vmcs_config.cpu_based_2nd_exec_ctrl &
 857                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 858 }
 859
 860 static inline bool cpu_has_vmx_ple(void)
 861 {
 862         return vmcs_config.cpu_based_2nd_exec_ctrl &
 863                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 864 }
 865
 866 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 867 {
 868         return flexpriority_enabled && irqchip_in_kernel(kvm);
 869 }
 870
 871 static inline bool cpu_has_vmx_vpid(void)
 872 {
 873         return vmcs_config.cpu_based_2nd_exec_ctrl &
 874                 SECONDARY_EXEC_ENABLE_VPID;
 875 }
 876
 877 static inline bool cpu_has_vmx_rdtscp(void)
 878 {
 879         return vmcs_config.cpu_based_2nd_exec_ctrl &
 880                 SECONDARY_EXEC_RDTSCP;
 881 }
 882
 883 static inline bool cpu_has_vmx_invpcid(void)
 884 {
 885         return vmcs_config.cpu_based_2nd_exec_ctrl &
 886                 SECONDARY_EXEC_ENABLE_INVPCID;
 887 }
 888
 889 static inline bool cpu_has_virtual_nmis(void)
 890 {
 891         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 892 }
 893
 894 static inline bool cpu_has_vmx_wbinvd_exit(void)
 895 {
 896         return vmcs_config.cpu_based_2nd_exec_ctrl &
 897                 SECONDARY_EXEC_WBINVD_EXITING;
 898 }
 899
 900 static inline bool report_flexpriority(void)
 901 {
 902         return flexpriority_enabled;
 903 }
 904
 905 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 906 {
 907         return vmcs12->cpu_based_vm_exec_control & bit;
 908 }
 909
 910 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 911 {
 912         return (vmcs12->cpu_based_vm_exec_control &
 913                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 914                 (vmcs12->secondary_vm_exec_control & bit);
 915 }
 916
 917 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 918         struct kvm_vcpu *vcpu)
 919 {
 920         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 921 }
 922
 923 static inline bool is_exception(u32 intr_info)
 924 {
 925         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 926                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 927 }
 928
 929 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 930 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 931                         struct vmcs12 *vmcs12,
 932                         u32 reason, unsigned long qualification);
 933
 934 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 935 {
 936         int i;
 937
 938         for (i = 0; i < vmx->nmsrs; ++i)
 939                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 940                         return i;
 941         return -1;
 942 }
 943
 944 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 945 {
 946     struct {
 947         u64 vpid : 16;
 948         u64 rsvd : 48;
 949         u64 gva;
 950     } operand = { vpid, 0, gva };
 951
 952     asm volatile (__ex(ASM_VMX_INVVPID)
 953                   /* CF==1 or ZF==1 --> rc = -1 */
 954                   "; ja 1f ; ud2 ; 1:"
 955                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 956 }
 957
 958 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 959 {
 960         struct {
 961                 u64 eptp, gpa;
 962         } operand = {eptp, gpa};
 963
 964         asm volatile (__ex(ASM_VMX_INVEPT)
 965                         /* CF==1 or ZF==1 --> rc = -1 */
 966                         "; ja 1f ; ud2 ; 1:\n"
 967                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 968 }
 969
 970 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 971 {
 972         int i;
 973
 974         i = __find_msr_index(vmx, msr);
 975         if (i >= 0)
 976                 return &vmx->guest_msrs[i];
 977         return NULL;
 978 }
 979
 980 static void vmcs_clear(struct vmcs *vmcs)
 981 {
 982         u64 phys_addr = __pa(vmcs);
 983         u8 error;
 984
 985         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 986                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 987                       : "cc", "memory");
 988         if (error)
 989                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 990                        vmcs, phys_addr);
 991 }
 992
 993 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 994 {
 995         vmcs_clear(loaded_vmcs->vmcs);
 996         loaded_vmcs->cpu = -1;
 997         loaded_vmcs->launched = 0;
 998 }
 999
1000 static void vmcs_load(struct vmcs *vmcs)
1001 {
1002         u64 phys_addr = __pa(vmcs);
1003         u8 error;
1004
1005         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1006                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1007                         : "cc", "memory");
1008         if (error)
1009                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1010                        vmcs, phys_addr);
1011 }
1012
1013 #ifdef CONFIG_KEXEC
1014 /*
1015  * This bitmap is used to indicate whether the vmclear
1016  * operation is enabled on all cpus. All disabled by
1017  * default.
1018  */
1019 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1020
1021 static inline void crash_enable_local_vmclear(int cpu)
1022 {
1023         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1024 }
1025
1026 static inline void crash_disable_local_vmclear(int cpu)
1027 {
1028         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1029 }
1030
1031 static inline int crash_local_vmclear_enabled(int cpu)
1032 {
1033         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1034 }
1035
1036 static void crash_vmclear_local_loaded_vmcss(void)
1037 {
1038         int cpu = raw_smp_processor_id();
1039         struct loaded_vmcs *v;
1040
1041         if (!crash_local_vmclear_enabled(cpu))
1042                 return;
1043
1044         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1045                             loaded_vmcss_on_cpu_link)
1046                 vmcs_clear(v->vmcs);
1047 }
1048 #else
1049 static inline void crash_enable_local_vmclear(int cpu) { }
1050 static inline void crash_disable_local_vmclear(int cpu) { }
1051 #endif /* CONFIG_KEXEC */
1052
1053 static void __loaded_vmcs_clear(void *arg)
1054 {
1055         struct loaded_vmcs *loaded_vmcs = arg;
1056         int cpu = raw_smp_processor_id();
1057
1058         if (loaded_vmcs->cpu != cpu)
1059                 return; /* vcpu migration can race with cpu offline */
1060         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1061                 per_cpu(current_vmcs, cpu) = NULL;
1062         crash_disable_local_vmclear(cpu);
1063         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1064
1065         /*
1066          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1067          * is before setting loaded_vmcs->vcpu to -1 which is done in
1068          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1069          * then adds the vmcs into percpu list before it is deleted.
1070          */
1071         smp_wmb();
1072
1073         loaded_vmcs_init(loaded_vmcs);
1074         crash_enable_local_vmclear(cpu);
1075 }
1076
1077 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1078 {
1079         int cpu = loaded_vmcs->cpu;
1080
1081         if (cpu != -1)
1082                 smp_call_function_single(cpu,
1083                          __loaded_vmcs_clear, loaded_vmcs, 1);
1084 }
1085
1086 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1087 {
1088         if (vmx->vpid == 0)
1089                 return;
1090
1091         if (cpu_has_vmx_invvpid_single())
1092                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1093 }
1094
1095 static inline void vpid_sync_vcpu_global(void)
1096 {
1097         if (cpu_has_vmx_invvpid_global())
1098                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1099 }
1100
1101 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1102 {
1103         if (cpu_has_vmx_invvpid_single())
1104                 vpid_sync_vcpu_single(vmx);
1105         else
1106                 vpid_sync_vcpu_global();
1107 }
1108
1109 static inline void ept_sync_global(void)
1110 {
1111         if (cpu_has_vmx_invept_global())
1112                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1113 }
1114
1115 static inline void ept_sync_context(u64 eptp)
1116 {
1117         if (enable_ept) {
1118                 if (cpu_has_vmx_invept_context())
1119                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1120                 else
1121                         ept_sync_global();
1122         }
1123 }
1124
1125 static __always_inline unsigned long vmcs_readl(unsigned long field)
1126 {
1127         unsigned long value;
1128
1129         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1130                       : "=a"(value) : "d"(field) : "cc");
1131         return value;
1132 }
1133
1134 static __always_inline u16 vmcs_read16(unsigned long field)
1135 {
1136         return vmcs_readl(field);
1137 }
1138
1139 static __always_inline u32 vmcs_read32(unsigned long field)
1140 {
1141         return vmcs_readl(field);
1142 }
1143
1144 static __always_inline u64 vmcs_read64(unsigned long field)
1145 {
1146 #ifdef CONFIG_X86_64
1147         return vmcs_readl(field);
1148 #else
1149         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1150 #endif
1151 }
1152
1153 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1154 {
1155         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1156                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1157         dump_stack();
1158 }
1159
1160 static void vmcs_writel(unsigned long field, unsigned long value)
1161 {
1162         u8 error;
1163
1164         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1165                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1166         if (unlikely(error))
1167                 vmwrite_error(field, value);
1168 }
1169
1170 static void vmcs_write16(unsigned long field, u16 value)
1171 {
1172         vmcs_writel(field, value);
1173 }
1174
1175 static void vmcs_write32(unsigned long field, u32 value)
1176 {
1177         vmcs_writel(field, value);
1178 }
1179
1180 static void vmcs_write64(unsigned long field, u64 value)
1181 {
1182         vmcs_writel(field, value);
1183 #ifndef CONFIG_X86_64
1184         asm volatile ("");
1185         vmcs_writel(field+1, value >> 32);
1186 #endif
1187 }
1188
1189 static void vmcs_clear_bits(unsigned long field, u32 mask)
1190 {
1191         vmcs_writel(field, vmcs_readl(field) & ~mask);
1192 }
1193
1194 static void vmcs_set_bits(unsigned long field, u32 mask)
1195 {
1196         vmcs_writel(field, vmcs_readl(field) | mask);
1197 }
1198
1199 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1200 {
1201         vmx->segment_cache.bitmask = 0;
1202 }
1203
1204 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1205                                        unsigned field)
1206 {
1207         bool ret;
1208         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1209
1210         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1211                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1212                 vmx->segment_cache.bitmask = 0;
1213         }
1214         ret = vmx->segment_cache.bitmask & mask;
1215         vmx->segment_cache.bitmask |= mask;
1216         return ret;
1217 }
1218
1219 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1220 {
1221         u16 *p = &vmx->segment_cache.seg[seg].selector;
1222
1223         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1224                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1225         return *p;
1226 }
1227
1228 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1229 {
1230         ulong *p = &vmx->segment_cache.seg[seg].base;
1231
1232         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1233                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1234         return *p;
1235 }
1236
1237 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1238 {
1239         u32 *p = &vmx->segment_cache.seg[seg].limit;
1240
1241         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1242                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1243         return *p;
1244 }
1245
1246 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1247 {
1248         u32 *p = &vmx->segment_cache.seg[seg].ar;
1249
1250         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1251                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1252         return *p;
1253 }
1254
1255 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1256 {
1257         u32 eb;
1258
1259         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1260              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1261         if ((vcpu->guest_debug &
1262              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1263             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1264                 eb |= 1u << BP_VECTOR;
1265         if (to_vmx(vcpu)->rmode.vm86_active)
1266                 eb = ~0;
1267         if (enable_ept)
1268                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1269         if (vcpu->fpu_active)
1270                 eb &= ~(1u << NM_VECTOR);
1271
1272         /* When we are running a nested L2 guest and L1 specified for it a
1273          * certain exception bitmap, we must trap the same exceptions and pass
1274          * them to L1. When running L2, we will only handle the exceptions
1275          * specified above if L1 did not want them.
1276          */
1277         if (is_guest_mode(vcpu))
1278                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1279
1280         vmcs_write32(EXCEPTION_BITMAP, eb);
1281 }
1282
1283 static void clear_atomic_switch_msr_special(unsigned long entry,
1284                 unsigned long exit)
1285 {
1286         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1287         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1288 }
1289
1290 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1291 {
1292         unsigned i;
1293         struct msr_autoload *m = &vmx->msr_autoload;
1294
1295         switch (msr) {
1296         case MSR_EFER:
1297                 if (cpu_has_load_ia32_efer) {
1298                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1299                                         VM_EXIT_LOAD_IA32_EFER);
1300                         return;
1301                 }
1302                 break;
1303         case MSR_CORE_PERF_GLOBAL_CTRL:
1304                 if (cpu_has_load_perf_global_ctrl) {
1305                         clear_atomic_switch_msr_special(
1306                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1307                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1308                         return;
1309                 }
1310                 break;
1311         }
1312
1313         for (i = 0; i < m->nr; ++i)
1314                 if (m->guest[i].index == msr)
1315                         break;
1316
1317         if (i == m->nr)
1318                 return;
1319         --m->nr;
1320         m->guest[i] = m->guest[m->nr];
1321         m->host[i] = m->host[m->nr];
1322         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1323         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1324 }
1325
1326 static void add_atomic_switch_msr_special(unsigned long entry,
1327                 unsigned long exit, unsigned long guest_val_vmcs,
1328                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1329 {
1330         vmcs_write64(guest_val_vmcs, guest_val);
1331         vmcs_write64(host_val_vmcs, host_val);
1332         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1333         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1334 }
1335
1336 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1337                                   u64 guest_val, u64 host_val)
1338 {
1339         unsigned i;
1340         struct msr_autoload *m = &vmx->msr_autoload;
1341
1342         switch (msr) {
1343         case MSR_EFER:
1344                 if (cpu_has_load_ia32_efer) {
1345                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1346                                         VM_EXIT_LOAD_IA32_EFER,
1347                                         GUEST_IA32_EFER,
1348                                         HOST_IA32_EFER,
1349                                         guest_val, host_val);
1350                         return;
1351                 }
1352                 break;
1353         case MSR_CORE_PERF_GLOBAL_CTRL:
1354                 if (cpu_has_load_perf_global_ctrl) {
1355                         add_atomic_switch_msr_special(
1356                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1357                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1358                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1359                                         HOST_IA32_PERF_GLOBAL_CTRL,
1360                                         guest_val, host_val);
1361                         return;
1362                 }
1363                 break;
1364         }
1365
1366         for (i = 0; i < m->nr; ++i)
1367                 if (m->guest[i].index == msr)
1368                         break;
1369
1370         if (i == NR_AUTOLOAD_MSRS) {
1371                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1372                                 "Can't add msr %x\n", msr);
1373                 return;
1374         } else if (i == m->nr) {
1375                 ++m->nr;
1376                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1377                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1378         }
1379
1380         m->guest[i].index = msr;
1381         m->guest[i].value = guest_val;
1382         m->host[i].index = msr;
1383         m->host[i].value = host_val;
1384 }
1385
1386 static void reload_tss(void)
1387 {
1388         /*
1389          * VT restores TR but not its size.  Useless.
1390          */
1391         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1392         struct desc_struct *descs;
1393
1394         descs = (void *)gdt->address;
1395         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1396         load_TR_desc();
1397 }
1398
1399 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1400 {
1401         u64 guest_efer;
1402         u64 ignore_bits;
1403
1404         guest_efer = vmx->vcpu.arch.efer;
1405
1406         /*
1407          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1408          * outside long mode
1409          */
1410         ignore_bits = EFER_NX | EFER_SCE;
1411 #ifdef CONFIG_X86_64
1412         ignore_bits |= EFER_LMA | EFER_LME;
1413         /* SCE is meaningful only in long mode on Intel */
1414         if (guest_efer & EFER_LMA)
1415                 ignore_bits &= ~(u64)EFER_SCE;
1416 #endif
1417         guest_efer &= ~ignore_bits;
1418         guest_efer |= host_efer & ignore_bits;
1419         vmx->guest_msrs[efer_offset].data = guest_efer;
1420         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1421
1422         clear_atomic_switch_msr(vmx, MSR_EFER);
1423         /* On ept, can't emulate nx, and must switch nx atomically */
1424         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1425                 guest_efer = vmx->vcpu.arch.efer;
1426                 if (!(guest_efer & EFER_LMA))
1427                         guest_efer &= ~EFER_LME;
1428                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1429                 return false;
1430         }
1431
1432         return true;
1433 }
1434
1435 static unsigned long segment_base(u16 selector)
1436 {
1437         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1438         struct desc_struct *d;
1439         unsigned long table_base;
1440         unsigned long v;
1441
1442         if (!(selector & ~3))
1443                 return 0;
1444
1445         table_base = gdt->address;
1446
1447         if (selector & 4) {           /* from ldt */
1448                 u16 ldt_selector = kvm_read_ldt();
1449
1450                 if (!(ldt_selector & ~3))
1451                         return 0;
1452
1453                 table_base = segment_base(ldt_selector);
1454         }
1455         d = (struct desc_struct *)(table_base + (selector & ~7));
1456         v = get_desc_base(d);
1457 #ifdef CONFIG_X86_64
1458        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1459                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1460 #endif
1461         return v;
1462 }
1463
1464 static inline unsigned long kvm_read_tr_base(void)
1465 {
1466         u16 tr;
1467         asm("str %0" : "=g"(tr));
1468         return segment_base(tr);
1469 }
1470
1471 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1472 {
1473         struct vcpu_vmx *vmx = to_vmx(vcpu);
1474         int i;
1475
1476         if (vmx->host_state.loaded)
1477                 return;
1478
1479         vmx->host_state.loaded = 1;
1480         /*
1481          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1482          * allow segment selectors with cpl > 0 or ti == 1.
1483          */
1484         vmx->host_state.ldt_sel = kvm_read_ldt();
1485         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1486         savesegment(fs, vmx->host_state.fs_sel);
1487         if (!(vmx->host_state.fs_sel & 7)) {
1488                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1489                 vmx->host_state.fs_reload_needed = 0;
1490         } else {
1491                 vmcs_write16(HOST_FS_SELECTOR, 0);
1492                 vmx->host_state.fs_reload_needed = 1;
1493         }
1494         savesegment(gs, vmx->host_state.gs_sel);
1495         if (!(vmx->host_state.gs_sel & 7))
1496                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1497         else {
1498                 vmcs_write16(HOST_GS_SELECTOR, 0);
1499                 vmx->host_state.gs_ldt_reload_needed = 1;
1500         }
1501
1502 #ifdef CONFIG_X86_64
1503         savesegment(ds, vmx->host_state.ds_sel);
1504         savesegment(es, vmx->host_state.es_sel);
1505 #endif
1506
1507 #ifdef CONFIG_X86_64
1508         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1509         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1510 #else
1511         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1512         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1513 #endif
1514
1515 #ifdef CONFIG_X86_64
1516         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1517         if (is_long_mode(&vmx->vcpu))
1518                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1519 #endif
1520         for (i = 0; i < vmx->save_nmsrs; ++i)
1521                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1522                                    vmx->guest_msrs[i].data,
1523                                    vmx->guest_msrs[i].mask);
1524 }
1525
1526 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1527 {
1528         if (!vmx->host_state.loaded)
1529                 return;
1530
1531         ++vmx->vcpu.stat.host_state_reload;
1532         vmx->host_state.loaded = 0;
1533 #ifdef CONFIG_X86_64
1534         if (is_long_mode(&vmx->vcpu))
1535                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1536 #endif
1537         if (vmx->host_state.gs_ldt_reload_needed) {
1538                 kvm_load_ldt(vmx->host_state.ldt_sel);
1539 #ifdef CONFIG_X86_64
1540                 load_gs_index(vmx->host_state.gs_sel);
1541 #else
1542                 loadsegment(gs, vmx->host_state.gs_sel);
1543 #endif
1544         }
1545         if (vmx->host_state.fs_reload_needed)
1546                 loadsegment(fs, vmx->host_state.fs_sel);
1547 #ifdef CONFIG_X86_64
1548         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1549                 loadsegment(ds, vmx->host_state.ds_sel);
1550                 loadsegment(es, vmx->host_state.es_sel);
1551         }
1552 #endif
1553         reload_tss();
1554 #ifdef CONFIG_X86_64
1555         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1556 #endif
1557         /*
1558          * If the FPU is not active (through the host task or
1559          * the guest vcpu), then restore the cr0.TS bit.
1560          */
1561         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1562                 stts();
1563         load_gdt(&__get_cpu_var(host_gdt));
1564 }
1565
1566 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1567 {
1568         preempt_disable();
1569         __vmx_load_host_state(vmx);
1570         preempt_enable();
1571 }
1572
1573 /*
1574  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1575  * vcpu mutex is already taken.
1576  */
1577 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1578 {
1579         struct vcpu_vmx *vmx = to_vmx(vcpu);
1580         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1581
1582         if (!vmm_exclusive)
1583                 kvm_cpu_vmxon(phys_addr);
1584         else if (vmx->loaded_vmcs->cpu != cpu)
1585                 loaded_vmcs_clear(vmx->loaded_vmcs);
1586
1587         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1588                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1589                 vmcs_load(vmx->loaded_vmcs->vmcs);
1590         }
1591
1592         if (vmx->loaded_vmcs->cpu != cpu) {
1593                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1594                 unsigned long sysenter_esp;
1595
1596                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1597                 local_irq_disable();
1598                 crash_disable_local_vmclear(cpu);
1599
1600                 /*
1601                  * Read loaded_vmcs->cpu should be before fetching
1602                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1603                  * See the comments in __loaded_vmcs_clear().
1604                  */
1605                 smp_rmb();
1606
1607                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1608                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1609                 crash_enable_local_vmclear(cpu);
1610                 local_irq_enable();
1611
1612                 /*
1613                  * Linux uses per-cpu TSS and GDT, so set these when switching
1614                  * processors.
1615                  */
1616                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1617                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1618
1619                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1620                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1621                 vmx->loaded_vmcs->cpu = cpu;
1622         }
1623 }
1624
1625 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1626 {
1627         __vmx_load_host_state(to_vmx(vcpu));
1628         if (!vmm_exclusive) {
1629                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1630                 vcpu->cpu = -1;
1631                 kvm_cpu_vmxoff();
1632         }
1633 }
1634
1635 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1636 {
1637         ulong cr0;
1638
1639         if (vcpu->fpu_active)
1640                 return;
1641         vcpu->fpu_active = 1;
1642         cr0 = vmcs_readl(GUEST_CR0);
1643         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1644         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1645         vmcs_writel(GUEST_CR0, cr0);
1646         update_exception_bitmap(vcpu);
1647         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1648         if (is_guest_mode(vcpu))
1649                 vcpu->arch.cr0_guest_owned_bits &=
1650                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1651         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1652 }
1653
1654 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1655
1656 /*
1657  * Return the cr0 value that a nested guest would read. This is a combination
1658  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1659  * its hypervisor (cr0_read_shadow).
1660  */
1661 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1662 {
1663         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1664                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1665 }
1666 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1667 {
1668         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1669                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1670 }
1671
1672 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1673 {
1674         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1675          * set this *before* calling this function.
1676          */
1677         vmx_decache_cr0_guest_bits(vcpu);
1678         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1679         update_exception_bitmap(vcpu);
1680         vcpu->arch.cr0_guest_owned_bits = 0;
1681         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1682         if (is_guest_mode(vcpu)) {
1683                 /*
1684                  * L1's specified read shadow might not contain the TS bit,
1685                  * so now that we turned on shadowing of this bit, we need to
1686                  * set this bit of the shadow. Like in nested_vmx_run we need
1687                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1688                  * up-to-date here because we just decached cr0.TS (and we'll
1689                  * only update vmcs12->guest_cr0 on nested exit).
1690                  */
1691                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1692                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1693                         (vcpu->arch.cr0 & X86_CR0_TS);
1694                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1695         } else
1696                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1697 }
1698
1699 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1700 {
1701         unsigned long rflags, save_rflags;
1702
1703         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1704                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1705                 rflags = vmcs_readl(GUEST_RFLAGS);
1706                 if (to_vmx(vcpu)->rmode.vm86_active) {
1707                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1708                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1709                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1710                 }
1711                 to_vmx(vcpu)->rflags = rflags;
1712         }
1713         return to_vmx(vcpu)->rflags;
1714 }
1715
1716 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1717 {
1718         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1719         to_vmx(vcpu)->rflags = rflags;
1720         if (to_vmx(vcpu)->rmode.vm86_active) {
1721                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1722                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1723         }
1724         vmcs_writel(GUEST_RFLAGS, rflags);
1725 }
1726
1727 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1728 {
1729         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1730         int ret = 0;
1731
1732         if (interruptibility & GUEST_INTR_STATE_STI)
1733                 ret |= KVM_X86_SHADOW_INT_STI;
1734         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1735                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1736
1737         return ret & mask;
1738 }
1739
1740 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1741 {
1742         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1743         u32 interruptibility = interruptibility_old;
1744
1745         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1746
1747         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1748                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1749         else if (mask & KVM_X86_SHADOW_INT_STI)
1750                 interruptibility |= GUEST_INTR_STATE_STI;
1751
1752         if ((interruptibility != interruptibility_old))
1753                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1754 }
1755
1756 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1757 {
1758         unsigned long rip;
1759
1760         rip = kvm_rip_read(vcpu);
1761         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1762         kvm_rip_write(vcpu, rip);
1763
1764         /* skipping an emulated instruction also counts */
1765         vmx_set_interrupt_shadow(vcpu, 0);
1766 }
1767
1768 /*
1769  * KVM wants to inject page-faults which it got to the guest. This function
1770  * checks whether in a nested guest, we need to inject them to L1 or L2.
1771  * This function assumes it is called with the exit reason in vmcs02 being
1772  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1773  * is running).
1774  */
1775 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1776 {
1777         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1778
1779         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1780         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1781                 return 0;
1782
1783         nested_vmx_vmexit(vcpu);
1784         return 1;
1785 }
1786
1787 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1788                                 bool has_error_code, u32 error_code,
1789                                 bool reinject)
1790 {
1791         struct vcpu_vmx *vmx = to_vmx(vcpu);
1792         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1793
1794         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1795                 nested_pf_handled(vcpu))
1796                 return;
1797
1798         if (has_error_code) {
1799                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1800                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1801         }
1802
1803         if (vmx->rmode.vm86_active) {
1804                 int inc_eip = 0;
1805                 if (kvm_exception_is_soft(nr))
1806                         inc_eip = vcpu->arch.event_exit_inst_len;
1807                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1808                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1809                 return;
1810         }
1811
1812         if (kvm_exception_is_soft(nr)) {
1813                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1814                              vmx->vcpu.arch.event_exit_inst_len);
1815                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1816         } else
1817                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1818
1819         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1820 }
1821
1822 static bool vmx_rdtscp_supported(void)
1823 {
1824         return cpu_has_vmx_rdtscp();
1825 }
1826
1827 static bool vmx_invpcid_supported(void)
1828 {
1829         return cpu_has_vmx_invpcid() && enable_ept;
1830 }
1831
1832 /*
1833  * Swap MSR entry in host/guest MSR entry array.
1834  */
1835 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1836 {
1837         struct shared_msr_entry tmp;
1838
1839         tmp = vmx->guest_msrs[to];
1840         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1841         vmx->guest_msrs[from] = tmp;
1842 }
1843
1844 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1845 {
1846         unsigned long *msr_bitmap;
1847
1848         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1849                 if (is_long_mode(vcpu))
1850                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1851                 else
1852                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1853         } else {
1854                 if (is_long_mode(vcpu))
1855                         msr_bitmap = vmx_msr_bitmap_longmode;
1856                 else
1857                         msr_bitmap = vmx_msr_bitmap_legacy;
1858         }
1859
1860         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1861 }
1862
1863 /*
1864  * Set up the vmcs to automatically save and restore system
1865  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1866  * mode, as fiddling with msrs is very expensive.
1867  */
1868 static void setup_msrs(struct vcpu_vmx *vmx)
1869 {
1870         int save_nmsrs, index;
1871
1872         save_nmsrs = 0;
1873 #ifdef CONFIG_X86_64
1874         if (is_long_mode(&vmx->vcpu)) {
1875                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1876                 if (index >= 0)
1877                         move_msr_up(vmx, index, save_nmsrs++);
1878                 index = __find_msr_index(vmx, MSR_LSTAR);
1879                 if (index >= 0)
1880                         move_msr_up(vmx, index, save_nmsrs++);
1881                 index = __find_msr_index(vmx, MSR_CSTAR);
1882                 if (index >= 0)
1883                         move_msr_up(vmx, index, save_nmsrs++);
1884                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1885                 if (index >= 0 && vmx->rdtscp_enabled)
1886                         move_msr_up(vmx, index, save_nmsrs++);
1887                 /*
1888                  * MSR_STAR is only needed on long mode guests, and only
1889                  * if efer.sce is enabled.
1890                  */
1891                 index = __find_msr_index(vmx, MSR_STAR);
1892                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1893                         move_msr_up(vmx, index, save_nmsrs++);
1894         }
1895 #endif
1896         index = __find_msr_index(vmx, MSR_EFER);
1897         if (index >= 0 && update_transition_efer(vmx, index))
1898                 move_msr_up(vmx, index, save_nmsrs++);
1899
1900         vmx->save_nmsrs = save_nmsrs;
1901
1902         if (cpu_has_vmx_msr_bitmap())
1903                 vmx_set_msr_bitmap(&vmx->vcpu);
1904 }
1905
1906 /*
1907  * reads and returns guest's timestamp counter "register"
1908  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1909  */
1910 static u64 guest_read_tsc(void)
1911 {
1912         u64 host_tsc, tsc_offset;
1913
1914         rdtscll(host_tsc);
1915         tsc_offset = vmcs_read64(TSC_OFFSET);
1916         return host_tsc + tsc_offset;
1917 }
1918
1919 /*
1920  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1921  * counter, even if a nested guest (L2) is currently running.
1922  */
1923 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1924 {
1925         u64 tsc_offset;
1926
1927         tsc_offset = is_guest_mode(vcpu) ?
1928                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1929                 vmcs_read64(TSC_OFFSET);
1930         return host_tsc + tsc_offset;
1931 }
1932
1933 /*
1934  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1935  * software catchup for faster rates on slower CPUs.
1936  */
1937 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1938 {
1939         if (!scale)
1940                 return;
1941
1942         if (user_tsc_khz > tsc_khz) {
1943                 vcpu->arch.tsc_catchup = 1;
1944                 vcpu->arch.tsc_always_catchup = 1;
1945         } else
1946                 WARN(1, "user requested TSC rate below hardware speed\n");
1947 }
1948
1949 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1950 {
1951         return vmcs_read64(TSC_OFFSET);
1952 }
1953
1954 /*
1955  * writes 'offset' into guest's timestamp counter offset register
1956  */
1957 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1958 {
1959         if (is_guest_mode(vcpu)) {
1960                 /*
1961                  * We're here if L1 chose not to trap WRMSR to TSC. According
1962                  * to the spec, this should set L1's TSC; The offset that L1
1963                  * set for L2 remains unchanged, and still needs to be added
1964                  * to the newly set TSC to get L2's TSC.
1965                  */
1966                 struct vmcs12 *vmcs12;
1967                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1968                 /* recalculate vmcs02.TSC_OFFSET: */
1969                 vmcs12 = get_vmcs12(vcpu);
1970                 vmcs_write64(TSC_OFFSET, offset +
1971                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1972                          vmcs12->tsc_offset : 0));
1973         } else {
1974                 vmcs_write64(TSC_OFFSET, offset);
1975         }
1976 }
1977
1978 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1979 {
1980         u64 offset = vmcs_read64(TSC_OFFSET);
1981         vmcs_write64(TSC_OFFSET, offset + adjustment);
1982         if (is_guest_mode(vcpu)) {
1983                 /* Even when running L2, the adjustment needs to apply to L1 */
1984                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1985         }
1986 }
1987
1988 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1989 {
1990         return target_tsc - native_read_tsc();
1991 }
1992
1993 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1994 {
1995         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1996         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1997 }
1998
1999 /*
2000  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2001  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2002  * all guests if the "nested" module option is off, and can also be disabled
2003  * for a single guest by disabling its VMX cpuid bit.
2004  */
2005 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2006 {
2007         return nested && guest_cpuid_has_vmx(vcpu);
2008 }
2009
2010 /*
2011  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2012  * returned for the various VMX controls MSRs when nested VMX is enabled.
2013  * The same values should also be used to verify that vmcs12 control fields are
2014  * valid during nested entry from L1 to L2.
2015  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2016  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2017  * bit in the high half is on if the corresponding bit in the control field
2018  * may be on. See also vmx_control_verify().
2019  * TODO: allow these variables to be modified (downgraded) by module options
2020  * or other means.
2021  */
2022 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2023 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2024 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2025 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2026 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2027 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2028 static __init void nested_vmx_setup_ctls_msrs(void)
2029 {
2030         /*
2031          * Note that as a general rule, the high half of the MSRs (bits in
2032          * the control fields which may be 1) should be initialized by the
2033          * intersection of the underlying hardware's MSR (i.e., features which
2034          * can be supported) and the list of features we want to expose -
2035          * because they are known to be properly supported in our code.
2036          * Also, usually, the low half of the MSRs (bits which must be 1) can
2037          * be set to 0, meaning that L1 may turn off any of these bits. The
2038          * reason is that if one of these bits is necessary, it will appear
2039          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2040          * fields of vmcs01 and vmcs02, will turn these bits off - and
2041          * nested_vmx_exit_handled() will not pass related exits to L1.
2042          * These rules have exceptions below.
2043          */
2044
2045         /* pin-based controls */
2046         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2047               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2048         /*
2049          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2050          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2051          */
2052         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2053         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2054                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2055                 PIN_BASED_VMX_PREEMPTION_TIMER;
2056         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2057
2058         /*
2059          * Exit controls
2060          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2061          * 17 must be 1.
2062          */
2063         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2064         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2065 #ifdef CONFIG_X86_64
2066         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2067 #else
2068         nested_vmx_exit_ctls_high = 0;
2069 #endif
2070         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2071
2072         /* entry controls */
2073         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2074                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2075         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2076         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2077         nested_vmx_entry_ctls_high &=
2078                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2079         nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2080
2081         /* cpu-based controls */
2082         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2083                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2084         nested_vmx_procbased_ctls_low = 0;
2085         nested_vmx_procbased_ctls_high &=
2086                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2087                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2088                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2089                 CPU_BASED_CR3_STORE_EXITING |
2090 #ifdef CONFIG_X86_64
2091                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2092 #endif
2093                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2094                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2095                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2096                 CPU_BASED_PAUSE_EXITING |
2097                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2098         /*
2099          * We can allow some features even when not supported by the
2100          * hardware. For example, L1 can specify an MSR bitmap - and we
2101          * can use it to avoid exits to L1 - even when L0 runs L2
2102          * without MSR bitmaps.
2103          */
2104         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2105
2106         /* secondary cpu-based controls */
2107         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2108                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2109         nested_vmx_secondary_ctls_low = 0;
2110         nested_vmx_secondary_ctls_high &=
2111                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2112                 SECONDARY_EXEC_WBINVD_EXITING;
2113
2114         /* miscellaneous data */
2115         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2116         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2117                 VMX_MISC_SAVE_EFER_LMA;
2118         nested_vmx_misc_high = 0;
2119 }
2120
2121 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2122 {
2123         /*
2124          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2125          */
2126         return ((control & high) | low) == control;
2127 }
2128
2129 static inline u64 vmx_control_msr(u32 low, u32 high)
2130 {
2131         return low | ((u64)high << 32);
2132 }
2133
2134 /*
2135  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2136  * also let it use VMX-specific MSRs.
2137  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2138  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2139  * like all other MSRs).
2140  */
2141 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2142 {
2143         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2144                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2145                 /*
2146                  * According to the spec, processors which do not support VMX
2147                  * should throw a #GP(0) when VMX capability MSRs are read.
2148                  */
2149                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2150                 return 1;
2151         }
2152
2153         switch (msr_index) {
2154         case MSR_IA32_FEATURE_CONTROL:
2155                 *pdata = 0;
2156                 break;
2157         case MSR_IA32_VMX_BASIC:
2158                 /*
2159                  * This MSR reports some information about VMX support. We
2160                  * should return information about the VMX we emulate for the
2161                  * guest, and the VMCS structure we give it - not about the
2162                  * VMX support of the underlying hardware.
2163                  */
2164                 *pdata = VMCS12_REVISION |
2165                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2166                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2167                 break;
2168         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2169         case MSR_IA32_VMX_PINBASED_CTLS:
2170                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2171                                         nested_vmx_pinbased_ctls_high);
2172                 break;
2173         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2174         case MSR_IA32_VMX_PROCBASED_CTLS:
2175                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2176                                         nested_vmx_procbased_ctls_high);
2177                 break;
2178         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2179         case MSR_IA32_VMX_EXIT_CTLS:
2180                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2181                                         nested_vmx_exit_ctls_high);
2182                 break;
2183         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2184         case MSR_IA32_VMX_ENTRY_CTLS:
2185                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2186                                         nested_vmx_entry_ctls_high);
2187                 break;
2188         case MSR_IA32_VMX_MISC:
2189                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2190                                          nested_vmx_misc_high);
2191                 break;
2192         /*
2193          * These MSRs specify bits which the guest must keep fixed (on or off)
2194          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2195          * We picked the standard core2 setting.
2196          */
2197 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2198 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2199         case MSR_IA32_VMX_CR0_FIXED0:
2200                 *pdata = VMXON_CR0_ALWAYSON;
2201                 break;
2202         case MSR_IA32_VMX_CR0_FIXED1:
2203                 *pdata = -1ULL;
2204                 break;
2205         case MSR_IA32_VMX_CR4_FIXED0:
2206                 *pdata = VMXON_CR4_ALWAYSON;
2207                 break;
2208         case MSR_IA32_VMX_CR4_FIXED1:
2209                 *pdata = -1ULL;
2210                 break;
2211         case MSR_IA32_VMX_VMCS_ENUM:
2212                 *pdata = 0x1f;
2213                 break;
2214         case MSR_IA32_VMX_PROCBASED_CTLS2:
2215                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2216                                         nested_vmx_secondary_ctls_high);
2217                 break;
2218         case MSR_IA32_VMX_EPT_VPID_CAP:
2219                 /* Currently, no nested ept or nested vpid */
2220                 *pdata = 0;
2221                 break;
2222         default:
2223                 return 0;
2224         }
2225
2226         return 1;
2227 }
2228
2229 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2230 {
2231         if (!nested_vmx_allowed(vcpu))
2232                 return 0;
2233
2234         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2235                 /* TODO: the right thing. */
2236                 return 1;
2237         /*
2238          * No need to treat VMX capability MSRs specially: If we don't handle
2239          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2240          */
2241         return 0;
2242 }
2243
2244 /*
2245  * Reads an msr value (of 'msr_index') into 'pdata'.
2246  * Returns 0 on success, non-0 otherwise.
2247  * Assumes vcpu_load() was already called.
2248  */
2249 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2250 {
2251         u64 data;
2252         struct shared_msr_entry *msr;
2253
2254         if (!pdata) {
2255                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2256                 return -EINVAL;
2257         }
2258
2259         switch (msr_index) {
2260 #ifdef CONFIG_X86_64
2261         case MSR_FS_BASE:
2262                 data = vmcs_readl(GUEST_FS_BASE);
2263                 break;
2264         case MSR_GS_BASE:
2265                 data = vmcs_readl(GUEST_GS_BASE);
2266                 break;
2267         case MSR_KERNEL_GS_BASE:
2268                 vmx_load_host_state(to_vmx(vcpu));
2269                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2270                 break;
2271 #endif
2272         case MSR_EFER:
2273                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2274         case MSR_IA32_TSC:
2275                 data = guest_read_tsc();
2276                 break;
2277         case MSR_IA32_SYSENTER_CS:
2278                 data = vmcs_read32(GUEST_SYSENTER_CS);
2279                 break;
2280         case MSR_IA32_SYSENTER_EIP:
2281                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2282                 break;
2283         case MSR_IA32_SYSENTER_ESP:
2284                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2285                 break;
2286         case MSR_TSC_AUX:
2287                 if (!to_vmx(vcpu)->rdtscp_enabled)
2288                         return 1;
2289                 /* Otherwise falls through */
2290         default:
2291                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2292                         return 0;
2293                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2294                 if (msr) {
2295                         data = msr->data;
2296                         break;
2297                 }
2298                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2299         }
2300
2301         *pdata = data;
2302         return 0;
2303 }
2304
2305 /*
2306  * Writes msr value into into the appropriate "register".
2307  * Returns 0 on success, non-0 otherwise.
2308  * Assumes vcpu_load() was already called.
2309  */
2310 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2311 {
2312         struct vcpu_vmx *vmx = to_vmx(vcpu);
2313         struct shared_msr_entry *msr;
2314         int ret = 0;
2315         u32 msr_index = msr_info->index;
2316         u64 data = msr_info->data;
2317
2318         switch (msr_index) {
2319         case MSR_EFER:
2320                 ret = kvm_set_msr_common(vcpu, msr_info);
2321                 break;
2322 #ifdef CONFIG_X86_64
2323         case MSR_FS_BASE:
2324                 vmx_segment_cache_clear(vmx);
2325                 vmcs_writel(GUEST_FS_BASE, data);
2326                 break;
2327         case MSR_GS_BASE:
2328                 vmx_segment_cache_clear(vmx);
2329                 vmcs_writel(GUEST_GS_BASE, data);
2330                 break;
2331         case MSR_KERNEL_GS_BASE:
2332                 vmx_load_host_state(vmx);
2333                 vmx->msr_guest_kernel_gs_base = data;
2334                 break;
2335 #endif
2336         case MSR_IA32_SYSENTER_CS:
2337                 vmcs_write32(GUEST_SYSENTER_CS, data);
2338                 break;
2339         case MSR_IA32_SYSENTER_EIP:
2340                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2341                 break;
2342         case MSR_IA32_SYSENTER_ESP:
2343                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2344                 break;
2345         case MSR_IA32_TSC:
2346                 kvm_write_tsc(vcpu, msr_info);
2347                 break;
2348         case MSR_IA32_CR_PAT:
2349                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2350                         vmcs_write64(GUEST_IA32_PAT, data);
2351                         vcpu->arch.pat = data;
2352                         break;
2353                 }
2354                 ret = kvm_set_msr_common(vcpu, msr_info);
2355                 break;
2356         case MSR_IA32_TSC_ADJUST:
2357                 ret = kvm_set_msr_common(vcpu, msr_info);
2358                 break;
2359         case MSR_TSC_AUX:
2360                 if (!vmx->rdtscp_enabled)
2361                         return 1;
2362                 /* Check reserved bit, higher 32 bits should be zero */
2363                 if ((data >> 32) != 0)
2364                         return 1;
2365                 /* Otherwise falls through */
2366         default:
2367                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2368                         break;
2369                 msr = find_msr_entry(vmx, msr_index);
2370                 if (msr) {
2371                         msr->data = data;
2372                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2373                                 preempt_disable();
2374                                 kvm_set_shared_msr(msr->index, msr->data,
2375                                                    msr->mask);
2376                                 preempt_enable();
2377                         }
2378                         break;
2379                 }
2380                 ret = kvm_set_msr_common(vcpu, msr_info);
2381         }
2382
2383         return ret;
2384 }
2385
2386 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2387 {
2388         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2389         switch (reg) {
2390         case VCPU_REGS_RSP:
2391                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2392                 break;
2393         case VCPU_REGS_RIP:
2394                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2395                 break;
2396         case VCPU_EXREG_PDPTR:
2397                 if (enable_ept)
2398                         ept_save_pdptrs(vcpu);
2399                 break;
2400         default:
2401                 break;
2402         }
2403 }
2404
2405 static __init int cpu_has_kvm_support(void)
2406 {
2407         return cpu_has_vmx();
2408 }
2409
2410 static __init int vmx_disabled_by_bios(void)
2411 {
2412         u64 msr;
2413
2414         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2415         if (msr & FEATURE_CONTROL_LOCKED) {
2416                 /* launched w/ TXT and VMX disabled */
2417                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2418                         && tboot_enabled())
2419                         return 1;
2420                 /* launched w/o TXT and VMX only enabled w/ TXT */
2421                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2422                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2423                         && !tboot_enabled()) {
2424                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2425                                 "activate TXT before enabling KVM\n");
2426                         return 1;
2427                 }
2428                 /* launched w/o TXT and VMX disabled */
2429                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2430                         && !tboot_enabled())
2431                         return 1;
2432         }
2433
2434         return 0;
2435 }
2436
2437 static void kvm_cpu_vmxon(u64 addr)
2438 {
2439         asm volatile (ASM_VMX_VMXON_RAX
2440                         : : "a"(&addr), "m"(addr)
2441                         : "memory", "cc");
2442 }
2443
2444 static int hardware_enable(void *garbage)
2445 {
2446         int cpu = raw_smp_processor_id();
2447         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2448         u64 old, test_bits;
2449
2450         if (read_cr4() & X86_CR4_VMXE)
2451                 return -EBUSY;
2452
2453         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2454
2455         /*
2456          * Now we can enable the vmclear operation in kdump
2457          * since the loaded_vmcss_on_cpu list on this cpu
2458          * has been initialized.
2459          *
2460          * Though the cpu is not in VMX operation now, there
2461          * is no problem to enable the vmclear operation
2462          * for the loaded_vmcss_on_cpu list is empty!
2463          */
2464         crash_enable_local_vmclear(cpu);
2465
2466         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2467
2468         test_bits = FEATURE_CONTROL_LOCKED;
2469         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2470         if (tboot_enabled())
2471                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2472
2473         if ((old & test_bits) != test_bits) {
2474                 /* enable and lock */
2475                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2476         }
2477         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2478
2479         if (vmm_exclusive) {
2480                 kvm_cpu_vmxon(phys_addr);
2481                 ept_sync_global();
2482         }
2483
2484         store_gdt(&__get_cpu_var(host_gdt));
2485
2486         return 0;
2487 }
2488
2489 static void vmclear_local_loaded_vmcss(void)
2490 {
2491         int cpu = raw_smp_processor_id();
2492         struct loaded_vmcs *v, *n;
2493
2494         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2495                                  loaded_vmcss_on_cpu_link)
2496                 __loaded_vmcs_clear(v);
2497 }
2498
2499
2500 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2501  * tricks.
2502  */
2503 static void kvm_cpu_vmxoff(void)
2504 {
2505         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2506 }
2507
2508 static void hardware_disable(void *garbage)
2509 {
2510         if (vmm_exclusive) {
2511                 vmclear_local_loaded_vmcss();
2512                 kvm_cpu_vmxoff();
2513         }
2514         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2515 }
2516
2517 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2518                                       u32 msr, u32 *result)
2519 {
2520         u32 vmx_msr_low, vmx_msr_high;
2521         u32 ctl = ctl_min | ctl_opt;
2522
2523         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2524
2525         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2526         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2527
2528         /* Ensure minimum (required) set of control bits are supported. */
2529         if (ctl_min & ~ctl)
2530                 return -EIO;
2531
2532         *result = ctl;
2533         return 0;
2534 }
2535
2536 static __init bool allow_1_setting(u32 msr, u32 ctl)
2537 {
2538         u32 vmx_msr_low, vmx_msr_high;
2539
2540         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2541         return vmx_msr_high & ctl;
2542 }
2543
2544 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2545 {
2546         u32 vmx_msr_low, vmx_msr_high;
2547         u32 min, opt, min2, opt2;
2548         u32 _pin_based_exec_control = 0;
2549         u32 _cpu_based_exec_control = 0;
2550         u32 _cpu_based_2nd_exec_control = 0;
2551         u32 _vmexit_control = 0;
2552         u32 _vmentry_control = 0;
2553
2554         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2555         opt = PIN_BASED_VIRTUAL_NMIS;
2556         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2557                                 &_pin_based_exec_control) < 0)
2558                 return -EIO;
2559
2560         min = CPU_BASED_HLT_EXITING |
2561 #ifdef CONFIG_X86_64
2562               CPU_BASED_CR8_LOAD_EXITING |
2563               CPU_BASED_CR8_STORE_EXITING |
2564 #endif
2565               CPU_BASED_CR3_LOAD_EXITING |
2566               CPU_BASED_CR3_STORE_EXITING |
2567               CPU_BASED_USE_IO_BITMAPS |
2568               CPU_BASED_MOV_DR_EXITING |
2569               CPU_BASED_USE_TSC_OFFSETING |
2570               CPU_BASED_MWAIT_EXITING |
2571               CPU_BASED_MONITOR_EXITING |
2572               CPU_BASED_INVLPG_EXITING |
2573               CPU_BASED_RDPMC_EXITING;
2574
2575         opt = CPU_BASED_TPR_SHADOW |
2576               CPU_BASED_USE_MSR_BITMAPS |
2577               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2578         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2579                                 &_cpu_based_exec_control) < 0)
2580                 return -EIO;
2581 #ifdef CONFIG_X86_64
2582         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2583                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2584                                            ~CPU_BASED_CR8_STORE_EXITING;
2585 #endif
2586         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2587                 min2 = 0;
2588                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2589                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2590                         SECONDARY_EXEC_WBINVD_EXITING |
2591                         SECONDARY_EXEC_ENABLE_VPID |
2592                         SECONDARY_EXEC_ENABLE_EPT |
2593                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2594                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2595                         SECONDARY_EXEC_RDTSCP |
2596                         SECONDARY_EXEC_ENABLE_INVPCID |
2597                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2598                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
2599                 if (adjust_vmx_controls(min2, opt2,
2600                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2601                                         &_cpu_based_2nd_exec_control) < 0)
2602                         return -EIO;
2603         }
2604 #ifndef CONFIG_X86_64
2605         if (!(_cpu_based_2nd_exec_control &
2606                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2607                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2608 #endif
2609
2610         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2611                 _cpu_based_2nd_exec_control &= ~(
2612                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2613                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2614                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2615
2616         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2617                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2618                    enabled */
2619                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2620                                              CPU_BASED_CR3_STORE_EXITING |
2621                                              CPU_BASED_INVLPG_EXITING);
2622                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2623                       vmx_capability.ept, vmx_capability.vpid);
2624         }
2625
2626         min = 0;
2627 #ifdef CONFIG_X86_64
2628         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2629 #endif
2630         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2631         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2632                                 &_vmexit_control) < 0)
2633                 return -EIO;
2634
2635         min = 0;
2636         opt = VM_ENTRY_LOAD_IA32_PAT;
2637         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2638                                 &_vmentry_control) < 0)
2639                 return -EIO;
2640
2641         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2642
2643         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2644         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2645                 return -EIO;
2646
2647 #ifdef CONFIG_X86_64
2648         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2649         if (vmx_msr_high & (1u<<16))
2650                 return -EIO;
2651 #endif
2652
2653         /* Require Write-Back (WB) memory type for VMCS accesses. */
2654         if (((vmx_msr_high >> 18) & 15) != 6)
2655                 return -EIO;
2656
2657         vmcs_conf->size = vmx_msr_high & 0x1fff;
2658         vmcs_conf->order = get_order(vmcs_config.size);
2659         vmcs_conf->revision_id = vmx_msr_low;
2660
2661         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2662         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2663         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2664         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2665         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2666
2667         cpu_has_load_ia32_efer =
2668                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2669                                 VM_ENTRY_LOAD_IA32_EFER)
2670                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2671                                    VM_EXIT_LOAD_IA32_EFER);
2672
2673         cpu_has_load_perf_global_ctrl =
2674                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2675                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2676                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2677                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2678
2679         /*
2680          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2681          * but due to arrata below it can't be used. Workaround is to use
2682          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2683          *
2684          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2685          *
2686          * AAK155             (model 26)
2687          * AAP115             (model 30)
2688          * AAT100             (model 37)
2689          * BC86,AAY89,BD102   (model 44)
2690          * BA97               (model 46)
2691          *
2692          */
2693         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2694                 switch (boot_cpu_data.x86_model) {
2695                 case 26:
2696                 case 30:
2697                 case 37:
2698                 case 44:
2699                 case 46:
2700                         cpu_has_load_perf_global_ctrl = false;
2701                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2702                                         "does not work properly. Using workaround\n");
2703                         break;
2704                 default:
2705                         break;
2706                 }
2707         }
2708
2709         return 0;
2710 }
2711
2712 static struct vmcs *alloc_vmcs_cpu(int cpu)
2713 {
2714         int node = cpu_to_node(cpu);
2715         struct page *pages;
2716         struct vmcs *vmcs;
2717
2718         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2719         if (!pages)
2720                 return NULL;
2721         vmcs = page_address(pages);
2722         memset(vmcs, 0, vmcs_config.size);
2723         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2724         return vmcs;
2725 }
2726
2727 static struct vmcs *alloc_vmcs(void)
2728 {
2729         return alloc_vmcs_cpu(raw_smp_processor_id());
2730 }
2731
2732 static void free_vmcs(struct vmcs *vmcs)
2733 {
2734         free_pages((unsigned long)vmcs, vmcs_config.order);
2735 }
2736
2737 /*
2738  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2739  */
2740 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2741 {
2742         if (!loaded_vmcs->vmcs)
2743                 return;
2744         loaded_vmcs_clear(loaded_vmcs);
2745         free_vmcs(loaded_vmcs->vmcs);
2746         loaded_vmcs->vmcs = NULL;
2747 }
2748
2749 static void free_kvm_area(void)
2750 {
2751         int cpu;
2752
2753         for_each_possible_cpu(cpu) {
2754                 free_vmcs(per_cpu(vmxarea, cpu));
2755                 per_cpu(vmxarea, cpu) = NULL;
2756         }
2757 }
2758
2759 static __init int alloc_kvm_area(void)
2760 {
2761         int cpu;
2762
2763         for_each_possible_cpu(cpu) {
2764                 struct vmcs *vmcs;
2765
2766                 vmcs = alloc_vmcs_cpu(cpu);
2767                 if (!vmcs) {
2768                         free_kvm_area();
2769                         return -ENOMEM;
2770                 }
2771
2772                 per_cpu(vmxarea, cpu) = vmcs;
2773         }
2774         return 0;
2775 }
2776
2777 static __init int hardware_setup(void)
2778 {
2779         if (setup_vmcs_config(&vmcs_config) < 0)
2780                 return -EIO;
2781
2782         if (boot_cpu_has(X86_FEATURE_NX))
2783                 kvm_enable_efer_bits(EFER_NX);
2784
2785         if (!cpu_has_vmx_vpid())
2786                 enable_vpid = 0;
2787
2788         if (!cpu_has_vmx_ept() ||
2789             !cpu_has_vmx_ept_4levels()) {
2790                 enable_ept = 0;
2791                 enable_unrestricted_guest = 0;
2792                 enable_ept_ad_bits = 0;
2793         }
2794
2795         if (!cpu_has_vmx_ept_ad_bits())
2796                 enable_ept_ad_bits = 0;
2797
2798         if (!cpu_has_vmx_unrestricted_guest())
2799                 enable_unrestricted_guest = 0;
2800
2801         if (!cpu_has_vmx_flexpriority())
2802                 flexpriority_enabled = 0;
2803
2804         if (!cpu_has_vmx_tpr_shadow())
2805                 kvm_x86_ops->update_cr8_intercept = NULL;
2806
2807         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2808                 kvm_disable_largepages();
2809
2810         if (!cpu_has_vmx_ple())
2811                 ple_gap = 0;
2812
2813         if (!cpu_has_vmx_apic_register_virt() ||
2814                                 !cpu_has_vmx_virtual_intr_delivery())
2815                 enable_apicv_reg_vid = 0;
2816
2817         if (enable_apicv_reg_vid)
2818                 kvm_x86_ops->update_cr8_intercept = NULL;
2819         else
2820                 kvm_x86_ops->hwapic_irr_update = NULL;
2821
2822         if (nested)
2823                 nested_vmx_setup_ctls_msrs();
2824
2825         return alloc_kvm_area();
2826 }
2827
2828 static __exit void hardware_unsetup(void)
2829 {
2830         free_kvm_area();
2831 }
2832
2833 static bool emulation_required(struct kvm_vcpu *vcpu)
2834 {
2835         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2836 }
2837
2838 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2839                 struct kvm_segment *save)
2840 {
2841         if (!emulate_invalid_guest_state) {
2842                 /*
2843                  * CS and SS RPL should be equal during guest entry according
2844                  * to VMX spec, but in reality it is not always so. Since vcpu
2845                  * is in the middle of the transition from real mode to
2846                  * protected mode it is safe to assume that RPL 0 is a good
2847                  * default value.
2848                  */
2849                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2850                         save->selector &= ~SELECTOR_RPL_MASK;
2851                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2852                 save->s = 1;
2853         }
2854         vmx_set_segment(vcpu, save, seg);
2855 }
2856
2857 static void enter_pmode(struct kvm_vcpu *vcpu)
2858 {
2859         unsigned long flags;
2860         struct vcpu_vmx *vmx = to_vmx(vcpu);
2861
2862         /*
2863          * Update real mode segment cache. It may be not up-to-date if sement
2864          * register was written while vcpu was in a guest mode.
2865          */
2866         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2867         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2868         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2869         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2870         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2871         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2872
2873         vmx->rmode.vm86_active = 0;
2874
2875         vmx_segment_cache_clear(vmx);
2876
2877         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2878
2879         flags = vmcs_readl(GUEST_RFLAGS);
2880         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2881         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2882         vmcs_writel(GUEST_RFLAGS, flags);
2883
2884         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2885                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2886
2887         update_exception_bitmap(vcpu);
2888
2889         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2890         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2891         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2892         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2893         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2894         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2895
2896         /* CPL is always 0 when CPU enters protected mode */
2897         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2898         vmx->cpl = 0;
2899 }
2900
2901 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2902 {
2903         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2904         struct kvm_segment var = *save;
2905
2906         var.dpl = 0x3;
2907         if (seg == VCPU_SREG_CS)
2908                 var.type = 0x3;
2909
2910         if (!emulate_invalid_guest_state) {
2911                 var.selector = var.base >> 4;
2912                 var.base = var.base & 0xffff0;
2913                 var.limit = 0xffff;
2914                 var.g = 0;
2915                 var.db = 0;
2916                 var.present = 1;
2917                 var.s = 1;
2918                 var.l = 0;
2919                 var.unusable = 0;
2920                 var.type = 0x3;
2921                 var.avl = 0;
2922                 if (save->base & 0xf)
2923                         printk_once(KERN_WARNING "kvm: segment base is not "
2924                                         "paragraph aligned when entering "
2925                                         "protected mode (seg=%d)", seg);
2926         }
2927
2928         vmcs_write16(sf->selector, var.selector);
2929         vmcs_write32(sf->base, var.base);
2930         vmcs_write32(sf->limit, var.limit);
2931         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2932 }
2933
2934 static void enter_rmode(struct kvm_vcpu *vcpu)
2935 {
2936         unsigned long flags;
2937         struct vcpu_vmx *vmx = to_vmx(vcpu);
2938
2939         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2940         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2941         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2942         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2943         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2944         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2945         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2946
2947         vmx->rmode.vm86_active = 1;
2948
2949         /*
2950          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2951          * vcpu. Warn the user that an update is overdue.
2952          */
2953         if (!vcpu->kvm->arch.tss_addr)
2954                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2955                              "called before entering vcpu\n");
2956
2957         vmx_segment_cache_clear(vmx);
2958
2959         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
2960         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2961         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2962
2963         flags = vmcs_readl(GUEST_RFLAGS);
2964         vmx->rmode.save_rflags = flags;
2965
2966         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2967
2968         vmcs_writel(GUEST_RFLAGS, flags);
2969         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2970         update_exception_bitmap(vcpu);
2971
2972         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2973         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2974         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2975         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2976         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2977         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2978
2979         kvm_mmu_reset_context(vcpu);
2980 }
2981
2982 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2983 {
2984         struct vcpu_vmx *vmx = to_vmx(vcpu);
2985         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2986
2987         if (!msr)
2988                 return;
2989
2990         /*
2991          * Force kernel_gs_base reloading before EFER changes, as control
2992          * of this msr depends on is_long_mode().
2993          */
2994         vmx_load_host_state(to_vmx(vcpu));
2995         vcpu->arch.efer = efer;
2996         if (efer & EFER_LMA) {
2997                 vmcs_write32(VM_ENTRY_CONTROLS,
2998                              vmcs_read32(VM_ENTRY_CONTROLS) |
2999                              VM_ENTRY_IA32E_MODE);
3000                 msr->data = efer;
3001         } else {
3002                 vmcs_write32(VM_ENTRY_CONTROLS,
3003                              vmcs_read32(VM_ENTRY_CONTROLS) &
3004                              ~VM_ENTRY_IA32E_MODE);
3005
3006                 msr->data = efer & ~EFER_LME;
3007         }
3008         setup_msrs(vmx);
3009 }
3010
3011 #ifdef CONFIG_X86_64
3012
3013 static void enter_lmode(struct kvm_vcpu *vcpu)
3014 {
3015         u32 guest_tr_ar;
3016
3017         vmx_segment_cache_clear(to_vmx(vcpu));
3018
3019         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3020         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3021                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3022                                      __func__);
3023                 vmcs_write32(GUEST_TR_AR_BYTES,
3024                              (guest_tr_ar & ~AR_TYPE_MASK)
3025                              | AR_TYPE_BUSY_64_TSS);
3026         }
3027         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3028 }
3029
3030 static void exit_lmode(struct kvm_vcpu *vcpu)
3031 {
3032         vmcs_write32(VM_ENTRY_CONTROLS,
3033                      vmcs_read32(VM_ENTRY_CONTROLS)
3034                      & ~VM_ENTRY_IA32E_MODE);
3035         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3036 }
3037
3038 #endif
3039
3040 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3041 {
3042         vpid_sync_context(to_vmx(vcpu));
3043         if (enable_ept) {
3044                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3045                         return;
3046                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3047         }
3048 }
3049
3050 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3051 {
3052         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3053
3054         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3055         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3056 }
3057
3058 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3059 {
3060         if (enable_ept && is_paging(vcpu))
3061                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3062         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3063 }
3064
3065 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3066 {
3067         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3068
3069         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3070         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3071 }
3072
3073 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3074 {
3075         if (!test_bit(VCPU_EXREG_PDPTR,
3076                       (unsigned long *)&vcpu->arch.regs_dirty))
3077                 return;
3078
3079         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3080                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3081                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3082                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3083                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3084         }
3085 }
3086
3087 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3088 {
3089         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3090                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3091                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3092                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3093                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3094         }
3095
3096         __set_bit(VCPU_EXREG_PDPTR,
3097                   (unsigned long *)&vcpu->arch.regs_avail);
3098         __set_bit(VCPU_EXREG_PDPTR,
3099                   (unsigned long *)&vcpu->arch.regs_dirty);
3100 }
3101
3102 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3103
3104 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3105                                         unsigned long cr0,
3106                                         struct kvm_vcpu *vcpu)
3107 {
3108         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3109                 vmx_decache_cr3(vcpu);
3110         if (!(cr0 & X86_CR0_PG)) {
3111                 /* From paging/starting to nonpaging */
3112                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3113                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3114                              (CPU_BASED_CR3_LOAD_EXITING |
3115                               CPU_BASED_CR3_STORE_EXITING));
3116                 vcpu->arch.cr0 = cr0;
3117                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3118         } else if (!is_paging(vcpu)) {
3119                 /* From nonpaging to paging */
3120                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3121                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3122                              ~(CPU_BASED_CR3_LOAD_EXITING |
3123                                CPU_BASED_CR3_STORE_EXITING));
3124                 vcpu->arch.cr0 = cr0;
3125                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3126         }
3127
3128         if (!(cr0 & X86_CR0_WP))
3129                 *hw_cr0 &= ~X86_CR0_WP;
3130 }
3131
3132 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3133 {
3134         struct vcpu_vmx *vmx = to_vmx(vcpu);
3135         unsigned long hw_cr0;
3136
3137         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3138         if (enable_unrestricted_guest)
3139                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3140         else {
3141                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3142
3143                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3144                         enter_pmode(vcpu);
3145
3146                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3147                         enter_rmode(vcpu);
3148         }
3149
3150 #ifdef CONFIG_X86_64
3151         if (vcpu->arch.efer & EFER_LME) {
3152                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3153                         enter_lmode(vcpu);
3154                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3155                         exit_lmode(vcpu);
3156         }
3157 #endif
3158
3159         if (enable_ept)
3160                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3161
3162         if (!vcpu->fpu_active)
3163                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3164
3165         vmcs_writel(CR0_READ_SHADOW, cr0);
3166         vmcs_writel(GUEST_CR0, hw_cr0);
3167         vcpu->arch.cr0 = cr0;
3168
3169         /* depends on vcpu->arch.cr0 to be set to a new value */
3170         vmx->emulation_required = emulation_required(vcpu);
3171 }
3172
3173 static u64 construct_eptp(unsigned long root_hpa)
3174 {
3175         u64 eptp;
3176
3177         /* TODO write the value reading from MSR */
3178         eptp = VMX_EPT_DEFAULT_MT |
3179                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3180         if (enable_ept_ad_bits)
3181                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3182         eptp |= (root_hpa & PAGE_MASK);
3183
3184         return eptp;
3185 }
3186
3187 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3188 {
3189         unsigned long guest_cr3;
3190         u64 eptp;
3191
3192         guest_cr3 = cr3;
3193         if (enable_ept) {
3194                 eptp = construct_eptp(cr3);
3195                 vmcs_write64(EPT_POINTER, eptp);
3196                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3197                         vcpu->kvm->arch.ept_identity_map_addr;
3198                 ept_load_pdptrs(vcpu);
3199         }
3200
3201         vmx_flush_tlb(vcpu);
3202         vmcs_writel(GUEST_CR3, guest_cr3);
3203 }
3204
3205 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3206 {
3207         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3208                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3209
3210         if (cr4 & X86_CR4_VMXE) {
3211                 /*
3212                  * To use VMXON (and later other VMX instructions), a guest
3213                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3214                  * So basically the check on whether to allow nested VMX
3215                  * is here.
3216                  */
3217                 if (!nested_vmx_allowed(vcpu))
3218                         return 1;
3219         }
3220         if (to_vmx(vcpu)->nested.vmxon &&
3221             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3222                 return 1;
3223
3224         vcpu->arch.cr4 = cr4;
3225         if (enable_ept) {
3226                 if (!is_paging(vcpu)) {
3227                         hw_cr4 &= ~X86_CR4_PAE;
3228                         hw_cr4 |= X86_CR4_PSE;
3229                         /*
3230                          * SMEP is disabled if CPU is in non-paging mode in
3231                          * hardware. However KVM always uses paging mode to
3232                          * emulate guest non-paging mode with TDP.
3233                          * To emulate this behavior, SMEP needs to be manually
3234                          * disabled when guest switches to non-paging mode.
3235                          */
3236                         hw_cr4 &= ~X86_CR4_SMEP;
3237                 } else if (!(cr4 & X86_CR4_PAE)) {
3238                         hw_cr4 &= ~X86_CR4_PAE;
3239                 }
3240         }
3241
3242         vmcs_writel(CR4_READ_SHADOW, cr4);
3243         vmcs_writel(GUEST_CR4, hw_cr4);
3244         return 0;
3245 }
3246
3247 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3248                             struct kvm_segment *var, int seg)
3249 {
3250         struct vcpu_vmx *vmx = to_vmx(vcpu);
3251         u32 ar;
3252
3253         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3254                 *var = vmx->rmode.segs[seg];
3255                 if (seg == VCPU_SREG_TR
3256                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3257                         return;
3258                 var->base = vmx_read_guest_seg_base(vmx, seg);
3259                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3260                 return;
3261         }
3262         var->base = vmx_read_guest_seg_base(vmx, seg);
3263         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3264         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3265         ar = vmx_read_guest_seg_ar(vmx, seg);
3266         var->type = ar & 15;
3267         var->s = (ar >> 4) & 1;
3268         var->dpl = (ar >> 5) & 3;
3269         var->present = (ar >> 7) & 1;
3270         var->avl = (ar >> 12) & 1;
3271         var->l = (ar >> 13) & 1;
3272         var->db = (ar >> 14) & 1;
3273         var->g = (ar >> 15) & 1;
3274         var->unusable = (ar >> 16) & 1;
3275 }
3276
3277 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3278 {
3279         struct kvm_segment s;
3280
3281         if (to_vmx(vcpu)->rmode.vm86_active) {
3282                 vmx_get_segment(vcpu, &s, seg);
3283                 return s.base;
3284         }
3285         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3286 }
3287
3288 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3289 {
3290         struct vcpu_vmx *vmx = to_vmx(vcpu);
3291
3292         if (!is_protmode(vcpu))
3293                 return 0;
3294
3295         if (!is_long_mode(vcpu)
3296             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3297                 return 3;
3298
3299         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3300                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3301                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3302         }
3303
3304         return vmx->cpl;
3305 }
3306
3307
3308 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3309 {
3310         u32 ar;
3311
3312         if (var->unusable || !var->present)
3313                 ar = 1 << 16;
3314         else {
3315                 ar = var->type & 15;
3316                 ar |= (var->s & 1) << 4;
3317                 ar |= (var->dpl & 3) << 5;
3318                 ar |= (var->present & 1) << 7;
3319                 ar |= (var->avl & 1) << 12;
3320                 ar |= (var->l & 1) << 13;
3321                 ar |= (var->db & 1) << 14;
3322                 ar |= (var->g & 1) << 15;
3323         }
3324
3325         return ar;
3326 }
3327
3328 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3329                             struct kvm_segment *var, int seg)
3330 {
3331         struct vcpu_vmx *vmx = to_vmx(vcpu);
3332         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3333
3334         vmx_segment_cache_clear(vmx);
3335         if (seg == VCPU_SREG_CS)
3336                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3337
3338         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3339                 vmx->rmode.segs[seg] = *var;
3340                 if (seg == VCPU_SREG_TR)
3341                         vmcs_write16(sf->selector, var->selector);
3342                 else if (var->s)
3343                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3344                 goto out;
3345         }
3346
3347         vmcs_writel(sf->base, var->base);
3348         vmcs_write32(sf->limit, var->limit);
3349         vmcs_write16(sf->selector, var->selector);
3350
3351         /*
3352          *   Fix the "Accessed" bit in AR field of segment registers for older
3353          * qemu binaries.
3354          *   IA32 arch specifies that at the time of processor reset the
3355          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3356          * is setting it to 0 in the userland code. This causes invalid guest
3357          * state vmexit when "unrestricted guest" mode is turned on.
3358          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3359          * tree. Newer qemu binaries with that qemu fix would not need this
3360          * kvm hack.
3361          */
3362         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3363                 var->type |= 0x1; /* Accessed */
3364
3365         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3366
3367 out:
3368         vmx->emulation_required |= emulation_required(vcpu);
3369 }
3370
3371 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3372 {
3373         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3374
3375         *db = (ar >> 14) & 1;
3376         *l = (ar >> 13) & 1;
3377 }
3378
3379 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3380 {
3381         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3382         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3383 }
3384
3385 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3386 {
3387         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3388         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3389 }
3390
3391 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3392 {
3393         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3394         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3395 }
3396
3397 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3398 {
3399         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3400         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3401 }
3402
3403 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3404 {
3405         struct kvm_segment var;
3406         u32 ar;
3407
3408         vmx_get_segment(vcpu, &var, seg);
3409         var.dpl = 0x3;
3410         if (seg == VCPU_SREG_CS)
3411                 var.type = 0x3;
3412         ar = vmx_segment_access_rights(&var);
3413
3414         if (var.base != (var.selector << 4))
3415                 return false;
3416         if (var.limit != 0xffff)
3417                 return false;
3418         if (ar != 0xf3)
3419                 return false;
3420
3421         return true;
3422 }
3423
3424 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3425 {
3426         struct kvm_segment cs;
3427         unsigned int cs_rpl;
3428
3429         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3430         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3431
3432         if (cs.unusable)
3433                 return false;
3434         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3435                 return false;
3436         if (!cs.s)
3437                 return false;
3438         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3439                 if (cs.dpl > cs_rpl)
3440                         return false;
3441         } else {
3442                 if (cs.dpl != cs_rpl)
3443                         return false;
3444         }
3445         if (!cs.present)
3446                 return false;
3447
3448         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3449         return true;
3450 }
3451
3452 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3453 {
3454         struct kvm_segment ss;
3455         unsigned int ss_rpl;
3456
3457         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3458         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3459
3460         if (ss.unusable)
3461                 return true;
3462         if (ss.type != 3 && ss.type != 7)
3463                 return false;
3464         if (!ss.s)
3465                 return false;
3466         if (ss.dpl != ss_rpl) /* DPL != RPL */
3467                 return false;
3468         if (!ss.present)
3469                 return false;
3470
3471         return true;
3472 }
3473
3474 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3475 {
3476         struct kvm_segment var;
3477         unsigned int rpl;
3478
3479         vmx_get_segment(vcpu, &var, seg);
3480         rpl = var.selector & SELECTOR_RPL_MASK;
3481
3482         if (var.unusable)
3483                 return true;
3484         if (!var.s)
3485                 return false;
3486         if (!var.present)
3487                 return false;
3488         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3489                 if (var.dpl < rpl) /* DPL < RPL */
3490                         return false;
3491         }
3492
3493         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3494          * rights flags
3495          */
3496         return true;
3497 }
3498
3499 static bool tr_valid(struct kvm_vcpu *vcpu)
3500 {
3501         struct kvm_segment tr;
3502
3503         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3504
3505         if (tr.unusable)
3506                 return false;
3507         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3508                 return false;
3509         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3510                 return false;
3511         if (!tr.present)
3512                 return false;
3513
3514         return true;
3515 }
3516
3517 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3518 {
3519         struct kvm_segment ldtr;
3520
3521         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3522
3523         if (ldtr.unusable)
3524                 return true;
3525         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3526                 return false;
3527         if (ldtr.type != 2)
3528                 return false;
3529         if (!ldtr.present)
3530                 return false;
3531
3532         return true;
3533 }
3534
3535 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3536 {
3537         struct kvm_segment cs, ss;
3538
3539         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3540         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3541
3542         return ((cs.selector & SELECTOR_RPL_MASK) ==
3543                  (ss.selector & SELECTOR_RPL_MASK));
3544 }
3545
3546 /*
3547  * Check if guest state is valid. Returns true if valid, false if
3548  * not.
3549  * We assume that registers are always usable
3550  */
3551 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3552 {
3553         if (enable_unrestricted_guest)
3554                 return true;
3555
3556         /* real mode guest state checks */
3557         if (!is_protmode(vcpu)) {
3558                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3559                         return false;
3560                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3561                         return false;
3562                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3563                         return false;
3564                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3565                         return false;
3566                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3567                         return false;
3568                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3569                         return false;
3570         } else {
3571         /* protected mode guest state checks */
3572                 if (!cs_ss_rpl_check(vcpu))
3573                         return false;
3574                 if (!code_segment_valid(vcpu))
3575                         return false;
3576                 if (!stack_segment_valid(vcpu))
3577                         return false;
3578                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3579                         return false;
3580                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3581                         return false;
3582                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3583                         return false;
3584                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3585                         return false;
3586                 if (!tr_valid(vcpu))
3587                         return false;
3588                 if (!ldtr_valid(vcpu))
3589                         return false;
3590         }
3591         /* TODO:
3592          * - Add checks on RIP
3593          * - Add checks on RFLAGS
3594          */
3595
3596         return true;
3597 }
3598
3599 static int init_rmode_tss(struct kvm *kvm)
3600 {
3601         gfn_t fn;
3602         u16 data = 0;
3603         int r, idx, ret = 0;
3604
3605         idx = srcu_read_lock(&kvm->srcu);
3606         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3607         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3608         if (r < 0)
3609                 goto out;
3610         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3611         r = kvm_write_guest_page(kvm, fn++, &data,
3612                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3613         if (r < 0)
3614                 goto out;
3615         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3616         if (r < 0)
3617                 goto out;
3618         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3619         if (r < 0)
3620                 goto out;
3621         data = ~0;
3622         r = kvm_write_guest_page(kvm, fn, &data,
3623                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3624                                  sizeof(u8));
3625         if (r < 0)
3626                 goto out;
3627
3628         ret = 1;
3629 out:
3630         srcu_read_unlock(&kvm->srcu, idx);
3631         return ret;
3632 }
3633
3634 static int init_rmode_identity_map(struct kvm *kvm)
3635 {
3636         int i, idx, r, ret;
3637         pfn_t identity_map_pfn;
3638         u32 tmp;
3639
3640         if (!enable_ept)
3641                 return 1;
3642         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3643                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3644                         "haven't been allocated!\n");
3645                 return 0;
3646         }
3647         if (likely(kvm->arch.ept_identity_pagetable_done))
3648                 return 1;
3649         ret = 0;
3650         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3651         idx = srcu_read_lock(&kvm->srcu);
3652         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3653         if (r < 0)
3654                 goto out;
3655         /* Set up identity-mapping pagetable for EPT in real mode */
3656         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3657                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3658                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3659                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3660                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3661                 if (r < 0)
3662                         goto out;
3663         }
3664         kvm->arch.ept_identity_pagetable_done = true;
3665         ret = 1;
3666 out:
3667         srcu_read_unlock(&kvm->srcu, idx);
3668         return ret;
3669 }
3670
3671 static void seg_setup(int seg)
3672 {
3673         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3674         unsigned int ar;
3675
3676         vmcs_write16(sf->selector, 0);
3677         vmcs_writel(sf->base, 0);
3678         vmcs_write32(sf->limit, 0xffff);
3679         ar = 0x93;
3680         if (seg == VCPU_SREG_CS)
3681                 ar |= 0x08; /* code segment */
3682
3683         vmcs_write32(sf->ar_bytes, ar);
3684 }
3685
3686 static int alloc_apic_access_page(struct kvm *kvm)
3687 {
3688         struct page *page;
3689         struct kvm_userspace_memory_region kvm_userspace_mem;
3690         int r = 0;
3691
3692         mutex_lock(&kvm->slots_lock);
3693         if (kvm->arch.apic_access_page)
3694                 goto out;
3695         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3696         kvm_userspace_mem.flags = 0;
3697         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3698         kvm_userspace_mem.memory_size = PAGE_SIZE;
3699         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3700         if (r)
3701                 goto out;
3702
3703         page = gfn_to_page(kvm, 0xfee00);
3704         if (is_error_page(page)) {
3705                 r = -EFAULT;
3706                 goto out;
3707         }
3708
3709         kvm->arch.apic_access_page = page;
3710 out:
3711         mutex_unlock(&kvm->slots_lock);
3712         return r;
3713 }
3714
3715 static int alloc_identity_pagetable(struct kvm *kvm)
3716 {
3717         struct page *page;
3718         struct kvm_userspace_memory_region kvm_userspace_mem;
3719         int r = 0;
3720
3721         mutex_lock(&kvm->slots_lock);
3722         if (kvm->arch.ept_identity_pagetable)
3723                 goto out;
3724         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3725         kvm_userspace_mem.flags = 0;
3726         kvm_userspace_mem.guest_phys_addr =
3727                 kvm->arch.ept_identity_map_addr;
3728         kvm_userspace_mem.memory_size = PAGE_SIZE;
3729         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3730         if (r)
3731                 goto out;
3732
3733         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3734         if (is_error_page(page)) {
3735                 r = -EFAULT;
3736                 goto out;
3737         }
3738
3739         kvm->arch.ept_identity_pagetable = page;
3740 out:
3741         mutex_unlock(&kvm->slots_lock);
3742         return r;
3743 }
3744
3745 static void allocate_vpid(struct vcpu_vmx *vmx)
3746 {
3747         int vpid;
3748
3749         vmx->vpid = 0;
3750         if (!enable_vpid)
3751                 return;
3752         spin_lock(&vmx_vpid_lock);
3753         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3754         if (vpid < VMX_NR_VPIDS) {
3755                 vmx->vpid = vpid;
3756                 __set_bit(vpid, vmx_vpid_bitmap);
3757         }
3758         spin_unlock(&vmx_vpid_lock);
3759 }
3760
3761 static void free_vpid(struct vcpu_vmx *vmx)
3762 {
3763         if (!enable_vpid)
3764                 return;
3765         spin_lock(&vmx_vpid_lock);
3766         if (vmx->vpid != 0)
3767                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3768         spin_unlock(&vmx_vpid_lock);
3769 }
3770
3771 #define MSR_TYPE_R      1
3772 #define MSR_TYPE_W      2
3773 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3774                                                 u32 msr, int type)
3775 {
3776         int f = sizeof(unsigned long);
3777
3778         if (!cpu_has_vmx_msr_bitmap())
3779                 return;
3780
3781         /*
3782          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3783          * have the write-low and read-high bitmap offsets the wrong way round.
3784          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3785          */
3786         if (msr <= 0x1fff) {
3787                 if (type & MSR_TYPE_R)
3788                         /* read-low */
3789                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3790
3791                 if (type & MSR_TYPE_W)
3792                         /* write-low */
3793                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3794
3795         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3796                 msr &= 0x1fff;
3797                 if (type & MSR_TYPE_R)
3798                         /* read-high */
3799                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3800
3801                 if (type & MSR_TYPE_W)
3802                         /* write-high */
3803                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3804
3805         }
3806 }
3807
3808 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3809                                                 u32 msr, int type)
3810 {
3811         int f = sizeof(unsigned long);
3812
3813         if (!cpu_has_vmx_msr_bitmap())
3814                 return;
3815
3816         /*
3817          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3818          * have the write-low and read-high bitmap offsets the wrong way round.
3819          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3820          */
3821         if (msr <= 0x1fff) {
3822                 if (type & MSR_TYPE_R)
3823                         /* read-low */
3824                         __set_bit(msr, msr_bitmap + 0x000 / f);
3825
3826                 if (type & MSR_TYPE_W)
3827                         /* write-low */
3828                         __set_bit(msr, msr_bitmap + 0x800 / f);
3829
3830         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3831                 msr &= 0x1fff;
3832                 if (type & MSR_TYPE_R)
3833                         /* read-high */
3834                         __set_bit(msr, msr_bitmap + 0x400 / f);
3835
3836                 if (type & MSR_TYPE_W)
3837                         /* write-high */
3838                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3839
3840         }
3841 }
3842
3843 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3844 {
3845         if (!longmode_only)
3846                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3847                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3848         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3849                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3850 }
3851
3852 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3853 {
3854         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3855                         msr, MSR_TYPE_R);
3856         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3857                         msr, MSR_TYPE_R);
3858 }
3859
3860 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3861 {
3862         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3863                         msr, MSR_TYPE_R);
3864         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3865                         msr, MSR_TYPE_R);
3866 }
3867
3868 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3869 {
3870         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3871                         msr, MSR_TYPE_W);
3872         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3873                         msr, MSR_TYPE_W);
3874 }
3875
3876 /*
3877  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3878  * will not change in the lifetime of the guest.
3879  * Note that host-state that does change is set elsewhere. E.g., host-state
3880  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3881  */
3882 static void vmx_set_constant_host_state(void)
3883 {
3884         u32 low32, high32;
3885         unsigned long tmpl;
3886         struct desc_ptr dt;
3887
3888         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
3889         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3890         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3891
3892         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3893 #ifdef CONFIG_X86_64
3894         /*
3895          * Load null selectors, so we can avoid reloading them in
3896          * __vmx_load_host_state(), in case userspace uses the null selectors
3897          * too (the expected case).
3898          */
3899         vmcs_write16(HOST_DS_SELECTOR, 0);
3900         vmcs_write16(HOST_ES_SELECTOR, 0);
3901 #else
3902         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3903         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3904 #endif
3905         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3906         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3907
3908         native_store_idt(&dt);
3909         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3910
3911         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3912
3913         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3914         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3915         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3916         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3917
3918         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3919                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3920                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3921         }
3922 }
3923
3924 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3925 {
3926         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3927         if (enable_ept)
3928                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3929         if (is_guest_mode(&vmx->vcpu))
3930                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3931                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3932         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3933 }
3934
3935 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3936 {
3937         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3938         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3939                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3940 #ifdef CONFIG_X86_64
3941                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3942                                 CPU_BASED_CR8_LOAD_EXITING;
3943 #endif
3944         }
3945         if (!enable_ept)
3946                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3947                                 CPU_BASED_CR3_LOAD_EXITING  |
3948                                 CPU_BASED_INVLPG_EXITING;
3949         return exec_control;
3950 }
3951
3952 static int vmx_vm_has_apicv(struct kvm *kvm)
3953 {
3954         return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3955 }
3956
3957 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3958 {
3959         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3960         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3961                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3962         if (vmx->vpid == 0)
3963                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3964         if (!enable_ept) {
3965                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3966                 enable_unrestricted_guest = 0;
3967                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3968                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3969         }
3970         if (!enable_unrestricted_guest)
3971                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3972         if (!ple_gap)
3973                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3974         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3975                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3976                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3977         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3978         return exec_control;
3979 }
3980
3981 static void ept_set_mmio_spte_mask(void)
3982 {
3983         /*
3984          * EPT Misconfigurations can be generated if the value of bits 2:0
3985          * of an EPT paging-structure entry is 110b (write/execute).
3986          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3987          * spte.
3988          */
3989         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3990 }
3991
3992 /*
3993  * Sets up the vmcs for emulated real mode.
3994  */
3995 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3996 {
3997 #ifdef CONFIG_X86_64
3998         unsigned long a;
3999 #endif
4000         int i;
4001
4002         /* I/O */
4003         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4004         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4005
4006         if (cpu_has_vmx_msr_bitmap())
4007                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4008
4009         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4010
4011         /* Control */
4012         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4013                 vmcs_config.pin_based_exec_ctrl);
4014
4015         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4016
4017         if (cpu_has_secondary_exec_ctrls()) {
4018                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4019                                 vmx_secondary_exec_control(vmx));
4020         }
4021
4022         if (enable_apicv_reg_vid) {
4023                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4024                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4025                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4026                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4027
4028                 vmcs_write16(GUEST_INTR_STATUS, 0);
4029         }
4030
4031         if (ple_gap) {
4032                 vmcs_write32(PLE_GAP, ple_gap);
4033                 vmcs_write32(PLE_WINDOW, ple_window);
4034         }
4035
4036         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4037         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4038         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4039
4040         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4041         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4042         vmx_set_constant_host_state();
4043 #ifdef CONFIG_X86_64
4044         rdmsrl(MSR_FS_BASE, a);
4045         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4046         rdmsrl(MSR_GS_BASE, a);
4047         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4048 #else
4049         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4050         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4051 #endif
4052
4053         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4054         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4055         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4056         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4057         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4058
4059         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4060                 u32 msr_low, msr_high;
4061                 u64 host_pat;
4062                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4063                 host_pat = msr_low | ((u64) msr_high << 32);
4064                 /* Write the default value follow host pat */
4065                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4066                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4067                 vmx->vcpu.arch.pat = host_pat;
4068         }
4069
4070         for (i = 0; i < NR_VMX_MSR; ++i) {
4071                 u32 index = vmx_msr_index[i];
4072                 u32 data_low, data_high;
4073                 int j = vmx->nmsrs;
4074
4075                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4076                         continue;
4077                 if (wrmsr_safe(index, data_low, data_high) < 0)
4078                         continue;
4079                 vmx->guest_msrs[j].index = i;
4080                 vmx->guest_msrs[j].data = 0;
4081                 vmx->guest_msrs[j].mask = -1ull;
4082                 ++vmx->nmsrs;
4083         }
4084
4085         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4086
4087         /* 22.2.1, 20.8.1 */
4088         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4089
4090         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4091         set_cr4_guest_host_mask(vmx);
4092
4093         return 0;
4094 }
4095
4096 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4097 {
4098         struct vcpu_vmx *vmx = to_vmx(vcpu);
4099         u64 msr;
4100
4101         vmx->rmode.vm86_active = 0;
4102
4103         vmx->soft_vnmi_blocked = 0;
4104
4105         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4106         kvm_set_cr8(&vmx->vcpu, 0);
4107         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4108         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4109                 msr |= MSR_IA32_APICBASE_BSP;
4110         kvm_set_apic_base(&vmx->vcpu, msr);
4111
4112         vmx_segment_cache_clear(vmx);
4113
4114         seg_setup(VCPU_SREG_CS);
4115         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4116         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4117
4118         seg_setup(VCPU_SREG_DS);
4119         seg_setup(VCPU_SREG_ES);
4120         seg_setup(VCPU_SREG_FS);
4121         seg_setup(VCPU_SREG_GS);
4122         seg_setup(VCPU_SREG_SS);
4123
4124         vmcs_write16(GUEST_TR_SELECTOR, 0);
4125         vmcs_writel(GUEST_TR_BASE, 0);
4126         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4127         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4128
4129         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4130         vmcs_writel(GUEST_LDTR_BASE, 0);
4131         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4132         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4133
4134         vmcs_write32(GUEST_SYSENTER_CS, 0);
4135         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4136         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4137
4138         vmcs_writel(GUEST_RFLAGS, 0x02);
4139         kvm_rip_write(vcpu, 0xfff0);
4140
4141         vmcs_writel(GUEST_GDTR_BASE, 0);
4142         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4143
4144         vmcs_writel(GUEST_IDTR_BASE, 0);
4145         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4146
4147         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4148         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4149         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4150
4151         /* Special registers */
4152         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4153
4154         setup_msrs(vmx);
4155
4156         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4157
4158         if (cpu_has_vmx_tpr_shadow()) {
4159                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4160                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4161                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4162                                      __pa(vmx->vcpu.arch.apic->regs));
4163                 vmcs_write32(TPR_THRESHOLD, 0);
4164         }
4165
4166         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4167                 vmcs_write64(APIC_ACCESS_ADDR,
4168                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4169
4170         if (vmx->vpid != 0)
4171                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4172
4173         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4174         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4175         vmx_set_cr4(&vmx->vcpu, 0);
4176         vmx_set_efer(&vmx->vcpu, 0);
4177         vmx_fpu_activate(&vmx->vcpu);
4178         update_exception_bitmap(&vmx->vcpu);
4179
4180         vpid_sync_context(vmx);
4181 }
4182
4183 /*
4184  * In nested virtualization, check if L1 asked to exit on external interrupts.
4185  * For most existing hypervisors, this will always return true.
4186  */
4187 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4188 {
4189         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4190                 PIN_BASED_EXT_INTR_MASK;
4191 }
4192
4193 static void enable_irq_window(struct kvm_vcpu *vcpu)
4194 {
4195         u32 cpu_based_vm_exec_control;
4196         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4197                 /*
4198                  * We get here if vmx_interrupt_allowed() said we can't
4199                  * inject to L1 now because L2 must run. Ask L2 to exit
4200                  * right after entry, so we can inject to L1 more promptly.
4201                  */
4202                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4203                 return;
4204         }
4205
4206         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4207         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4208         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4209 }
4210
4211 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4212 {
4213         u32 cpu_based_vm_exec_control;
4214
4215         if (!cpu_has_virtual_nmis()) {
4216                 enable_irq_window(vcpu);
4217                 return;
4218         }
4219
4220         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4221                 enable_irq_window(vcpu);
4222                 return;
4223         }
4224         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4225         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4226         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4227 }
4228
4229 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4230 {
4231         struct vcpu_vmx *vmx = to_vmx(vcpu);
4232         uint32_t intr;
4233         int irq = vcpu->arch.interrupt.nr;
4234
4235         trace_kvm_inj_virq(irq);
4236
4237         ++vcpu->stat.irq_injections;
4238         if (vmx->rmode.vm86_active) {
4239                 int inc_eip = 0;
4240                 if (vcpu->arch.interrupt.soft)
4241                         inc_eip = vcpu->arch.event_exit_inst_len;
4242                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4243                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4244                 return;
4245         }
4246         intr = irq | INTR_INFO_VALID_MASK;
4247         if (vcpu->arch.interrupt.soft) {
4248                 intr |= INTR_TYPE_SOFT_INTR;
4249                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4250                              vmx->vcpu.arch.event_exit_inst_len);
4251         } else
4252                 intr |= INTR_TYPE_EXT_INTR;
4253         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4254 }
4255
4256 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4257 {
4258         struct vcpu_vmx *vmx = to_vmx(vcpu);
4259
4260         if (is_guest_mode(vcpu))
4261                 return;
4262
4263         if (!cpu_has_virtual_nmis()) {
4264                 /*
4265                  * Tracking the NMI-blocked state in software is built upon
4266                  * finding the next open IRQ window. This, in turn, depends on
4267                  * well-behaving guests: They have to keep IRQs disabled at
4268                  * least as long as the NMI handler runs. Otherwise we may
4269                  * cause NMI nesting, maybe breaking the guest. But as this is
4270                  * highly unlikely, we can live with the residual risk.
4271                  */
4272                 vmx->soft_vnmi_blocked = 1;
4273                 vmx->vnmi_blocked_time = 0;
4274         }
4275
4276         ++vcpu->stat.nmi_injections;
4277         vmx->nmi_known_unmasked = false;
4278         if (vmx->rmode.vm86_active) {
4279                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4280                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4281                 return;
4282         }
4283         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4284                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4285 }
4286
4287 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4288 {
4289         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4290                 return 0;
4291
4292         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4293                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4294                    | GUEST_INTR_STATE_NMI));
4295 }
4296
4297 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4298 {
4299         if (!cpu_has_virtual_nmis())
4300                 return to_vmx(vcpu)->soft_vnmi_blocked;
4301         if (to_vmx(vcpu)->nmi_known_unmasked)
4302                 return false;
4303         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4304 }
4305
4306 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4307 {
4308         struct vcpu_vmx *vmx = to_vmx(vcpu);
4309
4310         if (!cpu_has_virtual_nmis()) {
4311                 if (vmx->soft_vnmi_blocked != masked) {
4312                         vmx->soft_vnmi_blocked = masked;
4313                         vmx->vnmi_blocked_time = 0;
4314                 }
4315         } else {
4316                 vmx->nmi_known_unmasked = !masked;
4317                 if (masked)
4318                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4319                                       GUEST_INTR_STATE_NMI);
4320                 else
4321                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4322                                         GUEST_INTR_STATE_NMI);
4323         }
4324 }
4325
4326 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4327 {
4328         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4329                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4330                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4331                     (vmcs12->idt_vectoring_info_field &
4332                      VECTORING_INFO_VALID_MASK))
4333                         return 0;
4334                 nested_vmx_vmexit(vcpu);
4335                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4336                 vmcs12->vm_exit_intr_info = 0;
4337                 /* fall through to normal code, but now in L1, not L2 */
4338         }
4339
4340         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4341                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4342                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4343 }
4344
4345 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4346 {
4347         int ret;
4348         struct kvm_userspace_memory_region tss_mem = {
4349                 .slot = TSS_PRIVATE_MEMSLOT,
4350                 .guest_phys_addr = addr,
4351                 .memory_size = PAGE_SIZE * 3,
4352                 .flags = 0,
4353         };
4354
4355         ret = kvm_set_memory_region(kvm, &tss_mem);
4356         if (ret)
4357                 return ret;
4358         kvm->arch.tss_addr = addr;
4359         if (!init_rmode_tss(kvm))
4360                 return  -ENOMEM;
4361
4362         return 0;
4363 }
4364
4365 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4366 {
4367         switch (vec) {
4368         case BP_VECTOR:
4369                 /*
4370                  * Update instruction length as we may reinject the exception
4371                  * from user space while in guest debugging mode.
4372                  */
4373                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4374                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4375                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4376                         return false;
4377                 /* fall through */
4378         case DB_VECTOR:
4379                 if (vcpu->guest_debug &
4380                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4381                         return false;
4382                 /* fall through */
4383         case DE_VECTOR:
4384         case OF_VECTOR:
4385         case BR_VECTOR:
4386         case UD_VECTOR:
4387         case DF_VECTOR:
4388         case SS_VECTOR:
4389         case GP_VECTOR:
4390         case MF_VECTOR:
4391                 return true;
4392         break;
4393         }
4394         return false;
4395 }
4396
4397 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4398                                   int vec, u32 err_code)
4399 {
4400         /*
4401          * Instruction with address size override prefix opcode 0x67
4402          * Cause the #SS fault with 0 error code in VM86 mode.
4403          */
4404         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4405                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4406                         if (vcpu->arch.halt_request) {
4407                                 vcpu->arch.halt_request = 0;
4408                                 return kvm_emulate_halt(vcpu);
4409                         }
4410                         return 1;
4411                 }
4412                 return 0;
4413         }
4414
4415         /*
4416          * Forward all other exceptions that are valid in real mode.
4417          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4418          *        the required debugging infrastructure rework.
4419          */
4420         kvm_queue_exception(vcpu, vec);
4421         return 1;
4422 }
4423
4424 /*
4425  * Trigger machine check on the host. We assume all the MSRs are already set up
4426  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4427  * We pass a fake environment to the machine check handler because we want
4428  * the guest to be always treated like user space, no matter what context
4429  * it used internally.
4430  */
4431 static void kvm_machine_check(void)
4432 {
4433 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4434         struct pt_regs regs = {
4435                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4436                 .flags = X86_EFLAGS_IF,
4437         };
4438
4439         do_machine_check(&regs, 0);
4440 #endif
4441 }
4442
4443 static int handle_machine_check(struct kvm_vcpu *vcpu)
4444 {
4445         /* already handled by vcpu_run */
4446         return 1;
4447 }
4448
4449 static int handle_exception(struct kvm_vcpu *vcpu)
4450 {
4451         struct vcpu_vmx *vmx = to_vmx(vcpu);
4452         struct kvm_run *kvm_run = vcpu->run;
4453         u32 intr_info, ex_no, error_code;
4454         unsigned long cr2, rip, dr6;
4455         u32 vect_info;
4456         enum emulation_result er;
4457
4458         vect_info = vmx->idt_vectoring_info;
4459         intr_info = vmx->exit_intr_info;
4460
4461         if (is_machine_check(intr_info))
4462                 return handle_machine_check(vcpu);
4463
4464         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4465                 return 1;  /* already handled by vmx_vcpu_run() */
4466
4467         if (is_no_device(intr_info)) {
4468                 vmx_fpu_activate(vcpu);
4469                 return 1;
4470         }
4471
4472         if (is_invalid_opcode(intr_info)) {
4473                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4474                 if (er != EMULATE_DONE)
4475                         kvm_queue_exception(vcpu, UD_VECTOR);
4476                 return 1;
4477         }
4478
4479         error_code = 0;
4480         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4481                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4482
4483         /*
4484          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4485          * MMIO, it is better to report an internal error.
4486          * See the comments in vmx_handle_exit.
4487          */
4488         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4489             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4490                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4491                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4492                 vcpu->run->internal.ndata = 2;
4493                 vcpu->run->internal.data[0] = vect_info;
4494                 vcpu->run->internal.data[1] = intr_info;
4495                 return 0;
4496         }
4497
4498         if (is_page_fault(intr_info)) {
4499                 /* EPT won't cause page fault directly */
4500                 BUG_ON(enable_ept);
4501                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4502                 trace_kvm_page_fault(cr2, error_code);
4503
4504                 if (kvm_event_needs_reinjection(vcpu))
4505                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4506                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4507         }
4508
4509         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4510
4511         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4512                 return handle_rmode_exception(vcpu, ex_no, error_code);
4513
4514         switch (ex_no) {
4515         case DB_VECTOR:
4516                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4517                 if (!(vcpu->guest_debug &
4518                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4519                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4520                         kvm_queue_exception(vcpu, DB_VECTOR);
4521                         return 1;
4522                 }
4523                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4524                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4525                 /* fall through */
4526         case BP_VECTOR:
4527                 /*
4528                  * Update instruction length as we may reinject #BP from
4529                  * user space while in guest debugging mode. Reading it for
4530                  * #DB as well causes no harm, it is not used in that case.
4531                  */
4532                 vmx->vcpu.arch.event_exit_inst_len =
4533                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4534                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4535                 rip = kvm_rip_read(vcpu);
4536                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4537                 kvm_run->debug.arch.exception = ex_no;
4538                 break;
4539         default:
4540                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4541                 kvm_run->ex.exception = ex_no;
4542                 kvm_run->ex.error_code = error_code;
4543                 break;
4544         }
4545         return 0;
4546 }
4547
4548 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4549 {
4550         ++vcpu->stat.irq_exits;
4551         return 1;
4552 }
4553
4554 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4555 {
4556         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4557         return 0;
4558 }
4559
4560 static int handle_io(struct kvm_vcpu *vcpu)
4561 {
4562         unsigned long exit_qualification;
4563         int size, in, string;
4564         unsigned port;
4565
4566         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4567         string = (exit_qualification & 16) != 0;
4568         in = (exit_qualification & 8) != 0;
4569
4570         ++vcpu->stat.io_exits;
4571
4572         if (string || in)
4573                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4574
4575         port = exit_qualification >> 16;
4576         size = (exit_qualification & 7) + 1;
4577         skip_emulated_instruction(vcpu);
4578
4579         return kvm_fast_pio_out(vcpu, size, port);
4580 }
4581
4582 static void
4583 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4584 {
4585         /*
4586          * Patch in the VMCALL instruction:
4587          */
4588         hypercall[0] = 0x0f;
4589         hypercall[1] = 0x01;
4590         hypercall[2] = 0xc1;
4591 }
4592
4593 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4594 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4595 {
4596         if (is_guest_mode(vcpu)) {
4597                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4598                 unsigned long orig_val = val;
4599
4600                 /*
4601                  * We get here when L2 changed cr0 in a way that did not change
4602                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4603                  * but did change L0 shadowed bits. So we first calculate the
4604                  * effective cr0 value that L1 would like to write into the
4605                  * hardware. It consists of the L2-owned bits from the new
4606                  * value combined with the L1-owned bits from L1's guest_cr0.
4607                  */
4608                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4609                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4610
4611                 /* TODO: will have to take unrestricted guest mode into
4612                  * account */
4613                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4614                         return 1;
4615
4616                 if (kvm_set_cr0(vcpu, val))
4617                         return 1;
4618                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4619                 return 0;
4620         } else {
4621                 if (to_vmx(vcpu)->nested.vmxon &&
4622                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4623                         return 1;
4624                 return kvm_set_cr0(vcpu, val);
4625         }
4626 }
4627
4628 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4629 {
4630         if (is_guest_mode(vcpu)) {
4631                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4632                 unsigned long orig_val = val;
4633
4634                 /* analogously to handle_set_cr0 */
4635                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4636                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4637                 if (kvm_set_cr4(vcpu, val))
4638                         return 1;
4639                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4640                 return 0;
4641         } else
4642                 return kvm_set_cr4(vcpu, val);
4643 }
4644
4645 /* called to set cr0 as approriate for clts instruction exit. */
4646 static void handle_clts(struct kvm_vcpu *vcpu)
4647 {
4648         if (is_guest_mode(vcpu)) {
4649                 /*
4650                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4651                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4652                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4653                  */
4654                 vmcs_writel(CR0_READ_SHADOW,
4655                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4656                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4657         } else
4658                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4659 }
4660
4661 static int handle_cr(struct kvm_vcpu *vcpu)
4662 {
4663         unsigned long exit_qualification, val;
4664         int cr;
4665         int reg;
4666         int err;
4667
4668         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4669         cr = exit_qualification & 15;
4670         reg = (exit_qualification >> 8) & 15;
4671         switch ((exit_qualification >> 4) & 3) {
4672         case 0: /* mov to cr */
4673                 val = kvm_register_read(vcpu, reg);
4674                 trace_kvm_cr_write(cr, val);
4675                 switch (cr) {
4676                 case 0:
4677                         err = handle_set_cr0(vcpu, val);
4678                         kvm_complete_insn_gp(vcpu, err);
4679                         return 1;
4680                 case 3:
4681                         err = kvm_set_cr3(vcpu, val);
4682                         kvm_complete_insn_gp(vcpu, err);
4683                         return 1;
4684                 case 4:
4685                         err = handle_set_cr4(vcpu, val);
4686                         kvm_complete_insn_gp(vcpu, err);
4687                         return 1;
4688                 case 8: {
4689                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4690                                 u8 cr8 = kvm_register_read(vcpu, reg);
4691                                 err = kvm_set_cr8(vcpu, cr8);
4692                                 kvm_complete_insn_gp(vcpu, err);
4693                                 if (irqchip_in_kernel(vcpu->kvm))
4694                                         return 1;
4695                                 if (cr8_prev <= cr8)
4696                                         return 1;
4697                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4698                                 return 0;
4699                         }
4700                 }
4701                 break;
4702         case 2: /* clts */
4703                 handle_clts(vcpu);
4704                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4705                 skip_emulated_instruction(vcpu);
4706                 vmx_fpu_activate(vcpu);
4707                 return 1;
4708         case 1: /*mov from cr*/
4709                 switch (cr) {
4710                 case 3:
4711                         val = kvm_read_cr3(vcpu);
4712                         kvm_register_write(vcpu, reg, val);
4713                         trace_kvm_cr_read(cr, val);
4714                         skip_emulated_instruction(vcpu);
4715                         return 1;
4716                 case 8:
4717                         val = kvm_get_cr8(vcpu);
4718                         kvm_register_write(vcpu, reg, val);
4719                         trace_kvm_cr_read(cr, val);
4720                         skip_emulated_instruction(vcpu);
4721                         return 1;
4722                 }
4723                 break;
4724         case 3: /* lmsw */
4725                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4726                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4727                 kvm_lmsw(vcpu, val);
4728
4729                 skip_emulated_instruction(vcpu);
4730                 return 1;
4731         default:
4732                 break;
4733         }
4734         vcpu->run->exit_reason = 0;
4735         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4736                (int)(exit_qualification >> 4) & 3, cr);
4737         return 0;
4738 }
4739
4740 static int handle_dr(struct kvm_vcpu *vcpu)
4741 {
4742         unsigned long exit_qualification;
4743         int dr, reg;
4744
4745         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4746         if (!kvm_require_cpl(vcpu, 0))
4747                 return 1;
4748         dr = vmcs_readl(GUEST_DR7);
4749         if (dr & DR7_GD) {
4750                 /*
4751                  * As the vm-exit takes precedence over the debug trap, we
4752                  * need to emulate the latter, either for the host or the
4753                  * guest debugging itself.
4754                  */
4755                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4756                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4757                         vcpu->run->debug.arch.dr7 = dr;
4758                         vcpu->run->debug.arch.pc =
4759                                 vmcs_readl(GUEST_CS_BASE) +
4760                                 vmcs_readl(GUEST_RIP);
4761                         vcpu->run->debug.arch.exception = DB_VECTOR;
4762                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4763                         return 0;
4764                 } else {
4765                         vcpu->arch.dr7 &= ~DR7_GD;
4766                         vcpu->arch.dr6 |= DR6_BD;
4767                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4768                         kvm_queue_exception(vcpu, DB_VECTOR);
4769                         return 1;
4770                 }
4771         }
4772
4773         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4774         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4775         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4776         if (exit_qualification & TYPE_MOV_FROM_DR) {
4777                 unsigned long val;
4778                 if (!kvm_get_dr(vcpu, dr, &val))
4779                         kvm_register_write(vcpu, reg, val);
4780         } else
4781                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4782         skip_emulated_instruction(vcpu);
4783         return 1;
4784 }
4785
4786 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4787 {
4788         vmcs_writel(GUEST_DR7, val);
4789 }
4790
4791 static int handle_cpuid(struct kvm_vcpu *vcpu)
4792 {
4793         kvm_emulate_cpuid(vcpu);
4794         return 1;
4795 }
4796
4797 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4798 {
4799         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4800         u64 data;
4801
4802         if (vmx_get_msr(vcpu, ecx, &data)) {
4803                 trace_kvm_msr_read_ex(ecx);
4804                 kvm_inject_gp(vcpu, 0);
4805                 return 1;
4806         }
4807
4808         trace_kvm_msr_read(ecx, data);
4809
4810         /* FIXME: handling of bits 32:63 of rax, rdx */
4811         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4812         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4813         skip_emulated_instruction(vcpu);
4814         return 1;
4815 }
4816
4817 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4818 {
4819         struct msr_data msr;
4820         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4821         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4822                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4823
4824         msr.data = data;
4825         msr.index = ecx;
4826         msr.host_initiated = false;
4827         if (vmx_set_msr(vcpu, &msr) != 0) {
4828                 trace_kvm_msr_write_ex(ecx, data);
4829                 kvm_inject_gp(vcpu, 0);
4830                 return 1;
4831         }
4832
4833         trace_kvm_msr_write(ecx, data);
4834         skip_emulated_instruction(vcpu);
4835         return 1;
4836 }
4837
4838 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4839 {
4840         kvm_make_request(KVM_REQ_EVENT, vcpu);
4841         return 1;
4842 }
4843
4844 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4845 {
4846         u32 cpu_based_vm_exec_control;
4847
4848         /* clear pending irq */
4849         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4850         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4851         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4852
4853         kvm_make_request(KVM_REQ_EVENT, vcpu);
4854
4855         ++vcpu->stat.irq_window_exits;
4856
4857         /*
4858          * If the user space waits to inject interrupts, exit as soon as
4859          * possible
4860          */
4861         if (!irqchip_in_kernel(vcpu->kvm) &&
4862             vcpu->run->request_interrupt_window &&
4863             !kvm_cpu_has_interrupt(vcpu)) {
4864                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4865                 return 0;
4866         }
4867         return 1;
4868 }
4869
4870 static int handle_halt(struct kvm_vcpu *vcpu)
4871 {
4872         skip_emulated_instruction(vcpu);
4873         return kvm_emulate_halt(vcpu);
4874 }
4875
4876 static int handle_vmcall(struct kvm_vcpu *vcpu)
4877 {
4878         skip_emulated_instruction(vcpu);
4879         kvm_emulate_hypercall(vcpu);
4880         return 1;
4881 }
4882
4883 static int handle_invd(struct kvm_vcpu *vcpu)
4884 {
4885         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4886 }
4887
4888 static int handle_invlpg(struct kvm_vcpu *vcpu)
4889 {
4890         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4891
4892         kvm_mmu_invlpg(vcpu, exit_qualification);
4893         skip_emulated_instruction(vcpu);
4894         return 1;
4895 }
4896
4897 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4898 {
4899         int err;
4900
4901         err = kvm_rdpmc(vcpu);
4902         kvm_complete_insn_gp(vcpu, err);
4903
4904         return 1;
4905 }
4906
4907 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4908 {
4909         skip_emulated_instruction(vcpu);
4910         kvm_emulate_wbinvd(vcpu);
4911         return 1;
4912 }
4913
4914 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4915 {
4916         u64 new_bv = kvm_read_edx_eax(vcpu);
4917         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4918
4919         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4920                 skip_emulated_instruction(vcpu);
4921         return 1;
4922 }
4923
4924 static int handle_apic_access(struct kvm_vcpu *vcpu)
4925 {
4926         if (likely(fasteoi)) {
4927                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4928                 int access_type, offset;
4929
4930                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4931                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4932                 /*
4933                  * Sane guest uses MOV to write EOI, with written value
4934                  * not cared. So make a short-circuit here by avoiding
4935                  * heavy instruction emulation.
4936                  */
4937                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4938                     (offset == APIC_EOI)) {
4939                         kvm_lapic_set_eoi(vcpu);
4940                         skip_emulated_instruction(vcpu);
4941                         return 1;
4942                 }
4943         }
4944         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4945 }
4946
4947 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4948 {
4949         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4950         int vector = exit_qualification & 0xff;
4951
4952         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4953         kvm_apic_set_eoi_accelerated(vcpu, vector);
4954         return 1;
4955 }
4956
4957 static int handle_apic_write(struct kvm_vcpu *vcpu)
4958 {
4959         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4960         u32 offset = exit_qualification & 0xfff;
4961
4962         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4963         kvm_apic_write_nodecode(vcpu, offset);
4964         return 1;
4965 }
4966
4967 static int handle_task_switch(struct kvm_vcpu *vcpu)
4968 {
4969         struct vcpu_vmx *vmx = to_vmx(vcpu);
4970         unsigned long exit_qualification;
4971         bool has_error_code = false;
4972         u32 error_code = 0;
4973         u16 tss_selector;
4974         int reason, type, idt_v, idt_index;
4975
4976         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4977         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4978         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4979
4980         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4981
4982         reason = (u32)exit_qualification >> 30;
4983         if (reason == TASK_SWITCH_GATE && idt_v) {
4984                 switch (type) {
4985                 case INTR_TYPE_NMI_INTR:
4986                         vcpu->arch.nmi_injected = false;
4987                         vmx_set_nmi_mask(vcpu, true);
4988                         break;
4989                 case INTR_TYPE_EXT_INTR:
4990                 case INTR_TYPE_SOFT_INTR:
4991                         kvm_clear_interrupt_queue(vcpu);
4992                         break;
4993                 case INTR_TYPE_HARD_EXCEPTION:
4994                         if (vmx->idt_vectoring_info &
4995                             VECTORING_INFO_DELIVER_CODE_MASK) {
4996                                 has_error_code = true;
4997                                 error_code =
4998                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4999                         }
5000                         /* fall through */
5001                 case INTR_TYPE_SOFT_EXCEPTION:
5002                         kvm_clear_exception_queue(vcpu);
5003                         break;
5004                 default:
5005                         break;
5006                 }
5007         }
5008         tss_selector = exit_qualification;
5009
5010         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5011                        type != INTR_TYPE_EXT_INTR &&
5012                        type != INTR_TYPE_NMI_INTR))
5013                 skip_emulated_instruction(vcpu);
5014
5015         if (kvm_task_switch(vcpu, tss_selector,
5016                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5017                             has_error_code, error_code) == EMULATE_FAIL) {
5018                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5019                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5020                 vcpu->run->internal.ndata = 0;
5021                 return 0;
5022         }
5023
5024         /* clear all local breakpoint enable flags */
5025         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5026
5027         /*
5028          * TODO: What about debug traps on tss switch?
5029          *       Are we supposed to inject them and update dr6?
5030          */
5031
5032         return 1;
5033 }
5034
5035 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5036 {
5037         unsigned long exit_qualification;
5038         gpa_t gpa;
5039         u32 error_code;
5040         int gla_validity;
5041
5042         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5043
5044         gla_validity = (exit_qualification >> 7) & 0x3;
5045         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5046                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5047                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5048                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5049                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5050                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5051                         (long unsigned int)exit_qualification);
5052                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5053                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5054                 return 0;
5055         }
5056
5057         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5058         trace_kvm_page_fault(gpa, exit_qualification);
5059
5060         /* It is a write fault? */
5061         error_code = exit_qualification & (1U << 1);
5062         /* ept page table is present? */
5063         error_code |= (exit_qualification >> 3) & 0x1;
5064
5065         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5066 }
5067
5068 static u64 ept_rsvd_mask(u64 spte, int level)
5069 {
5070         int i;
5071         u64 mask = 0;
5072
5073         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5074                 mask |= (1ULL << i);
5075
5076         if (level > 2)
5077                 /* bits 7:3 reserved */
5078                 mask |= 0xf8;
5079         else if (level == 2) {
5080                 if (spte & (1ULL << 7))
5081                         /* 2MB ref, bits 20:12 reserved */
5082                         mask |= 0x1ff000;
5083                 else
5084                         /* bits 6:3 reserved */
5085                         mask |= 0x78;
5086         }
5087
5088         return mask;
5089 }
5090
5091 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5092                                        int level)
5093 {
5094         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5095
5096         /* 010b (write-only) */
5097         WARN_ON((spte & 0x7) == 0x2);
5098
5099         /* 110b (write/execute) */
5100         WARN_ON((spte & 0x7) == 0x6);
5101
5102         /* 100b (execute-only) and value not supported by logical processor */
5103         if (!cpu_has_vmx_ept_execute_only())
5104                 WARN_ON((spte & 0x7) == 0x4);
5105
5106         /* not 000b */
5107         if ((spte & 0x7)) {
5108                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5109
5110                 if (rsvd_bits != 0) {
5111                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5112                                          __func__, rsvd_bits);
5113                         WARN_ON(1);
5114                 }
5115
5116                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5117                         u64 ept_mem_type = (spte & 0x38) >> 3;
5118
5119                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5120                             ept_mem_type == 7) {
5121                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5122                                                 __func__, ept_mem_type);
5123                                 WARN_ON(1);
5124                         }
5125                 }
5126         }
5127 }
5128
5129 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5130 {
5131         u64 sptes[4];
5132         int nr_sptes, i, ret;
5133         gpa_t gpa;
5134
5135         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5136
5137         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5138         if (likely(ret == 1))
5139                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5140                                               EMULATE_DONE;
5141         if (unlikely(!ret))
5142                 return 1;
5143
5144         /* It is the real ept misconfig */
5145         printk(KERN_ERR "EPT: Misconfiguration.\n");
5146         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5147
5148         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5149
5150         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5151                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5152
5153         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5154         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5155
5156         return 0;
5157 }
5158
5159 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5160 {
5161         u32 cpu_based_vm_exec_control;
5162
5163         /* clear pending NMI */
5164         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5165         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5166         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5167         ++vcpu->stat.nmi_window_exits;
5168         kvm_make_request(KVM_REQ_EVENT, vcpu);
5169
5170         return 1;
5171 }
5172
5173 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5174 {
5175         struct vcpu_vmx *vmx = to_vmx(vcpu);
5176         enum emulation_result err = EMULATE_DONE;
5177         int ret = 1;
5178         u32 cpu_exec_ctrl;
5179         bool intr_window_requested;
5180         unsigned count = 130;
5181
5182         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5183         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5184
5185         while (!guest_state_valid(vcpu) && count-- != 0) {
5186                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5187                         return handle_interrupt_window(&vmx->vcpu);
5188
5189                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5190                         return 1;
5191
5192                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5193
5194                 if (err == EMULATE_DO_MMIO) {
5195                         ret = 0;
5196                         goto out;
5197                 }
5198
5199                 if (err != EMULATE_DONE) {
5200                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5201                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5202                         vcpu->run->internal.ndata = 0;
5203                         return 0;
5204                 }
5205
5206                 if (signal_pending(current))
5207                         goto out;
5208                 if (need_resched())
5209                         schedule();
5210         }
5211
5212         vmx->emulation_required = emulation_required(vcpu);
5213 out:
5214         return ret;
5215 }
5216
5217 /*
5218  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5219  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5220  */
5221 static int handle_pause(struct kvm_vcpu *vcpu)
5222 {
5223         skip_emulated_instruction(vcpu);
5224         kvm_vcpu_on_spin(vcpu);
5225
5226         return 1;
5227 }
5228
5229 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5230 {
5231         kvm_queue_exception(vcpu, UD_VECTOR);
5232         return 1;
5233 }
5234
5235 /*
5236  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5237  * We could reuse a single VMCS for all the L2 guests, but we also want the
5238  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5239  * allows keeping them loaded on the processor, and in the future will allow
5240  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5241  * every entry if they never change.
5242  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5243  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5244  *
5245  * The following functions allocate and free a vmcs02 in this pool.
5246  */
5247
5248 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5249 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5250 {
5251         struct vmcs02_list *item;
5252         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5253                 if (item->vmptr == vmx->nested.current_vmptr) {
5254                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5255                         return &item->vmcs02;
5256                 }
5257
5258         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5259                 /* Recycle the least recently used VMCS. */
5260                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5261                         struct vmcs02_list, list);
5262                 item->vmptr = vmx->nested.current_vmptr;
5263                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5264                 return &item->vmcs02;
5265         }
5266
5267         /* Create a new VMCS */
5268         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5269         if (!item)
5270                 return NULL;
5271         item->vmcs02.vmcs = alloc_vmcs();
5272         if (!item->vmcs02.vmcs) {
5273                 kfree(item);
5274                 return NULL;
5275         }
5276         loaded_vmcs_init(&item->vmcs02);
5277         item->vmptr = vmx->nested.current_vmptr;
5278         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5279         vmx->nested.vmcs02_num++;
5280         return &item->vmcs02;
5281 }
5282
5283 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5284 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5285 {
5286         struct vmcs02_list *item;
5287         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5288                 if (item->vmptr == vmptr) {
5289                         free_loaded_vmcs(&item->vmcs02);
5290                         list_del(&item->list);
5291                         kfree(item);
5292                         vmx->nested.vmcs02_num--;
5293                         return;
5294                 }
5295 }
5296
5297 /*
5298  * Free all VMCSs saved for this vcpu, except the one pointed by
5299  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5300  * currently used, if running L2), and vmcs01 when running L2.
5301  */
5302 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5303 {
5304         struct vmcs02_list *item, *n;
5305         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5306                 if (vmx->loaded_vmcs != &item->vmcs02)
5307                         free_loaded_vmcs(&item->vmcs02);
5308                 list_del(&item->list);
5309                 kfree(item);
5310         }
5311         vmx->nested.vmcs02_num = 0;
5312
5313         if (vmx->loaded_vmcs != &vmx->vmcs01)
5314                 free_loaded_vmcs(&vmx->vmcs01);
5315 }
5316
5317 /*
5318  * Emulate the VMXON instruction.
5319  * Currently, we just remember that VMX is active, and do not save or even
5320  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5321  * do not currently need to store anything in that guest-allocated memory
5322  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5323  * argument is different from the VMXON pointer (which the spec says they do).
5324  */
5325 static int handle_vmon(struct kvm_vcpu *vcpu)
5326 {
5327         struct kvm_segment cs;
5328         struct vcpu_vmx *vmx = to_vmx(vcpu);
5329
5330         /* The Intel VMX Instruction Reference lists a bunch of bits that
5331          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5332          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5333          * Otherwise, we should fail with #UD. We test these now:
5334          */
5335         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5336             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5337             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5338                 kvm_queue_exception(vcpu, UD_VECTOR);
5339                 return 1;
5340         }
5341
5342         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5343         if (is_long_mode(vcpu) && !cs.l) {
5344                 kvm_queue_exception(vcpu, UD_VECTOR);
5345                 return 1;
5346         }
5347
5348         if (vmx_get_cpl(vcpu)) {
5349                 kvm_inject_gp(vcpu, 0);
5350                 return 1;
5351         }
5352
5353         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5354         vmx->nested.vmcs02_num = 0;
5355
5356         vmx->nested.vmxon = true;
5357
5358         skip_emulated_instruction(vcpu);
5359         return 1;
5360 }
5361
5362 /*
5363  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5364  * for running VMX instructions (except VMXON, whose prerequisites are
5365  * slightly different). It also specifies what exception to inject otherwise.
5366  */
5367 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5368 {
5369         struct kvm_segment cs;
5370         struct vcpu_vmx *vmx = to_vmx(vcpu);
5371
5372         if (!vmx->nested.vmxon) {
5373                 kvm_queue_exception(vcpu, UD_VECTOR);
5374                 return 0;
5375         }
5376
5377         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5378         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5379             (is_long_mode(vcpu) && !cs.l)) {
5380                 kvm_queue_exception(vcpu, UD_VECTOR);
5381                 return 0;
5382         }
5383
5384         if (vmx_get_cpl(vcpu)) {
5385                 kvm_inject_gp(vcpu, 0);
5386                 return 0;
5387         }
5388
5389         return 1;
5390 }
5391
5392 /*
5393  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5394  * just stops using VMX.
5395  */
5396 static void free_nested(struct vcpu_vmx *vmx)
5397 {
5398         if (!vmx->nested.vmxon)
5399                 return;
5400         vmx->nested.vmxon = false;
5401         if (vmx->nested.current_vmptr != -1ull) {
5402                 kunmap(vmx->nested.current_vmcs12_page);
5403                 nested_release_page(vmx->nested.current_vmcs12_page);
5404                 vmx->nested.current_vmptr = -1ull;
5405                 vmx->nested.current_vmcs12 = NULL;
5406         }
5407         /* Unpin physical memory we referred to in current vmcs02 */
5408         if (vmx->nested.apic_access_page) {
5409                 nested_release_page(vmx->nested.apic_access_page);
5410                 vmx->nested.apic_access_page = 0;
5411         }
5412
5413         nested_free_all_saved_vmcss(vmx);
5414 }
5415
5416 /* Emulate the VMXOFF instruction */
5417 static int handle_vmoff(struct kvm_vcpu *vcpu)
5418 {
5419         if (!nested_vmx_check_permission(vcpu))
5420                 return 1;
5421         free_nested(to_vmx(vcpu));
5422         skip_emulated_instruction(vcpu);
5423         return 1;
5424 }
5425
5426 /*
5427  * Decode the memory-address operand of a vmx instruction, as recorded on an
5428  * exit caused by such an instruction (run by a guest hypervisor).
5429  * On success, returns 0. When the operand is invalid, returns 1 and throws
5430  * #UD or #GP.
5431  */
5432 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5433                                  unsigned long exit_qualification,
5434                                  u32 vmx_instruction_info, gva_t *ret)
5435 {
5436         /*
5437          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5438          * Execution", on an exit, vmx_instruction_info holds most of the
5439          * addressing components of the operand. Only the displacement part
5440          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5441          * For how an actual address is calculated from all these components,
5442          * refer to Vol. 1, "Operand Addressing".
5443          */
5444         int  scaling = vmx_instruction_info & 3;
5445         int  addr_size = (vmx_instruction_info >> 7) & 7;
5446         bool is_reg = vmx_instruction_info & (1u << 10);
5447         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5448         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5449         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5450         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5451         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5452
5453         if (is_reg) {
5454                 kvm_queue_exception(vcpu, UD_VECTOR);
5455                 return 1;
5456         }
5457
5458         /* Addr = segment_base + offset */
5459         /* offset = base + [index * scale] + displacement */
5460         *ret = vmx_get_segment_base(vcpu, seg_reg);
5461         if (base_is_valid)
5462                 *ret += kvm_register_read(vcpu, base_reg);
5463         if (index_is_valid)
5464                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5465         *ret += exit_qualification; /* holds the displacement */
5466
5467         if (addr_size == 1) /* 32 bit */
5468                 *ret &= 0xffffffff;
5469
5470         /*
5471          * TODO: throw #GP (and return 1) in various cases that the VM*
5472          * instructions require it - e.g., offset beyond segment limit,
5473          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5474          * address, and so on. Currently these are not checked.
5475          */
5476         return 0;
5477 }
5478
5479 /*
5480  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5481  * set the success or error code of an emulated VMX instruction, as specified
5482  * by Vol 2B, VMX Instruction Reference, "Conventions".
5483  */
5484 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5485 {
5486         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5487                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5488                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5489 }
5490
5491 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5492 {
5493         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5494                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5495                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5496                         | X86_EFLAGS_CF);
5497 }
5498
5499 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5500                                         u32 vm_instruction_error)
5501 {
5502         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5503                 /*
5504                  * failValid writes the error number to the current VMCS, which
5505                  * can't be done there isn't a current VMCS.
5506                  */
5507                 nested_vmx_failInvalid(vcpu);
5508                 return;
5509         }
5510         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5511                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5512                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5513                         | X86_EFLAGS_ZF);
5514         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5515 }
5516
5517 /* Emulate the VMCLEAR instruction */
5518 static int handle_vmclear(struct kvm_vcpu *vcpu)
5519 {
5520         struct vcpu_vmx *vmx = to_vmx(vcpu);
5521         gva_t gva;
5522         gpa_t vmptr;
5523         struct vmcs12 *vmcs12;
5524         struct page *page;
5525         struct x86_exception e;
5526
5527         if (!nested_vmx_check_permission(vcpu))
5528                 return 1;
5529
5530         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5531                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5532                 return 1;
5533
5534         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5535                                 sizeof(vmptr), &e)) {
5536                 kvm_inject_page_fault(vcpu, &e);
5537                 return 1;
5538         }
5539
5540         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5541                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5542                 skip_emulated_instruction(vcpu);
5543                 return 1;
5544         }
5545
5546         if (vmptr == vmx->nested.current_vmptr) {
5547                 kunmap(vmx->nested.current_vmcs12_page);
5548                 nested_release_page(vmx->nested.current_vmcs12_page);
5549                 vmx->nested.current_vmptr = -1ull;
5550                 vmx->nested.current_vmcs12 = NULL;
5551         }
5552
5553         page = nested_get_page(vcpu, vmptr);
5554         if (page == NULL) {
5555                 /*
5556                  * For accurate processor emulation, VMCLEAR beyond available
5557                  * physical memory should do nothing at all. However, it is
5558                  * possible that a nested vmx bug, not a guest hypervisor bug,
5559                  * resulted in this case, so let's shut down before doing any
5560                  * more damage:
5561                  */
5562                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5563                 return 1;
5564         }
5565         vmcs12 = kmap(page);
5566         vmcs12->launch_state = 0;
5567         kunmap(page);
5568         nested_release_page(page);
5569
5570         nested_free_vmcs02(vmx, vmptr);
5571
5572         skip_emulated_instruction(vcpu);
5573         nested_vmx_succeed(vcpu);
5574         return 1;
5575 }
5576
5577 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5578
5579 /* Emulate the VMLAUNCH instruction */
5580 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5581 {
5582         return nested_vmx_run(vcpu, true);
5583 }
5584
5585 /* Emulate the VMRESUME instruction */
5586 static int handle_vmresume(struct kvm_vcpu *vcpu)
5587 {
5588
5589         return nested_vmx_run(vcpu, false);
5590 }
5591
5592 enum vmcs_field_type {
5593         VMCS_FIELD_TYPE_U16 = 0,
5594         VMCS_FIELD_TYPE_U64 = 1,
5595         VMCS_FIELD_TYPE_U32 = 2,
5596         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5597 };
5598
5599 static inline int vmcs_field_type(unsigned long field)
5600 {
5601         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5602                 return VMCS_FIELD_TYPE_U32;
5603         return (field >> 13) & 0x3 ;
5604 }
5605
5606 static inline int vmcs_field_readonly(unsigned long field)
5607 {
5608         return (((field >> 10) & 0x3) == 1);
5609 }
5610
5611 /*
5612  * Read a vmcs12 field. Since these can have varying lengths and we return
5613  * one type, we chose the biggest type (u64) and zero-extend the return value
5614  * to that size. Note that the caller, handle_vmread, might need to use only
5615  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5616  * 64-bit fields are to be returned).
5617  */
5618 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5619                                         unsigned long field, u64 *ret)
5620 {
5621         short offset = vmcs_field_to_offset(field);
5622         char *p;
5623
5624         if (offset < 0)
5625                 return 0;
5626
5627         p = ((char *)(get_vmcs12(vcpu))) + offset;
5628
5629         switch (vmcs_field_type(field)) {
5630         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5631                 *ret = *((natural_width *)p);
5632                 return 1;
5633         case VMCS_FIELD_TYPE_U16:
5634                 *ret = *((u16 *)p);
5635                 return 1;
5636         case VMCS_FIELD_TYPE_U32:
5637                 *ret = *((u32 *)p);
5638                 return 1;
5639         case VMCS_FIELD_TYPE_U64:
5640                 *ret = *((u64 *)p);
5641                 return 1;
5642         default:
5643                 return 0; /* can never happen. */
5644         }
5645 }
5646
5647 /*
5648  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5649  * used before) all generate the same failure when it is missing.
5650  */
5651 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5652 {
5653         struct vcpu_vmx *vmx = to_vmx(vcpu);
5654         if (vmx->nested.current_vmptr == -1ull) {
5655                 nested_vmx_failInvalid(vcpu);
5656                 skip_emulated_instruction(vcpu);
5657                 return 0;
5658         }
5659         return 1;
5660 }
5661
5662 static int handle_vmread(struct kvm_vcpu *vcpu)
5663 {
5664         unsigned long field;
5665         u64 field_value;
5666         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5667         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5668         gva_t gva = 0;
5669
5670         if (!nested_vmx_check_permission(vcpu) ||
5671             !nested_vmx_check_vmcs12(vcpu))
5672                 return 1;
5673
5674         /* Decode instruction info and find the field to read */
5675         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5676         /* Read the field, zero-extended to a u64 field_value */
5677         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5678                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5679                 skip_emulated_instruction(vcpu);
5680                 return 1;
5681         }
5682         /*
5683          * Now copy part of this value to register or memory, as requested.
5684          * Note that the number of bits actually copied is 32 or 64 depending
5685          * on the guest's mode (32 or 64 bit), not on the given field's length.
5686          */
5687         if (vmx_instruction_info & (1u << 10)) {
5688                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5689                         field_value);
5690         } else {
5691                 if (get_vmx_mem_address(vcpu, exit_qualification,
5692                                 vmx_instruction_info, &gva))
5693                         return 1;
5694                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5695                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5696                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5697         }
5698
5699         nested_vmx_succeed(vcpu);
5700         skip_emulated_instruction(vcpu);
5701         return 1;
5702 }
5703
5704
5705 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5706 {
5707         unsigned long field;
5708         gva_t gva;
5709         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5710         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5711         char *p;
5712         short offset;
5713         /* The value to write might be 32 or 64 bits, depending on L1's long
5714          * mode, and eventually we need to write that into a field of several
5715          * possible lengths. The code below first zero-extends the value to 64
5716          * bit (field_value), and then copies only the approriate number of
5717          * bits into the vmcs12 field.
5718          */
5719         u64 field_value = 0;
5720         struct x86_exception e;
5721
5722         if (!nested_vmx_check_permission(vcpu) ||
5723             !nested_vmx_check_vmcs12(vcpu))
5724                 return 1;
5725
5726         if (vmx_instruction_info & (1u << 10))
5727                 field_value = kvm_register_read(vcpu,
5728                         (((vmx_instruction_info) >> 3) & 0xf));
5729         else {
5730                 if (get_vmx_mem_address(vcpu, exit_qualification,
5731                                 vmx_instruction_info, &gva))
5732                         return 1;
5733                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5734                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5735                         kvm_inject_page_fault(vcpu, &e);
5736                         return 1;
5737                 }
5738         }
5739
5740
5741         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5742         if (vmcs_field_readonly(field)) {
5743                 nested_vmx_failValid(vcpu,
5744                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5745                 skip_emulated_instruction(vcpu);
5746                 return 1;
5747         }
5748
5749         offset = vmcs_field_to_offset(field);
5750         if (offset < 0) {
5751                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5752                 skip_emulated_instruction(vcpu);
5753                 return 1;
5754         }
5755         p = ((char *) get_vmcs12(vcpu)) + offset;
5756
5757         switch (vmcs_field_type(field)) {
5758         case VMCS_FIELD_TYPE_U16:
5759                 *(u16 *)p = field_value;
5760                 break;
5761         case VMCS_FIELD_TYPE_U32:
5762                 *(u32 *)p = field_value;
5763                 break;
5764         case VMCS_FIELD_TYPE_U64:
5765                 *(u64 *)p = field_value;
5766                 break;
5767         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5768                 *(natural_width *)p = field_value;
5769                 break;
5770         default:
5771                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5772                 skip_emulated_instruction(vcpu);
5773                 return 1;
5774         }
5775
5776         nested_vmx_succeed(vcpu);
5777         skip_emulated_instruction(vcpu);
5778         return 1;
5779 }
5780
5781 /* Emulate the VMPTRLD instruction */
5782 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5783 {
5784         struct vcpu_vmx *vmx = to_vmx(vcpu);
5785         gva_t gva;
5786         gpa_t vmptr;
5787         struct x86_exception e;
5788
5789         if (!nested_vmx_check_permission(vcpu))
5790                 return 1;
5791
5792         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5793                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5794                 return 1;
5795
5796         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5797                                 sizeof(vmptr), &e)) {
5798                 kvm_inject_page_fault(vcpu, &e);
5799                 return 1;
5800         }
5801
5802         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5803                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5804                 skip_emulated_instruction(vcpu);
5805                 return 1;
5806         }
5807
5808         if (vmx->nested.current_vmptr != vmptr) {
5809                 struct vmcs12 *new_vmcs12;
5810                 struct page *page;
5811                 page = nested_get_page(vcpu, vmptr);
5812                 if (page == NULL) {
5813                         nested_vmx_failInvalid(vcpu);
5814                         skip_emulated_instruction(vcpu);
5815                         return 1;
5816                 }
5817                 new_vmcs12 = kmap(page);
5818                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5819                         kunmap(page);
5820                         nested_release_page_clean(page);
5821                         nested_vmx_failValid(vcpu,
5822                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5823                         skip_emulated_instruction(vcpu);
5824                         return 1;
5825                 }
5826                 if (vmx->nested.current_vmptr != -1ull) {
5827                         kunmap(vmx->nested.current_vmcs12_page);
5828                         nested_release_page(vmx->nested.current_vmcs12_page);
5829                 }
5830
5831                 vmx->nested.current_vmptr = vmptr;
5832                 vmx->nested.current_vmcs12 = new_vmcs12;
5833                 vmx->nested.current_vmcs12_page = page;
5834         }
5835
5836         nested_vmx_succeed(vcpu);
5837         skip_emulated_instruction(vcpu);
5838         return 1;
5839 }
5840
5841 /* Emulate the VMPTRST instruction */
5842 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5843 {
5844         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5845         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5846         gva_t vmcs_gva;
5847         struct x86_exception e;
5848
5849         if (!nested_vmx_check_permission(vcpu))
5850                 return 1;
5851
5852         if (get_vmx_mem_address(vcpu, exit_qualification,
5853                         vmx_instruction_info, &vmcs_gva))
5854                 return 1;
5855         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5856         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5857                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5858                                  sizeof(u64), &e)) {
5859                 kvm_inject_page_fault(vcpu, &e);
5860                 return 1;
5861         }
5862         nested_vmx_succeed(vcpu);
5863         skip_emulated_instruction(vcpu);
5864         return 1;
5865 }
5866
5867 /*
5868  * The exit handlers return 1 if the exit was handled fully and guest execution
5869  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5870  * to be done to userspace and return 0.
5871  */
5872 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5873         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5874         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5875         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5876         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5877         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5878         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5879         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5880         [EXIT_REASON_CPUID]                   = handle_cpuid,
5881         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5882         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5883         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5884         [EXIT_REASON_HLT]                     = handle_halt,
5885         [EXIT_REASON_INVD]                    = handle_invd,
5886         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5887         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5888         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5889         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5890         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5891         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5892         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5893         [EXIT_REASON_VMREAD]                  = handle_vmread,
5894         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5895         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5896         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5897         [EXIT_REASON_VMON]                    = handle_vmon,
5898         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5899         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5900         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5901         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5902         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5903         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5904         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5905         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5906         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5907         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5908         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5909         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5910         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5911 };
5912
5913 static const int kvm_vmx_max_exit_handlers =
5914         ARRAY_SIZE(kvm_vmx_exit_handlers);
5915
5916 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5917                                        struct vmcs12 *vmcs12)
5918 {
5919         unsigned long exit_qualification;
5920         gpa_t bitmap, last_bitmap;
5921         unsigned int port;
5922         int size;
5923         u8 b;
5924
5925         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5926                 return 1;
5927
5928         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5929                 return 0;
5930
5931         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5932
5933         port = exit_qualification >> 16;
5934         size = (exit_qualification & 7) + 1;
5935
5936         last_bitmap = (gpa_t)-1;
5937         b = -1;
5938
5939         while (size > 0) {
5940                 if (port < 0x8000)
5941                         bitmap = vmcs12->io_bitmap_a;
5942                 else if (port < 0x10000)
5943                         bitmap = vmcs12->io_bitmap_b;
5944                 else
5945                         return 1;
5946                 bitmap += (port & 0x7fff) / 8;
5947
5948                 if (last_bitmap != bitmap)
5949                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5950                                 return 1;
5951                 if (b & (1 << (port & 7)))
5952                         return 1;
5953
5954                 port++;
5955                 size--;
5956                 last_bitmap = bitmap;
5957         }
5958
5959         return 0;
5960 }
5961
5962 /*
5963  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5964  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5965  * disinterest in the current event (read or write a specific MSR) by using an
5966  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5967  */
5968 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5969         struct vmcs12 *vmcs12, u32 exit_reason)
5970 {
5971         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5972         gpa_t bitmap;
5973
5974         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5975                 return 1;
5976
5977         /*
5978          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5979          * for the four combinations of read/write and low/high MSR numbers.
5980          * First we need to figure out which of the four to use:
5981          */
5982         bitmap = vmcs12->msr_bitmap;
5983         if (exit_reason == EXIT_REASON_MSR_WRITE)
5984                 bitmap += 2048;
5985         if (msr_index >= 0xc0000000) {
5986                 msr_index -= 0xc0000000;
5987                 bitmap += 1024;
5988         }
5989
5990         /* Then read the msr_index'th bit from this bitmap: */
5991         if (msr_index < 1024*8) {
5992                 unsigned char b;
5993                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
5994                         return 1;
5995                 return 1 & (b >> (msr_index & 7));
5996         } else
5997                 return 1; /* let L1 handle the wrong parameter */
5998 }
5999
6000 /*
6001  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6002  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6003  * intercept (via guest_host_mask etc.) the current event.
6004  */
6005 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6006         struct vmcs12 *vmcs12)
6007 {
6008         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6009         int cr = exit_qualification & 15;
6010         int reg = (exit_qualification >> 8) & 15;
6011         unsigned long val = kvm_register_read(vcpu, reg);
6012
6013         switch ((exit_qualification >> 4) & 3) {
6014         case 0: /* mov to cr */
6015                 switch (cr) {
6016                 case 0:
6017                         if (vmcs12->cr0_guest_host_mask &
6018                             (val ^ vmcs12->cr0_read_shadow))
6019                                 return 1;
6020                         break;
6021                 case 3:
6022                         if ((vmcs12->cr3_target_count >= 1 &&
6023                                         vmcs12->cr3_target_value0 == val) ||
6024                                 (vmcs12->cr3_target_count >= 2 &&
6025                                         vmcs12->cr3_target_value1 == val) ||
6026                                 (vmcs12->cr3_target_count >= 3 &&
6027                                         vmcs12->cr3_target_value2 == val) ||
6028                                 (vmcs12->cr3_target_count >= 4 &&
6029                                         vmcs12->cr3_target_value3 == val))
6030                                 return 0;
6031                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6032                                 return 1;
6033                         break;
6034                 case 4:
6035                         if (vmcs12->cr4_guest_host_mask &
6036                             (vmcs12->cr4_read_shadow ^ val))
6037                                 return 1;
6038                         break;
6039                 case 8:
6040                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6041                                 return 1;
6042                         break;
6043                 }
6044                 break;
6045         case 2: /* clts */
6046                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6047                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6048                         return 1;
6049                 break;
6050         case 1: /* mov from cr */
6051                 switch (cr) {
6052                 case 3:
6053                         if (vmcs12->cpu_based_vm_exec_control &
6054                             CPU_BASED_CR3_STORE_EXITING)
6055                                 return 1;
6056                         break;
6057                 case 8:
6058                         if (vmcs12->cpu_based_vm_exec_control &
6059                             CPU_BASED_CR8_STORE_EXITING)
6060                                 return 1;
6061                         break;
6062                 }
6063                 break;
6064         case 3: /* lmsw */
6065                 /*
6066                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6067                  * cr0. Other attempted changes are ignored, with no exit.
6068                  */
6069                 if (vmcs12->cr0_guest_host_mask & 0xe &
6070                     (val ^ vmcs12->cr0_read_shadow))
6071                         return 1;
6072                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6073                     !(vmcs12->cr0_read_shadow & 0x1) &&
6074                     (val & 0x1))
6075                         return 1;
6076                 break;
6077         }
6078         return 0;
6079 }
6080
6081 /*
6082  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6083  * should handle it ourselves in L0 (and then continue L2). Only call this
6084  * when in is_guest_mode (L2).
6085  */
6086 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6087 {
6088         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6089         struct vcpu_vmx *vmx = to_vmx(vcpu);
6090         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6091         u32 exit_reason = vmx->exit_reason;
6092
6093         if (vmx->nested.nested_run_pending)
6094                 return 0;
6095
6096         if (unlikely(vmx->fail)) {
6097                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6098                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6099                 return 1;
6100         }
6101
6102         switch (exit_reason) {
6103         case EXIT_REASON_EXCEPTION_NMI:
6104                 if (!is_exception(intr_info))
6105                         return 0;
6106                 else if (is_page_fault(intr_info))
6107                         return enable_ept;
6108                 return vmcs12->exception_bitmap &
6109                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6110         case EXIT_REASON_EXTERNAL_INTERRUPT:
6111                 return 0;
6112         case EXIT_REASON_TRIPLE_FAULT:
6113                 return 1;
6114         case EXIT_REASON_PENDING_INTERRUPT:
6115                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6116         case EXIT_REASON_NMI_WINDOW:
6117                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6118         case EXIT_REASON_TASK_SWITCH:
6119                 return 1;
6120         case EXIT_REASON_CPUID:
6121                 return 1;
6122         case EXIT_REASON_HLT:
6123                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6124         case EXIT_REASON_INVD:
6125                 return 1;
6126         case EXIT_REASON_INVLPG:
6127                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6128         case EXIT_REASON_RDPMC:
6129                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6130         case EXIT_REASON_RDTSC:
6131                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6132         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6133         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6134         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6135         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6136         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6137                 /*
6138                  * VMX instructions trap unconditionally. This allows L1 to
6139                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6140                  */
6141                 return 1;
6142         case EXIT_REASON_CR_ACCESS:
6143                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6144         case EXIT_REASON_DR_ACCESS:
6145                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6146         case EXIT_REASON_IO_INSTRUCTION:
6147                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6148         case EXIT_REASON_MSR_READ:
6149         case EXIT_REASON_MSR_WRITE:
6150                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6151         case EXIT_REASON_INVALID_STATE:
6152                 return 1;
6153         case EXIT_REASON_MWAIT_INSTRUCTION:
6154                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6155         case EXIT_REASON_MONITOR_INSTRUCTION:
6156                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6157         case EXIT_REASON_PAUSE_INSTRUCTION:
6158                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6159                         nested_cpu_has2(vmcs12,
6160                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6161         case EXIT_REASON_MCE_DURING_VMENTRY:
6162                 return 0;
6163         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6164                 return 1;
6165         case EXIT_REASON_APIC_ACCESS:
6166                 return nested_cpu_has2(vmcs12,
6167                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6168         case EXIT_REASON_EPT_VIOLATION:
6169         case EXIT_REASON_EPT_MISCONFIG:
6170                 return 0;
6171         case EXIT_REASON_PREEMPTION_TIMER:
6172                 return vmcs12->pin_based_vm_exec_control &
6173                         PIN_BASED_VMX_PREEMPTION_TIMER;
6174         case EXIT_REASON_WBINVD:
6175                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6176         case EXIT_REASON_XSETBV:
6177                 return 1;
6178         default:
6179                 return 1;
6180         }
6181 }
6182
6183 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6184 {
6185         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6186         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6187 }
6188
6189 /*
6190  * The guest has exited.  See if we can fix it or if we need userspace
6191  * assistance.
6192  */
6193 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6194 {
6195         struct vcpu_vmx *vmx = to_vmx(vcpu);
6196         u32 exit_reason = vmx->exit_reason;
6197         u32 vectoring_info = vmx->idt_vectoring_info;
6198
6199         /* If guest state is invalid, start emulating */
6200         if (vmx->emulation_required)
6201                 return handle_invalid_guest_state(vcpu);
6202
6203         /*
6204          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6205          * we did not inject a still-pending event to L1 now because of
6206          * nested_run_pending, we need to re-enable this bit.
6207          */
6208         if (vmx->nested.nested_run_pending)
6209                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6210
6211         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6212             exit_reason == EXIT_REASON_VMRESUME))
6213                 vmx->nested.nested_run_pending = 1;
6214         else
6215                 vmx->nested.nested_run_pending = 0;
6216
6217         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6218                 nested_vmx_vmexit(vcpu);
6219                 return 1;
6220         }
6221
6222         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6223                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6224                 vcpu->run->fail_entry.hardware_entry_failure_reason
6225                         = exit_reason;
6226                 return 0;
6227         }
6228
6229         if (unlikely(vmx->fail)) {
6230                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6231                 vcpu->run->fail_entry.hardware_entry_failure_reason
6232                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6233                 return 0;
6234         }
6235
6236         /*
6237          * Note:
6238          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6239          * delivery event since it indicates guest is accessing MMIO.
6240          * The vm-exit can be triggered again after return to guest that
6241          * will cause infinite loop.
6242          */
6243         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6244                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6245                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6246                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6247                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6248                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6249                 vcpu->run->internal.ndata = 2;
6250                 vcpu->run->internal.data[0] = vectoring_info;
6251                 vcpu->run->internal.data[1] = exit_reason;
6252                 return 0;
6253         }
6254
6255         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6256             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6257                                         get_vmcs12(vcpu), vcpu)))) {
6258                 if (vmx_interrupt_allowed(vcpu)) {
6259                         vmx->soft_vnmi_blocked = 0;
6260                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6261                            vcpu->arch.nmi_pending) {
6262                         /*
6263                          * This CPU don't support us in finding the end of an
6264                          * NMI-blocked window if the guest runs with IRQs
6265                          * disabled. So we pull the trigger after 1 s of
6266                          * futile waiting, but inform the user about this.
6267                          */
6268                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6269                                "state on VCPU %d after 1 s timeout\n",
6270                                __func__, vcpu->vcpu_id);
6271                         vmx->soft_vnmi_blocked = 0;
6272                 }
6273         }
6274
6275         if (exit_reason < kvm_vmx_max_exit_handlers
6276             && kvm_vmx_exit_handlers[exit_reason])
6277                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6278         else {
6279                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6280                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6281         }
6282         return 0;
6283 }
6284
6285 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6286 {
6287         if (irr == -1 || tpr < irr) {
6288                 vmcs_write32(TPR_THRESHOLD, 0);
6289                 return;
6290         }
6291
6292         vmcs_write32(TPR_THRESHOLD, irr);
6293 }
6294
6295 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6296 {
6297         u32 sec_exec_control;
6298
6299         /*
6300          * There is not point to enable virtualize x2apic without enable
6301          * apicv
6302          */
6303         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6304                                 !vmx_vm_has_apicv(vcpu->kvm))
6305                 return;
6306
6307         if (!vm_need_tpr_shadow(vcpu->kvm))
6308                 return;
6309
6310         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6311
6312         if (set) {
6313                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6314                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6315         } else {
6316                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6317                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6318         }
6319         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6320
6321         vmx_set_msr_bitmap(vcpu);
6322 }
6323
6324 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6325 {
6326         u16 status;
6327         u8 old;
6328
6329         if (!vmx_vm_has_apicv(kvm))
6330                 return;
6331
6332         if (isr == -1)
6333                 isr = 0;
6334
6335         status = vmcs_read16(GUEST_INTR_STATUS);
6336         old = status >> 8;
6337         if (isr != old) {
6338                 status &= 0xff;
6339                 status |= isr << 8;
6340                 vmcs_write16(GUEST_INTR_STATUS, status);
6341         }
6342 }
6343
6344 static void vmx_set_rvi(int vector)
6345 {
6346         u16 status;
6347         u8 old;
6348
6349         status = vmcs_read16(GUEST_INTR_STATUS);
6350         old = (u8)status & 0xff;
6351         if ((u8)vector != old) {
6352                 status &= ~0xff;
6353                 status |= (u8)vector;
6354                 vmcs_write16(GUEST_INTR_STATUS, status);
6355         }
6356 }
6357
6358 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6359 {
6360         if (max_irr == -1)
6361                 return;
6362
6363         vmx_set_rvi(max_irr);
6364 }
6365
6366 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6367 {
6368         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6369         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6370         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6371         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6372 }
6373
6374 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6375 {
6376         u32 exit_intr_info;
6377
6378         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6379               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6380                 return;
6381
6382         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6383         exit_intr_info = vmx->exit_intr_info;
6384
6385         /* Handle machine checks before interrupts are enabled */
6386         if (is_machine_check(exit_intr_info))
6387                 kvm_machine_check();
6388
6389         /* We need to handle NMIs before interrupts are enabled */
6390         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6391             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6392                 kvm_before_handle_nmi(&vmx->vcpu);
6393                 asm("int $2");
6394                 kvm_after_handle_nmi(&vmx->vcpu);
6395         }
6396 }
6397
6398 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6399 {
6400         u32 exit_intr_info;
6401         bool unblock_nmi;
6402         u8 vector;
6403         bool idtv_info_valid;
6404
6405         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6406
6407         if (cpu_has_virtual_nmis()) {
6408                 if (vmx->nmi_known_unmasked)
6409                         return;
6410                 /*
6411                  * Can't use vmx->exit_intr_info since we're not sure what
6412                  * the exit reason is.
6413                  */
6414                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6415                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6416                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6417                 /*
6418                  * SDM 3: 27.7.1.2 (September 2008)
6419                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6420                  * a guest IRET fault.
6421                  * SDM 3: 23.2.2 (September 2008)
6422                  * Bit 12 is undefined in any of the following cases:
6423                  *  If the VM exit sets the valid bit in the IDT-vectoring
6424                  *   information field.
6425                  *  If the VM exit is due to a double fault.
6426                  */
6427                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6428                     vector != DF_VECTOR && !idtv_info_valid)
6429                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6430                                       GUEST_INTR_STATE_NMI);
6431                 else
6432                         vmx->nmi_known_unmasked =
6433                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6434                                   & GUEST_INTR_STATE_NMI);
6435         } else if (unlikely(vmx->soft_vnmi_blocked))
6436                 vmx->vnmi_blocked_time +=
6437                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6438 }
6439
6440 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6441                                       u32 idt_vectoring_info,
6442                                       int instr_len_field,
6443                                       int error_code_field)
6444 {
6445         u8 vector;
6446         int type;
6447         bool idtv_info_valid;
6448
6449         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6450
6451         vcpu->arch.nmi_injected = false;
6452         kvm_clear_exception_queue(vcpu);
6453         kvm_clear_interrupt_queue(vcpu);
6454
6455         if (!idtv_info_valid)
6456                 return;
6457
6458         kvm_make_request(KVM_REQ_EVENT, vcpu);
6459
6460         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6461         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6462
6463         switch (type) {
6464         case INTR_TYPE_NMI_INTR:
6465                 vcpu->arch.nmi_injected = true;
6466                 /*
6467                  * SDM 3: 27.7.1.2 (September 2008)
6468                  * Clear bit "block by NMI" before VM entry if a NMI
6469                  * delivery faulted.
6470                  */
6471                 vmx_set_nmi_mask(vcpu, false);
6472                 break;
6473         case INTR_TYPE_SOFT_EXCEPTION:
6474                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6475                 /* fall through */
6476         case INTR_TYPE_HARD_EXCEPTION:
6477                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6478                         u32 err = vmcs_read32(error_code_field);
6479                         kvm_queue_exception_e(vcpu, vector, err);
6480                 } else
6481                         kvm_queue_exception(vcpu, vector);
6482                 break;
6483         case INTR_TYPE_SOFT_INTR:
6484                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6485                 /* fall through */
6486         case INTR_TYPE_EXT_INTR:
6487                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6488                 break;
6489         default:
6490                 break;
6491         }
6492 }
6493
6494 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6495 {
6496         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6497                                   VM_EXIT_INSTRUCTION_LEN,
6498                                   IDT_VECTORING_ERROR_CODE);
6499 }
6500
6501 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6502 {
6503         __vmx_complete_interrupts(vcpu,
6504                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6505                                   VM_ENTRY_INSTRUCTION_LEN,
6506                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6507
6508         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6509 }
6510
6511 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6512 {
6513         int i, nr_msrs;
6514         struct perf_guest_switch_msr *msrs;
6515
6516         msrs = perf_guest_get_msrs(&nr_msrs);
6517
6518         if (!msrs)
6519                 return;
6520
6521         for (i = 0; i < nr_msrs; i++)
6522                 if (msrs[i].host == msrs[i].guest)
6523                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6524                 else
6525                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6526                                         msrs[i].host);
6527 }
6528
6529 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6530 {
6531         struct vcpu_vmx *vmx = to_vmx(vcpu);
6532         unsigned long debugctlmsr;
6533
6534         /* Record the guest's net vcpu time for enforced NMI injections. */
6535         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6536                 vmx->entry_time = ktime_get();
6537
6538         /* Don't enter VMX if guest state is invalid, let the exit handler
6539            start emulation until we arrive back to a valid state */
6540         if (vmx->emulation_required)
6541                 return;
6542
6543         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6544                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6545         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6546                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6547
6548         /* When single-stepping over STI and MOV SS, we must clear the
6549          * corresponding interruptibility bits in the guest state. Otherwise
6550          * vmentry fails as it then expects bit 14 (BS) in pending debug
6551          * exceptions being set, but that's not correct for the guest debugging
6552          * case. */
6553         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6554                 vmx_set_interrupt_shadow(vcpu, 0);
6555
6556         atomic_switch_perf_msrs(vmx);
6557         debugctlmsr = get_debugctlmsr();
6558
6559         vmx->__launched = vmx->loaded_vmcs->launched;
6560         asm(
6561                 /* Store host registers */
6562                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6563                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6564                 "push %%" _ASM_CX " \n\t"
6565                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6566                 "je 1f \n\t"
6567                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6568                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6569                 "1: \n\t"
6570                 /* Reload cr2 if changed */
6571                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6572                 "mov %%cr2, %%" _ASM_DX " \n\t"
6573                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6574                 "je 2f \n\t"
6575                 "mov %%" _ASM_AX", %%cr2 \n\t"
6576                 "2: \n\t"
6577                 /* Check if vmlaunch of vmresume is needed */
6578                 "cmpl $0, %c[launched](%0) \n\t"
6579                 /* Load guest registers.  Don't clobber flags. */
6580                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6581                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6582                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6583                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6584                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6585                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6586 #ifdef CONFIG_X86_64
6587                 "mov %c[r8](%0),  %%r8  \n\t"
6588                 "mov %c[r9](%0),  %%r9  \n\t"
6589                 "mov %c[r10](%0), %%r10 \n\t"
6590                 "mov %c[r11](%0), %%r11 \n\t"
6591                 "mov %c[r12](%0), %%r12 \n\t"
6592                 "mov %c[r13](%0), %%r13 \n\t"
6593                 "mov %c[r14](%0), %%r14 \n\t"
6594                 "mov %c[r15](%0), %%r15 \n\t"
6595 #endif
6596                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6597
6598                 /* Enter guest mode */
6599                 "jne 1f \n\t"
6600                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6601                 "jmp 2f \n\t"
6602                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6603                 "2: "
6604                 /* Save guest registers, load host registers, keep flags */
6605                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6606                 "pop %0 \n\t"
6607                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6608                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6609                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6610                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6611                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6612                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6613                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6614 #ifdef CONFIG_X86_64
6615                 "mov %%r8,  %c[r8](%0) \n\t"
6616                 "mov %%r9,  %c[r9](%0) \n\t"
6617                 "mov %%r10, %c[r10](%0) \n\t"
6618                 "mov %%r11, %c[r11](%0) \n\t"
6619                 "mov %%r12, %c[r12](%0) \n\t"
6620                 "mov %%r13, %c[r13](%0) \n\t"
6621                 "mov %%r14, %c[r14](%0) \n\t"
6622                 "mov %%r15, %c[r15](%0) \n\t"
6623 #endif
6624                 "mov %%cr2, %%" _ASM_AX "   \n\t"
6625                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6626
6627                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
6628                 "setbe %c[fail](%0) \n\t"
6629                 ".pushsection .rodata \n\t"
6630                 ".global vmx_return \n\t"
6631                 "vmx_return: " _ASM_PTR " 2b \n\t"
6632                 ".popsection"
6633               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6634                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6635                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6636                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6637                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6638                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6639                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6640                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6641                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6642                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6643                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6644 #ifdef CONFIG_X86_64
6645                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6646                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6647                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6648                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6649                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6650                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6651                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6652                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6653 #endif
6654                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6655                 [wordsize]"i"(sizeof(ulong))
6656               : "cc", "memory"
6657 #ifdef CONFIG_X86_64
6658                 , "rax", "rbx", "rdi", "rsi"
6659                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6660 #else
6661                 , "eax", "ebx", "edi", "esi"
6662 #endif
6663               );
6664
6665         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6666         if (debugctlmsr)
6667                 update_debugctlmsr(debugctlmsr);
6668
6669 #ifndef CONFIG_X86_64
6670         /*
6671          * The sysexit path does not restore ds/es, so we must set them to
6672          * a reasonable value ourselves.
6673          *
6674          * We can't defer this to vmx_load_host_state() since that function
6675          * may be executed in interrupt context, which saves and restore segments
6676          * around it, nullifying its effect.
6677          */
6678         loadsegment(ds, __USER_DS);
6679         loadsegment(es, __USER_DS);
6680 #endif
6681
6682         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6683                                   | (1 << VCPU_EXREG_RFLAGS)
6684                                   | (1 << VCPU_EXREG_CPL)
6685                                   | (1 << VCPU_EXREG_PDPTR)
6686                                   | (1 << VCPU_EXREG_SEGMENTS)
6687                                   | (1 << VCPU_EXREG_CR3));
6688         vcpu->arch.regs_dirty = 0;
6689
6690         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6691
6692         vmx->loaded_vmcs->launched = 1;
6693
6694         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6695         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6696
6697         vmx_complete_atomic_exit(vmx);
6698         vmx_recover_nmi_blocking(vmx);
6699         vmx_complete_interrupts(vmx);
6700 }
6701
6702 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6703 {
6704         struct vcpu_vmx *vmx = to_vmx(vcpu);
6705
6706         free_vpid(vmx);
6707         free_nested(vmx);
6708         free_loaded_vmcs(vmx->loaded_vmcs);
6709         kfree(vmx->guest_msrs);
6710         kvm_vcpu_uninit(vcpu);
6711         kmem_cache_free(kvm_vcpu_cache, vmx);
6712 }
6713
6714 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6715 {
6716         int err;
6717         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6718         int cpu;
6719
6720         if (!vmx)
6721                 return ERR_PTR(-ENOMEM);
6722
6723         allocate_vpid(vmx);
6724
6725         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6726         if (err)
6727                 goto free_vcpu;
6728
6729         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6730         err = -ENOMEM;
6731         if (!vmx->guest_msrs) {
6732                 goto uninit_vcpu;
6733         }
6734
6735         vmx->loaded_vmcs = &vmx->vmcs01;
6736         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6737         if (!vmx->loaded_vmcs->vmcs)
6738                 goto free_msrs;
6739         if (!vmm_exclusive)
6740                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6741         loaded_vmcs_init(vmx->loaded_vmcs);
6742         if (!vmm_exclusive)
6743                 kvm_cpu_vmxoff();
6744
6745         cpu = get_cpu();
6746         vmx_vcpu_load(&vmx->vcpu, cpu);
6747         vmx->vcpu.cpu = cpu;
6748         err = vmx_vcpu_setup(vmx);
6749         vmx_vcpu_put(&vmx->vcpu);
6750         put_cpu();
6751         if (err)
6752                 goto free_vmcs;
6753         if (vm_need_virtualize_apic_accesses(kvm)) {
6754                 err = alloc_apic_access_page(kvm);
6755                 if (err)
6756                         goto free_vmcs;
6757         }
6758
6759         if (enable_ept) {
6760                 if (!kvm->arch.ept_identity_map_addr)
6761                         kvm->arch.ept_identity_map_addr =
6762                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6763                 err = -ENOMEM;
6764                 if (alloc_identity_pagetable(kvm) != 0)
6765                         goto free_vmcs;
6766                 if (!init_rmode_identity_map(kvm))
6767                         goto free_vmcs;
6768         }
6769
6770         vmx->nested.current_vmptr = -1ull;
6771         vmx->nested.current_vmcs12 = NULL;
6772
6773         return &vmx->vcpu;
6774
6775 free_vmcs:
6776         free_loaded_vmcs(vmx->loaded_vmcs);
6777 free_msrs:
6778         kfree(vmx->guest_msrs);
6779 uninit_vcpu:
6780         kvm_vcpu_uninit(&vmx->vcpu);
6781 free_vcpu:
6782         free_vpid(vmx);
6783         kmem_cache_free(kvm_vcpu_cache, vmx);
6784         return ERR_PTR(err);
6785 }
6786
6787 static void __init vmx_check_processor_compat(void *rtn)
6788 {
6789         struct vmcs_config vmcs_conf;
6790
6791         *(int *)rtn = 0;
6792         if (setup_vmcs_config(&vmcs_conf) < 0)
6793                 *(int *)rtn = -EIO;
6794         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6795                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6796                                 smp_processor_id());
6797                 *(int *)rtn = -EIO;
6798         }
6799 }
6800
6801 static int get_ept_level(void)
6802 {
6803         return VMX_EPT_DEFAULT_GAW + 1;
6804 }
6805
6806 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6807 {
6808         u64 ret;
6809
6810         /* For VT-d and EPT combination
6811          * 1. MMIO: always map as UC
6812          * 2. EPT with VT-d:
6813          *   a. VT-d without snooping control feature: can't guarantee the
6814          *      result, try to trust guest.
6815          *   b. VT-d with snooping control feature: snooping control feature of
6816          *      VT-d engine can guarantee the cache correctness. Just set it
6817          *      to WB to keep consistent with host. So the same as item 3.
6818          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6819          *    consistent with host MTRR
6820          */
6821         if (is_mmio)
6822                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6823         else if (vcpu->kvm->arch.iommu_domain &&
6824                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6825                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6826                       VMX_EPT_MT_EPTE_SHIFT;
6827         else
6828                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6829                         | VMX_EPT_IPAT_BIT;
6830
6831         return ret;
6832 }
6833
6834 static int vmx_get_lpage_level(void)
6835 {
6836         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6837                 return PT_DIRECTORY_LEVEL;
6838         else
6839                 /* For shadow and EPT supported 1GB page */
6840                 return PT_PDPE_LEVEL;
6841 }
6842
6843 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6844 {
6845         struct kvm_cpuid_entry2 *best;
6846         struct vcpu_vmx *vmx = to_vmx(vcpu);
6847         u32 exec_control;
6848
6849         vmx->rdtscp_enabled = false;
6850         if (vmx_rdtscp_supported()) {
6851                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6852                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6853                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6854                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6855                                 vmx->rdtscp_enabled = true;
6856                         else {
6857                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6858                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6859                                                 exec_control);
6860                         }
6861                 }
6862         }
6863
6864         /* Exposing INVPCID only when PCID is exposed */
6865         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6866         if (vmx_invpcid_supported() &&
6867             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6868             guest_cpuid_has_pcid(vcpu)) {
6869                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6870                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6871                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6872                              exec_control);
6873         } else {
6874                 if (cpu_has_secondary_exec_ctrls()) {
6875                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6876                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6877                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6878                                      exec_control);
6879                 }
6880                 if (best)
6881                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
6882         }
6883 }
6884
6885 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6886 {
6887         if (func == 1 && nested)
6888                 entry->ecx |= bit(X86_FEATURE_VMX);
6889 }
6890
6891 /*
6892  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6893  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6894  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6895  * guest in a way that will both be appropriate to L1's requests, and our
6896  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6897  * function also has additional necessary side-effects, like setting various
6898  * vcpu->arch fields.
6899  */
6900 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6901 {
6902         struct vcpu_vmx *vmx = to_vmx(vcpu);
6903         u32 exec_control;
6904
6905         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6906         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6907         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6908         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6909         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6910         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6911         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6912         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6913         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6914         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6915         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6916         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6917         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6918         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6919         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6920         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6921         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6922         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6923         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6924         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6925         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6926         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6927         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6928         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6929         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6930         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6931         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6932         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6933         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6934         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6935         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6936         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6937         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6938         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6939         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6940         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6941
6942         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6943         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6944                 vmcs12->vm_entry_intr_info_field);
6945         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6946                 vmcs12->vm_entry_exception_error_code);
6947         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6948                 vmcs12->vm_entry_instruction_len);
6949         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6950                 vmcs12->guest_interruptibility_info);
6951         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6952         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6953         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
6954         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6955         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6956                 vmcs12->guest_pending_dbg_exceptions);
6957         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6958         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6959
6960         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6961
6962         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6963                 (vmcs_config.pin_based_exec_ctrl |
6964                  vmcs12->pin_based_vm_exec_control));
6965
6966         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
6967                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
6968                              vmcs12->vmx_preemption_timer_value);
6969
6970         /*
6971          * Whether page-faults are trapped is determined by a combination of
6972          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6973          * If enable_ept, L0 doesn't care about page faults and we should
6974          * set all of these to L1's desires. However, if !enable_ept, L0 does
6975          * care about (at least some) page faults, and because it is not easy
6976          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6977          * to exit on each and every L2 page fault. This is done by setting
6978          * MASK=MATCH=0 and (see below) EB.PF=1.
6979          * Note that below we don't need special code to set EB.PF beyond the
6980          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6981          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6982          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6983          *
6984          * A problem with this approach (when !enable_ept) is that L1 may be
6985          * injected with more page faults than it asked for. This could have
6986          * caused problems, but in practice existing hypervisors don't care.
6987          * To fix this, we will need to emulate the PFEC checking (on the L1
6988          * page tables), using walk_addr(), when injecting PFs to L1.
6989          */
6990         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6991                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6992         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6993                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6994
6995         if (cpu_has_secondary_exec_ctrls()) {
6996                 u32 exec_control = vmx_secondary_exec_control(vmx);
6997                 if (!vmx->rdtscp_enabled)
6998                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6999                 /* Take the following fields only from vmcs12 */
7000                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7001                 if (nested_cpu_has(vmcs12,
7002                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7003                         exec_control |= vmcs12->secondary_vm_exec_control;
7004
7005                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7006                         /*
7007                          * Translate L1 physical address to host physical
7008                          * address for vmcs02. Keep the page pinned, so this
7009                          * physical address remains valid. We keep a reference
7010                          * to it so we can release it later.
7011                          */
7012                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7013                                 nested_release_page(vmx->nested.apic_access_page);
7014                         vmx->nested.apic_access_page =
7015                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7016                         /*
7017                          * If translation failed, no matter: This feature asks
7018                          * to exit when accessing the given address, and if it
7019                          * can never be accessed, this feature won't do
7020                          * anything anyway.
7021                          */
7022                         if (!vmx->nested.apic_access_page)
7023                                 exec_control &=
7024                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7025                         else
7026                                 vmcs_write64(APIC_ACCESS_ADDR,
7027                                   page_to_phys(vmx->nested.apic_access_page));
7028                 }
7029
7030                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7031         }
7032
7033
7034         /*
7035          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7036          * Some constant fields are set here by vmx_set_constant_host_state().
7037          * Other fields are different per CPU, and will be set later when
7038          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7039          */
7040         vmx_set_constant_host_state();
7041
7042         /*
7043          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7044          * entry, but only if the current (host) sp changed from the value
7045          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7046          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7047          * here we just force the write to happen on entry.
7048          */
7049         vmx->host_rsp = 0;
7050
7051         exec_control = vmx_exec_control(vmx); /* L0's desires */
7052         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7053         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7054         exec_control &= ~CPU_BASED_TPR_SHADOW;
7055         exec_control |= vmcs12->cpu_based_vm_exec_control;
7056         /*
7057          * Merging of IO and MSR bitmaps not currently supported.
7058          * Rather, exit every time.
7059          */
7060         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7061         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7062         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7063
7064         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7065
7066         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7067          * bitwise-or of what L1 wants to trap for L2, and what we want to
7068          * trap. Note that CR0.TS also needs updating - we do this later.
7069          */
7070         update_exception_bitmap(vcpu);
7071         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7072         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7073
7074         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7075         vmcs_write32(VM_EXIT_CONTROLS,
7076                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7077         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7078                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7079
7080         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7081                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7082         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7083                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7084
7085
7086         set_cr4_guest_host_mask(vmx);
7087
7088         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7089                 vmcs_write64(TSC_OFFSET,
7090                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7091         else
7092                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7093
7094         if (enable_vpid) {
7095                 /*
7096                  * Trivially support vpid by letting L2s share their parent
7097                  * L1's vpid. TODO: move to a more elaborate solution, giving
7098                  * each L2 its own vpid and exposing the vpid feature to L1.
7099                  */
7100                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7101                 vmx_flush_tlb(vcpu);
7102         }
7103
7104         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7105                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7106         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7107                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7108         else
7109                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7110         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7111         vmx_set_efer(vcpu, vcpu->arch.efer);
7112
7113         /*
7114          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7115          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7116          * The CR0_READ_SHADOW is what L2 should have expected to read given
7117          * the specifications by L1; It's not enough to take
7118          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7119          * have more bits than L1 expected.
7120          */
7121         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7122         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7123
7124         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7125         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7126
7127         /* shadow page tables on either EPT or shadow page tables */
7128         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7129         kvm_mmu_reset_context(vcpu);
7130
7131         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7132         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7133 }
7134
7135 /*
7136  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7137  * for running an L2 nested guest.
7138  */
7139 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7140 {
7141         struct vmcs12 *vmcs12;
7142         struct vcpu_vmx *vmx = to_vmx(vcpu);
7143         int cpu;
7144         struct loaded_vmcs *vmcs02;
7145
7146         if (!nested_vmx_check_permission(vcpu) ||
7147             !nested_vmx_check_vmcs12(vcpu))
7148                 return 1;
7149
7150         skip_emulated_instruction(vcpu);
7151         vmcs12 = get_vmcs12(vcpu);
7152
7153         /*
7154          * The nested entry process starts with enforcing various prerequisites
7155          * on vmcs12 as required by the Intel SDM, and act appropriately when
7156          * they fail: As the SDM explains, some conditions should cause the
7157          * instruction to fail, while others will cause the instruction to seem
7158          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7159          * To speed up the normal (success) code path, we should avoid checking
7160          * for misconfigurations which will anyway be caught by the processor
7161          * when using the merged vmcs02.
7162          */
7163         if (vmcs12->launch_state == launch) {
7164                 nested_vmx_failValid(vcpu,
7165                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7166                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7167                 return 1;
7168         }
7169
7170         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7171                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7172                 /*TODO: Also verify bits beyond physical address width are 0*/
7173                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7174                 return 1;
7175         }
7176
7177         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7178                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7179                 /*TODO: Also verify bits beyond physical address width are 0*/
7180                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7181                 return 1;
7182         }
7183
7184         if (vmcs12->vm_entry_msr_load_count > 0 ||
7185             vmcs12->vm_exit_msr_load_count > 0 ||
7186             vmcs12->vm_exit_msr_store_count > 0) {
7187                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7188                                     __func__);
7189                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7190                 return 1;
7191         }
7192
7193         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7194               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7195             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7196               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7197             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7198               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7199             !vmx_control_verify(vmcs12->vm_exit_controls,
7200               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7201             !vmx_control_verify(vmcs12->vm_entry_controls,
7202               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7203         {
7204                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7205                 return 1;
7206         }
7207
7208         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7209             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7210                 nested_vmx_failValid(vcpu,
7211                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7212                 return 1;
7213         }
7214
7215         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7216             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7217                 nested_vmx_entry_failure(vcpu, vmcs12,
7218                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7219                 return 1;
7220         }
7221         if (vmcs12->vmcs_link_pointer != -1ull) {
7222                 nested_vmx_entry_failure(vcpu, vmcs12,
7223                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7224                 return 1;
7225         }
7226
7227         /*
7228          * We're finally done with prerequisite checking, and can start with
7229          * the nested entry.
7230          */
7231
7232         vmcs02 = nested_get_current_vmcs02(vmx);
7233         if (!vmcs02)
7234                 return -ENOMEM;
7235
7236         enter_guest_mode(vcpu);
7237
7238         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7239
7240         cpu = get_cpu();
7241         vmx->loaded_vmcs = vmcs02;
7242         vmx_vcpu_put(vcpu);
7243         vmx_vcpu_load(vcpu, cpu);
7244         vcpu->cpu = cpu;
7245         put_cpu();
7246
7247         vmx_segment_cache_clear(vmx);
7248
7249         vmcs12->launch_state = 1;
7250
7251         prepare_vmcs02(vcpu, vmcs12);
7252
7253         /*
7254          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7255          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7256          * returned as far as L1 is concerned. It will only return (and set
7257          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7258          */
7259         return 1;
7260 }
7261
7262 /*
7263  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7264  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7265  * This function returns the new value we should put in vmcs12.guest_cr0.
7266  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7267  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7268  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7269  *     didn't trap the bit, because if L1 did, so would L0).
7270  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7271  *     been modified by L2, and L1 knows it. So just leave the old value of
7272  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7273  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7274  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7275  *     changed these bits, and therefore they need to be updated, but L0
7276  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7277  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7278  */
7279 static inline unsigned long
7280 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7281 {
7282         return
7283         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7284         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7285         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7286                         vcpu->arch.cr0_guest_owned_bits));
7287 }
7288
7289 static inline unsigned long
7290 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7291 {
7292         return
7293         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7294         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7295         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7296                         vcpu->arch.cr4_guest_owned_bits));
7297 }
7298
7299 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7300                                        struct vmcs12 *vmcs12)
7301 {
7302         u32 idt_vectoring;
7303         unsigned int nr;
7304
7305         if (vcpu->arch.exception.pending) {
7306                 nr = vcpu->arch.exception.nr;
7307                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7308
7309                 if (kvm_exception_is_soft(nr)) {
7310                         vmcs12->vm_exit_instruction_len =
7311                                 vcpu->arch.event_exit_inst_len;
7312                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7313                 } else
7314                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7315
7316                 if (vcpu->arch.exception.has_error_code) {
7317                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7318                         vmcs12->idt_vectoring_error_code =
7319                                 vcpu->arch.exception.error_code;
7320                 }
7321
7322                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7323         } else if (vcpu->arch.nmi_pending) {
7324                 vmcs12->idt_vectoring_info_field =
7325                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7326         } else if (vcpu->arch.interrupt.pending) {
7327                 nr = vcpu->arch.interrupt.nr;
7328                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7329
7330                 if (vcpu->arch.interrupt.soft) {
7331                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
7332                         vmcs12->vm_entry_instruction_len =
7333                                 vcpu->arch.event_exit_inst_len;
7334                 } else
7335                         idt_vectoring |= INTR_TYPE_EXT_INTR;
7336
7337                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7338         }
7339 }
7340
7341 /*
7342  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7343  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7344  * and this function updates it to reflect the changes to the guest state while
7345  * L2 was running (and perhaps made some exits which were handled directly by L0
7346  * without going back to L1), and to reflect the exit reason.
7347  * Note that we do not have to copy here all VMCS fields, just those that
7348  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7349  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7350  * which already writes to vmcs12 directly.
7351  */
7352 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7353 {
7354         /* update guest state fields: */
7355         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7356         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7357
7358         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7359         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7360         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7361         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7362
7363         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7364         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7365         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7366         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7367         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7368         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7369         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7370         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7371         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7372         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7373         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7374         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7375         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7376         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7377         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7378         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7379         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7380         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7381         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7382         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7383         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7384         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7385         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7386         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7387         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7388         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7389         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7390         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7391         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7392         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7393         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7394         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7395         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7396         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7397         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7398         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7399
7400         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7401         vmcs12->guest_interruptibility_info =
7402                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7403         vmcs12->guest_pending_dbg_exceptions =
7404                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7405
7406         vmcs12->vm_entry_controls =
7407                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7408                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7409
7410         /* TODO: These cannot have changed unless we have MSR bitmaps and
7411          * the relevant bit asks not to trap the change */
7412         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7413         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
7414                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7415         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7416         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7417         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7418
7419         /* update exit information fields: */
7420
7421         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
7422         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7423
7424         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7425         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7426         vmcs12->idt_vectoring_info_field = 0;
7427         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7428         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7429
7430         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7431                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7432                  * instead of reading the real value. */
7433                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7434
7435                 /*
7436                  * Transfer the event that L0 or L1 may wanted to inject into
7437                  * L2 to IDT_VECTORING_INFO_FIELD.
7438                  */
7439                 vmcs12_save_pending_event(vcpu, vmcs12);
7440         }
7441
7442         /*
7443          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7444          * preserved above and would only end up incorrectly in L1.
7445          */
7446         vcpu->arch.nmi_injected = false;
7447         kvm_clear_exception_queue(vcpu);
7448         kvm_clear_interrupt_queue(vcpu);
7449 }
7450
7451 /*
7452  * A part of what we need to when the nested L2 guest exits and we want to
7453  * run its L1 parent, is to reset L1's guest state to the host state specified
7454  * in vmcs12.
7455  * This function is to be called not only on normal nested exit, but also on
7456  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7457  * Failures During or After Loading Guest State").
7458  * This function should be called when the active VMCS is L1's (vmcs01).
7459  */
7460 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7461                                    struct vmcs12 *vmcs12)
7462 {
7463         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7464                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7465         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7466                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7467         else
7468                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7469         vmx_set_efer(vcpu, vcpu->arch.efer);
7470
7471         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7472         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7473         vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
7474         /*
7475          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7476          * actually changed, because it depends on the current state of
7477          * fpu_active (which may have changed).
7478          * Note that vmx_set_cr0 refers to efer set above.
7479          */
7480         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7481         /*
7482          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7483          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7484          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7485          */
7486         update_exception_bitmap(vcpu);
7487         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7488         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7489
7490         /*
7491          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7492          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7493          */
7494         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7495         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7496
7497         /* shadow page tables on either EPT or shadow page tables */
7498         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7499         kvm_mmu_reset_context(vcpu);
7500
7501         if (enable_vpid) {
7502                 /*
7503                  * Trivially support vpid by letting L2s share their parent
7504                  * L1's vpid. TODO: move to a more elaborate solution, giving
7505                  * each L2 its own vpid and exposing the vpid feature to L1.
7506                  */
7507                 vmx_flush_tlb(vcpu);
7508         }
7509
7510
7511         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7512         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7513         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7514         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7515         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7516         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7517         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7518         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7519         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7520         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7521         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7522         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7523         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7524         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7525         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7526
7527         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7528                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7529         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7530                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7531                         vmcs12->host_ia32_perf_global_ctrl);
7532
7533         kvm_set_dr(vcpu, 7, 0x400);
7534         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
7535 }
7536
7537 /*
7538  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7539  * and modify vmcs12 to make it see what it would expect to see there if
7540  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7541  */
7542 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7543 {
7544         struct vcpu_vmx *vmx = to_vmx(vcpu);
7545         int cpu;
7546         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7547
7548         /* trying to cancel vmlaunch/vmresume is a bug */
7549         WARN_ON_ONCE(vmx->nested.nested_run_pending);
7550
7551         leave_guest_mode(vcpu);
7552         prepare_vmcs12(vcpu, vmcs12);
7553
7554         cpu = get_cpu();
7555         vmx->loaded_vmcs = &vmx->vmcs01;
7556         vmx_vcpu_put(vcpu);
7557         vmx_vcpu_load(vcpu, cpu);
7558         vcpu->cpu = cpu;
7559         put_cpu();
7560
7561         vmx_segment_cache_clear(vmx);
7562
7563         /* if no vmcs02 cache requested, remove the one we used */
7564         if (VMCS02_POOL_SIZE == 0)
7565                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7566
7567         load_vmcs12_host_state(vcpu, vmcs12);
7568
7569         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7570         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7571
7572         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7573         vmx->host_rsp = 0;
7574
7575         /* Unpin physical memory we referred to in vmcs02 */
7576         if (vmx->nested.apic_access_page) {
7577                 nested_release_page(vmx->nested.apic_access_page);
7578                 vmx->nested.apic_access_page = 0;
7579         }
7580
7581         /*
7582          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7583          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7584          * success or failure flag accordingly.
7585          */
7586         if (unlikely(vmx->fail)) {
7587                 vmx->fail = 0;
7588                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7589         } else
7590                 nested_vmx_succeed(vcpu);
7591 }
7592
7593 /*
7594  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7595  * 23.7 "VM-entry failures during or after loading guest state" (this also
7596  * lists the acceptable exit-reason and exit-qualification parameters).
7597  * It should only be called before L2 actually succeeded to run, and when
7598  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7599  */
7600 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7601                         struct vmcs12 *vmcs12,
7602                         u32 reason, unsigned long qualification)
7603 {
7604         load_vmcs12_host_state(vcpu, vmcs12);
7605         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7606         vmcs12->exit_qualification = qualification;
7607         nested_vmx_succeed(vcpu);
7608 }
7609
7610 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7611                                struct x86_instruction_info *info,
7612                                enum x86_intercept_stage stage)
7613 {
7614         return X86EMUL_CONTINUE;
7615 }
7616
7617 static struct kvm_x86_ops vmx_x86_ops = {
7618         .cpu_has_kvm_support = cpu_has_kvm_support,
7619         .disabled_by_bios = vmx_disabled_by_bios,
7620         .hardware_setup = hardware_setup,
7621         .hardware_unsetup = hardware_unsetup,
7622         .check_processor_compatibility = vmx_check_processor_compat,
7623         .hardware_enable = hardware_enable,
7624         .hardware_disable = hardware_disable,
7625         .cpu_has_accelerated_tpr = report_flexpriority,
7626
7627         .vcpu_create = vmx_create_vcpu,
7628         .vcpu_free = vmx_free_vcpu,
7629         .vcpu_reset = vmx_vcpu_reset,
7630
7631         .prepare_guest_switch = vmx_save_host_state,
7632         .vcpu_load = vmx_vcpu_load,
7633         .vcpu_put = vmx_vcpu_put,
7634
7635         .update_db_bp_intercept = update_exception_bitmap,
7636         .get_msr = vmx_get_msr,
7637         .set_msr = vmx_set_msr,
7638         .get_segment_base = vmx_get_segment_base,
7639         .get_segment = vmx_get_segment,
7640         .set_segment = vmx_set_segment,
7641         .get_cpl = vmx_get_cpl,
7642         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7643         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7644         .decache_cr3 = vmx_decache_cr3,
7645         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7646         .set_cr0 = vmx_set_cr0,
7647         .set_cr3 = vmx_set_cr3,
7648         .set_cr4 = vmx_set_cr4,
7649         .set_efer = vmx_set_efer,
7650         .get_idt = vmx_get_idt,
7651         .set_idt = vmx_set_idt,
7652         .get_gdt = vmx_get_gdt,
7653         .set_gdt = vmx_set_gdt,
7654         .set_dr7 = vmx_set_dr7,
7655         .cache_reg = vmx_cache_reg,
7656         .get_rflags = vmx_get_rflags,
7657         .set_rflags = vmx_set_rflags,
7658         .fpu_activate = vmx_fpu_activate,
7659         .fpu_deactivate = vmx_fpu_deactivate,
7660
7661         .tlb_flush = vmx_flush_tlb,
7662
7663         .run = vmx_vcpu_run,
7664         .handle_exit = vmx_handle_exit,
7665         .skip_emulated_instruction = skip_emulated_instruction,
7666         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7667         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7668         .patch_hypercall = vmx_patch_hypercall,
7669         .set_irq = vmx_inject_irq,
7670         .set_nmi = vmx_inject_nmi,
7671         .queue_exception = vmx_queue_exception,
7672         .cancel_injection = vmx_cancel_injection,
7673         .interrupt_allowed = vmx_interrupt_allowed,
7674         .nmi_allowed = vmx_nmi_allowed,
7675         .get_nmi_mask = vmx_get_nmi_mask,
7676         .set_nmi_mask = vmx_set_nmi_mask,
7677         .enable_nmi_window = enable_nmi_window,
7678         .enable_irq_window = enable_irq_window,
7679         .update_cr8_intercept = update_cr8_intercept,
7680         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
7681         .vm_has_apicv = vmx_vm_has_apicv,
7682         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7683         .hwapic_irr_update = vmx_hwapic_irr_update,
7684         .hwapic_isr_update = vmx_hwapic_isr_update,
7685
7686         .set_tss_addr = vmx_set_tss_addr,
7687         .get_tdp_level = get_ept_level,
7688         .get_mt_mask = vmx_get_mt_mask,
7689
7690         .get_exit_info = vmx_get_exit_info,
7691
7692         .get_lpage_level = vmx_get_lpage_level,
7693
7694         .cpuid_update = vmx_cpuid_update,
7695
7696         .rdtscp_supported = vmx_rdtscp_supported,
7697         .invpcid_supported = vmx_invpcid_supported,
7698
7699         .set_supported_cpuid = vmx_set_supported_cpuid,
7700
7701         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7702
7703         .set_tsc_khz = vmx_set_tsc_khz,
7704         .read_tsc_offset = vmx_read_tsc_offset,
7705         .write_tsc_offset = vmx_write_tsc_offset,
7706         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7707         .compute_tsc_offset = vmx_compute_tsc_offset,
7708         .read_l1_tsc = vmx_read_l1_tsc,
7709
7710         .set_tdp_cr3 = vmx_set_cr3,
7711
7712         .check_intercept = vmx_check_intercept,
7713 };
7714
7715 static int __init vmx_init(void)
7716 {
7717         int r, i, msr;
7718
7719         rdmsrl_safe(MSR_EFER, &host_efer);
7720
7721         for (i = 0; i < NR_VMX_MSR; ++i)
7722                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7723
7724         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7725         if (!vmx_io_bitmap_a)
7726                 return -ENOMEM;
7727
7728         r = -ENOMEM;
7729
7730         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7731         if (!vmx_io_bitmap_b)
7732                 goto out;
7733
7734         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7735         if (!vmx_msr_bitmap_legacy)
7736                 goto out1;
7737
7738         vmx_msr_bitmap_legacy_x2apic =
7739                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7740         if (!vmx_msr_bitmap_legacy_x2apic)
7741                 goto out2;
7742
7743         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7744         if (!vmx_msr_bitmap_longmode)
7745                 goto out3;
7746
7747         vmx_msr_bitmap_longmode_x2apic =
7748                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7749         if (!vmx_msr_bitmap_longmode_x2apic)
7750                 goto out4;
7751
7752         /*
7753          * Allow direct access to the PC debug port (it is often used for I/O
7754          * delays, but the vmexits simply slow things down).
7755          */
7756         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7757         clear_bit(0x80, vmx_io_bitmap_a);
7758
7759         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7760
7761         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7762         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7763
7764         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7765
7766         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7767                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7768         if (r)
7769                 goto out5;
7770
7771 #ifdef CONFIG_KEXEC
7772         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7773                            crash_vmclear_local_loaded_vmcss);
7774 #endif
7775
7776         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7777         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7778         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7779         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7780         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7781         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7782         memcpy(vmx_msr_bitmap_legacy_x2apic,
7783                         vmx_msr_bitmap_legacy, PAGE_SIZE);
7784         memcpy(vmx_msr_bitmap_longmode_x2apic,
7785                         vmx_msr_bitmap_longmode, PAGE_SIZE);
7786
7787         if (enable_apicv_reg_vid) {
7788                 for (msr = 0x800; msr <= 0x8ff; msr++)
7789                         vmx_disable_intercept_msr_read_x2apic(msr);
7790
7791                 /* According SDM, in x2apic mode, the whole id reg is used.
7792                  * But in KVM, it only use the highest eight bits. Need to
7793                  * intercept it */
7794                 vmx_enable_intercept_msr_read_x2apic(0x802);
7795                 /* TMCCT */
7796                 vmx_enable_intercept_msr_read_x2apic(0x839);
7797                 /* TPR */
7798                 vmx_disable_intercept_msr_write_x2apic(0x808);
7799                 /* EOI */
7800                 vmx_disable_intercept_msr_write_x2apic(0x80b);
7801                 /* SELF-IPI */
7802                 vmx_disable_intercept_msr_write_x2apic(0x83f);
7803         }
7804
7805         if (enable_ept) {
7806                 kvm_mmu_set_mask_ptes(0ull,
7807                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7808                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7809                         0ull, VMX_EPT_EXECUTABLE_MASK);
7810                 ept_set_mmio_spte_mask();
7811                 kvm_enable_tdp();
7812         } else
7813                 kvm_disable_tdp();
7814
7815         return 0;
7816
7817 out5:
7818         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
7819 out4:
7820         free_page((unsigned long)vmx_msr_bitmap_longmode);
7821 out3:
7822         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7823 out2:
7824         free_page((unsigned long)vmx_msr_bitmap_legacy);
7825 out1:
7826         free_page((unsigned long)vmx_io_bitmap_b);
7827 out:
7828         free_page((unsigned long)vmx_io_bitmap_a);
7829         return r;
7830 }
7831
7832 static void __exit vmx_exit(void)
7833 {
7834         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7835         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
7836         free_page((unsigned long)vmx_msr_bitmap_legacy);
7837         free_page((unsigned long)vmx_msr_bitmap_longmode);
7838         free_page((unsigned long)vmx_io_bitmap_b);
7839         free_page((unsigned long)vmx_io_bitmap_a);
7840
7841 #ifdef CONFIG_KEXEC
7842         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7843         synchronize_rcu();
7844 #endif
7845
7846         kvm_exit();
7847 }
7848
7849 module_init(vmx_init)
7850 module_exit(vmx_exit)