arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601 };
 602
 603 enum segment_cache_field {
 604         SEG_FIELD_SEL = 0,
 605         SEG_FIELD_BASE = 1,
 606         SEG_FIELD_LIMIT = 2,
 607         SEG_FIELD_AR = 3,
 608
 609         SEG_FIELD_NR = 4
 610 };
 611
 612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 613 {
 614         return container_of(vcpu, struct vcpu_vmx, vcpu);
 615 }
 616
 617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 618 {
 619         return &(to_vmx(vcpu)->pi_desc);
 620 }
 621
 622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 623 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 624 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 625                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 626
 627
 628 static unsigned long shadow_read_only_fields[] = {
 629         /*
 630          * We do NOT shadow fields that are modified when L0
 631          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 632          * VMXON...) executed by L1.
 633          * For example, VM_INSTRUCTION_ERROR is read
 634          * by L1 if a vmx instruction fails (part of the error path).
 635          * Note the code assumes this logic. If for some reason
 636          * we start shadowing these fields then we need to
 637          * force a shadow sync when L0 emulates vmx instructions
 638          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 639          * by nested_vmx_failValid)
 640          */
 641         VM_EXIT_REASON,
 642         VM_EXIT_INTR_INFO,
 643         VM_EXIT_INSTRUCTION_LEN,
 644         IDT_VECTORING_INFO_FIELD,
 645         IDT_VECTORING_ERROR_CODE,
 646         VM_EXIT_INTR_ERROR_CODE,
 647         EXIT_QUALIFICATION,
 648         GUEST_LINEAR_ADDRESS,
 649         GUEST_PHYSICAL_ADDRESS
 650 };
 651 static int max_shadow_read_only_fields =
 652         ARRAY_SIZE(shadow_read_only_fields);
 653
 654 static unsigned long shadow_read_write_fields[] = {
 655         TPR_THRESHOLD,
 656         GUEST_RIP,
 657         GUEST_RSP,
 658         GUEST_CR0,
 659         GUEST_CR3,
 660         GUEST_CR4,
 661         GUEST_INTERRUPTIBILITY_INFO,
 662         GUEST_RFLAGS,
 663         GUEST_CS_SELECTOR,
 664         GUEST_CS_AR_BYTES,
 665         GUEST_CS_LIMIT,
 666         GUEST_CS_BASE,
 667         GUEST_ES_BASE,
 668         GUEST_BNDCFGS,
 669         CR0_GUEST_HOST_MASK,
 670         CR0_READ_SHADOW,
 671         CR4_READ_SHADOW,
 672         TSC_OFFSET,
 673         EXCEPTION_BITMAP,
 674         CPU_BASED_VM_EXEC_CONTROL,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         VM_ENTRY_INTR_INFO_FIELD,
 677         VM_ENTRY_INSTRUCTION_LEN,
 678         VM_ENTRY_EXCEPTION_ERROR_CODE,
 679         HOST_FS_BASE,
 680         HOST_GS_BASE,
 681         HOST_FS_SELECTOR,
 682         HOST_GS_SELECTOR
 683 };
 684 static int max_shadow_read_write_fields =
 685         ARRAY_SIZE(shadow_read_write_fields);
 686
 687 static const unsigned short vmcs_field_to_offset_table[] = {
 688         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 689         FIELD(POSTED_INTR_NV, posted_intr_nv),
 690         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 691         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 692         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 693         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 694         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 695         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 696         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 697         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 698         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 699         FIELD(HOST_ES_SELECTOR, host_es_selector),
 700         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 701         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 702         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 703         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 704         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 705         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 706         FIELD64(IO_BITMAP_A, io_bitmap_a),
 707         FIELD64(IO_BITMAP_B, io_bitmap_b),
 708         FIELD64(MSR_BITMAP, msr_bitmap),
 709         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 710         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 711         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 712         FIELD64(TSC_OFFSET, tsc_offset),
 713         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 714         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 715         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 716         FIELD64(EPT_POINTER, ept_pointer),
 717         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 718         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 719         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 720         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 721         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 722         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 723         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 724         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 725         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 726         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 727         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 728         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 729         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 730         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 731         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 732         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 733         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 734         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 735         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 736         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 737         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 738         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 740         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 741         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 742         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 743         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 744         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 745         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 746         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 747         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 748         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 749         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 750         FIELD(TPR_THRESHOLD, tpr_threshold),
 751         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 752         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 753         FIELD(VM_EXIT_REASON, vm_exit_reason),
 754         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 755         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 756         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 757         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 758         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 759         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 760         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 761         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 762         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 763         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 764         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 765         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 766         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 767         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 768         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 769         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 770         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 771         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 772         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 773         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 774         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 775         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 776         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 777         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 778         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 779         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 780         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 781         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 782         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 783         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 784         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 785         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 786         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 787         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 788         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 789         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 790         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 791         FIELD(EXIT_QUALIFICATION, exit_qualification),
 792         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 793         FIELD(GUEST_CR0, guest_cr0),
 794         FIELD(GUEST_CR3, guest_cr3),
 795         FIELD(GUEST_CR4, guest_cr4),
 796         FIELD(GUEST_ES_BASE, guest_es_base),
 797         FIELD(GUEST_CS_BASE, guest_cs_base),
 798         FIELD(GUEST_SS_BASE, guest_ss_base),
 799         FIELD(GUEST_DS_BASE, guest_ds_base),
 800         FIELD(GUEST_FS_BASE, guest_fs_base),
 801         FIELD(GUEST_GS_BASE, guest_gs_base),
 802         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 803         FIELD(GUEST_TR_BASE, guest_tr_base),
 804         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 805         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 806         FIELD(GUEST_DR7, guest_dr7),
 807         FIELD(GUEST_RSP, guest_rsp),
 808         FIELD(GUEST_RIP, guest_rip),
 809         FIELD(GUEST_RFLAGS, guest_rflags),
 810         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 811         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 812         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 813         FIELD(HOST_CR0, host_cr0),
 814         FIELD(HOST_CR3, host_cr3),
 815         FIELD(HOST_CR4, host_cr4),
 816         FIELD(HOST_FS_BASE, host_fs_base),
 817         FIELD(HOST_GS_BASE, host_gs_base),
 818         FIELD(HOST_TR_BASE, host_tr_base),
 819         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 820         FIELD(HOST_IDTR_BASE, host_idtr_base),
 821         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 822         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 823         FIELD(HOST_RSP, host_rsp),
 824         FIELD(HOST_RIP, host_rip),
 825 };
 826
 827 static inline short vmcs_field_to_offset(unsigned long field)
 828 {
 829         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 830
 831         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 832             vmcs_field_to_offset_table[field] == 0)
 833                 return -ENOENT;
 834
 835         return vmcs_field_to_offset_table[field];
 836 }
 837
 838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 839 {
 840         return to_vmx(vcpu)->nested.current_vmcs12;
 841 }
 842
 843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 844 {
 845         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 846         if (is_error_page(page))
 847                 return NULL;
 848
 849         return page;
 850 }
 851
 852 static void nested_release_page(struct page *page)
 853 {
 854         kvm_release_page_dirty(page);
 855 }
 856
 857 static void nested_release_page_clean(struct page *page)
 858 {
 859         kvm_release_page_clean(page);
 860 }
 861
 862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 863 static u64 construct_eptp(unsigned long root_hpa);
 864 static void kvm_cpu_vmxon(u64 addr);
 865 static void kvm_cpu_vmxoff(void);
 866 static bool vmx_mpx_supported(void);
 867 static bool vmx_xsaves_supported(void);
 868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 872                             struct kvm_segment *var, int seg);
 873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 875 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 876 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 877 static int alloc_identity_pagetable(struct kvm *kvm);
 878
 879 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 880 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 881 /*
 882  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 883  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 884  */
 885 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 886 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 887
 888 /*
 889  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 890  * can find which vCPU should be waken up.
 891  */
 892 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 893 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 894
 895 static unsigned long *vmx_io_bitmap_a;
 896 static unsigned long *vmx_io_bitmap_b;
 897 static unsigned long *vmx_msr_bitmap_legacy;
 898 static unsigned long *vmx_msr_bitmap_longmode;
 899 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 900 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 901 static unsigned long *vmx_msr_bitmap_nested;
 902 static unsigned long *vmx_vmread_bitmap;
 903 static unsigned long *vmx_vmwrite_bitmap;
 904
 905 static bool cpu_has_load_ia32_efer;
 906 static bool cpu_has_load_perf_global_ctrl;
 907
 908 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 909 static DEFINE_SPINLOCK(vmx_vpid_lock);
 910
 911 static struct vmcs_config {
 912         int size;
 913         int order;
 914         u32 revision_id;
 915         u32 pin_based_exec_ctrl;
 916         u32 cpu_based_exec_ctrl;
 917         u32 cpu_based_2nd_exec_ctrl;
 918         u32 vmexit_ctrl;
 919         u32 vmentry_ctrl;
 920 } vmcs_config;
 921
 922 static struct vmx_capability {
 923         u32 ept;
 924         u32 vpid;
 925 } vmx_capability;
 926
 927 #define VMX_SEGMENT_FIELD(seg)                                  \
 928         [VCPU_SREG_##seg] = {                                   \
 929                 .selector = GUEST_##seg##_SELECTOR,             \
 930                 .base = GUEST_##seg##_BASE,                     \
 931                 .limit = GUEST_##seg##_LIMIT,                   \
 932                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 933         }
 934
 935 static const struct kvm_vmx_segment_field {
 936         unsigned selector;
 937         unsigned base;
 938         unsigned limit;
 939         unsigned ar_bytes;
 940 } kvm_vmx_segment_fields[] = {
 941         VMX_SEGMENT_FIELD(CS),
 942         VMX_SEGMENT_FIELD(DS),
 943         VMX_SEGMENT_FIELD(ES),
 944         VMX_SEGMENT_FIELD(FS),
 945         VMX_SEGMENT_FIELD(GS),
 946         VMX_SEGMENT_FIELD(SS),
 947         VMX_SEGMENT_FIELD(TR),
 948         VMX_SEGMENT_FIELD(LDTR),
 949 };
 950
 951 static u64 host_efer;
 952
 953 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 954
 955 /*
 956  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 957  * away by decrementing the array size.
 958  */
 959 static const u32 vmx_msr_index[] = {
 960 #ifdef CONFIG_X86_64
 961         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 962 #endif
 963         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 964 };
 965
 966 static inline bool is_page_fault(u32 intr_info)
 967 {
 968         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 969                              INTR_INFO_VALID_MASK)) ==
 970                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 971 }
 972
 973 static inline bool is_no_device(u32 intr_info)
 974 {
 975         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 976                              INTR_INFO_VALID_MASK)) ==
 977                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 978 }
 979
 980 static inline bool is_invalid_opcode(u32 intr_info)
 981 {
 982         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 983                              INTR_INFO_VALID_MASK)) ==
 984                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 985 }
 986
 987 static inline bool is_external_interrupt(u32 intr_info)
 988 {
 989         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 990                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 991 }
 992
 993 static inline bool is_machine_check(u32 intr_info)
 994 {
 995         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 996                              INTR_INFO_VALID_MASK)) ==
 997                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 998 }
 999
1000 static inline bool cpu_has_vmx_msr_bitmap(void)
1001 {
1002         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1003 }
1004
1005 static inline bool cpu_has_vmx_tpr_shadow(void)
1006 {
1007         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1008 }
1009
1010 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1011 {
1012         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1013 }
1014
1015 static inline bool cpu_has_secondary_exec_ctrls(void)
1016 {
1017         return vmcs_config.cpu_based_exec_ctrl &
1018                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1019 }
1020
1021 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1022 {
1023         return vmcs_config.cpu_based_2nd_exec_ctrl &
1024                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1025 }
1026
1027 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1028 {
1029         return vmcs_config.cpu_based_2nd_exec_ctrl &
1030                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1031 }
1032
1033 static inline bool cpu_has_vmx_apic_register_virt(void)
1034 {
1035         return vmcs_config.cpu_based_2nd_exec_ctrl &
1036                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1037 }
1038
1039 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1040 {
1041         return vmcs_config.cpu_based_2nd_exec_ctrl &
1042                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1043 }
1044
1045 static inline bool cpu_has_vmx_posted_intr(void)
1046 {
1047         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1048                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1049 }
1050
1051 static inline bool cpu_has_vmx_apicv(void)
1052 {
1053         return cpu_has_vmx_apic_register_virt() &&
1054                 cpu_has_vmx_virtual_intr_delivery() &&
1055                 cpu_has_vmx_posted_intr();
1056 }
1057
1058 static inline bool cpu_has_vmx_flexpriority(void)
1059 {
1060         return cpu_has_vmx_tpr_shadow() &&
1061                 cpu_has_vmx_virtualize_apic_accesses();
1062 }
1063
1064 static inline bool cpu_has_vmx_ept_execute_only(void)
1065 {
1066         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1067 }
1068
1069 static inline bool cpu_has_vmx_ept_2m_page(void)
1070 {
1071         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1072 }
1073
1074 static inline bool cpu_has_vmx_ept_1g_page(void)
1075 {
1076         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1077 }
1078
1079 static inline bool cpu_has_vmx_ept_4levels(void)
1080 {
1081         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1082 }
1083
1084 static inline bool cpu_has_vmx_ept_ad_bits(void)
1085 {
1086         return vmx_capability.ept & VMX_EPT_AD_BIT;
1087 }
1088
1089 static inline bool cpu_has_vmx_invept_context(void)
1090 {
1091         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1092 }
1093
1094 static inline bool cpu_has_vmx_invept_global(void)
1095 {
1096         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1097 }
1098
1099 static inline bool cpu_has_vmx_invvpid_single(void)
1100 {
1101         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1102 }
1103
1104 static inline bool cpu_has_vmx_invvpid_global(void)
1105 {
1106         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1107 }
1108
1109 static inline bool cpu_has_vmx_ept(void)
1110 {
1111         return vmcs_config.cpu_based_2nd_exec_ctrl &
1112                 SECONDARY_EXEC_ENABLE_EPT;
1113 }
1114
1115 static inline bool cpu_has_vmx_unrestricted_guest(void)
1116 {
1117         return vmcs_config.cpu_based_2nd_exec_ctrl &
1118                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1119 }
1120
1121 static inline bool cpu_has_vmx_ple(void)
1122 {
1123         return vmcs_config.cpu_based_2nd_exec_ctrl &
1124                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1125 }
1126
1127 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1128 {
1129         return flexpriority_enabled && lapic_in_kernel(vcpu);
1130 }
1131
1132 static inline bool cpu_has_vmx_vpid(void)
1133 {
1134         return vmcs_config.cpu_based_2nd_exec_ctrl &
1135                 SECONDARY_EXEC_ENABLE_VPID;
1136 }
1137
1138 static inline bool cpu_has_vmx_rdtscp(void)
1139 {
1140         return vmcs_config.cpu_based_2nd_exec_ctrl &
1141                 SECONDARY_EXEC_RDTSCP;
1142 }
1143
1144 static inline bool cpu_has_vmx_invpcid(void)
1145 {
1146         return vmcs_config.cpu_based_2nd_exec_ctrl &
1147                 SECONDARY_EXEC_ENABLE_INVPCID;
1148 }
1149
1150 static inline bool cpu_has_virtual_nmis(void)
1151 {
1152         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1153 }
1154
1155 static inline bool cpu_has_vmx_wbinvd_exit(void)
1156 {
1157         return vmcs_config.cpu_based_2nd_exec_ctrl &
1158                 SECONDARY_EXEC_WBINVD_EXITING;
1159 }
1160
1161 static inline bool cpu_has_vmx_shadow_vmcs(void)
1162 {
1163         u64 vmx_msr;
1164         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1165         /* check if the cpu supports writing r/o exit information fields */
1166         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1167                 return false;
1168
1169         return vmcs_config.cpu_based_2nd_exec_ctrl &
1170                 SECONDARY_EXEC_SHADOW_VMCS;
1171 }
1172
1173 static inline bool cpu_has_vmx_pml(void)
1174 {
1175         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1176 }
1177
1178 static inline bool cpu_has_vmx_tsc_scaling(void)
1179 {
1180         return vmcs_config.cpu_based_2nd_exec_ctrl &
1181                 SECONDARY_EXEC_TSC_SCALING;
1182 }
1183
1184 static inline bool report_flexpriority(void)
1185 {
1186         return flexpriority_enabled;
1187 }
1188
1189 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1190 {
1191         return vmcs12->cpu_based_vm_exec_control & bit;
1192 }
1193
1194 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1195 {
1196         return (vmcs12->cpu_based_vm_exec_control &
1197                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1198                 (vmcs12->secondary_vm_exec_control & bit);
1199 }
1200
1201 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1202 {
1203         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1204 }
1205
1206 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1207 {
1208         return vmcs12->pin_based_vm_exec_control &
1209                 PIN_BASED_VMX_PREEMPTION_TIMER;
1210 }
1211
1212 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1213 {
1214         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1215 }
1216
1217 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1218 {
1219         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1220                 vmx_xsaves_supported();
1221 }
1222
1223 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1224 {
1225         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1226 }
1227
1228 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1229 {
1230         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1231 }
1232
1233 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1234 {
1235         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1236 }
1237
1238 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1239 {
1240         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1241 }
1242
1243 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1244 {
1245         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1246 }
1247
1248 static inline bool is_exception(u32 intr_info)
1249 {
1250         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1251                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1252 }
1253
1254 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1255                               u32 exit_intr_info,
1256                               unsigned long exit_qualification);
1257 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1258                         struct vmcs12 *vmcs12,
1259                         u32 reason, unsigned long qualification);
1260
1261 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1262 {
1263         int i;
1264
1265         for (i = 0; i < vmx->nmsrs; ++i)
1266                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1267                         return i;
1268         return -1;
1269 }
1270
1271 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1272 {
1273     struct {
1274         u64 vpid : 16;
1275         u64 rsvd : 48;
1276         u64 gva;
1277     } operand = { vpid, 0, gva };
1278
1279     asm volatile (__ex(ASM_VMX_INVVPID)
1280                   /* CF==1 or ZF==1 --> rc = -1 */
1281                   "; ja 1f ; ud2 ; 1:"
1282                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1283 }
1284
1285 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1286 {
1287         struct {
1288                 u64 eptp, gpa;
1289         } operand = {eptp, gpa};
1290
1291         asm volatile (__ex(ASM_VMX_INVEPT)
1292                         /* CF==1 or ZF==1 --> rc = -1 */
1293                         "; ja 1f ; ud2 ; 1:\n"
1294                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1295 }
1296
1297 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1298 {
1299         int i;
1300
1301         i = __find_msr_index(vmx, msr);
1302         if (i >= 0)
1303                 return &vmx->guest_msrs[i];
1304         return NULL;
1305 }
1306
1307 static void vmcs_clear(struct vmcs *vmcs)
1308 {
1309         u64 phys_addr = __pa(vmcs);
1310         u8 error;
1311
1312         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1313                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1314                       : "cc", "memory");
1315         if (error)
1316                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1317                        vmcs, phys_addr);
1318 }
1319
1320 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1321 {
1322         vmcs_clear(loaded_vmcs->vmcs);
1323         loaded_vmcs->cpu = -1;
1324         loaded_vmcs->launched = 0;
1325 }
1326
1327 static void vmcs_load(struct vmcs *vmcs)
1328 {
1329         u64 phys_addr = __pa(vmcs);
1330         u8 error;
1331
1332         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1333                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1334                         : "cc", "memory");
1335         if (error)
1336                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1337                        vmcs, phys_addr);
1338 }
1339
1340 #ifdef CONFIG_KEXEC_CORE
1341 /*
1342  * This bitmap is used to indicate whether the vmclear
1343  * operation is enabled on all cpus. All disabled by
1344  * default.
1345  */
1346 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1347
1348 static inline void crash_enable_local_vmclear(int cpu)
1349 {
1350         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1351 }
1352
1353 static inline void crash_disable_local_vmclear(int cpu)
1354 {
1355         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1356 }
1357
1358 static inline int crash_local_vmclear_enabled(int cpu)
1359 {
1360         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1361 }
1362
1363 static void crash_vmclear_local_loaded_vmcss(void)
1364 {
1365         int cpu = raw_smp_processor_id();
1366         struct loaded_vmcs *v;
1367
1368         if (!crash_local_vmclear_enabled(cpu))
1369                 return;
1370
1371         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1372                             loaded_vmcss_on_cpu_link)
1373                 vmcs_clear(v->vmcs);
1374 }
1375 #else
1376 static inline void crash_enable_local_vmclear(int cpu) { }
1377 static inline void crash_disable_local_vmclear(int cpu) { }
1378 #endif /* CONFIG_KEXEC_CORE */
1379
1380 static void __loaded_vmcs_clear(void *arg)
1381 {
1382         struct loaded_vmcs *loaded_vmcs = arg;
1383         int cpu = raw_smp_processor_id();
1384
1385         if (loaded_vmcs->cpu != cpu)
1386                 return; /* vcpu migration can race with cpu offline */
1387         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1388                 per_cpu(current_vmcs, cpu) = NULL;
1389         crash_disable_local_vmclear(cpu);
1390         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1391
1392         /*
1393          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1394          * is before setting loaded_vmcs->vcpu to -1 which is done in
1395          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1396          * then adds the vmcs into percpu list before it is deleted.
1397          */
1398         smp_wmb();
1399
1400         loaded_vmcs_init(loaded_vmcs);
1401         crash_enable_local_vmclear(cpu);
1402 }
1403
1404 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1405 {
1406         int cpu = loaded_vmcs->cpu;
1407
1408         if (cpu != -1)
1409                 smp_call_function_single(cpu,
1410                          __loaded_vmcs_clear, loaded_vmcs, 1);
1411 }
1412
1413 static inline void vpid_sync_vcpu_single(int vpid)
1414 {
1415         if (vpid == 0)
1416                 return;
1417
1418         if (cpu_has_vmx_invvpid_single())
1419                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1420 }
1421
1422 static inline void vpid_sync_vcpu_global(void)
1423 {
1424         if (cpu_has_vmx_invvpid_global())
1425                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1426 }
1427
1428 static inline void vpid_sync_context(int vpid)
1429 {
1430         if (cpu_has_vmx_invvpid_single())
1431                 vpid_sync_vcpu_single(vpid);
1432         else
1433                 vpid_sync_vcpu_global();
1434 }
1435
1436 static inline void ept_sync_global(void)
1437 {
1438         if (cpu_has_vmx_invept_global())
1439                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1440 }
1441
1442 static inline void ept_sync_context(u64 eptp)
1443 {
1444         if (enable_ept) {
1445                 if (cpu_has_vmx_invept_context())
1446                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1447                 else
1448                         ept_sync_global();
1449         }
1450 }
1451
1452 static __always_inline void vmcs_check16(unsigned long field)
1453 {
1454         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1455                          "16-bit accessor invalid for 64-bit field");
1456         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1457                          "16-bit accessor invalid for 64-bit high field");
1458         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1459                          "16-bit accessor invalid for 32-bit high field");
1460         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1461                          "16-bit accessor invalid for natural width field");
1462 }
1463
1464 static __always_inline void vmcs_check32(unsigned long field)
1465 {
1466         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1467                          "32-bit accessor invalid for 16-bit field");
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1469                          "32-bit accessor invalid for natural width field");
1470 }
1471
1472 static __always_inline void vmcs_check64(unsigned long field)
1473 {
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1475                          "64-bit accessor invalid for 16-bit field");
1476         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1477                          "64-bit accessor invalid for 64-bit high field");
1478         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1479                          "64-bit accessor invalid for 32-bit field");
1480         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1481                          "64-bit accessor invalid for natural width field");
1482 }
1483
1484 static __always_inline void vmcs_checkl(unsigned long field)
1485 {
1486         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1487                          "Natural width accessor invalid for 16-bit field");
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1489                          "Natural width accessor invalid for 64-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491                          "Natural width accessor invalid for 64-bit high field");
1492         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493                          "Natural width accessor invalid for 32-bit field");
1494 }
1495
1496 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1497 {
1498         unsigned long value;
1499
1500         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1501                       : "=a"(value) : "d"(field) : "cc");
1502         return value;
1503 }
1504
1505 static __always_inline u16 vmcs_read16(unsigned long field)
1506 {
1507         vmcs_check16(field);
1508         return __vmcs_readl(field);
1509 }
1510
1511 static __always_inline u32 vmcs_read32(unsigned long field)
1512 {
1513         vmcs_check32(field);
1514         return __vmcs_readl(field);
1515 }
1516
1517 static __always_inline u64 vmcs_read64(unsigned long field)
1518 {
1519         vmcs_check64(field);
1520 #ifdef CONFIG_X86_64
1521         return __vmcs_readl(field);
1522 #else
1523         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1524 #endif
1525 }
1526
1527 static __always_inline unsigned long vmcs_readl(unsigned long field)
1528 {
1529         vmcs_checkl(field);
1530         return __vmcs_readl(field);
1531 }
1532
1533 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1534 {
1535         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1536                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1537         dump_stack();
1538 }
1539
1540 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1541 {
1542         u8 error;
1543
1544         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1545                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1546         if (unlikely(error))
1547                 vmwrite_error(field, value);
1548 }
1549
1550 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1551 {
1552         vmcs_check16(field);
1553         __vmcs_writel(field, value);
1554 }
1555
1556 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1557 {
1558         vmcs_check32(field);
1559         __vmcs_writel(field, value);
1560 }
1561
1562 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1563 {
1564         vmcs_check64(field);
1565         __vmcs_writel(field, value);
1566 #ifndef CONFIG_X86_64
1567         asm volatile ("");
1568         __vmcs_writel(field+1, value >> 32);
1569 #endif
1570 }
1571
1572 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1573 {
1574         vmcs_checkl(field);
1575         __vmcs_writel(field, value);
1576 }
1577
1578 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1579 {
1580         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1581                          "vmcs_clear_bits does not support 64-bit fields");
1582         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1583 }
1584
1585 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1586 {
1587         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1588                          "vmcs_set_bits does not support 64-bit fields");
1589         __vmcs_writel(field, __vmcs_readl(field) | mask);
1590 }
1591
1592 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1593 {
1594         vmcs_write32(VM_ENTRY_CONTROLS, val);
1595         vmx->vm_entry_controls_shadow = val;
1596 }
1597
1598 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1599 {
1600         if (vmx->vm_entry_controls_shadow != val)
1601                 vm_entry_controls_init(vmx, val);
1602 }
1603
1604 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1605 {
1606         return vmx->vm_entry_controls_shadow;
1607 }
1608
1609
1610 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1611 {
1612         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1613 }
1614
1615 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1616 {
1617         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1618 }
1619
1620 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1621 {
1622         vmcs_write32(VM_EXIT_CONTROLS, val);
1623         vmx->vm_exit_controls_shadow = val;
1624 }
1625
1626 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1627 {
1628         if (vmx->vm_exit_controls_shadow != val)
1629                 vm_exit_controls_init(vmx, val);
1630 }
1631
1632 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1633 {
1634         return vmx->vm_exit_controls_shadow;
1635 }
1636
1637
1638 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1639 {
1640         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1641 }
1642
1643 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1644 {
1645         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1646 }
1647
1648 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1649 {
1650         vmx->segment_cache.bitmask = 0;
1651 }
1652
1653 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1654                                        unsigned field)
1655 {
1656         bool ret;
1657         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1658
1659         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1660                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1661                 vmx->segment_cache.bitmask = 0;
1662         }
1663         ret = vmx->segment_cache.bitmask & mask;
1664         vmx->segment_cache.bitmask |= mask;
1665         return ret;
1666 }
1667
1668 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1669 {
1670         u16 *p = &vmx->segment_cache.seg[seg].selector;
1671
1672         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1673                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1674         return *p;
1675 }
1676
1677 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1678 {
1679         ulong *p = &vmx->segment_cache.seg[seg].base;
1680
1681         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1682                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1683         return *p;
1684 }
1685
1686 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1687 {
1688         u32 *p = &vmx->segment_cache.seg[seg].limit;
1689
1690         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1691                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1692         return *p;
1693 }
1694
1695 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1696 {
1697         u32 *p = &vmx->segment_cache.seg[seg].ar;
1698
1699         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1700                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1701         return *p;
1702 }
1703
1704 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1705 {
1706         u32 eb;
1707
1708         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1709              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1710         if ((vcpu->guest_debug &
1711              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1712             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1713                 eb |= 1u << BP_VECTOR;
1714         if (to_vmx(vcpu)->rmode.vm86_active)
1715                 eb = ~0;
1716         if (enable_ept)
1717                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1718         if (vcpu->fpu_active)
1719                 eb &= ~(1u << NM_VECTOR);
1720
1721         /* When we are running a nested L2 guest and L1 specified for it a
1722          * certain exception bitmap, we must trap the same exceptions and pass
1723          * them to L1. When running L2, we will only handle the exceptions
1724          * specified above if L1 did not want them.
1725          */
1726         if (is_guest_mode(vcpu))
1727                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1728
1729         vmcs_write32(EXCEPTION_BITMAP, eb);
1730 }
1731
1732 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1733                 unsigned long entry, unsigned long exit)
1734 {
1735         vm_entry_controls_clearbit(vmx, entry);
1736         vm_exit_controls_clearbit(vmx, exit);
1737 }
1738
1739 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1740 {
1741         unsigned i;
1742         struct msr_autoload *m = &vmx->msr_autoload;
1743
1744         switch (msr) {
1745         case MSR_EFER:
1746                 if (cpu_has_load_ia32_efer) {
1747                         clear_atomic_switch_msr_special(vmx,
1748                                         VM_ENTRY_LOAD_IA32_EFER,
1749                                         VM_EXIT_LOAD_IA32_EFER);
1750                         return;
1751                 }
1752                 break;
1753         case MSR_CORE_PERF_GLOBAL_CTRL:
1754                 if (cpu_has_load_perf_global_ctrl) {
1755                         clear_atomic_switch_msr_special(vmx,
1756                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1757                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1758                         return;
1759                 }
1760                 break;
1761         }
1762
1763         for (i = 0; i < m->nr; ++i)
1764                 if (m->guest[i].index == msr)
1765                         break;
1766
1767         if (i == m->nr)
1768                 return;
1769         --m->nr;
1770         m->guest[i] = m->guest[m->nr];
1771         m->host[i] = m->host[m->nr];
1772         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1773         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1774 }
1775
1776 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1777                 unsigned long entry, unsigned long exit,
1778                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1779                 u64 guest_val, u64 host_val)
1780 {
1781         vmcs_write64(guest_val_vmcs, guest_val);
1782         vmcs_write64(host_val_vmcs, host_val);
1783         vm_entry_controls_setbit(vmx, entry);
1784         vm_exit_controls_setbit(vmx, exit);
1785 }
1786
1787 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1788                                   u64 guest_val, u64 host_val)
1789 {
1790         unsigned i;
1791         struct msr_autoload *m = &vmx->msr_autoload;
1792
1793         switch (msr) {
1794         case MSR_EFER:
1795                 if (cpu_has_load_ia32_efer) {
1796                         add_atomic_switch_msr_special(vmx,
1797                                         VM_ENTRY_LOAD_IA32_EFER,
1798                                         VM_EXIT_LOAD_IA32_EFER,
1799                                         GUEST_IA32_EFER,
1800                                         HOST_IA32_EFER,
1801                                         guest_val, host_val);
1802                         return;
1803                 }
1804                 break;
1805         case MSR_CORE_PERF_GLOBAL_CTRL:
1806                 if (cpu_has_load_perf_global_ctrl) {
1807                         add_atomic_switch_msr_special(vmx,
1808                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1809                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1810                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1811                                         HOST_IA32_PERF_GLOBAL_CTRL,
1812                                         guest_val, host_val);
1813                         return;
1814                 }
1815                 break;
1816         case MSR_IA32_PEBS_ENABLE:
1817                 /* PEBS needs a quiescent period after being disabled (to write
1818                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1819                  * provide that period, so a CPU could write host's record into
1820                  * guest's memory.
1821                  */
1822                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1823         }
1824
1825         for (i = 0; i < m->nr; ++i)
1826                 if (m->guest[i].index == msr)
1827                         break;
1828
1829         if (i == NR_AUTOLOAD_MSRS) {
1830                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1831                                 "Can't add msr %x\n", msr);
1832                 return;
1833         } else if (i == m->nr) {
1834                 ++m->nr;
1835                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1836                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1837         }
1838
1839         m->guest[i].index = msr;
1840         m->guest[i].value = guest_val;
1841         m->host[i].index = msr;
1842         m->host[i].value = host_val;
1843 }
1844
1845 static void reload_tss(void)
1846 {
1847         /*
1848          * VT restores TR but not its size.  Useless.
1849          */
1850         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1851         struct desc_struct *descs;
1852
1853         descs = (void *)gdt->address;
1854         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1855         load_TR_desc();
1856 }
1857
1858 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1859 {
1860         u64 guest_efer;
1861         u64 ignore_bits;
1862
1863         guest_efer = vmx->vcpu.arch.efer;
1864
1865         /*
1866          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1867          * outside long mode
1868          */
1869         ignore_bits = EFER_NX | EFER_SCE;
1870 #ifdef CONFIG_X86_64
1871         ignore_bits |= EFER_LMA | EFER_LME;
1872         /* SCE is meaningful only in long mode on Intel */
1873         if (guest_efer & EFER_LMA)
1874                 ignore_bits &= ~(u64)EFER_SCE;
1875 #endif
1876         guest_efer &= ~ignore_bits;
1877         guest_efer |= host_efer & ignore_bits;
1878         vmx->guest_msrs[efer_offset].data = guest_efer;
1879         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1880
1881         clear_atomic_switch_msr(vmx, MSR_EFER);
1882
1883         /*
1884          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1885          * On CPUs that support "load IA32_EFER", always switch EFER
1886          * atomically, since it's faster than switching it manually.
1887          */
1888         if (cpu_has_load_ia32_efer ||
1889             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1890                 guest_efer = vmx->vcpu.arch.efer;
1891                 if (!(guest_efer & EFER_LMA))
1892                         guest_efer &= ~EFER_LME;
1893                 if (guest_efer != host_efer)
1894                         add_atomic_switch_msr(vmx, MSR_EFER,
1895                                               guest_efer, host_efer);
1896                 return false;
1897         }
1898
1899         return true;
1900 }
1901
1902 static unsigned long segment_base(u16 selector)
1903 {
1904         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1905         struct desc_struct *d;
1906         unsigned long table_base;
1907         unsigned long v;
1908
1909         if (!(selector & ~3))
1910                 return 0;
1911
1912         table_base = gdt->address;
1913
1914         if (selector & 4) {           /* from ldt */
1915                 u16 ldt_selector = kvm_read_ldt();
1916
1917                 if (!(ldt_selector & ~3))
1918                         return 0;
1919
1920                 table_base = segment_base(ldt_selector);
1921         }
1922         d = (struct desc_struct *)(table_base + (selector & ~7));
1923         v = get_desc_base(d);
1924 #ifdef CONFIG_X86_64
1925        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1926                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1927 #endif
1928         return v;
1929 }
1930
1931 static inline unsigned long kvm_read_tr_base(void)
1932 {
1933         u16 tr;
1934         asm("str %0" : "=g"(tr));
1935         return segment_base(tr);
1936 }
1937
1938 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1939 {
1940         struct vcpu_vmx *vmx = to_vmx(vcpu);
1941         int i;
1942
1943         if (vmx->host_state.loaded)
1944                 return;
1945
1946         vmx->host_state.loaded = 1;
1947         /*
1948          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1949          * allow segment selectors with cpl > 0 or ti == 1.
1950          */
1951         vmx->host_state.ldt_sel = kvm_read_ldt();
1952         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1953         savesegment(fs, vmx->host_state.fs_sel);
1954         if (!(vmx->host_state.fs_sel & 7)) {
1955                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1956                 vmx->host_state.fs_reload_needed = 0;
1957         } else {
1958                 vmcs_write16(HOST_FS_SELECTOR, 0);
1959                 vmx->host_state.fs_reload_needed = 1;
1960         }
1961         savesegment(gs, vmx->host_state.gs_sel);
1962         if (!(vmx->host_state.gs_sel & 7))
1963                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1964         else {
1965                 vmcs_write16(HOST_GS_SELECTOR, 0);
1966                 vmx->host_state.gs_ldt_reload_needed = 1;
1967         }
1968
1969 #ifdef CONFIG_X86_64
1970         savesegment(ds, vmx->host_state.ds_sel);
1971         savesegment(es, vmx->host_state.es_sel);
1972 #endif
1973
1974 #ifdef CONFIG_X86_64
1975         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1976         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1977 #else
1978         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1979         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1980 #endif
1981
1982 #ifdef CONFIG_X86_64
1983         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1984         if (is_long_mode(&vmx->vcpu))
1985                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1986 #endif
1987         if (boot_cpu_has(X86_FEATURE_MPX))
1988                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1989         for (i = 0; i < vmx->save_nmsrs; ++i)
1990                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1991                                    vmx->guest_msrs[i].data,
1992                                    vmx->guest_msrs[i].mask);
1993 }
1994
1995 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1996 {
1997         if (!vmx->host_state.loaded)
1998                 return;
1999
2000         ++vmx->vcpu.stat.host_state_reload;
2001         vmx->host_state.loaded = 0;
2002 #ifdef CONFIG_X86_64
2003         if (is_long_mode(&vmx->vcpu))
2004                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2005 #endif
2006         if (vmx->host_state.gs_ldt_reload_needed) {
2007                 kvm_load_ldt(vmx->host_state.ldt_sel);
2008 #ifdef CONFIG_X86_64
2009                 load_gs_index(vmx->host_state.gs_sel);
2010 #else
2011                 loadsegment(gs, vmx->host_state.gs_sel);
2012 #endif
2013         }
2014         if (vmx->host_state.fs_reload_needed)
2015                 loadsegment(fs, vmx->host_state.fs_sel);
2016 #ifdef CONFIG_X86_64
2017         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2018                 loadsegment(ds, vmx->host_state.ds_sel);
2019                 loadsegment(es, vmx->host_state.es_sel);
2020         }
2021 #endif
2022         reload_tss();
2023 #ifdef CONFIG_X86_64
2024         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2025 #endif
2026         if (vmx->host_state.msr_host_bndcfgs)
2027                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2028         /*
2029          * If the FPU is not active (through the host task or
2030          * the guest vcpu), then restore the cr0.TS bit.
2031          */
2032         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2033                 stts();
2034         load_gdt(this_cpu_ptr(&host_gdt));
2035 }
2036
2037 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2038 {
2039         preempt_disable();
2040         __vmx_load_host_state(vmx);
2041         preempt_enable();
2042 }
2043
2044 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2045 {
2046         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2047         struct pi_desc old, new;
2048         unsigned int dest;
2049
2050         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2051                 !irq_remapping_cap(IRQ_POSTING_CAP))
2052                 return;
2053
2054         do {
2055                 old.control = new.control = pi_desc->control;
2056
2057                 /*
2058                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2059                  * are two possible cases:
2060                  * 1. After running 'pre_block', context switch
2061                  *    happened. For this case, 'sn' was set in
2062                  *    vmx_vcpu_put(), so we need to clear it here.
2063                  * 2. After running 'pre_block', we were blocked,
2064                  *    and woken up by some other guy. For this case,
2065                  *    we don't need to do anything, 'pi_post_block'
2066                  *    will do everything for us. However, we cannot
2067                  *    check whether it is case #1 or case #2 here
2068                  *    (maybe, not needed), so we also clear sn here,
2069                  *    I think it is not a big deal.
2070                  */
2071                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2072                         if (vcpu->cpu != cpu) {
2073                                 dest = cpu_physical_id(cpu);
2074
2075                                 if (x2apic_enabled())
2076                                         new.ndst = dest;
2077                                 else
2078                                         new.ndst = (dest << 8) & 0xFF00;
2079                         }
2080
2081                         /* set 'NV' to 'notification vector' */
2082                         new.nv = POSTED_INTR_VECTOR;
2083                 }
2084
2085                 /* Allow posting non-urgent interrupts */
2086                 new.sn = 0;
2087         } while (cmpxchg(&pi_desc->control, old.control,
2088                         new.control) != old.control);
2089 }
2090 /*
2091  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2092  * vcpu mutex is already taken.
2093  */
2094 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2095 {
2096         struct vcpu_vmx *vmx = to_vmx(vcpu);
2097         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2098
2099         if (!vmm_exclusive)
2100                 kvm_cpu_vmxon(phys_addr);
2101         else if (vmx->loaded_vmcs->cpu != cpu)
2102                 loaded_vmcs_clear(vmx->loaded_vmcs);
2103
2104         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2105                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2106                 vmcs_load(vmx->loaded_vmcs->vmcs);
2107         }
2108
2109         if (vmx->loaded_vmcs->cpu != cpu) {
2110                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2111                 unsigned long sysenter_esp;
2112
2113                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2114                 local_irq_disable();
2115                 crash_disable_local_vmclear(cpu);
2116
2117                 /*
2118                  * Read loaded_vmcs->cpu should be before fetching
2119                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2120                  * See the comments in __loaded_vmcs_clear().
2121                  */
2122                 smp_rmb();
2123
2124                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2125                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2126                 crash_enable_local_vmclear(cpu);
2127                 local_irq_enable();
2128
2129                 /*
2130                  * Linux uses per-cpu TSS and GDT, so set these when switching
2131                  * processors.
2132                  */
2133                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2134                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2135
2136                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2137                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2138
2139                 vmx->loaded_vmcs->cpu = cpu;
2140         }
2141
2142         /* Setup TSC multiplier */
2143         if (kvm_has_tsc_control &&
2144             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2145                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2146                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2147         }
2148
2149         vmx_vcpu_pi_load(vcpu, cpu);
2150 }
2151
2152 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2153 {
2154         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2155
2156         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2157                 !irq_remapping_cap(IRQ_POSTING_CAP))
2158                 return;
2159
2160         /* Set SN when the vCPU is preempted */
2161         if (vcpu->preempted)
2162                 pi_set_sn(pi_desc);
2163 }
2164
2165 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2166 {
2167         vmx_vcpu_pi_put(vcpu);
2168
2169         __vmx_load_host_state(to_vmx(vcpu));
2170         if (!vmm_exclusive) {
2171                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2172                 vcpu->cpu = -1;
2173                 kvm_cpu_vmxoff();
2174         }
2175 }
2176
2177 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2178 {
2179         ulong cr0;
2180
2181         if (vcpu->fpu_active)
2182                 return;
2183         vcpu->fpu_active = 1;
2184         cr0 = vmcs_readl(GUEST_CR0);
2185         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2186         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2187         vmcs_writel(GUEST_CR0, cr0);
2188         update_exception_bitmap(vcpu);
2189         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2190         if (is_guest_mode(vcpu))
2191                 vcpu->arch.cr0_guest_owned_bits &=
2192                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2193         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2194 }
2195
2196 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2197
2198 /*
2199  * Return the cr0 value that a nested guest would read. This is a combination
2200  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2201  * its hypervisor (cr0_read_shadow).
2202  */
2203 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2204 {
2205         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2206                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2207 }
2208 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2209 {
2210         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2211                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2212 }
2213
2214 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2215 {
2216         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2217          * set this *before* calling this function.
2218          */
2219         vmx_decache_cr0_guest_bits(vcpu);
2220         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2221         update_exception_bitmap(vcpu);
2222         vcpu->arch.cr0_guest_owned_bits = 0;
2223         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2224         if (is_guest_mode(vcpu)) {
2225                 /*
2226                  * L1's specified read shadow might not contain the TS bit,
2227                  * so now that we turned on shadowing of this bit, we need to
2228                  * set this bit of the shadow. Like in nested_vmx_run we need
2229                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2230                  * up-to-date here because we just decached cr0.TS (and we'll
2231                  * only update vmcs12->guest_cr0 on nested exit).
2232                  */
2233                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2234                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2235                         (vcpu->arch.cr0 & X86_CR0_TS);
2236                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2237         } else
2238                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2239 }
2240
2241 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2242 {
2243         unsigned long rflags, save_rflags;
2244
2245         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2246                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2247                 rflags = vmcs_readl(GUEST_RFLAGS);
2248                 if (to_vmx(vcpu)->rmode.vm86_active) {
2249                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2250                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2251                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2252                 }
2253                 to_vmx(vcpu)->rflags = rflags;
2254         }
2255         return to_vmx(vcpu)->rflags;
2256 }
2257
2258 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2259 {
2260         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2261         to_vmx(vcpu)->rflags = rflags;
2262         if (to_vmx(vcpu)->rmode.vm86_active) {
2263                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2264                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2265         }
2266         vmcs_writel(GUEST_RFLAGS, rflags);
2267 }
2268
2269 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2270 {
2271         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2272         int ret = 0;
2273
2274         if (interruptibility & GUEST_INTR_STATE_STI)
2275                 ret |= KVM_X86_SHADOW_INT_STI;
2276         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2277                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2278
2279         return ret;
2280 }
2281
2282 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2283 {
2284         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2285         u32 interruptibility = interruptibility_old;
2286
2287         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2288
2289         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2290                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2291         else if (mask & KVM_X86_SHADOW_INT_STI)
2292                 interruptibility |= GUEST_INTR_STATE_STI;
2293
2294         if ((interruptibility != interruptibility_old))
2295                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2296 }
2297
2298 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2299 {
2300         unsigned long rip;
2301
2302         rip = kvm_rip_read(vcpu);
2303         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2304         kvm_rip_write(vcpu, rip);
2305
2306         /* skipping an emulated instruction also counts */
2307         vmx_set_interrupt_shadow(vcpu, 0);
2308 }
2309
2310 /*
2311  * KVM wants to inject page-faults which it got to the guest. This function
2312  * checks whether in a nested guest, we need to inject them to L1 or L2.
2313  */
2314 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2315 {
2316         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2317
2318         if (!(vmcs12->exception_bitmap & (1u << nr)))
2319                 return 0;
2320
2321         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2322                           vmcs_read32(VM_EXIT_INTR_INFO),
2323                           vmcs_readl(EXIT_QUALIFICATION));
2324         return 1;
2325 }
2326
2327 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2328                                 bool has_error_code, u32 error_code,
2329                                 bool reinject)
2330 {
2331         struct vcpu_vmx *vmx = to_vmx(vcpu);
2332         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2333
2334         if (!reinject && is_guest_mode(vcpu) &&
2335             nested_vmx_check_exception(vcpu, nr))
2336                 return;
2337
2338         if (has_error_code) {
2339                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2340                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2341         }
2342
2343         if (vmx->rmode.vm86_active) {
2344                 int inc_eip = 0;
2345                 if (kvm_exception_is_soft(nr))
2346                         inc_eip = vcpu->arch.event_exit_inst_len;
2347                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2348                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2349                 return;
2350         }
2351
2352         if (kvm_exception_is_soft(nr)) {
2353                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2354                              vmx->vcpu.arch.event_exit_inst_len);
2355                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2356         } else
2357                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2358
2359         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2360 }
2361
2362 static bool vmx_rdtscp_supported(void)
2363 {
2364         return cpu_has_vmx_rdtscp();
2365 }
2366
2367 static bool vmx_invpcid_supported(void)
2368 {
2369         return cpu_has_vmx_invpcid() && enable_ept;
2370 }
2371
2372 /*
2373  * Swap MSR entry in host/guest MSR entry array.
2374  */
2375 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2376 {
2377         struct shared_msr_entry tmp;
2378
2379         tmp = vmx->guest_msrs[to];
2380         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2381         vmx->guest_msrs[from] = tmp;
2382 }
2383
2384 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2385 {
2386         unsigned long *msr_bitmap;
2387
2388         if (is_guest_mode(vcpu))
2389                 msr_bitmap = vmx_msr_bitmap_nested;
2390         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2391                 if (is_long_mode(vcpu))
2392                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2393                 else
2394                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2395         } else {
2396                 if (is_long_mode(vcpu))
2397                         msr_bitmap = vmx_msr_bitmap_longmode;
2398                 else
2399                         msr_bitmap = vmx_msr_bitmap_legacy;
2400         }
2401
2402         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2403 }
2404
2405 /*
2406  * Set up the vmcs to automatically save and restore system
2407  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2408  * mode, as fiddling with msrs is very expensive.
2409  */
2410 static void setup_msrs(struct vcpu_vmx *vmx)
2411 {
2412         int save_nmsrs, index;
2413
2414         save_nmsrs = 0;
2415 #ifdef CONFIG_X86_64
2416         if (is_long_mode(&vmx->vcpu)) {
2417                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2418                 if (index >= 0)
2419                         move_msr_up(vmx, index, save_nmsrs++);
2420                 index = __find_msr_index(vmx, MSR_LSTAR);
2421                 if (index >= 0)
2422                         move_msr_up(vmx, index, save_nmsrs++);
2423                 index = __find_msr_index(vmx, MSR_CSTAR);
2424                 if (index >= 0)
2425                         move_msr_up(vmx, index, save_nmsrs++);
2426                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2427                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2428                         move_msr_up(vmx, index, save_nmsrs++);
2429                 /*
2430                  * MSR_STAR is only needed on long mode guests, and only
2431                  * if efer.sce is enabled.
2432                  */
2433                 index = __find_msr_index(vmx, MSR_STAR);
2434                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2435                         move_msr_up(vmx, index, save_nmsrs++);
2436         }
2437 #endif
2438         index = __find_msr_index(vmx, MSR_EFER);
2439         if (index >= 0 && update_transition_efer(vmx, index))
2440                 move_msr_up(vmx, index, save_nmsrs++);
2441
2442         vmx->save_nmsrs = save_nmsrs;
2443
2444         if (cpu_has_vmx_msr_bitmap())
2445                 vmx_set_msr_bitmap(&vmx->vcpu);
2446 }
2447
2448 /*
2449  * reads and returns guest's timestamp counter "register"
2450  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2451  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2452  */
2453 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2454 {
2455         u64 host_tsc, tsc_offset;
2456
2457         host_tsc = rdtsc();
2458         tsc_offset = vmcs_read64(TSC_OFFSET);
2459         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2460 }
2461
2462 /*
2463  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2464  * counter, even if a nested guest (L2) is currently running.
2465  */
2466 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2467 {
2468         u64 tsc_offset;
2469
2470         tsc_offset = is_guest_mode(vcpu) ?
2471                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2472                 vmcs_read64(TSC_OFFSET);
2473         return host_tsc + tsc_offset;
2474 }
2475
2476 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2477 {
2478         return vmcs_read64(TSC_OFFSET);
2479 }
2480
2481 /*
2482  * writes 'offset' into guest's timestamp counter offset register
2483  */
2484 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2485 {
2486         if (is_guest_mode(vcpu)) {
2487                 /*
2488                  * We're here if L1 chose not to trap WRMSR to TSC. According
2489                  * to the spec, this should set L1's TSC; The offset that L1
2490                  * set for L2 remains unchanged, and still needs to be added
2491                  * to the newly set TSC to get L2's TSC.
2492                  */
2493                 struct vmcs12 *vmcs12;
2494                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2495                 /* recalculate vmcs02.TSC_OFFSET: */
2496                 vmcs12 = get_vmcs12(vcpu);
2497                 vmcs_write64(TSC_OFFSET, offset +
2498                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2499                          vmcs12->tsc_offset : 0));
2500         } else {
2501                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2502                                            vmcs_read64(TSC_OFFSET), offset);
2503                 vmcs_write64(TSC_OFFSET, offset);
2504         }
2505 }
2506
2507 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2508 {
2509         u64 offset = vmcs_read64(TSC_OFFSET);
2510
2511         vmcs_write64(TSC_OFFSET, offset + adjustment);
2512         if (is_guest_mode(vcpu)) {
2513                 /* Even when running L2, the adjustment needs to apply to L1 */
2514                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2515         } else
2516                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2517                                            offset + adjustment);
2518 }
2519
2520 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2521 {
2522         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2523         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2524 }
2525
2526 /*
2527  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2528  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2529  * all guests if the "nested" module option is off, and can also be disabled
2530  * for a single guest by disabling its VMX cpuid bit.
2531  */
2532 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2533 {
2534         return nested && guest_cpuid_has_vmx(vcpu);
2535 }
2536
2537 /*
2538  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2539  * returned for the various VMX controls MSRs when nested VMX is enabled.
2540  * The same values should also be used to verify that vmcs12 control fields are
2541  * valid during nested entry from L1 to L2.
2542  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2543  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2544  * bit in the high half is on if the corresponding bit in the control field
2545  * may be on. See also vmx_control_verify().
2546  */
2547 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2548 {
2549         /*
2550          * Note that as a general rule, the high half of the MSRs (bits in
2551          * the control fields which may be 1) should be initialized by the
2552          * intersection of the underlying hardware's MSR (i.e., features which
2553          * can be supported) and the list of features we want to expose -
2554          * because they are known to be properly supported in our code.
2555          * Also, usually, the low half of the MSRs (bits which must be 1) can
2556          * be set to 0, meaning that L1 may turn off any of these bits. The
2557          * reason is that if one of these bits is necessary, it will appear
2558          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2559          * fields of vmcs01 and vmcs02, will turn these bits off - and
2560          * nested_vmx_exit_handled() will not pass related exits to L1.
2561          * These rules have exceptions below.
2562          */
2563
2564         /* pin-based controls */
2565         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2566                 vmx->nested.nested_vmx_pinbased_ctls_low,
2567                 vmx->nested.nested_vmx_pinbased_ctls_high);
2568         vmx->nested.nested_vmx_pinbased_ctls_low |=
2569                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2570         vmx->nested.nested_vmx_pinbased_ctls_high &=
2571                 PIN_BASED_EXT_INTR_MASK |
2572                 PIN_BASED_NMI_EXITING |
2573                 PIN_BASED_VIRTUAL_NMIS;
2574         vmx->nested.nested_vmx_pinbased_ctls_high |=
2575                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2576                 PIN_BASED_VMX_PREEMPTION_TIMER;
2577         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2578                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2579                         PIN_BASED_POSTED_INTR;
2580
2581         /* exit controls */
2582         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2583                 vmx->nested.nested_vmx_exit_ctls_low,
2584                 vmx->nested.nested_vmx_exit_ctls_high);
2585         vmx->nested.nested_vmx_exit_ctls_low =
2586                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2587
2588         vmx->nested.nested_vmx_exit_ctls_high &=
2589 #ifdef CONFIG_X86_64
2590                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2591 #endif
2592                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2593         vmx->nested.nested_vmx_exit_ctls_high |=
2594                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2595                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2596                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2597
2598         if (vmx_mpx_supported())
2599                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2600
2601         /* We support free control of debug control saving. */
2602         vmx->nested.nested_vmx_true_exit_ctls_low =
2603                 vmx->nested.nested_vmx_exit_ctls_low &
2604                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2605
2606         /* entry controls */
2607         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2608                 vmx->nested.nested_vmx_entry_ctls_low,
2609                 vmx->nested.nested_vmx_entry_ctls_high);
2610         vmx->nested.nested_vmx_entry_ctls_low =
2611                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2612         vmx->nested.nested_vmx_entry_ctls_high &=
2613 #ifdef CONFIG_X86_64
2614                 VM_ENTRY_IA32E_MODE |
2615 #endif
2616                 VM_ENTRY_LOAD_IA32_PAT;
2617         vmx->nested.nested_vmx_entry_ctls_high |=
2618                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2619         if (vmx_mpx_supported())
2620                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2621
2622         /* We support free control of debug control loading. */
2623         vmx->nested.nested_vmx_true_entry_ctls_low =
2624                 vmx->nested.nested_vmx_entry_ctls_low &
2625                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2626
2627         /* cpu-based controls */
2628         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2629                 vmx->nested.nested_vmx_procbased_ctls_low,
2630                 vmx->nested.nested_vmx_procbased_ctls_high);
2631         vmx->nested.nested_vmx_procbased_ctls_low =
2632                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2633         vmx->nested.nested_vmx_procbased_ctls_high &=
2634                 CPU_BASED_VIRTUAL_INTR_PENDING |
2635                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2636                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2637                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2638                 CPU_BASED_CR3_STORE_EXITING |
2639 #ifdef CONFIG_X86_64
2640                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2641 #endif
2642                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2643                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2644                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2645                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2646                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2647         /*
2648          * We can allow some features even when not supported by the
2649          * hardware. For example, L1 can specify an MSR bitmap - and we
2650          * can use it to avoid exits to L1 - even when L0 runs L2
2651          * without MSR bitmaps.
2652          */
2653         vmx->nested.nested_vmx_procbased_ctls_high |=
2654                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2655                 CPU_BASED_USE_MSR_BITMAPS;
2656
2657         /* We support free control of CR3 access interception. */
2658         vmx->nested.nested_vmx_true_procbased_ctls_low =
2659                 vmx->nested.nested_vmx_procbased_ctls_low &
2660                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2661
2662         /* secondary cpu-based controls */
2663         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2664                 vmx->nested.nested_vmx_secondary_ctls_low,
2665                 vmx->nested.nested_vmx_secondary_ctls_high);
2666         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2667         vmx->nested.nested_vmx_secondary_ctls_high &=
2668                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2669                 SECONDARY_EXEC_RDTSCP |
2670                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2671                 SECONDARY_EXEC_ENABLE_VPID |
2672                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2673                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2674                 SECONDARY_EXEC_WBINVD_EXITING |
2675                 SECONDARY_EXEC_XSAVES |
2676                 SECONDARY_EXEC_PCOMMIT;
2677
2678         if (enable_ept) {
2679                 /* nested EPT: emulate EPT also to L1 */
2680                 vmx->nested.nested_vmx_secondary_ctls_high |=
2681                         SECONDARY_EXEC_ENABLE_EPT;
2682                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2683                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2684                          VMX_EPT_INVEPT_BIT;
2685                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2686                 /*
2687                  * For nested guests, we don't do anything specific
2688                  * for single context invalidation. Hence, only advertise
2689                  * support for global context invalidation.
2690                  */
2691                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2692         } else
2693                 vmx->nested.nested_vmx_ept_caps = 0;
2694
2695         if (enable_vpid)
2696                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2697                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2698         else
2699                 vmx->nested.nested_vmx_vpid_caps = 0;
2700
2701         if (enable_unrestricted_guest)
2702                 vmx->nested.nested_vmx_secondary_ctls_high |=
2703                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2704
2705         /* miscellaneous data */
2706         rdmsr(MSR_IA32_VMX_MISC,
2707                 vmx->nested.nested_vmx_misc_low,
2708                 vmx->nested.nested_vmx_misc_high);
2709         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2710         vmx->nested.nested_vmx_misc_low |=
2711                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2712                 VMX_MISC_ACTIVITY_HLT;
2713         vmx->nested.nested_vmx_misc_high = 0;
2714 }
2715
2716 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2717 {
2718         /*
2719          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2720          */
2721         return ((control & high) | low) == control;
2722 }
2723
2724 static inline u64 vmx_control_msr(u32 low, u32 high)
2725 {
2726         return low | ((u64)high << 32);
2727 }
2728
2729 /* Returns 0 on success, non-0 otherwise. */
2730 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2731 {
2732         struct vcpu_vmx *vmx = to_vmx(vcpu);
2733
2734         switch (msr_index) {
2735         case MSR_IA32_VMX_BASIC:
2736                 /*
2737                  * This MSR reports some information about VMX support. We
2738                  * should return information about the VMX we emulate for the
2739                  * guest, and the VMCS structure we give it - not about the
2740                  * VMX support of the underlying hardware.
2741                  */
2742                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2743                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2744                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2745                 break;
2746         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2747         case MSR_IA32_VMX_PINBASED_CTLS:
2748                 *pdata = vmx_control_msr(
2749                         vmx->nested.nested_vmx_pinbased_ctls_low,
2750                         vmx->nested.nested_vmx_pinbased_ctls_high);
2751                 break;
2752         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2753                 *pdata = vmx_control_msr(
2754                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2755                         vmx->nested.nested_vmx_procbased_ctls_high);
2756                 break;
2757         case MSR_IA32_VMX_PROCBASED_CTLS:
2758                 *pdata = vmx_control_msr(
2759                         vmx->nested.nested_vmx_procbased_ctls_low,
2760                         vmx->nested.nested_vmx_procbased_ctls_high);
2761                 break;
2762         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2763                 *pdata = vmx_control_msr(
2764                         vmx->nested.nested_vmx_true_exit_ctls_low,
2765                         vmx->nested.nested_vmx_exit_ctls_high);
2766                 break;
2767         case MSR_IA32_VMX_EXIT_CTLS:
2768                 *pdata = vmx_control_msr(
2769                         vmx->nested.nested_vmx_exit_ctls_low,
2770                         vmx->nested.nested_vmx_exit_ctls_high);
2771                 break;
2772         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2773                 *pdata = vmx_control_msr(
2774                         vmx->nested.nested_vmx_true_entry_ctls_low,
2775                         vmx->nested.nested_vmx_entry_ctls_high);
2776                 break;
2777         case MSR_IA32_VMX_ENTRY_CTLS:
2778                 *pdata = vmx_control_msr(
2779                         vmx->nested.nested_vmx_entry_ctls_low,
2780                         vmx->nested.nested_vmx_entry_ctls_high);
2781                 break;
2782         case MSR_IA32_VMX_MISC:
2783                 *pdata = vmx_control_msr(
2784                         vmx->nested.nested_vmx_misc_low,
2785                         vmx->nested.nested_vmx_misc_high);
2786                 break;
2787         /*
2788          * These MSRs specify bits which the guest must keep fixed (on or off)
2789          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2790          * We picked the standard core2 setting.
2791          */
2792 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2793 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2794         case MSR_IA32_VMX_CR0_FIXED0:
2795                 *pdata = VMXON_CR0_ALWAYSON;
2796                 break;
2797         case MSR_IA32_VMX_CR0_FIXED1:
2798                 *pdata = -1ULL;
2799                 break;
2800         case MSR_IA32_VMX_CR4_FIXED0:
2801                 *pdata = VMXON_CR4_ALWAYSON;
2802                 break;
2803         case MSR_IA32_VMX_CR4_FIXED1:
2804                 *pdata = -1ULL;
2805                 break;
2806         case MSR_IA32_VMX_VMCS_ENUM:
2807                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2808                 break;
2809         case MSR_IA32_VMX_PROCBASED_CTLS2:
2810                 *pdata = vmx_control_msr(
2811                         vmx->nested.nested_vmx_secondary_ctls_low,
2812                         vmx->nested.nested_vmx_secondary_ctls_high);
2813                 break;
2814         case MSR_IA32_VMX_EPT_VPID_CAP:
2815                 /* Currently, no nested vpid support */
2816                 *pdata = vmx->nested.nested_vmx_ept_caps |
2817                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2818                 break;
2819         default:
2820                 return 1;
2821         }
2822
2823         return 0;
2824 }
2825
2826 /*
2827  * Reads an msr value (of 'msr_index') into 'pdata'.
2828  * Returns 0 on success, non-0 otherwise.
2829  * Assumes vcpu_load() was already called.
2830  */
2831 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2832 {
2833         struct shared_msr_entry *msr;
2834
2835         switch (msr_info->index) {
2836 #ifdef CONFIG_X86_64
2837         case MSR_FS_BASE:
2838                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2839                 break;
2840         case MSR_GS_BASE:
2841                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2842                 break;
2843         case MSR_KERNEL_GS_BASE:
2844                 vmx_load_host_state(to_vmx(vcpu));
2845                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2846                 break;
2847 #endif
2848         case MSR_EFER:
2849                 return kvm_get_msr_common(vcpu, msr_info);
2850         case MSR_IA32_TSC:
2851                 msr_info->data = guest_read_tsc(vcpu);
2852                 break;
2853         case MSR_IA32_SYSENTER_CS:
2854                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2855                 break;
2856         case MSR_IA32_SYSENTER_EIP:
2857                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2858                 break;
2859         case MSR_IA32_SYSENTER_ESP:
2860                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2861                 break;
2862         case MSR_IA32_BNDCFGS:
2863                 if (!vmx_mpx_supported())
2864                         return 1;
2865                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2866                 break;
2867         case MSR_IA32_FEATURE_CONTROL:
2868                 if (!nested_vmx_allowed(vcpu))
2869                         return 1;
2870                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2871                 break;
2872         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2873                 if (!nested_vmx_allowed(vcpu))
2874                         return 1;
2875                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2876         case MSR_IA32_XSS:
2877                 if (!vmx_xsaves_supported())
2878                         return 1;
2879                 msr_info->data = vcpu->arch.ia32_xss;
2880                 break;
2881         case MSR_TSC_AUX:
2882                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2883                         return 1;
2884                 /* Otherwise falls through */
2885         default:
2886                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2887                 if (msr) {
2888                         msr_info->data = msr->data;
2889                         break;
2890                 }
2891                 return kvm_get_msr_common(vcpu, msr_info);
2892         }
2893
2894         return 0;
2895 }
2896
2897 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2898
2899 /*
2900  * Writes msr value into into the appropriate "register".
2901  * Returns 0 on success, non-0 otherwise.
2902  * Assumes vcpu_load() was already called.
2903  */
2904 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2905 {
2906         struct vcpu_vmx *vmx = to_vmx(vcpu);
2907         struct shared_msr_entry *msr;
2908         int ret = 0;
2909         u32 msr_index = msr_info->index;
2910         u64 data = msr_info->data;
2911
2912         switch (msr_index) {
2913         case MSR_EFER:
2914                 ret = kvm_set_msr_common(vcpu, msr_info);
2915                 break;
2916 #ifdef CONFIG_X86_64
2917         case MSR_FS_BASE:
2918                 vmx_segment_cache_clear(vmx);
2919                 vmcs_writel(GUEST_FS_BASE, data);
2920                 break;
2921         case MSR_GS_BASE:
2922                 vmx_segment_cache_clear(vmx);
2923                 vmcs_writel(GUEST_GS_BASE, data);
2924                 break;
2925         case MSR_KERNEL_GS_BASE:
2926                 vmx_load_host_state(vmx);
2927                 vmx->msr_guest_kernel_gs_base = data;
2928                 break;
2929 #endif
2930         case MSR_IA32_SYSENTER_CS:
2931                 vmcs_write32(GUEST_SYSENTER_CS, data);
2932                 break;
2933         case MSR_IA32_SYSENTER_EIP:
2934                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2935                 break;
2936         case MSR_IA32_SYSENTER_ESP:
2937                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2938                 break;
2939         case MSR_IA32_BNDCFGS:
2940                 if (!vmx_mpx_supported())
2941                         return 1;
2942                 vmcs_write64(GUEST_BNDCFGS, data);
2943                 break;
2944         case MSR_IA32_TSC:
2945                 kvm_write_tsc(vcpu, msr_info);
2946                 break;
2947         case MSR_IA32_CR_PAT:
2948                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2949                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2950                                 return 1;
2951                         vmcs_write64(GUEST_IA32_PAT, data);
2952                         vcpu->arch.pat = data;
2953                         break;
2954                 }
2955                 ret = kvm_set_msr_common(vcpu, msr_info);
2956                 break;
2957         case MSR_IA32_TSC_ADJUST:
2958                 ret = kvm_set_msr_common(vcpu, msr_info);
2959                 break;
2960         case MSR_IA32_FEATURE_CONTROL:
2961                 if (!nested_vmx_allowed(vcpu) ||
2962                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2963                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2964                         return 1;
2965                 vmx->nested.msr_ia32_feature_control = data;
2966                 if (msr_info->host_initiated && data == 0)
2967                         vmx_leave_nested(vcpu);
2968                 break;
2969         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2970                 return 1; /* they are read-only */
2971         case MSR_IA32_XSS:
2972                 if (!vmx_xsaves_supported())
2973                         return 1;
2974                 /*
2975                  * The only supported bit as of Skylake is bit 8, but
2976                  * it is not supported on KVM.
2977                  */
2978                 if (data != 0)
2979                         return 1;
2980                 vcpu->arch.ia32_xss = data;
2981                 if (vcpu->arch.ia32_xss != host_xss)
2982                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2983                                 vcpu->arch.ia32_xss, host_xss);
2984                 else
2985                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2986                 break;
2987         case MSR_TSC_AUX:
2988                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2989                         return 1;
2990                 /* Check reserved bit, higher 32 bits should be zero */
2991                 if ((data >> 32) != 0)
2992                         return 1;
2993                 /* Otherwise falls through */
2994         default:
2995                 msr = find_msr_entry(vmx, msr_index);
2996                 if (msr) {
2997                         u64 old_msr_data = msr->data;
2998                         msr->data = data;
2999                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3000                                 preempt_disable();
3001                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3002                                                          msr->mask);
3003                                 preempt_enable();
3004                                 if (ret)
3005                                         msr->data = old_msr_data;
3006                         }
3007                         break;
3008                 }
3009                 ret = kvm_set_msr_common(vcpu, msr_info);
3010         }
3011
3012         return ret;
3013 }
3014
3015 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3016 {
3017         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3018         switch (reg) {
3019         case VCPU_REGS_RSP:
3020                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3021                 break;
3022         case VCPU_REGS_RIP:
3023                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3024                 break;
3025         case VCPU_EXREG_PDPTR:
3026                 if (enable_ept)
3027                         ept_save_pdptrs(vcpu);
3028                 break;
3029         default:
3030                 break;
3031         }
3032 }
3033
3034 static __init int cpu_has_kvm_support(void)
3035 {
3036         return cpu_has_vmx();
3037 }
3038
3039 static __init int vmx_disabled_by_bios(void)
3040 {
3041         u64 msr;
3042
3043         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3044         if (msr & FEATURE_CONTROL_LOCKED) {
3045                 /* launched w/ TXT and VMX disabled */
3046                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3047                         && tboot_enabled())
3048                         return 1;
3049                 /* launched w/o TXT and VMX only enabled w/ TXT */
3050                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3051                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3052                         && !tboot_enabled()) {
3053                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3054                                 "activate TXT before enabling KVM\n");
3055                         return 1;
3056                 }
3057                 /* launched w/o TXT and VMX disabled */
3058                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3059                         && !tboot_enabled())
3060                         return 1;
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void kvm_cpu_vmxon(u64 addr)
3067 {
3068         asm volatile (ASM_VMX_VMXON_RAX
3069                         : : "a"(&addr), "m"(addr)
3070                         : "memory", "cc");
3071 }
3072
3073 static int hardware_enable(void)
3074 {
3075         int cpu = raw_smp_processor_id();
3076         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3077         u64 old, test_bits;
3078
3079         if (cr4_read_shadow() & X86_CR4_VMXE)
3080                 return -EBUSY;
3081
3082         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3083         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3084         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3085
3086         /*
3087          * Now we can enable the vmclear operation in kdump
3088          * since the loaded_vmcss_on_cpu list on this cpu
3089          * has been initialized.
3090          *
3091          * Though the cpu is not in VMX operation now, there
3092          * is no problem to enable the vmclear operation
3093          * for the loaded_vmcss_on_cpu list is empty!
3094          */
3095         crash_enable_local_vmclear(cpu);
3096
3097         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3098
3099         test_bits = FEATURE_CONTROL_LOCKED;
3100         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3101         if (tboot_enabled())
3102                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3103
3104         if ((old & test_bits) != test_bits) {
3105                 /* enable and lock */
3106                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3107         }
3108         cr4_set_bits(X86_CR4_VMXE);
3109
3110         if (vmm_exclusive) {
3111                 kvm_cpu_vmxon(phys_addr);
3112                 ept_sync_global();
3113         }
3114
3115         native_store_gdt(this_cpu_ptr(&host_gdt));
3116
3117         return 0;
3118 }
3119
3120 static void vmclear_local_loaded_vmcss(void)
3121 {
3122         int cpu = raw_smp_processor_id();
3123         struct loaded_vmcs *v, *n;
3124
3125         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3126                                  loaded_vmcss_on_cpu_link)
3127                 __loaded_vmcs_clear(v);
3128 }
3129
3130
3131 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3132  * tricks.
3133  */
3134 static void kvm_cpu_vmxoff(void)
3135 {
3136         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3137 }
3138
3139 static void hardware_disable(void)
3140 {
3141         if (vmm_exclusive) {
3142                 vmclear_local_loaded_vmcss();
3143                 kvm_cpu_vmxoff();
3144         }
3145         cr4_clear_bits(X86_CR4_VMXE);
3146 }
3147
3148 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3149                                       u32 msr, u32 *result)
3150 {
3151         u32 vmx_msr_low, vmx_msr_high;
3152         u32 ctl = ctl_min | ctl_opt;
3153
3154         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3155
3156         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3157         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3158
3159         /* Ensure minimum (required) set of control bits are supported. */
3160         if (ctl_min & ~ctl)
3161                 return -EIO;
3162
3163         *result = ctl;
3164         return 0;
3165 }
3166
3167 static __init bool allow_1_setting(u32 msr, u32 ctl)
3168 {
3169         u32 vmx_msr_low, vmx_msr_high;
3170
3171         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3172         return vmx_msr_high & ctl;
3173 }
3174
3175 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3176 {
3177         u32 vmx_msr_low, vmx_msr_high;
3178         u32 min, opt, min2, opt2;
3179         u32 _pin_based_exec_control = 0;
3180         u32 _cpu_based_exec_control = 0;
3181         u32 _cpu_based_2nd_exec_control = 0;
3182         u32 _vmexit_control = 0;
3183         u32 _vmentry_control = 0;
3184
3185         min = CPU_BASED_HLT_EXITING |
3186 #ifdef CONFIG_X86_64
3187               CPU_BASED_CR8_LOAD_EXITING |
3188               CPU_BASED_CR8_STORE_EXITING |
3189 #endif
3190               CPU_BASED_CR3_LOAD_EXITING |
3191               CPU_BASED_CR3_STORE_EXITING |
3192               CPU_BASED_USE_IO_BITMAPS |
3193               CPU_BASED_MOV_DR_EXITING |
3194               CPU_BASED_USE_TSC_OFFSETING |
3195               CPU_BASED_MWAIT_EXITING |
3196               CPU_BASED_MONITOR_EXITING |
3197               CPU_BASED_INVLPG_EXITING |
3198               CPU_BASED_RDPMC_EXITING;
3199
3200         opt = CPU_BASED_TPR_SHADOW |
3201               CPU_BASED_USE_MSR_BITMAPS |
3202               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3203         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3204                                 &_cpu_based_exec_control) < 0)
3205                 return -EIO;
3206 #ifdef CONFIG_X86_64
3207         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3208                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3209                                            ~CPU_BASED_CR8_STORE_EXITING;
3210 #endif
3211         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3212                 min2 = 0;
3213                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3214                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3215                         SECONDARY_EXEC_WBINVD_EXITING |
3216                         SECONDARY_EXEC_ENABLE_VPID |
3217                         SECONDARY_EXEC_ENABLE_EPT |
3218                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3219                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3220                         SECONDARY_EXEC_RDTSCP |
3221                         SECONDARY_EXEC_ENABLE_INVPCID |
3222                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3223                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3224                         SECONDARY_EXEC_SHADOW_VMCS |
3225                         SECONDARY_EXEC_XSAVES |
3226                         SECONDARY_EXEC_ENABLE_PML |
3227                         SECONDARY_EXEC_PCOMMIT |
3228                         SECONDARY_EXEC_TSC_SCALING;
3229                 if (adjust_vmx_controls(min2, opt2,
3230                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3231                                         &_cpu_based_2nd_exec_control) < 0)
3232                         return -EIO;
3233         }
3234 #ifndef CONFIG_X86_64
3235         if (!(_cpu_based_2nd_exec_control &
3236                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3237                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3238 #endif
3239
3240         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3241                 _cpu_based_2nd_exec_control &= ~(
3242                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3243                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3244                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3245
3246         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3247                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3248                    enabled */
3249                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3250                                              CPU_BASED_CR3_STORE_EXITING |
3251                                              CPU_BASED_INVLPG_EXITING);
3252                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3253                       vmx_capability.ept, vmx_capability.vpid);
3254         }
3255
3256         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3257 #ifdef CONFIG_X86_64
3258         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3259 #endif
3260         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3261                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3262         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3263                                 &_vmexit_control) < 0)
3264                 return -EIO;
3265
3266         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3267         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3268         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3269                                 &_pin_based_exec_control) < 0)
3270                 return -EIO;
3271
3272         if (!(_cpu_based_2nd_exec_control &
3273                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3274                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3275                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3276
3277         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3278         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3279         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3280                                 &_vmentry_control) < 0)
3281                 return -EIO;
3282
3283         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3284
3285         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3286         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3287                 return -EIO;
3288
3289 #ifdef CONFIG_X86_64
3290         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3291         if (vmx_msr_high & (1u<<16))
3292                 return -EIO;
3293 #endif
3294
3295         /* Require Write-Back (WB) memory type for VMCS accesses. */
3296         if (((vmx_msr_high >> 18) & 15) != 6)
3297                 return -EIO;
3298
3299         vmcs_conf->size = vmx_msr_high & 0x1fff;
3300         vmcs_conf->order = get_order(vmcs_config.size);
3301         vmcs_conf->revision_id = vmx_msr_low;
3302
3303         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3304         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3305         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3306         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3307         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3308
3309         cpu_has_load_ia32_efer =
3310                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3311                                 VM_ENTRY_LOAD_IA32_EFER)
3312                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3313                                    VM_EXIT_LOAD_IA32_EFER);
3314
3315         cpu_has_load_perf_global_ctrl =
3316                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3317                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3318                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3319                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3320
3321         /*
3322          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3323          * but due to arrata below it can't be used. Workaround is to use
3324          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3325          *
3326          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3327          *
3328          * AAK155             (model 26)
3329          * AAP115             (model 30)
3330          * AAT100             (model 37)
3331          * BC86,AAY89,BD102   (model 44)
3332          * BA97               (model 46)
3333          *
3334          */
3335         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3336                 switch (boot_cpu_data.x86_model) {
3337                 case 26:
3338                 case 30:
3339                 case 37:
3340                 case 44:
3341                 case 46:
3342                         cpu_has_load_perf_global_ctrl = false;
3343                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3344                                         "does not work properly. Using workaround\n");
3345                         break;
3346                 default:
3347                         break;
3348                 }
3349         }
3350
3351         if (cpu_has_xsaves)
3352                 rdmsrl(MSR_IA32_XSS, host_xss);
3353
3354         return 0;
3355 }
3356
3357 static struct vmcs *alloc_vmcs_cpu(int cpu)
3358 {
3359         int node = cpu_to_node(cpu);
3360         struct page *pages;
3361         struct vmcs *vmcs;
3362
3363         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3364         if (!pages)
3365                 return NULL;
3366         vmcs = page_address(pages);
3367         memset(vmcs, 0, vmcs_config.size);
3368         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3369         return vmcs;
3370 }
3371
3372 static struct vmcs *alloc_vmcs(void)
3373 {
3374         return alloc_vmcs_cpu(raw_smp_processor_id());
3375 }
3376
3377 static void free_vmcs(struct vmcs *vmcs)
3378 {
3379         free_pages((unsigned long)vmcs, vmcs_config.order);
3380 }
3381
3382 /*
3383  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3384  */
3385 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3386 {
3387         if (!loaded_vmcs->vmcs)
3388                 return;
3389         loaded_vmcs_clear(loaded_vmcs);
3390         free_vmcs(loaded_vmcs->vmcs);
3391         loaded_vmcs->vmcs = NULL;
3392 }
3393
3394 static void free_kvm_area(void)
3395 {
3396         int cpu;
3397
3398         for_each_possible_cpu(cpu) {
3399                 free_vmcs(per_cpu(vmxarea, cpu));
3400                 per_cpu(vmxarea, cpu) = NULL;
3401         }
3402 }
3403
3404 static void init_vmcs_shadow_fields(void)
3405 {
3406         int i, j;
3407
3408         /* No checks for read only fields yet */
3409
3410         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3411                 switch (shadow_read_write_fields[i]) {
3412                 case GUEST_BNDCFGS:
3413                         if (!vmx_mpx_supported())
3414                                 continue;
3415                         break;
3416                 default:
3417                         break;
3418                 }
3419
3420                 if (j < i)
3421                         shadow_read_write_fields[j] =
3422                                 shadow_read_write_fields[i];
3423                 j++;
3424         }
3425         max_shadow_read_write_fields = j;
3426
3427         /* shadowed fields guest access without vmexit */
3428         for (i = 0; i < max_shadow_read_write_fields; i++) {
3429                 clear_bit(shadow_read_write_fields[i],
3430                           vmx_vmwrite_bitmap);
3431                 clear_bit(shadow_read_write_fields[i],
3432                           vmx_vmread_bitmap);
3433         }
3434         for (i = 0; i < max_shadow_read_only_fields; i++)
3435                 clear_bit(shadow_read_only_fields[i],
3436                           vmx_vmread_bitmap);
3437 }
3438
3439 static __init int alloc_kvm_area(void)
3440 {
3441         int cpu;
3442
3443         for_each_possible_cpu(cpu) {
3444                 struct vmcs *vmcs;
3445
3446                 vmcs = alloc_vmcs_cpu(cpu);
3447                 if (!vmcs) {
3448                         free_kvm_area();
3449                         return -ENOMEM;
3450                 }
3451
3452                 per_cpu(vmxarea, cpu) = vmcs;
3453         }
3454         return 0;
3455 }
3456
3457 static bool emulation_required(struct kvm_vcpu *vcpu)
3458 {
3459         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3460 }
3461
3462 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3463                 struct kvm_segment *save)
3464 {
3465         if (!emulate_invalid_guest_state) {
3466                 /*
3467                  * CS and SS RPL should be equal during guest entry according
3468                  * to VMX spec, but in reality it is not always so. Since vcpu
3469                  * is in the middle of the transition from real mode to
3470                  * protected mode it is safe to assume that RPL 0 is a good
3471                  * default value.
3472                  */
3473                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3474                         save->selector &= ~SEGMENT_RPL_MASK;
3475                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3476                 save->s = 1;
3477         }
3478         vmx_set_segment(vcpu, save, seg);
3479 }
3480
3481 static void enter_pmode(struct kvm_vcpu *vcpu)
3482 {
3483         unsigned long flags;
3484         struct vcpu_vmx *vmx = to_vmx(vcpu);
3485
3486         /*
3487          * Update real mode segment cache. It may be not up-to-date if sement
3488          * register was written while vcpu was in a guest mode.
3489          */
3490         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3491         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3492         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3493         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3494         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3495         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3496
3497         vmx->rmode.vm86_active = 0;
3498
3499         vmx_segment_cache_clear(vmx);
3500
3501         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3502
3503         flags = vmcs_readl(GUEST_RFLAGS);
3504         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3505         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3506         vmcs_writel(GUEST_RFLAGS, flags);
3507
3508         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3509                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3510
3511         update_exception_bitmap(vcpu);
3512
3513         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3514         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3515         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3516         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3517         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3518         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3519 }
3520
3521 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3522 {
3523         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3524         struct kvm_segment var = *save;
3525
3526         var.dpl = 0x3;
3527         if (seg == VCPU_SREG_CS)
3528                 var.type = 0x3;
3529
3530         if (!emulate_invalid_guest_state) {
3531                 var.selector = var.base >> 4;
3532                 var.base = var.base & 0xffff0;
3533                 var.limit = 0xffff;
3534                 var.g = 0;
3535                 var.db = 0;
3536                 var.present = 1;
3537                 var.s = 1;
3538                 var.l = 0;
3539                 var.unusable = 0;
3540                 var.type = 0x3;
3541                 var.avl = 0;
3542                 if (save->base & 0xf)
3543                         printk_once(KERN_WARNING "kvm: segment base is not "
3544                                         "paragraph aligned when entering "
3545                                         "protected mode (seg=%d)", seg);
3546         }
3547
3548         vmcs_write16(sf->selector, var.selector);
3549         vmcs_write32(sf->base, var.base);
3550         vmcs_write32(sf->limit, var.limit);
3551         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3552 }
3553
3554 static void enter_rmode(struct kvm_vcpu *vcpu)
3555 {
3556         unsigned long flags;
3557         struct vcpu_vmx *vmx = to_vmx(vcpu);
3558
3559         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3560         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3561         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3562         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3563         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3564         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3565         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3566
3567         vmx->rmode.vm86_active = 1;
3568
3569         /*
3570          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3571          * vcpu. Warn the user that an update is overdue.
3572          */
3573         if (!vcpu->kvm->arch.tss_addr)
3574                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3575                              "called before entering vcpu\n");
3576
3577         vmx_segment_cache_clear(vmx);
3578
3579         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3580         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3581         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3582
3583         flags = vmcs_readl(GUEST_RFLAGS);
3584         vmx->rmode.save_rflags = flags;
3585
3586         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3587
3588         vmcs_writel(GUEST_RFLAGS, flags);
3589         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3590         update_exception_bitmap(vcpu);
3591
3592         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3593         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3594         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3595         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3596         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3597         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3598
3599         kvm_mmu_reset_context(vcpu);
3600 }
3601
3602 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3603 {
3604         struct vcpu_vmx *vmx = to_vmx(vcpu);
3605         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3606
3607         if (!msr)
3608                 return;
3609
3610         /*
3611          * Force kernel_gs_base reloading before EFER changes, as control
3612          * of this msr depends on is_long_mode().
3613          */
3614         vmx_load_host_state(to_vmx(vcpu));
3615         vcpu->arch.efer = efer;
3616         if (efer & EFER_LMA) {
3617                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3618                 msr->data = efer;
3619         } else {
3620                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3621
3622                 msr->data = efer & ~EFER_LME;
3623         }
3624         setup_msrs(vmx);
3625 }
3626
3627 #ifdef CONFIG_X86_64
3628
3629 static void enter_lmode(struct kvm_vcpu *vcpu)
3630 {
3631         u32 guest_tr_ar;
3632
3633         vmx_segment_cache_clear(to_vmx(vcpu));
3634
3635         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3636         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3637                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3638                                      __func__);
3639                 vmcs_write32(GUEST_TR_AR_BYTES,
3640                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3641                              | VMX_AR_TYPE_BUSY_64_TSS);
3642         }
3643         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3644 }
3645
3646 static void exit_lmode(struct kvm_vcpu *vcpu)
3647 {
3648         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3649         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3650 }
3651
3652 #endif
3653
3654 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3655 {
3656         vpid_sync_context(vpid);
3657         if (enable_ept) {
3658                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3659                         return;
3660                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3661         }
3662 }
3663
3664 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3665 {
3666         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3667 }
3668
3669 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3670 {
3671         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3672
3673         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3674         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3675 }
3676
3677 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3678 {
3679         if (enable_ept && is_paging(vcpu))
3680                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3681         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3682 }
3683
3684 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3685 {
3686         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3687
3688         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3689         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3690 }
3691
3692 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3693 {
3694         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3695
3696         if (!test_bit(VCPU_EXREG_PDPTR,
3697                       (unsigned long *)&vcpu->arch.regs_dirty))
3698                 return;
3699
3700         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3701                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3702                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3703                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3704                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3705         }
3706 }
3707
3708 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3709 {
3710         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3711
3712         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3713                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3714                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3715                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3716                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3717         }
3718
3719         __set_bit(VCPU_EXREG_PDPTR,
3720                   (unsigned long *)&vcpu->arch.regs_avail);
3721         __set_bit(VCPU_EXREG_PDPTR,
3722                   (unsigned long *)&vcpu->arch.regs_dirty);
3723 }
3724
3725 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3726
3727 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3728                                         unsigned long cr0,
3729                                         struct kvm_vcpu *vcpu)
3730 {
3731         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3732                 vmx_decache_cr3(vcpu);
3733         if (!(cr0 & X86_CR0_PG)) {
3734                 /* From paging/starting to nonpaging */
3735                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3736                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3737                              (CPU_BASED_CR3_LOAD_EXITING |
3738                               CPU_BASED_CR3_STORE_EXITING));
3739                 vcpu->arch.cr0 = cr0;
3740                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3741         } else if (!is_paging(vcpu)) {
3742                 /* From nonpaging to paging */
3743                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3744                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3745                              ~(CPU_BASED_CR3_LOAD_EXITING |
3746                                CPU_BASED_CR3_STORE_EXITING));
3747                 vcpu->arch.cr0 = cr0;
3748                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3749         }
3750
3751         if (!(cr0 & X86_CR0_WP))
3752                 *hw_cr0 &= ~X86_CR0_WP;
3753 }
3754
3755 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3756 {
3757         struct vcpu_vmx *vmx = to_vmx(vcpu);
3758         unsigned long hw_cr0;
3759
3760         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3761         if (enable_unrestricted_guest)
3762                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3763         else {
3764                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3765
3766                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3767                         enter_pmode(vcpu);
3768
3769                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3770                         enter_rmode(vcpu);
3771         }
3772
3773 #ifdef CONFIG_X86_64
3774         if (vcpu->arch.efer & EFER_LME) {
3775                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3776                         enter_lmode(vcpu);
3777                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3778                         exit_lmode(vcpu);
3779         }
3780 #endif
3781
3782         if (enable_ept)
3783                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3784
3785         if (!vcpu->fpu_active)
3786                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3787
3788         vmcs_writel(CR0_READ_SHADOW, cr0);
3789         vmcs_writel(GUEST_CR0, hw_cr0);
3790         vcpu->arch.cr0 = cr0;
3791
3792         /* depends on vcpu->arch.cr0 to be set to a new value */
3793         vmx->emulation_required = emulation_required(vcpu);
3794 }
3795
3796 static u64 construct_eptp(unsigned long root_hpa)
3797 {
3798         u64 eptp;
3799
3800         /* TODO write the value reading from MSR */
3801         eptp = VMX_EPT_DEFAULT_MT |
3802                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3803         if (enable_ept_ad_bits)
3804                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3805         eptp |= (root_hpa & PAGE_MASK);
3806
3807         return eptp;
3808 }
3809
3810 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3811 {
3812         unsigned long guest_cr3;
3813         u64 eptp;
3814
3815         guest_cr3 = cr3;
3816         if (enable_ept) {
3817                 eptp = construct_eptp(cr3);
3818                 vmcs_write64(EPT_POINTER, eptp);
3819                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3820                         guest_cr3 = kvm_read_cr3(vcpu);
3821                 else
3822                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3823                 ept_load_pdptrs(vcpu);
3824         }
3825
3826         vmx_flush_tlb(vcpu);
3827         vmcs_writel(GUEST_CR3, guest_cr3);
3828 }
3829
3830 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3831 {
3832         /*
3833          * Pass through host's Machine Check Enable value to hw_cr4, which
3834          * is in force while we are in guest mode.  Do not let guests control
3835          * this bit, even if host CR4.MCE == 0.
3836          */
3837         unsigned long hw_cr4 =
3838                 (cr4_read_shadow() & X86_CR4_MCE) |
3839                 (cr4 & ~X86_CR4_MCE) |
3840                 (to_vmx(vcpu)->rmode.vm86_active ?
3841                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3842
3843         if (cr4 & X86_CR4_VMXE) {
3844                 /*
3845                  * To use VMXON (and later other VMX instructions), a guest
3846                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3847                  * So basically the check on whether to allow nested VMX
3848                  * is here.
3849                  */
3850                 if (!nested_vmx_allowed(vcpu))
3851                         return 1;
3852         }
3853         if (to_vmx(vcpu)->nested.vmxon &&
3854             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3855                 return 1;
3856
3857         vcpu->arch.cr4 = cr4;
3858         if (enable_ept) {
3859                 if (!is_paging(vcpu)) {
3860                         hw_cr4 &= ~X86_CR4_PAE;
3861                         hw_cr4 |= X86_CR4_PSE;
3862                 } else if (!(cr4 & X86_CR4_PAE)) {
3863                         hw_cr4 &= ~X86_CR4_PAE;
3864                 }
3865         }
3866
3867         if (!enable_unrestricted_guest && !is_paging(vcpu))
3868                 /*
3869                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3870                  * hardware.  However KVM always uses paging mode without
3871                  * unrestricted guest.
3872                  * To emulate this behavior, SMEP/SMAP needs to be manually
3873                  * disabled when guest switches to non-paging mode.
3874                  */
3875                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3876
3877         vmcs_writel(CR4_READ_SHADOW, cr4);
3878         vmcs_writel(GUEST_CR4, hw_cr4);
3879         return 0;
3880 }
3881
3882 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3883                             struct kvm_segment *var, int seg)
3884 {
3885         struct vcpu_vmx *vmx = to_vmx(vcpu);
3886         u32 ar;
3887
3888         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3889                 *var = vmx->rmode.segs[seg];
3890                 if (seg == VCPU_SREG_TR
3891                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3892                         return;
3893                 var->base = vmx_read_guest_seg_base(vmx, seg);
3894                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3895                 return;
3896         }
3897         var->base = vmx_read_guest_seg_base(vmx, seg);
3898         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3899         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3900         ar = vmx_read_guest_seg_ar(vmx, seg);
3901         var->unusable = (ar >> 16) & 1;
3902         var->type = ar & 15;
3903         var->s = (ar >> 4) & 1;
3904         var->dpl = (ar >> 5) & 3;
3905         /*
3906          * Some userspaces do not preserve unusable property. Since usable
3907          * segment has to be present according to VMX spec we can use present
3908          * property to amend userspace bug by making unusable segment always
3909          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3910          * segment as unusable.
3911          */
3912         var->present = !var->unusable;
3913         var->avl = (ar >> 12) & 1;
3914         var->l = (ar >> 13) & 1;
3915         var->db = (ar >> 14) & 1;
3916         var->g = (ar >> 15) & 1;
3917 }
3918
3919 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3920 {
3921         struct kvm_segment s;
3922
3923         if (to_vmx(vcpu)->rmode.vm86_active) {
3924                 vmx_get_segment(vcpu, &s, seg);
3925                 return s.base;
3926         }
3927         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3928 }
3929
3930 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3931 {
3932         struct vcpu_vmx *vmx = to_vmx(vcpu);
3933
3934         if (unlikely(vmx->rmode.vm86_active))
3935                 return 0;
3936         else {
3937                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3938                 return VMX_AR_DPL(ar);
3939         }
3940 }
3941
3942 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3943 {
3944         u32 ar;
3945
3946         if (var->unusable || !var->present)
3947                 ar = 1 << 16;
3948         else {
3949                 ar = var->type & 15;
3950                 ar |= (var->s & 1) << 4;
3951                 ar |= (var->dpl & 3) << 5;
3952                 ar |= (var->present & 1) << 7;
3953                 ar |= (var->avl & 1) << 12;
3954                 ar |= (var->l & 1) << 13;
3955                 ar |= (var->db & 1) << 14;
3956                 ar |= (var->g & 1) << 15;
3957         }
3958
3959         return ar;
3960 }
3961
3962 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3963                             struct kvm_segment *var, int seg)
3964 {
3965         struct vcpu_vmx *vmx = to_vmx(vcpu);
3966         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3967
3968         vmx_segment_cache_clear(vmx);
3969
3970         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3971                 vmx->rmode.segs[seg] = *var;
3972                 if (seg == VCPU_SREG_TR)
3973                         vmcs_write16(sf->selector, var->selector);
3974                 else if (var->s)
3975                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3976                 goto out;
3977         }
3978
3979         vmcs_writel(sf->base, var->base);
3980         vmcs_write32(sf->limit, var->limit);
3981         vmcs_write16(sf->selector, var->selector);
3982
3983         /*
3984          *   Fix the "Accessed" bit in AR field of segment registers for older
3985          * qemu binaries.
3986          *   IA32 arch specifies that at the time of processor reset the
3987          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3988          * is setting it to 0 in the userland code. This causes invalid guest
3989          * state vmexit when "unrestricted guest" mode is turned on.
3990          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3991          * tree. Newer qemu binaries with that qemu fix would not need this
3992          * kvm hack.
3993          */
3994         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3995                 var->type |= 0x1; /* Accessed */
3996
3997         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3998
3999 out:
4000         vmx->emulation_required = emulation_required(vcpu);
4001 }
4002
4003 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4004 {
4005         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4006
4007         *db = (ar >> 14) & 1;
4008         *l = (ar >> 13) & 1;
4009 }
4010
4011 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4012 {
4013         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4014         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4015 }
4016
4017 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4018 {
4019         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4020         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4021 }
4022
4023 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4024 {
4025         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4026         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4027 }
4028
4029 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4030 {
4031         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4032         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4033 }
4034
4035 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4036 {
4037         struct kvm_segment var;
4038         u32 ar;
4039
4040         vmx_get_segment(vcpu, &var, seg);
4041         var.dpl = 0x3;
4042         if (seg == VCPU_SREG_CS)
4043                 var.type = 0x3;
4044         ar = vmx_segment_access_rights(&var);
4045
4046         if (var.base != (var.selector << 4))
4047                 return false;
4048         if (var.limit != 0xffff)
4049                 return false;
4050         if (ar != 0xf3)
4051                 return false;
4052
4053         return true;
4054 }
4055
4056 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4057 {
4058         struct kvm_segment cs;
4059         unsigned int cs_rpl;
4060
4061         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4062         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4063
4064         if (cs.unusable)
4065                 return false;
4066         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4067                 return false;
4068         if (!cs.s)
4069                 return false;
4070         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4071                 if (cs.dpl > cs_rpl)
4072                         return false;
4073         } else {
4074                 if (cs.dpl != cs_rpl)
4075                         return false;
4076         }
4077         if (!cs.present)
4078                 return false;
4079
4080         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4081         return true;
4082 }
4083
4084 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4085 {
4086         struct kvm_segment ss;
4087         unsigned int ss_rpl;
4088
4089         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4090         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4091
4092         if (ss.unusable)
4093                 return true;
4094         if (ss.type != 3 && ss.type != 7)
4095                 return false;
4096         if (!ss.s)
4097                 return false;
4098         if (ss.dpl != ss_rpl) /* DPL != RPL */
4099                 return false;
4100         if (!ss.present)
4101                 return false;
4102
4103         return true;
4104 }
4105
4106 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4107 {
4108         struct kvm_segment var;
4109         unsigned int rpl;
4110
4111         vmx_get_segment(vcpu, &var, seg);
4112         rpl = var.selector & SEGMENT_RPL_MASK;
4113
4114         if (var.unusable)
4115                 return true;
4116         if (!var.s)
4117                 return false;
4118         if (!var.present)
4119                 return false;
4120         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4121                 if (var.dpl < rpl) /* DPL < RPL */
4122                         return false;
4123         }
4124
4125         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4126          * rights flags
4127          */
4128         return true;
4129 }
4130
4131 static bool tr_valid(struct kvm_vcpu *vcpu)
4132 {
4133         struct kvm_segment tr;
4134
4135         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4136
4137         if (tr.unusable)
4138                 return false;
4139         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4140                 return false;
4141         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4142                 return false;
4143         if (!tr.present)
4144                 return false;
4145
4146         return true;
4147 }
4148
4149 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4150 {
4151         struct kvm_segment ldtr;
4152
4153         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4154
4155         if (ldtr.unusable)
4156                 return true;
4157         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4158                 return false;
4159         if (ldtr.type != 2)
4160                 return false;
4161         if (!ldtr.present)
4162                 return false;
4163
4164         return true;
4165 }
4166
4167 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4168 {
4169         struct kvm_segment cs, ss;
4170
4171         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4172         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4173
4174         return ((cs.selector & SEGMENT_RPL_MASK) ==
4175                  (ss.selector & SEGMENT_RPL_MASK));
4176 }
4177
4178 /*
4179  * Check if guest state is valid. Returns true if valid, false if
4180  * not.
4181  * We assume that registers are always usable
4182  */
4183 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4184 {
4185         if (enable_unrestricted_guest)
4186                 return true;
4187
4188         /* real mode guest state checks */
4189         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4190                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4191                         return false;
4192                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4193                         return false;
4194                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4195                         return false;
4196                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4197                         return false;
4198                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4199                         return false;
4200                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4201                         return false;
4202         } else {
4203         /* protected mode guest state checks */
4204                 if (!cs_ss_rpl_check(vcpu))
4205                         return false;
4206                 if (!code_segment_valid(vcpu))
4207                         return false;
4208                 if (!stack_segment_valid(vcpu))
4209                         return false;
4210                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4211                         return false;
4212                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4213                         return false;
4214                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4215                         return false;
4216                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4217                         return false;
4218                 if (!tr_valid(vcpu))
4219                         return false;
4220                 if (!ldtr_valid(vcpu))
4221                         return false;
4222         }
4223         /* TODO:
4224          * - Add checks on RIP
4225          * - Add checks on RFLAGS
4226          */
4227
4228         return true;
4229 }
4230
4231 static int init_rmode_tss(struct kvm *kvm)
4232 {
4233         gfn_t fn;
4234         u16 data = 0;
4235         int idx, r;
4236
4237         idx = srcu_read_lock(&kvm->srcu);
4238         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4239         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4240         if (r < 0)
4241                 goto out;
4242         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4243         r = kvm_write_guest_page(kvm, fn++, &data,
4244                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4245         if (r < 0)
4246                 goto out;
4247         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4248         if (r < 0)
4249                 goto out;
4250         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4251         if (r < 0)
4252                 goto out;
4253         data = ~0;
4254         r = kvm_write_guest_page(kvm, fn, &data,
4255                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4256                                  sizeof(u8));
4257 out:
4258         srcu_read_unlock(&kvm->srcu, idx);
4259         return r;
4260 }
4261
4262 static int init_rmode_identity_map(struct kvm *kvm)
4263 {
4264         int i, idx, r = 0;
4265         kvm_pfn_t identity_map_pfn;
4266         u32 tmp;
4267
4268         if (!enable_ept)
4269                 return 0;
4270
4271         /* Protect kvm->arch.ept_identity_pagetable_done. */
4272         mutex_lock(&kvm->slots_lock);
4273
4274         if (likely(kvm->arch.ept_identity_pagetable_done))
4275                 goto out2;
4276
4277         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4278
4279         r = alloc_identity_pagetable(kvm);
4280         if (r < 0)
4281                 goto out2;
4282
4283         idx = srcu_read_lock(&kvm->srcu);
4284         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4285         if (r < 0)
4286                 goto out;
4287         /* Set up identity-mapping pagetable for EPT in real mode */
4288         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4289                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4290                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4291                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4292                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4293                 if (r < 0)
4294                         goto out;
4295         }
4296         kvm->arch.ept_identity_pagetable_done = true;
4297
4298 out:
4299         srcu_read_unlock(&kvm->srcu, idx);
4300
4301 out2:
4302         mutex_unlock(&kvm->slots_lock);
4303         return r;
4304 }
4305
4306 static void seg_setup(int seg)
4307 {
4308         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4309         unsigned int ar;
4310
4311         vmcs_write16(sf->selector, 0);
4312         vmcs_writel(sf->base, 0);
4313         vmcs_write32(sf->limit, 0xffff);
4314         ar = 0x93;
4315         if (seg == VCPU_SREG_CS)
4316                 ar |= 0x08; /* code segment */
4317
4318         vmcs_write32(sf->ar_bytes, ar);
4319 }
4320
4321 static int alloc_apic_access_page(struct kvm *kvm)
4322 {
4323         struct page *page;
4324         int r = 0;
4325
4326         mutex_lock(&kvm->slots_lock);
4327         if (kvm->arch.apic_access_page_done)
4328                 goto out;
4329         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4330                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4331         if (r)
4332                 goto out;
4333
4334         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4335         if (is_error_page(page)) {
4336                 r = -EFAULT;
4337                 goto out;
4338         }
4339
4340         /*
4341          * Do not pin the page in memory, so that memory hot-unplug
4342          * is able to migrate it.
4343          */
4344         put_page(page);
4345         kvm->arch.apic_access_page_done = true;
4346 out:
4347         mutex_unlock(&kvm->slots_lock);
4348         return r;
4349 }
4350
4351 static int alloc_identity_pagetable(struct kvm *kvm)
4352 {
4353         /* Called with kvm->slots_lock held. */
4354
4355         int r = 0;
4356
4357         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4358
4359         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4360                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4361
4362         return r;
4363 }
4364
4365 static int allocate_vpid(void)
4366 {
4367         int vpid;
4368
4369         if (!enable_vpid)
4370                 return 0;
4371         spin_lock(&vmx_vpid_lock);
4372         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4373         if (vpid < VMX_NR_VPIDS)
4374                 __set_bit(vpid, vmx_vpid_bitmap);
4375         else
4376                 vpid = 0;
4377         spin_unlock(&vmx_vpid_lock);
4378         return vpid;
4379 }
4380
4381 static void free_vpid(int vpid)
4382 {
4383         if (!enable_vpid || vpid == 0)
4384                 return;
4385         spin_lock(&vmx_vpid_lock);
4386         __clear_bit(vpid, vmx_vpid_bitmap);
4387         spin_unlock(&vmx_vpid_lock);
4388 }
4389
4390 #define MSR_TYPE_R      1
4391 #define MSR_TYPE_W      2
4392 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4393                                                 u32 msr, int type)
4394 {
4395         int f = sizeof(unsigned long);
4396
4397         if (!cpu_has_vmx_msr_bitmap())
4398                 return;
4399
4400         /*
4401          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4402          * have the write-low and read-high bitmap offsets the wrong way round.
4403          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4404          */
4405         if (msr <= 0x1fff) {
4406                 if (type & MSR_TYPE_R)
4407                         /* read-low */
4408                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4409
4410                 if (type & MSR_TYPE_W)
4411                         /* write-low */
4412                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4413
4414         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4415                 msr &= 0x1fff;
4416                 if (type & MSR_TYPE_R)
4417                         /* read-high */
4418                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4419
4420                 if (type & MSR_TYPE_W)
4421                         /* write-high */
4422                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4423
4424         }
4425 }
4426
4427 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4428                                                 u32 msr, int type)
4429 {
4430         int f = sizeof(unsigned long);
4431
4432         if (!cpu_has_vmx_msr_bitmap())
4433                 return;
4434
4435         /*
4436          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4437          * have the write-low and read-high bitmap offsets the wrong way round.
4438          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4439          */
4440         if (msr <= 0x1fff) {
4441                 if (type & MSR_TYPE_R)
4442                         /* read-low */
4443                         __set_bit(msr, msr_bitmap + 0x000 / f);
4444
4445                 if (type & MSR_TYPE_W)
4446                         /* write-low */
4447                         __set_bit(msr, msr_bitmap + 0x800 / f);
4448
4449         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4450                 msr &= 0x1fff;
4451                 if (type & MSR_TYPE_R)
4452                         /* read-high */
4453                         __set_bit(msr, msr_bitmap + 0x400 / f);
4454
4455                 if (type & MSR_TYPE_W)
4456                         /* write-high */
4457                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4458
4459         }
4460 }
4461
4462 /*
4463  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4464  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4465  */
4466 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4467                                                unsigned long *msr_bitmap_nested,
4468                                                u32 msr, int type)
4469 {
4470         int f = sizeof(unsigned long);
4471
4472         if (!cpu_has_vmx_msr_bitmap()) {
4473                 WARN_ON(1);
4474                 return;
4475         }
4476
4477         /*
4478          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4479          * have the write-low and read-high bitmap offsets the wrong way round.
4480          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4481          */
4482         if (msr <= 0x1fff) {
4483                 if (type & MSR_TYPE_R &&
4484                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4485                         /* read-low */
4486                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4487
4488                 if (type & MSR_TYPE_W &&
4489                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4490                         /* write-low */
4491                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4492
4493         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4494                 msr &= 0x1fff;
4495                 if (type & MSR_TYPE_R &&
4496                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4497                         /* read-high */
4498                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4499
4500                 if (type & MSR_TYPE_W &&
4501                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4502                         /* write-high */
4503                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4504
4505         }
4506 }
4507
4508 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4509 {
4510         if (!longmode_only)
4511                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4512                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4513         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4514                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4515 }
4516
4517 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4518 {
4519         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4520                         msr, MSR_TYPE_R);
4521         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4522                         msr, MSR_TYPE_R);
4523 }
4524
4525 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4526 {
4527         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4528                         msr, MSR_TYPE_R);
4529         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4530                         msr, MSR_TYPE_R);
4531 }
4532
4533 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4534 {
4535         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4536                         msr, MSR_TYPE_W);
4537         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4538                         msr, MSR_TYPE_W);
4539 }
4540
4541 static bool vmx_get_enable_apicv(void)
4542 {
4543         return enable_apicv;
4544 }
4545
4546 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4547 {
4548         struct vcpu_vmx *vmx = to_vmx(vcpu);
4549         int max_irr;
4550         void *vapic_page;
4551         u16 status;
4552
4553         if (vmx->nested.pi_desc &&
4554             vmx->nested.pi_pending) {
4555                 vmx->nested.pi_pending = false;
4556                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4557                         return 0;
4558
4559                 max_irr = find_last_bit(
4560                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4561
4562                 if (max_irr == 256)
4563                         return 0;
4564
4565                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4566                 if (!vapic_page) {
4567                         WARN_ON(1);
4568                         return -ENOMEM;
4569                 }
4570                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4571                 kunmap(vmx->nested.virtual_apic_page);
4572
4573                 status = vmcs_read16(GUEST_INTR_STATUS);
4574                 if ((u8)max_irr > ((u8)status & 0xff)) {
4575                         status &= ~0xff;
4576                         status |= (u8)max_irr;
4577                         vmcs_write16(GUEST_INTR_STATUS, status);
4578                 }
4579         }
4580         return 0;
4581 }
4582
4583 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4584 {
4585 #ifdef CONFIG_SMP
4586         if (vcpu->mode == IN_GUEST_MODE) {
4587                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4588
4589                 /*
4590                  * Currently, we don't support urgent interrupt,
4591                  * all interrupts are recognized as non-urgent
4592                  * interrupt, so we cannot post interrupts when
4593                  * 'SN' is set.
4594                  *
4595                  * If the vcpu is in guest mode, it means it is
4596                  * running instead of being scheduled out and
4597                  * waiting in the run queue, and that's the only
4598                  * case when 'SN' is set currently, warning if
4599                  * 'SN' is set.
4600                  */
4601                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4602
4603                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4604                                 POSTED_INTR_VECTOR);
4605                 return true;
4606         }
4607 #endif
4608         return false;
4609 }
4610
4611 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4612                                                 int vector)
4613 {
4614         struct vcpu_vmx *vmx = to_vmx(vcpu);
4615
4616         if (is_guest_mode(vcpu) &&
4617             vector == vmx->nested.posted_intr_nv) {
4618                 /* the PIR and ON have been set by L1. */
4619                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4620                 /*
4621                  * If a posted intr is not recognized by hardware,
4622                  * we will accomplish it in the next vmentry.
4623                  */
4624                 vmx->nested.pi_pending = true;
4625                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4626                 return 0;
4627         }
4628         return -1;
4629 }
4630 /*
4631  * Send interrupt to vcpu via posted interrupt way.
4632  * 1. If target vcpu is running(non-root mode), send posted interrupt
4633  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4634  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4635  * interrupt from PIR in next vmentry.
4636  */
4637 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4638 {
4639         struct vcpu_vmx *vmx = to_vmx(vcpu);
4640         int r;
4641
4642         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4643         if (!r)
4644                 return;
4645
4646         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4647                 return;
4648
4649         r = pi_test_and_set_on(&vmx->pi_desc);
4650         kvm_make_request(KVM_REQ_EVENT, vcpu);
4651         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4652                 kvm_vcpu_kick(vcpu);
4653 }
4654
4655 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4656 {
4657         struct vcpu_vmx *vmx = to_vmx(vcpu);
4658
4659         if (!pi_test_and_clear_on(&vmx->pi_desc))
4660                 return;
4661
4662         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4663 }
4664
4665 /*
4666  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4667  * will not change in the lifetime of the guest.
4668  * Note that host-state that does change is set elsewhere. E.g., host-state
4669  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4670  */
4671 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4672 {
4673         u32 low32, high32;
4674         unsigned long tmpl;
4675         struct desc_ptr dt;
4676         unsigned long cr4;
4677
4678         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4679         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4680
4681         /* Save the most likely value for this task's CR4 in the VMCS. */
4682         cr4 = cr4_read_shadow();
4683         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4684         vmx->host_state.vmcs_host_cr4 = cr4;
4685
4686         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4687 #ifdef CONFIG_X86_64
4688         /*
4689          * Load null selectors, so we can avoid reloading them in
4690          * __vmx_load_host_state(), in case userspace uses the null selectors
4691          * too (the expected case).
4692          */
4693         vmcs_write16(HOST_DS_SELECTOR, 0);
4694         vmcs_write16(HOST_ES_SELECTOR, 0);
4695 #else
4696         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4697         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4698 #endif
4699         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4700         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4701
4702         native_store_idt(&dt);
4703         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4704         vmx->host_idt_base = dt.address;
4705
4706         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4707
4708         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4709         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4710         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4711         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4712
4713         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4714                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4715                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4716         }
4717 }
4718
4719 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4720 {
4721         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4722         if (enable_ept)
4723                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4724         if (is_guest_mode(&vmx->vcpu))
4725                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4726                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4727         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4728 }
4729
4730 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4731 {
4732         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4733
4734         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4735                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4736         return pin_based_exec_ctrl;
4737 }
4738
4739 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4740 {
4741         struct vcpu_vmx *vmx = to_vmx(vcpu);
4742
4743         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4744 }
4745
4746 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4747 {
4748         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4749
4750         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4751                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4752
4753         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4754                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4755 #ifdef CONFIG_X86_64
4756                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4757                                 CPU_BASED_CR8_LOAD_EXITING;
4758 #endif
4759         }
4760         if (!enable_ept)
4761                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4762                                 CPU_BASED_CR3_LOAD_EXITING  |
4763                                 CPU_BASED_INVLPG_EXITING;
4764         return exec_control;
4765 }
4766
4767 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4768 {
4769         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4770         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4771                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4772         if (vmx->vpid == 0)
4773                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4774         if (!enable_ept) {
4775                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4776                 enable_unrestricted_guest = 0;
4777                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4778                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4779         }
4780         if (!enable_unrestricted_guest)
4781                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4782         if (!ple_gap)
4783                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4784         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4785                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4786                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4787         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4788         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4789            (handle_vmptrld).
4790            We can NOT enable shadow_vmcs here because we don't have yet
4791            a current VMCS12
4792         */
4793         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4794
4795         if (!enable_pml)
4796                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4797
4798         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4799         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4800
4801         return exec_control;
4802 }
4803
4804 static void ept_set_mmio_spte_mask(void)
4805 {
4806         /*
4807          * EPT Misconfigurations can be generated if the value of bits 2:0
4808          * of an EPT paging-structure entry is 110b (write/execute).
4809          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4810          * spte.
4811          */
4812         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4813 }
4814
4815 #define VMX_XSS_EXIT_BITMAP 0
4816 /*
4817  * Sets up the vmcs for emulated real mode.
4818  */
4819 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4820 {
4821 #ifdef CONFIG_X86_64
4822         unsigned long a;
4823 #endif
4824         int i;
4825
4826         /* I/O */
4827         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4828         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4829
4830         if (enable_shadow_vmcs) {
4831                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4832                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4833         }
4834         if (cpu_has_vmx_msr_bitmap())
4835                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4836
4837         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4838
4839         /* Control */
4840         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4841
4842         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4843
4844         if (cpu_has_secondary_exec_ctrls())
4845                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4846                                 vmx_secondary_exec_control(vmx));
4847
4848         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4849                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4850                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4851                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4852                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4853
4854                 vmcs_write16(GUEST_INTR_STATUS, 0);
4855
4856                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4857                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4858         }
4859
4860         if (ple_gap) {
4861                 vmcs_write32(PLE_GAP, ple_gap);
4862                 vmx->ple_window = ple_window;
4863                 vmx->ple_window_dirty = true;
4864         }
4865
4866         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4867         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4868         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4869
4870         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4871         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4872         vmx_set_constant_host_state(vmx);
4873 #ifdef CONFIG_X86_64
4874         rdmsrl(MSR_FS_BASE, a);
4875         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4876         rdmsrl(MSR_GS_BASE, a);
4877         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4878 #else
4879         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4880         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4881 #endif
4882
4883         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4884         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4885         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4886         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4887         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4888
4889         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4890                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4891
4892         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4893                 u32 index = vmx_msr_index[i];
4894                 u32 data_low, data_high;
4895                 int j = vmx->nmsrs;
4896
4897                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4898                         continue;
4899                 if (wrmsr_safe(index, data_low, data_high) < 0)
4900                         continue;
4901                 vmx->guest_msrs[j].index = i;
4902                 vmx->guest_msrs[j].data = 0;
4903                 vmx->guest_msrs[j].mask = -1ull;
4904                 ++vmx->nmsrs;
4905         }
4906
4907
4908         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4909
4910         /* 22.2.1, 20.8.1 */
4911         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4912
4913         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4914         set_cr4_guest_host_mask(vmx);
4915
4916         if (vmx_xsaves_supported())
4917                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4918
4919         return 0;
4920 }
4921
4922 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4923 {
4924         struct vcpu_vmx *vmx = to_vmx(vcpu);
4925         struct msr_data apic_base_msr;
4926         u64 cr0;
4927
4928         vmx->rmode.vm86_active = 0;
4929
4930         vmx->soft_vnmi_blocked = 0;
4931
4932         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4933         kvm_set_cr8(vcpu, 0);
4934
4935         if (!init_event) {
4936                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4937                                      MSR_IA32_APICBASE_ENABLE;
4938                 if (kvm_vcpu_is_reset_bsp(vcpu))
4939                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4940                 apic_base_msr.host_initiated = true;
4941                 kvm_set_apic_base(vcpu, &apic_base_msr);
4942         }
4943
4944         vmx_segment_cache_clear(vmx);
4945
4946         seg_setup(VCPU_SREG_CS);
4947         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4948         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4949
4950         seg_setup(VCPU_SREG_DS);
4951         seg_setup(VCPU_SREG_ES);
4952         seg_setup(VCPU_SREG_FS);
4953         seg_setup(VCPU_SREG_GS);
4954         seg_setup(VCPU_SREG_SS);
4955
4956         vmcs_write16(GUEST_TR_SELECTOR, 0);
4957         vmcs_writel(GUEST_TR_BASE, 0);
4958         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4959         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4960
4961         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4962         vmcs_writel(GUEST_LDTR_BASE, 0);
4963         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4964         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4965
4966         if (!init_event) {
4967                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4968                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4969                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4970                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4971         }
4972
4973         vmcs_writel(GUEST_RFLAGS, 0x02);
4974         kvm_rip_write(vcpu, 0xfff0);
4975
4976         vmcs_writel(GUEST_GDTR_BASE, 0);
4977         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4978
4979         vmcs_writel(GUEST_IDTR_BASE, 0);
4980         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4981
4982         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4983         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4984         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4985
4986         setup_msrs(vmx);
4987
4988         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4989
4990         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4991                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4992                 if (cpu_need_tpr_shadow(vcpu))
4993                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4994                                      __pa(vcpu->arch.apic->regs));
4995                 vmcs_write32(TPR_THRESHOLD, 0);
4996         }
4997
4998         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4999
5000         if (kvm_vcpu_apicv_active(vcpu))
5001                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5002
5003         if (vmx->vpid != 0)
5004                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5005
5006         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5007         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5008         vmx->vcpu.arch.cr0 = cr0;
5009         vmx_set_cr4(vcpu, 0);
5010         vmx_set_efer(vcpu, 0);
5011         vmx_fpu_activate(vcpu);
5012         update_exception_bitmap(vcpu);
5013
5014         vpid_sync_context(vmx->vpid);
5015 }
5016
5017 /*
5018  * In nested virtualization, check if L1 asked to exit on external interrupts.
5019  * For most existing hypervisors, this will always return true.
5020  */
5021 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5022 {
5023         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5024                 PIN_BASED_EXT_INTR_MASK;
5025 }
5026
5027 /*
5028  * In nested virtualization, check if L1 has set
5029  * VM_EXIT_ACK_INTR_ON_EXIT
5030  */
5031 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5032 {
5033         return get_vmcs12(vcpu)->vm_exit_controls &
5034                 VM_EXIT_ACK_INTR_ON_EXIT;
5035 }
5036
5037 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5038 {
5039         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5040                 PIN_BASED_NMI_EXITING;
5041 }
5042
5043 static void enable_irq_window(struct kvm_vcpu *vcpu)
5044 {
5045         u32 cpu_based_vm_exec_control;
5046
5047         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5048         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5049         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5050 }
5051
5052 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5053 {
5054         u32 cpu_based_vm_exec_control;
5055
5056         if (!cpu_has_virtual_nmis() ||
5057             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5058                 enable_irq_window(vcpu);
5059                 return;
5060         }
5061
5062         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5063         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5064         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5065 }
5066
5067 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5068 {
5069         struct vcpu_vmx *vmx = to_vmx(vcpu);
5070         uint32_t intr;
5071         int irq = vcpu->arch.interrupt.nr;
5072
5073         trace_kvm_inj_virq(irq);
5074
5075         ++vcpu->stat.irq_injections;
5076         if (vmx->rmode.vm86_active) {
5077                 int inc_eip = 0;
5078                 if (vcpu->arch.interrupt.soft)
5079                         inc_eip = vcpu->arch.event_exit_inst_len;
5080                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5081                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5082                 return;
5083         }
5084         intr = irq | INTR_INFO_VALID_MASK;
5085         if (vcpu->arch.interrupt.soft) {
5086                 intr |= INTR_TYPE_SOFT_INTR;
5087                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5088                              vmx->vcpu.arch.event_exit_inst_len);
5089         } else
5090                 intr |= INTR_TYPE_EXT_INTR;
5091         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5092 }
5093
5094 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5095 {
5096         struct vcpu_vmx *vmx = to_vmx(vcpu);
5097
5098         if (is_guest_mode(vcpu))
5099                 return;
5100
5101         if (!cpu_has_virtual_nmis()) {
5102                 /*
5103                  * Tracking the NMI-blocked state in software is built upon
5104                  * finding the next open IRQ window. This, in turn, depends on
5105                  * well-behaving guests: They have to keep IRQs disabled at
5106                  * least as long as the NMI handler runs. Otherwise we may
5107                  * cause NMI nesting, maybe breaking the guest. But as this is
5108                  * highly unlikely, we can live with the residual risk.
5109                  */
5110                 vmx->soft_vnmi_blocked = 1;
5111                 vmx->vnmi_blocked_time = 0;
5112         }
5113
5114         ++vcpu->stat.nmi_injections;
5115         vmx->nmi_known_unmasked = false;
5116         if (vmx->rmode.vm86_active) {
5117                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5118                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5119                 return;
5120         }
5121         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5122                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5123 }
5124
5125 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5126 {
5127         if (!cpu_has_virtual_nmis())
5128                 return to_vmx(vcpu)->soft_vnmi_blocked;
5129         if (to_vmx(vcpu)->nmi_known_unmasked)
5130                 return false;
5131         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5132 }
5133
5134 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5135 {
5136         struct vcpu_vmx *vmx = to_vmx(vcpu);
5137
5138         if (!cpu_has_virtual_nmis()) {
5139                 if (vmx->soft_vnmi_blocked != masked) {
5140                         vmx->soft_vnmi_blocked = masked;
5141                         vmx->vnmi_blocked_time = 0;
5142                 }
5143         } else {
5144                 vmx->nmi_known_unmasked = !masked;
5145                 if (masked)
5146                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5147                                       GUEST_INTR_STATE_NMI);
5148                 else
5149                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5150                                         GUEST_INTR_STATE_NMI);
5151         }
5152 }
5153
5154 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5155 {
5156         if (to_vmx(vcpu)->nested.nested_run_pending)
5157                 return 0;
5158
5159         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5160                 return 0;
5161
5162         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5163                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5164                    | GUEST_INTR_STATE_NMI));
5165 }
5166
5167 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5168 {
5169         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5170                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5171                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5172                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5173 }
5174
5175 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5176 {
5177         int ret;
5178
5179         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5180                                     PAGE_SIZE * 3);
5181         if (ret)
5182                 return ret;
5183         kvm->arch.tss_addr = addr;
5184         return init_rmode_tss(kvm);
5185 }
5186
5187 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5188 {
5189         switch (vec) {
5190         case BP_VECTOR:
5191                 /*
5192                  * Update instruction length as we may reinject the exception
5193                  * from user space while in guest debugging mode.
5194                  */
5195                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5196                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5197                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5198                         return false;
5199                 /* fall through */
5200         case DB_VECTOR:
5201                 if (vcpu->guest_debug &
5202                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5203                         return false;
5204                 /* fall through */
5205         case DE_VECTOR:
5206         case OF_VECTOR:
5207         case BR_VECTOR:
5208         case UD_VECTOR:
5209         case DF_VECTOR:
5210         case SS_VECTOR:
5211         case GP_VECTOR:
5212         case MF_VECTOR:
5213                 return true;
5214         break;
5215         }
5216         return false;
5217 }
5218
5219 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5220                                   int vec, u32 err_code)
5221 {
5222         /*
5223          * Instruction with address size override prefix opcode 0x67
5224          * Cause the #SS fault with 0 error code in VM86 mode.
5225          */
5226         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5227                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5228                         if (vcpu->arch.halt_request) {
5229                                 vcpu->arch.halt_request = 0;
5230                                 return kvm_vcpu_halt(vcpu);
5231                         }
5232                         return 1;
5233                 }
5234                 return 0;
5235         }
5236
5237         /*
5238          * Forward all other exceptions that are valid in real mode.
5239          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5240          *        the required debugging infrastructure rework.
5241          */
5242         kvm_queue_exception(vcpu, vec);
5243         return 1;
5244 }
5245
5246 /*
5247  * Trigger machine check on the host. We assume all the MSRs are already set up
5248  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5249  * We pass a fake environment to the machine check handler because we want
5250  * the guest to be always treated like user space, no matter what context
5251  * it used internally.
5252  */
5253 static void kvm_machine_check(void)
5254 {
5255 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5256         struct pt_regs regs = {
5257                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5258                 .flags = X86_EFLAGS_IF,
5259         };
5260
5261         do_machine_check(&regs, 0);
5262 #endif
5263 }
5264
5265 static int handle_machine_check(struct kvm_vcpu *vcpu)
5266 {
5267         /* already handled by vcpu_run */
5268         return 1;
5269 }
5270
5271 static int handle_exception(struct kvm_vcpu *vcpu)
5272 {
5273         struct vcpu_vmx *vmx = to_vmx(vcpu);
5274         struct kvm_run *kvm_run = vcpu->run;
5275         u32 intr_info, ex_no, error_code;
5276         unsigned long cr2, rip, dr6;
5277         u32 vect_info;
5278         enum emulation_result er;
5279
5280         vect_info = vmx->idt_vectoring_info;
5281         intr_info = vmx->exit_intr_info;
5282
5283         if (is_machine_check(intr_info))
5284                 return handle_machine_check(vcpu);
5285
5286         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5287                 return 1;  /* already handled by vmx_vcpu_run() */
5288
5289         if (is_no_device(intr_info)) {
5290                 vmx_fpu_activate(vcpu);
5291                 return 1;
5292         }
5293
5294         if (is_invalid_opcode(intr_info)) {
5295                 if (is_guest_mode(vcpu)) {
5296                         kvm_queue_exception(vcpu, UD_VECTOR);
5297                         return 1;
5298                 }
5299                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5300                 if (er != EMULATE_DONE)
5301                         kvm_queue_exception(vcpu, UD_VECTOR);
5302                 return 1;
5303         }
5304
5305         error_code = 0;
5306         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5307                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5308
5309         /*
5310          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5311          * MMIO, it is better to report an internal error.
5312          * See the comments in vmx_handle_exit.
5313          */
5314         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5315             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5316                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5317                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5318                 vcpu->run->internal.ndata = 3;
5319                 vcpu->run->internal.data[0] = vect_info;
5320                 vcpu->run->internal.data[1] = intr_info;
5321                 vcpu->run->internal.data[2] = error_code;
5322                 return 0;
5323         }
5324
5325         if (is_page_fault(intr_info)) {
5326                 /* EPT won't cause page fault directly */
5327                 BUG_ON(enable_ept);
5328                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5329                 trace_kvm_page_fault(cr2, error_code);
5330
5331                 if (kvm_event_needs_reinjection(vcpu))
5332                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5333                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5334         }
5335
5336         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5337
5338         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5339                 return handle_rmode_exception(vcpu, ex_no, error_code);
5340
5341         switch (ex_no) {
5342         case AC_VECTOR:
5343                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5344                 return 1;
5345         case DB_VECTOR:
5346                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5347                 if (!(vcpu->guest_debug &
5348                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5349                         vcpu->arch.dr6 &= ~15;
5350                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5351                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5352                                 skip_emulated_instruction(vcpu);
5353
5354                         kvm_queue_exception(vcpu, DB_VECTOR);
5355                         return 1;
5356                 }
5357                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5358                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5359                 /* fall through */
5360         case BP_VECTOR:
5361                 /*
5362                  * Update instruction length as we may reinject #BP from
5363                  * user space while in guest debugging mode. Reading it for
5364                  * #DB as well causes no harm, it is not used in that case.
5365                  */
5366                 vmx->vcpu.arch.event_exit_inst_len =
5367                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5368                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5369                 rip = kvm_rip_read(vcpu);
5370                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5371                 kvm_run->debug.arch.exception = ex_no;
5372                 break;
5373         default:
5374                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5375                 kvm_run->ex.exception = ex_no;
5376                 kvm_run->ex.error_code = error_code;
5377                 break;
5378         }
5379         return 0;
5380 }
5381
5382 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5383 {
5384         ++vcpu->stat.irq_exits;
5385         return 1;
5386 }
5387
5388 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5389 {
5390         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5391         return 0;
5392 }
5393
5394 static int handle_io(struct kvm_vcpu *vcpu)
5395 {
5396         unsigned long exit_qualification;
5397         int size, in, string;
5398         unsigned port;
5399
5400         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5401         string = (exit_qualification & 16) != 0;
5402         in = (exit_qualification & 8) != 0;
5403
5404         ++vcpu->stat.io_exits;
5405
5406         if (string || in)
5407                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5408
5409         port = exit_qualification >> 16;
5410         size = (exit_qualification & 7) + 1;
5411         skip_emulated_instruction(vcpu);
5412
5413         return kvm_fast_pio_out(vcpu, size, port);
5414 }
5415
5416 static void
5417 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5418 {
5419         /*
5420          * Patch in the VMCALL instruction:
5421          */
5422         hypercall[0] = 0x0f;
5423         hypercall[1] = 0x01;
5424         hypercall[2] = 0xc1;
5425 }
5426
5427 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5428 {
5429         unsigned long always_on = VMXON_CR0_ALWAYSON;
5430         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5431
5432         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5433                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5434             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5435                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5436         return (val & always_on) == always_on;
5437 }
5438
5439 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5440 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5441 {
5442         if (is_guest_mode(vcpu)) {
5443                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5444                 unsigned long orig_val = val;
5445
5446                 /*
5447                  * We get here when L2 changed cr0 in a way that did not change
5448                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5449                  * but did change L0 shadowed bits. So we first calculate the
5450                  * effective cr0 value that L1 would like to write into the
5451                  * hardware. It consists of the L2-owned bits from the new
5452                  * value combined with the L1-owned bits from L1's guest_cr0.
5453                  */
5454                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5455                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5456
5457                 if (!nested_cr0_valid(vcpu, val))
5458                         return 1;
5459
5460                 if (kvm_set_cr0(vcpu, val))
5461                         return 1;
5462                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5463                 return 0;
5464         } else {
5465                 if (to_vmx(vcpu)->nested.vmxon &&
5466                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5467                         return 1;
5468                 return kvm_set_cr0(vcpu, val);
5469         }
5470 }
5471
5472 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5473 {
5474         if (is_guest_mode(vcpu)) {
5475                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5476                 unsigned long orig_val = val;
5477
5478                 /* analogously to handle_set_cr0 */
5479                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5480                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5481                 if (kvm_set_cr4(vcpu, val))
5482                         return 1;
5483                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5484                 return 0;
5485         } else
5486                 return kvm_set_cr4(vcpu, val);
5487 }
5488
5489 /* called to set cr0 as approriate for clts instruction exit. */
5490 static void handle_clts(struct kvm_vcpu *vcpu)
5491 {
5492         if (is_guest_mode(vcpu)) {
5493                 /*
5494                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5495                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5496                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5497                  */
5498                 vmcs_writel(CR0_READ_SHADOW,
5499                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5500                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5501         } else
5502                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5503 }
5504
5505 static int handle_cr(struct kvm_vcpu *vcpu)
5506 {
5507         unsigned long exit_qualification, val;
5508         int cr;
5509         int reg;
5510         int err;
5511
5512         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5513         cr = exit_qualification & 15;
5514         reg = (exit_qualification >> 8) & 15;
5515         switch ((exit_qualification >> 4) & 3) {
5516         case 0: /* mov to cr */
5517                 val = kvm_register_readl(vcpu, reg);
5518                 trace_kvm_cr_write(cr, val);
5519                 switch (cr) {
5520                 case 0:
5521                         err = handle_set_cr0(vcpu, val);
5522                         kvm_complete_insn_gp(vcpu, err);
5523                         return 1;
5524                 case 3:
5525                         err = kvm_set_cr3(vcpu, val);
5526                         kvm_complete_insn_gp(vcpu, err);
5527                         return 1;
5528                 case 4:
5529                         err = handle_set_cr4(vcpu, val);
5530                         kvm_complete_insn_gp(vcpu, err);
5531                         return 1;
5532                 case 8: {
5533                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5534                                 u8 cr8 = (u8)val;
5535                                 err = kvm_set_cr8(vcpu, cr8);
5536                                 kvm_complete_insn_gp(vcpu, err);
5537                                 if (lapic_in_kernel(vcpu))
5538                                         return 1;
5539                                 if (cr8_prev <= cr8)
5540                                         return 1;
5541                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5542                                 return 0;
5543                         }
5544                 }
5545                 break;
5546         case 2: /* clts */
5547                 handle_clts(vcpu);
5548                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5549                 skip_emulated_instruction(vcpu);
5550                 vmx_fpu_activate(vcpu);
5551                 return 1;
5552         case 1: /*mov from cr*/
5553                 switch (cr) {
5554                 case 3:
5555                         val = kvm_read_cr3(vcpu);
5556                         kvm_register_write(vcpu, reg, val);
5557                         trace_kvm_cr_read(cr, val);
5558                         skip_emulated_instruction(vcpu);
5559                         return 1;
5560                 case 8:
5561                         val = kvm_get_cr8(vcpu);
5562                         kvm_register_write(vcpu, reg, val);
5563                         trace_kvm_cr_read(cr, val);
5564                         skip_emulated_instruction(vcpu);
5565                         return 1;
5566                 }
5567                 break;
5568         case 3: /* lmsw */
5569                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5570                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5571                 kvm_lmsw(vcpu, val);
5572
5573                 skip_emulated_instruction(vcpu);
5574                 return 1;
5575         default:
5576                 break;
5577         }
5578         vcpu->run->exit_reason = 0;
5579         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5580                (int)(exit_qualification >> 4) & 3, cr);
5581         return 0;
5582 }
5583
5584 static int handle_dr(struct kvm_vcpu *vcpu)
5585 {
5586         unsigned long exit_qualification;
5587         int dr, dr7, reg;
5588
5589         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5590         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5591
5592         /* First, if DR does not exist, trigger UD */
5593         if (!kvm_require_dr(vcpu, dr))
5594                 return 1;
5595
5596         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5597         if (!kvm_require_cpl(vcpu, 0))
5598                 return 1;
5599         dr7 = vmcs_readl(GUEST_DR7);
5600         if (dr7 & DR7_GD) {
5601                 /*
5602                  * As the vm-exit takes precedence over the debug trap, we
5603                  * need to emulate the latter, either for the host or the
5604                  * guest debugging itself.
5605                  */
5606                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5607                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5608                         vcpu->run->debug.arch.dr7 = dr7;
5609                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5610                         vcpu->run->debug.arch.exception = DB_VECTOR;
5611                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5612                         return 0;
5613                 } else {
5614                         vcpu->arch.dr6 &= ~15;
5615                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5616                         kvm_queue_exception(vcpu, DB_VECTOR);
5617                         return 1;
5618                 }
5619         }
5620
5621         if (vcpu->guest_debug == 0) {
5622                 u32 cpu_based_vm_exec_control;
5623
5624                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5625                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5626                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5627
5628                 /*
5629                  * No more DR vmexits; force a reload of the debug registers
5630                  * and reenter on this instruction.  The next vmexit will
5631                  * retrieve the full state of the debug registers.
5632                  */
5633                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5634                 return 1;
5635         }
5636
5637         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5638         if (exit_qualification & TYPE_MOV_FROM_DR) {
5639                 unsigned long val;
5640
5641                 if (kvm_get_dr(vcpu, dr, &val))
5642                         return 1;
5643                 kvm_register_write(vcpu, reg, val);
5644         } else
5645                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5646                         return 1;
5647
5648         skip_emulated_instruction(vcpu);
5649         return 1;
5650 }
5651
5652 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5653 {
5654         return vcpu->arch.dr6;
5655 }
5656
5657 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5658 {
5659 }
5660
5661 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5662 {
5663         u32 cpu_based_vm_exec_control;
5664
5665         get_debugreg(vcpu->arch.db[0], 0);
5666         get_debugreg(vcpu->arch.db[1], 1);
5667         get_debugreg(vcpu->arch.db[2], 2);
5668         get_debugreg(vcpu->arch.db[3], 3);
5669         get_debugreg(vcpu->arch.dr6, 6);
5670         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5671
5672         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5673
5674         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5675         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5676         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5677 }
5678
5679 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5680 {
5681         vmcs_writel(GUEST_DR7, val);
5682 }
5683
5684 static int handle_cpuid(struct kvm_vcpu *vcpu)
5685 {
5686         kvm_emulate_cpuid(vcpu);
5687         return 1;
5688 }
5689
5690 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5691 {
5692         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5693         struct msr_data msr_info;
5694
5695         msr_info.index = ecx;
5696         msr_info.host_initiated = false;
5697         if (vmx_get_msr(vcpu, &msr_info)) {
5698                 trace_kvm_msr_read_ex(ecx);
5699                 kvm_inject_gp(vcpu, 0);
5700                 return 1;
5701         }
5702
5703         trace_kvm_msr_read(ecx, msr_info.data);
5704
5705         /* FIXME: handling of bits 32:63 of rax, rdx */
5706         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5707         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5708         skip_emulated_instruction(vcpu);
5709         return 1;
5710 }
5711
5712 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5713 {
5714         struct msr_data msr;
5715         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5716         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5717                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5718
5719         msr.data = data;
5720         msr.index = ecx;
5721         msr.host_initiated = false;
5722         if (kvm_set_msr(vcpu, &msr) != 0) {
5723                 trace_kvm_msr_write_ex(ecx, data);
5724                 kvm_inject_gp(vcpu, 0);
5725                 return 1;
5726         }
5727
5728         trace_kvm_msr_write(ecx, data);
5729         skip_emulated_instruction(vcpu);
5730         return 1;
5731 }
5732
5733 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5734 {
5735         kvm_make_request(KVM_REQ_EVENT, vcpu);
5736         return 1;
5737 }
5738
5739 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5740 {
5741         u32 cpu_based_vm_exec_control;
5742
5743         /* clear pending irq */
5744         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5745         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5746         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5747
5748         kvm_make_request(KVM_REQ_EVENT, vcpu);
5749
5750         ++vcpu->stat.irq_window_exits;
5751         return 1;
5752 }
5753
5754 static int handle_halt(struct kvm_vcpu *vcpu)
5755 {
5756         return kvm_emulate_halt(vcpu);
5757 }
5758
5759 static int handle_vmcall(struct kvm_vcpu *vcpu)
5760 {
5761         kvm_emulate_hypercall(vcpu);
5762         return 1;
5763 }
5764
5765 static int handle_invd(struct kvm_vcpu *vcpu)
5766 {
5767         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5768 }
5769
5770 static int handle_invlpg(struct kvm_vcpu *vcpu)
5771 {
5772         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5773
5774         kvm_mmu_invlpg(vcpu, exit_qualification);
5775         skip_emulated_instruction(vcpu);
5776         return 1;
5777 }
5778
5779 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5780 {
5781         int err;
5782
5783         err = kvm_rdpmc(vcpu);
5784         kvm_complete_insn_gp(vcpu, err);
5785
5786         return 1;
5787 }
5788
5789 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5790 {
5791         kvm_emulate_wbinvd(vcpu);
5792         return 1;
5793 }
5794
5795 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5796 {
5797         u64 new_bv = kvm_read_edx_eax(vcpu);
5798         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5799
5800         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5801                 skip_emulated_instruction(vcpu);
5802         return 1;
5803 }
5804
5805 static int handle_xsaves(struct kvm_vcpu *vcpu)
5806 {
5807         skip_emulated_instruction(vcpu);
5808         WARN(1, "this should never happen\n");
5809         return 1;
5810 }
5811
5812 static int handle_xrstors(struct kvm_vcpu *vcpu)
5813 {
5814         skip_emulated_instruction(vcpu);
5815         WARN(1, "this should never happen\n");
5816         return 1;
5817 }
5818
5819 static int handle_apic_access(struct kvm_vcpu *vcpu)
5820 {
5821         if (likely(fasteoi)) {
5822                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5823                 int access_type, offset;
5824
5825                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5826                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5827                 /*
5828                  * Sane guest uses MOV to write EOI, with written value
5829                  * not cared. So make a short-circuit here by avoiding
5830                  * heavy instruction emulation.
5831                  */
5832                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5833                     (offset == APIC_EOI)) {
5834                         kvm_lapic_set_eoi(vcpu);
5835                         skip_emulated_instruction(vcpu);
5836                         return 1;
5837                 }
5838         }
5839         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5840 }
5841
5842 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5843 {
5844         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5845         int vector = exit_qualification & 0xff;
5846
5847         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5848         kvm_apic_set_eoi_accelerated(vcpu, vector);
5849         return 1;
5850 }
5851
5852 static int handle_apic_write(struct kvm_vcpu *vcpu)
5853 {
5854         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5855         u32 offset = exit_qualification & 0xfff;
5856
5857         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5858         kvm_apic_write_nodecode(vcpu, offset);
5859         return 1;
5860 }
5861
5862 static int handle_task_switch(struct kvm_vcpu *vcpu)
5863 {
5864         struct vcpu_vmx *vmx = to_vmx(vcpu);
5865         unsigned long exit_qualification;
5866         bool has_error_code = false;
5867         u32 error_code = 0;
5868         u16 tss_selector;
5869         int reason, type, idt_v, idt_index;
5870
5871         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5872         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5873         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5874
5875         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5876
5877         reason = (u32)exit_qualification >> 30;
5878         if (reason == TASK_SWITCH_GATE && idt_v) {
5879                 switch (type) {
5880                 case INTR_TYPE_NMI_INTR:
5881                         vcpu->arch.nmi_injected = false;
5882                         vmx_set_nmi_mask(vcpu, true);
5883                         break;
5884                 case INTR_TYPE_EXT_INTR:
5885                 case INTR_TYPE_SOFT_INTR:
5886                         kvm_clear_interrupt_queue(vcpu);
5887                         break;
5888                 case INTR_TYPE_HARD_EXCEPTION:
5889                         if (vmx->idt_vectoring_info &
5890                             VECTORING_INFO_DELIVER_CODE_MASK) {
5891                                 has_error_code = true;
5892                                 error_code =
5893                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5894                         }
5895                         /* fall through */
5896                 case INTR_TYPE_SOFT_EXCEPTION:
5897                         kvm_clear_exception_queue(vcpu);
5898                         break;
5899                 default:
5900                         break;
5901                 }
5902         }
5903         tss_selector = exit_qualification;
5904
5905         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5906                        type != INTR_TYPE_EXT_INTR &&
5907                        type != INTR_TYPE_NMI_INTR))
5908                 skip_emulated_instruction(vcpu);
5909
5910         if (kvm_task_switch(vcpu, tss_selector,
5911                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5912                             has_error_code, error_code) == EMULATE_FAIL) {
5913                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5914                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5915                 vcpu->run->internal.ndata = 0;
5916                 return 0;
5917         }
5918
5919         /*
5920          * TODO: What about debug traps on tss switch?
5921          *       Are we supposed to inject them and update dr6?
5922          */
5923
5924         return 1;
5925 }
5926
5927 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5928 {
5929         unsigned long exit_qualification;
5930         gpa_t gpa;
5931         u32 error_code;
5932         int gla_validity;
5933
5934         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5935
5936         gla_validity = (exit_qualification >> 7) & 0x3;
5937         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5938                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5939                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5940                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5941                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5942                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5943                         (long unsigned int)exit_qualification);
5944                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5945                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5946                 return 0;
5947         }
5948
5949         /*
5950          * EPT violation happened while executing iret from NMI,
5951          * "blocked by NMI" bit has to be set before next VM entry.
5952          * There are errata that may cause this bit to not be set:
5953          * AAK134, BY25.
5954          */
5955         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5956                         cpu_has_virtual_nmis() &&
5957                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5958                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5959
5960         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5961         trace_kvm_page_fault(gpa, exit_qualification);
5962
5963         /* It is a write fault? */
5964         error_code = exit_qualification & PFERR_WRITE_MASK;
5965         /* It is a fetch fault? */
5966         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5967         /* ept page table is present? */
5968         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5969
5970         vcpu->arch.exit_qualification = exit_qualification;
5971
5972         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5973 }
5974
5975 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5976 {
5977         int ret;
5978         gpa_t gpa;
5979
5980         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5981         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5982                 skip_emulated_instruction(vcpu);
5983                 trace_kvm_fast_mmio(gpa);
5984                 return 1;
5985         }
5986
5987         ret = handle_mmio_page_fault(vcpu, gpa, true);
5988         if (likely(ret == RET_MMIO_PF_EMULATE))
5989                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5990                                               EMULATE_DONE;
5991
5992         if (unlikely(ret == RET_MMIO_PF_INVALID))
5993                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5994
5995         if (unlikely(ret == RET_MMIO_PF_RETRY))
5996                 return 1;
5997
5998         /* It is the real ept misconfig */
5999         WARN_ON(1);
6000
6001         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6002         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6003
6004         return 0;
6005 }
6006
6007 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6008 {
6009         u32 cpu_based_vm_exec_control;
6010
6011         /* clear pending NMI */
6012         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6013         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6014         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6015         ++vcpu->stat.nmi_window_exits;
6016         kvm_make_request(KVM_REQ_EVENT, vcpu);
6017
6018         return 1;
6019 }
6020
6021 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6022 {
6023         struct vcpu_vmx *vmx = to_vmx(vcpu);
6024         enum emulation_result err = EMULATE_DONE;
6025         int ret = 1;
6026         u32 cpu_exec_ctrl;
6027         bool intr_window_requested;
6028         unsigned count = 130;
6029
6030         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6031         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6032
6033         while (vmx->emulation_required && count-- != 0) {
6034                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6035                         return handle_interrupt_window(&vmx->vcpu);
6036
6037                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6038                         return 1;
6039
6040                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6041
6042                 if (err == EMULATE_USER_EXIT) {
6043                         ++vcpu->stat.mmio_exits;
6044                         ret = 0;
6045                         goto out;
6046                 }
6047
6048                 if (err != EMULATE_DONE) {
6049                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6050                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6051                         vcpu->run->internal.ndata = 0;
6052                         return 0;
6053                 }
6054
6055                 if (vcpu->arch.halt_request) {
6056                         vcpu->arch.halt_request = 0;
6057                         ret = kvm_vcpu_halt(vcpu);
6058                         goto out;
6059                 }
6060
6061                 if (signal_pending(current))
6062                         goto out;
6063                 if (need_resched())
6064                         schedule();
6065         }
6066
6067 out:
6068         return ret;
6069 }
6070
6071 static int __grow_ple_window(int val)
6072 {
6073         if (ple_window_grow < 1)
6074                 return ple_window;
6075
6076         val = min(val, ple_window_actual_max);
6077
6078         if (ple_window_grow < ple_window)
6079                 val *= ple_window_grow;
6080         else
6081                 val += ple_window_grow;
6082
6083         return val;
6084 }
6085
6086 static int __shrink_ple_window(int val, int modifier, int minimum)
6087 {
6088         if (modifier < 1)
6089                 return ple_window;
6090
6091         if (modifier < ple_window)
6092                 val /= modifier;
6093         else
6094                 val -= modifier;
6095
6096         return max(val, minimum);
6097 }
6098
6099 static void grow_ple_window(struct kvm_vcpu *vcpu)
6100 {
6101         struct vcpu_vmx *vmx = to_vmx(vcpu);
6102         int old = vmx->ple_window;
6103
6104         vmx->ple_window = __grow_ple_window(old);
6105
6106         if (vmx->ple_window != old)
6107                 vmx->ple_window_dirty = true;
6108
6109         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6110 }
6111
6112 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6113 {
6114         struct vcpu_vmx *vmx = to_vmx(vcpu);
6115         int old = vmx->ple_window;
6116
6117         vmx->ple_window = __shrink_ple_window(old,
6118                                               ple_window_shrink, ple_window);
6119
6120         if (vmx->ple_window != old)
6121                 vmx->ple_window_dirty = true;
6122
6123         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6124 }
6125
6126 /*
6127  * ple_window_actual_max is computed to be one grow_ple_window() below
6128  * ple_window_max. (See __grow_ple_window for the reason.)
6129  * This prevents overflows, because ple_window_max is int.
6130  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6131  * this process.
6132  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6133  */
6134 static void update_ple_window_actual_max(void)
6135 {
6136         ple_window_actual_max =
6137                         __shrink_ple_window(max(ple_window_max, ple_window),
6138                                             ple_window_grow, INT_MIN);
6139 }
6140
6141 /*
6142  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6143  */
6144 static void wakeup_handler(void)
6145 {
6146         struct kvm_vcpu *vcpu;
6147         int cpu = smp_processor_id();
6148
6149         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6150         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6151                         blocked_vcpu_list) {
6152                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6153
6154                 if (pi_test_on(pi_desc) == 1)
6155                         kvm_vcpu_kick(vcpu);
6156         }
6157         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6158 }
6159
6160 static __init int hardware_setup(void)
6161 {
6162         int r = -ENOMEM, i, msr;
6163
6164         rdmsrl_safe(MSR_EFER, &host_efer);
6165
6166         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6167                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6168
6169         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6170         if (!vmx_io_bitmap_a)
6171                 return r;
6172
6173         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6174         if (!vmx_io_bitmap_b)
6175                 goto out;
6176
6177         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6178         if (!vmx_msr_bitmap_legacy)
6179                 goto out1;
6180
6181         vmx_msr_bitmap_legacy_x2apic =
6182                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6183         if (!vmx_msr_bitmap_legacy_x2apic)
6184                 goto out2;
6185
6186         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6187         if (!vmx_msr_bitmap_longmode)
6188                 goto out3;
6189
6190         vmx_msr_bitmap_longmode_x2apic =
6191                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6192         if (!vmx_msr_bitmap_longmode_x2apic)
6193                 goto out4;
6194
6195         if (nested) {
6196                 vmx_msr_bitmap_nested =
6197                         (unsigned long *)__get_free_page(GFP_KERNEL);
6198                 if (!vmx_msr_bitmap_nested)
6199                         goto out5;
6200         }
6201
6202         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6203         if (!vmx_vmread_bitmap)
6204                 goto out6;
6205
6206         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6207         if (!vmx_vmwrite_bitmap)
6208                 goto out7;
6209
6210         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6211         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6212
6213         /*
6214          * Allow direct access to the PC debug port (it is often used for I/O
6215          * delays, but the vmexits simply slow things down).
6216          */
6217         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6218         clear_bit(0x80, vmx_io_bitmap_a);
6219
6220         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6221
6222         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6223         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6224         if (nested)
6225                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6226
6227         if (setup_vmcs_config(&vmcs_config) < 0) {
6228                 r = -EIO;
6229                 goto out8;
6230         }
6231
6232         if (boot_cpu_has(X86_FEATURE_NX))
6233                 kvm_enable_efer_bits(EFER_NX);
6234
6235         if (!cpu_has_vmx_vpid())
6236                 enable_vpid = 0;
6237         if (!cpu_has_vmx_shadow_vmcs())
6238                 enable_shadow_vmcs = 0;
6239         if (enable_shadow_vmcs)
6240                 init_vmcs_shadow_fields();
6241
6242         if (!cpu_has_vmx_ept() ||
6243             !cpu_has_vmx_ept_4levels()) {
6244                 enable_ept = 0;
6245                 enable_unrestricted_guest = 0;
6246                 enable_ept_ad_bits = 0;
6247         }
6248
6249         if (!cpu_has_vmx_ept_ad_bits())
6250                 enable_ept_ad_bits = 0;
6251
6252         if (!cpu_has_vmx_unrestricted_guest())
6253                 enable_unrestricted_guest = 0;
6254
6255         if (!cpu_has_vmx_flexpriority())
6256                 flexpriority_enabled = 0;
6257
6258         /*
6259          * set_apic_access_page_addr() is used to reload apic access
6260          * page upon invalidation.  No need to do anything if not
6261          * using the APIC_ACCESS_ADDR VMCS field.
6262          */
6263         if (!flexpriority_enabled)
6264                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6265
6266         if (!cpu_has_vmx_tpr_shadow())
6267                 kvm_x86_ops->update_cr8_intercept = NULL;
6268
6269         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6270                 kvm_disable_largepages();
6271
6272         if (!cpu_has_vmx_ple())
6273                 ple_gap = 0;
6274
6275         if (!cpu_has_vmx_apicv())
6276                 enable_apicv = 0;
6277
6278         if (cpu_has_vmx_tsc_scaling()) {
6279                 kvm_has_tsc_control = true;
6280                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6281                 kvm_tsc_scaling_ratio_frac_bits = 48;
6282         }
6283
6284         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6285         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6286         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6287         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6288         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6289         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6290         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6291
6292         memcpy(vmx_msr_bitmap_legacy_x2apic,
6293                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6294         memcpy(vmx_msr_bitmap_longmode_x2apic,
6295                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6296
6297         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6298
6299         if (enable_apicv) {
6300                 for (msr = 0x800; msr <= 0x8ff; msr++)
6301                         vmx_disable_intercept_msr_read_x2apic(msr);
6302
6303                 /* According SDM, in x2apic mode, the whole id reg is used.
6304                  * But in KVM, it only use the highest eight bits. Need to
6305                  * intercept it */
6306                 vmx_enable_intercept_msr_read_x2apic(0x802);
6307                 /* TMCCT */
6308                 vmx_enable_intercept_msr_read_x2apic(0x839);
6309                 /* TPR */
6310                 vmx_disable_intercept_msr_write_x2apic(0x808);
6311                 /* EOI */
6312                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6313                 /* SELF-IPI */
6314                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6315         }
6316
6317         if (enable_ept) {
6318                 kvm_mmu_set_mask_ptes(0ull,
6319                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6320                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6321                         0ull, VMX_EPT_EXECUTABLE_MASK);
6322                 ept_set_mmio_spte_mask();
6323                 kvm_enable_tdp();
6324         } else
6325                 kvm_disable_tdp();
6326
6327         update_ple_window_actual_max();
6328
6329         /*
6330          * Only enable PML when hardware supports PML feature, and both EPT
6331          * and EPT A/D bit features are enabled -- PML depends on them to work.
6332          */
6333         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6334                 enable_pml = 0;
6335
6336         if (!enable_pml) {
6337                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6338                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6339                 kvm_x86_ops->flush_log_dirty = NULL;
6340                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6341         }
6342
6343         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6344
6345         return alloc_kvm_area();
6346
6347 out8:
6348         free_page((unsigned long)vmx_vmwrite_bitmap);
6349 out7:
6350         free_page((unsigned long)vmx_vmread_bitmap);
6351 out6:
6352         if (nested)
6353                 free_page((unsigned long)vmx_msr_bitmap_nested);
6354 out5:
6355         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6356 out4:
6357         free_page((unsigned long)vmx_msr_bitmap_longmode);
6358 out3:
6359         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6360 out2:
6361         free_page((unsigned long)vmx_msr_bitmap_legacy);
6362 out1:
6363         free_page((unsigned long)vmx_io_bitmap_b);
6364 out:
6365         free_page((unsigned long)vmx_io_bitmap_a);
6366
6367     return r;
6368 }
6369
6370 static __exit void hardware_unsetup(void)
6371 {
6372         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6373         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6374         free_page((unsigned long)vmx_msr_bitmap_legacy);
6375         free_page((unsigned long)vmx_msr_bitmap_longmode);
6376         free_page((unsigned long)vmx_io_bitmap_b);
6377         free_page((unsigned long)vmx_io_bitmap_a);
6378         free_page((unsigned long)vmx_vmwrite_bitmap);
6379         free_page((unsigned long)vmx_vmread_bitmap);
6380         if (nested)
6381                 free_page((unsigned long)vmx_msr_bitmap_nested);
6382
6383         free_kvm_area();
6384 }
6385
6386 /*
6387  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6388  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6389  */
6390 static int handle_pause(struct kvm_vcpu *vcpu)
6391 {
6392         if (ple_gap)
6393                 grow_ple_window(vcpu);
6394
6395         skip_emulated_instruction(vcpu);
6396         kvm_vcpu_on_spin(vcpu);
6397
6398         return 1;
6399 }
6400
6401 static int handle_nop(struct kvm_vcpu *vcpu)
6402 {
6403         skip_emulated_instruction(vcpu);
6404         return 1;
6405 }
6406
6407 static int handle_mwait(struct kvm_vcpu *vcpu)
6408 {
6409         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6410         return handle_nop(vcpu);
6411 }
6412
6413 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6414 {
6415         return 1;
6416 }
6417
6418 static int handle_monitor(struct kvm_vcpu *vcpu)
6419 {
6420         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6421         return handle_nop(vcpu);
6422 }
6423
6424 /*
6425  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6426  * We could reuse a single VMCS for all the L2 guests, but we also want the
6427  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6428  * allows keeping them loaded on the processor, and in the future will allow
6429  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6430  * every entry if they never change.
6431  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6432  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6433  *
6434  * The following functions allocate and free a vmcs02 in this pool.
6435  */
6436
6437 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6438 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6439 {
6440         struct vmcs02_list *item;
6441         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6442                 if (item->vmptr == vmx->nested.current_vmptr) {
6443                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6444                         return &item->vmcs02;
6445                 }
6446
6447         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6448                 /* Recycle the least recently used VMCS. */
6449                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6450                         struct vmcs02_list, list);
6451                 item->vmptr = vmx->nested.current_vmptr;
6452                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6453                 return &item->vmcs02;
6454         }
6455
6456         /* Create a new VMCS */
6457         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6458         if (!item)
6459                 return NULL;
6460         item->vmcs02.vmcs = alloc_vmcs();
6461         if (!item->vmcs02.vmcs) {
6462                 kfree(item);
6463                 return NULL;
6464         }
6465         loaded_vmcs_init(&item->vmcs02);
6466         item->vmptr = vmx->nested.current_vmptr;
6467         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6468         vmx->nested.vmcs02_num++;
6469         return &item->vmcs02;
6470 }
6471
6472 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6473 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6474 {
6475         struct vmcs02_list *item;
6476         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6477                 if (item->vmptr == vmptr) {
6478                         free_loaded_vmcs(&item->vmcs02);
6479                         list_del(&item->list);
6480                         kfree(item);
6481                         vmx->nested.vmcs02_num--;
6482                         return;
6483                 }
6484 }
6485
6486 /*
6487  * Free all VMCSs saved for this vcpu, except the one pointed by
6488  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6489  * must be &vmx->vmcs01.
6490  */
6491 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6492 {
6493         struct vmcs02_list *item, *n;
6494
6495         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6496         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6497                 /*
6498                  * Something will leak if the above WARN triggers.  Better than
6499                  * a use-after-free.
6500                  */
6501                 if (vmx->loaded_vmcs == &item->vmcs02)
6502                         continue;
6503
6504                 free_loaded_vmcs(&item->vmcs02);
6505                 list_del(&item->list);
6506                 kfree(item);
6507                 vmx->nested.vmcs02_num--;
6508         }
6509 }
6510
6511 /*
6512  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6513  * set the success or error code of an emulated VMX instruction, as specified
6514  * by Vol 2B, VMX Instruction Reference, "Conventions".
6515  */
6516 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6517 {
6518         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6519                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6520                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6521 }
6522
6523 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6524 {
6525         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6526                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6527                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6528                         | X86_EFLAGS_CF);
6529 }
6530
6531 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6532                                         u32 vm_instruction_error)
6533 {
6534         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6535                 /*
6536                  * failValid writes the error number to the current VMCS, which
6537                  * can't be done there isn't a current VMCS.
6538                  */
6539                 nested_vmx_failInvalid(vcpu);
6540                 return;
6541         }
6542         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6543                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6544                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6545                         | X86_EFLAGS_ZF);
6546         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6547         /*
6548          * We don't need to force a shadow sync because
6549          * VM_INSTRUCTION_ERROR is not shadowed
6550          */
6551 }
6552
6553 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6554 {
6555         /* TODO: not to reset guest simply here. */
6556         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6557         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6558 }
6559
6560 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6561 {
6562         struct vcpu_vmx *vmx =
6563                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6564
6565         vmx->nested.preemption_timer_expired = true;
6566         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6567         kvm_vcpu_kick(&vmx->vcpu);
6568
6569         return HRTIMER_NORESTART;
6570 }
6571
6572 /*
6573  * Decode the memory-address operand of a vmx instruction, as recorded on an
6574  * exit caused by such an instruction (run by a guest hypervisor).
6575  * On success, returns 0. When the operand is invalid, returns 1 and throws
6576  * #UD or #GP.
6577  */
6578 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6579                                  unsigned long exit_qualification,
6580                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6581 {
6582         gva_t off;
6583         bool exn;
6584         struct kvm_segment s;
6585
6586         /*
6587          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6588          * Execution", on an exit, vmx_instruction_info holds most of the
6589          * addressing components of the operand. Only the displacement part
6590          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6591          * For how an actual address is calculated from all these components,
6592          * refer to Vol. 1, "Operand Addressing".
6593          */
6594         int  scaling = vmx_instruction_info & 3;
6595         int  addr_size = (vmx_instruction_info >> 7) & 7;
6596         bool is_reg = vmx_instruction_info & (1u << 10);
6597         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6598         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6599         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6600         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6601         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6602
6603         if (is_reg) {
6604                 kvm_queue_exception(vcpu, UD_VECTOR);
6605                 return 1;
6606         }
6607
6608         /* Addr = segment_base + offset */
6609         /* offset = base + [index * scale] + displacement */
6610         off = exit_qualification; /* holds the displacement */
6611         if (base_is_valid)
6612                 off += kvm_register_read(vcpu, base_reg);
6613         if (index_is_valid)
6614                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6615         vmx_get_segment(vcpu, &s, seg_reg);
6616         *ret = s.base + off;
6617
6618         if (addr_size == 1) /* 32 bit */
6619                 *ret &= 0xffffffff;
6620
6621         /* Checks for #GP/#SS exceptions. */
6622         exn = false;
6623         if (is_protmode(vcpu)) {
6624                 /* Protected mode: apply checks for segment validity in the
6625                  * following order:
6626                  * - segment type check (#GP(0) may be thrown)
6627                  * - usability check (#GP(0)/#SS(0))
6628                  * - limit check (#GP(0)/#SS(0))
6629                  */
6630                 if (wr)
6631                         /* #GP(0) if the destination operand is located in a
6632                          * read-only data segment or any code segment.
6633                          */
6634                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6635                 else
6636                         /* #GP(0) if the source operand is located in an
6637                          * execute-only code segment
6638                          */
6639                         exn = ((s.type & 0xa) == 8);
6640         }
6641         if (exn) {
6642                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6643                 return 1;
6644         }
6645         if (is_long_mode(vcpu)) {
6646                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6647                  * non-canonical form. This is an only check for long mode.
6648                  */
6649                 exn = is_noncanonical_address(*ret);
6650         } else if (is_protmode(vcpu)) {
6651                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6652                  */
6653                 exn = (s.unusable != 0);
6654                 /* Protected mode: #GP(0)/#SS(0) if the memory
6655                  * operand is outside the segment limit.
6656                  */
6657                 exn = exn || (off + sizeof(u64) > s.limit);
6658         }
6659         if (exn) {
6660                 kvm_queue_exception_e(vcpu,
6661                                       seg_reg == VCPU_SREG_SS ?
6662                                                 SS_VECTOR : GP_VECTOR,
6663                                       0);
6664                 return 1;
6665         }
6666
6667         return 0;
6668 }
6669
6670 /*
6671  * This function performs the various checks including
6672  * - if it's 4KB aligned
6673  * - No bits beyond the physical address width are set
6674  * - Returns 0 on success or else 1
6675  * (Intel SDM Section 30.3)
6676  */
6677 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6678                                   gpa_t *vmpointer)
6679 {
6680         gva_t gva;
6681         gpa_t vmptr;
6682         struct x86_exception e;
6683         struct page *page;
6684         struct vcpu_vmx *vmx = to_vmx(vcpu);
6685         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6686
6687         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6688                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6689                 return 1;
6690
6691         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6692                                 sizeof(vmptr), &e)) {
6693                 kvm_inject_page_fault(vcpu, &e);
6694                 return 1;
6695         }
6696
6697         switch (exit_reason) {
6698         case EXIT_REASON_VMON:
6699                 /*
6700                  * SDM 3: 24.11.5
6701                  * The first 4 bytes of VMXON region contain the supported
6702                  * VMCS revision identifier
6703                  *
6704                  * Note - IA32_VMX_BASIC[48] will never be 1
6705                  * for the nested case;
6706                  * which replaces physical address width with 32
6707                  *
6708                  */
6709                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6710                         nested_vmx_failInvalid(vcpu);
6711                         skip_emulated_instruction(vcpu);
6712                         return 1;
6713                 }
6714
6715                 page = nested_get_page(vcpu, vmptr);
6716                 if (page == NULL ||
6717                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6718                         nested_vmx_failInvalid(vcpu);
6719                         kunmap(page);
6720                         skip_emulated_instruction(vcpu);
6721                         return 1;
6722                 }
6723                 kunmap(page);
6724                 vmx->nested.vmxon_ptr = vmptr;
6725                 break;
6726         case EXIT_REASON_VMCLEAR:
6727                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6728                         nested_vmx_failValid(vcpu,
6729                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6730                         skip_emulated_instruction(vcpu);
6731                         return 1;
6732                 }
6733
6734                 if (vmptr == vmx->nested.vmxon_ptr) {
6735                         nested_vmx_failValid(vcpu,
6736                                              VMXERR_VMCLEAR_VMXON_POINTER);
6737                         skip_emulated_instruction(vcpu);
6738                         return 1;
6739                 }
6740                 break;
6741         case EXIT_REASON_VMPTRLD:
6742                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6743                         nested_vmx_failValid(vcpu,
6744                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6745                         skip_emulated_instruction(vcpu);
6746                         return 1;
6747                 }
6748
6749                 if (vmptr == vmx->nested.vmxon_ptr) {
6750                         nested_vmx_failValid(vcpu,
6751                                              VMXERR_VMCLEAR_VMXON_POINTER);
6752                         skip_emulated_instruction(vcpu);
6753                         return 1;
6754                 }
6755                 break;
6756         default:
6757                 return 1; /* shouldn't happen */
6758         }
6759
6760         if (vmpointer)
6761                 *vmpointer = vmptr;
6762         return 0;
6763 }
6764
6765 /*
6766  * Emulate the VMXON instruction.
6767  * Currently, we just remember that VMX is active, and do not save or even
6768  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6769  * do not currently need to store anything in that guest-allocated memory
6770  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6771  * argument is different from the VMXON pointer (which the spec says they do).
6772  */
6773 static int handle_vmon(struct kvm_vcpu *vcpu)
6774 {
6775         struct kvm_segment cs;
6776         struct vcpu_vmx *vmx = to_vmx(vcpu);
6777         struct vmcs *shadow_vmcs;
6778         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6779                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6780
6781         /* The Intel VMX Instruction Reference lists a bunch of bits that
6782          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6783          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6784          * Otherwise, we should fail with #UD. We test these now:
6785          */
6786         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6787             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6788             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6789                 kvm_queue_exception(vcpu, UD_VECTOR);
6790                 return 1;
6791         }
6792
6793         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6794         if (is_long_mode(vcpu) && !cs.l) {
6795                 kvm_queue_exception(vcpu, UD_VECTOR);
6796                 return 1;
6797         }
6798
6799         if (vmx_get_cpl(vcpu)) {
6800                 kvm_inject_gp(vcpu, 0);
6801                 return 1;
6802         }
6803
6804         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6805                 return 1;
6806
6807         if (vmx->nested.vmxon) {
6808                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6809                 skip_emulated_instruction(vcpu);
6810                 return 1;
6811         }
6812
6813         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6814                         != VMXON_NEEDED_FEATURES) {
6815                 kvm_inject_gp(vcpu, 0);
6816                 return 1;
6817         }
6818
6819         if (enable_shadow_vmcs) {
6820                 shadow_vmcs = alloc_vmcs();
6821                 if (!shadow_vmcs)
6822                         return -ENOMEM;
6823                 /* mark vmcs as shadow */
6824                 shadow_vmcs->revision_id |= (1u << 31);
6825                 /* init shadow vmcs */
6826                 vmcs_clear(shadow_vmcs);
6827                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6828         }
6829
6830         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6831         vmx->nested.vmcs02_num = 0;
6832
6833         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6834                      HRTIMER_MODE_REL);
6835         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6836
6837         vmx->nested.vmxon = true;
6838
6839         skip_emulated_instruction(vcpu);
6840         nested_vmx_succeed(vcpu);
6841         return 1;
6842 }
6843
6844 /*
6845  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6846  * for running VMX instructions (except VMXON, whose prerequisites are
6847  * slightly different). It also specifies what exception to inject otherwise.
6848  */
6849 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6850 {
6851         struct kvm_segment cs;
6852         struct vcpu_vmx *vmx = to_vmx(vcpu);
6853
6854         if (!vmx->nested.vmxon) {
6855                 kvm_queue_exception(vcpu, UD_VECTOR);
6856                 return 0;
6857         }
6858
6859         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6860         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6861             (is_long_mode(vcpu) && !cs.l)) {
6862                 kvm_queue_exception(vcpu, UD_VECTOR);
6863                 return 0;
6864         }
6865
6866         if (vmx_get_cpl(vcpu)) {
6867                 kvm_inject_gp(vcpu, 0);
6868                 return 0;
6869         }
6870
6871         return 1;
6872 }
6873
6874 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6875 {
6876         if (vmx->nested.current_vmptr == -1ull)
6877                 return;
6878
6879         /* current_vmptr and current_vmcs12 are always set/reset together */
6880         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6881                 return;
6882
6883         if (enable_shadow_vmcs) {
6884                 /* copy to memory all shadowed fields in case
6885                    they were modified */
6886                 copy_shadow_to_vmcs12(vmx);
6887                 vmx->nested.sync_shadow_vmcs = false;
6888                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6889                                 SECONDARY_EXEC_SHADOW_VMCS);
6890                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6891         }
6892         vmx->nested.posted_intr_nv = -1;
6893         kunmap(vmx->nested.current_vmcs12_page);
6894         nested_release_page(vmx->nested.current_vmcs12_page);
6895         vmx->nested.current_vmptr = -1ull;
6896         vmx->nested.current_vmcs12 = NULL;
6897 }
6898
6899 /*
6900  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6901  * just stops using VMX.
6902  */
6903 static void free_nested(struct vcpu_vmx *vmx)
6904 {
6905         if (!vmx->nested.vmxon)
6906                 return;
6907
6908         vmx->nested.vmxon = false;
6909         free_vpid(vmx->nested.vpid02);
6910         nested_release_vmcs12(vmx);
6911         if (enable_shadow_vmcs)
6912                 free_vmcs(vmx->nested.current_shadow_vmcs);
6913         /* Unpin physical memory we referred to in current vmcs02 */
6914         if (vmx->nested.apic_access_page) {
6915                 nested_release_page(vmx->nested.apic_access_page);
6916                 vmx->nested.apic_access_page = NULL;
6917         }
6918         if (vmx->nested.virtual_apic_page) {
6919                 nested_release_page(vmx->nested.virtual_apic_page);
6920                 vmx->nested.virtual_apic_page = NULL;
6921         }
6922         if (vmx->nested.pi_desc_page) {
6923                 kunmap(vmx->nested.pi_desc_page);
6924                 nested_release_page(vmx->nested.pi_desc_page);
6925                 vmx->nested.pi_desc_page = NULL;
6926                 vmx->nested.pi_desc = NULL;
6927         }
6928
6929         nested_free_all_saved_vmcss(vmx);
6930 }
6931
6932 /* Emulate the VMXOFF instruction */
6933 static int handle_vmoff(struct kvm_vcpu *vcpu)
6934 {
6935         if (!nested_vmx_check_permission(vcpu))
6936                 return 1;
6937         free_nested(to_vmx(vcpu));
6938         skip_emulated_instruction(vcpu);
6939         nested_vmx_succeed(vcpu);
6940         return 1;
6941 }
6942
6943 /* Emulate the VMCLEAR instruction */
6944 static int handle_vmclear(struct kvm_vcpu *vcpu)
6945 {
6946         struct vcpu_vmx *vmx = to_vmx(vcpu);
6947         gpa_t vmptr;
6948         struct vmcs12 *vmcs12;
6949         struct page *page;
6950
6951         if (!nested_vmx_check_permission(vcpu))
6952                 return 1;
6953
6954         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6955                 return 1;
6956
6957         if (vmptr == vmx->nested.current_vmptr)
6958                 nested_release_vmcs12(vmx);
6959
6960         page = nested_get_page(vcpu, vmptr);
6961         if (page == NULL) {
6962                 /*
6963                  * For accurate processor emulation, VMCLEAR beyond available
6964                  * physical memory should do nothing at all. However, it is
6965                  * possible that a nested vmx bug, not a guest hypervisor bug,
6966                  * resulted in this case, so let's shut down before doing any
6967                  * more damage:
6968                  */
6969                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6970                 return 1;
6971         }
6972         vmcs12 = kmap(page);
6973         vmcs12->launch_state = 0;
6974         kunmap(page);
6975         nested_release_page(page);
6976
6977         nested_free_vmcs02(vmx, vmptr);
6978
6979         skip_emulated_instruction(vcpu);
6980         nested_vmx_succeed(vcpu);
6981         return 1;
6982 }
6983
6984 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6985
6986 /* Emulate the VMLAUNCH instruction */
6987 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6988 {
6989         return nested_vmx_run(vcpu, true);
6990 }
6991
6992 /* Emulate the VMRESUME instruction */
6993 static int handle_vmresume(struct kvm_vcpu *vcpu)
6994 {
6995
6996         return nested_vmx_run(vcpu, false);
6997 }
6998
6999 enum vmcs_field_type {
7000         VMCS_FIELD_TYPE_U16 = 0,
7001         VMCS_FIELD_TYPE_U64 = 1,
7002         VMCS_FIELD_TYPE_U32 = 2,
7003         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7004 };
7005
7006 static inline int vmcs_field_type(unsigned long field)
7007 {
7008         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7009                 return VMCS_FIELD_TYPE_U32;
7010         return (field >> 13) & 0x3 ;
7011 }
7012
7013 static inline int vmcs_field_readonly(unsigned long field)
7014 {
7015         return (((field >> 10) & 0x3) == 1);
7016 }
7017
7018 /*
7019  * Read a vmcs12 field. Since these can have varying lengths and we return
7020  * one type, we chose the biggest type (u64) and zero-extend the return value
7021  * to that size. Note that the caller, handle_vmread, might need to use only
7022  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7023  * 64-bit fields are to be returned).
7024  */
7025 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7026                                   unsigned long field, u64 *ret)
7027 {
7028         short offset = vmcs_field_to_offset(field);
7029         char *p;
7030
7031         if (offset < 0)
7032                 return offset;
7033
7034         p = ((char *)(get_vmcs12(vcpu))) + offset;
7035
7036         switch (vmcs_field_type(field)) {
7037         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7038                 *ret = *((natural_width *)p);
7039                 return 0;
7040         case VMCS_FIELD_TYPE_U16:
7041                 *ret = *((u16 *)p);
7042                 return 0;
7043         case VMCS_FIELD_TYPE_U32:
7044                 *ret = *((u32 *)p);
7045                 return 0;
7046         case VMCS_FIELD_TYPE_U64:
7047                 *ret = *((u64 *)p);
7048                 return 0;
7049         default:
7050                 WARN_ON(1);
7051                 return -ENOENT;
7052         }
7053 }
7054
7055
7056 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7057                                    unsigned long field, u64 field_value){
7058         short offset = vmcs_field_to_offset(field);
7059         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7060         if (offset < 0)
7061                 return offset;
7062
7063         switch (vmcs_field_type(field)) {
7064         case VMCS_FIELD_TYPE_U16:
7065                 *(u16 *)p = field_value;
7066                 return 0;
7067         case VMCS_FIELD_TYPE_U32:
7068                 *(u32 *)p = field_value;
7069                 return 0;
7070         case VMCS_FIELD_TYPE_U64:
7071                 *(u64 *)p = field_value;
7072                 return 0;
7073         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7074                 *(natural_width *)p = field_value;
7075                 return 0;
7076         default:
7077                 WARN_ON(1);
7078                 return -ENOENT;
7079         }
7080
7081 }
7082
7083 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7084 {
7085         int i;
7086         unsigned long field;
7087         u64 field_value;
7088         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7089         const unsigned long *fields = shadow_read_write_fields;
7090         const int num_fields = max_shadow_read_write_fields;
7091
7092         preempt_disable();
7093
7094         vmcs_load(shadow_vmcs);
7095
7096         for (i = 0; i < num_fields; i++) {
7097                 field = fields[i];
7098                 switch (vmcs_field_type(field)) {
7099                 case VMCS_FIELD_TYPE_U16:
7100                         field_value = vmcs_read16(field);
7101                         break;
7102                 case VMCS_FIELD_TYPE_U32:
7103                         field_value = vmcs_read32(field);
7104                         break;
7105                 case VMCS_FIELD_TYPE_U64:
7106                         field_value = vmcs_read64(field);
7107                         break;
7108                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7109                         field_value = vmcs_readl(field);
7110                         break;
7111                 default:
7112                         WARN_ON(1);
7113                         continue;
7114                 }
7115                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7116         }
7117
7118         vmcs_clear(shadow_vmcs);
7119         vmcs_load(vmx->loaded_vmcs->vmcs);
7120
7121         preempt_enable();
7122 }
7123
7124 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7125 {
7126         const unsigned long *fields[] = {
7127                 shadow_read_write_fields,
7128                 shadow_read_only_fields
7129         };
7130         const int max_fields[] = {
7131                 max_shadow_read_write_fields,
7132                 max_shadow_read_only_fields
7133         };
7134         int i, q;
7135         unsigned long field;
7136         u64 field_value = 0;
7137         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7138
7139         vmcs_load(shadow_vmcs);
7140
7141         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7142                 for (i = 0; i < max_fields[q]; i++) {
7143                         field = fields[q][i];
7144                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7145
7146                         switch (vmcs_field_type(field)) {
7147                         case VMCS_FIELD_TYPE_U16:
7148                                 vmcs_write16(field, (u16)field_value);
7149                                 break;
7150                         case VMCS_FIELD_TYPE_U32:
7151                                 vmcs_write32(field, (u32)field_value);
7152                                 break;
7153                         case VMCS_FIELD_TYPE_U64:
7154                                 vmcs_write64(field, (u64)field_value);
7155                                 break;
7156                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7157                                 vmcs_writel(field, (long)field_value);
7158                                 break;
7159                         default:
7160                                 WARN_ON(1);
7161                                 break;
7162                         }
7163                 }
7164         }
7165
7166         vmcs_clear(shadow_vmcs);
7167         vmcs_load(vmx->loaded_vmcs->vmcs);
7168 }
7169
7170 /*
7171  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7172  * used before) all generate the same failure when it is missing.
7173  */
7174 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7175 {
7176         struct vcpu_vmx *vmx = to_vmx(vcpu);
7177         if (vmx->nested.current_vmptr == -1ull) {
7178                 nested_vmx_failInvalid(vcpu);
7179                 skip_emulated_instruction(vcpu);
7180                 return 0;
7181         }
7182         return 1;
7183 }
7184
7185 static int handle_vmread(struct kvm_vcpu *vcpu)
7186 {
7187         unsigned long field;
7188         u64 field_value;
7189         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7190         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7191         gva_t gva = 0;
7192
7193         if (!nested_vmx_check_permission(vcpu) ||
7194             !nested_vmx_check_vmcs12(vcpu))
7195                 return 1;
7196
7197         /* Decode instruction info and find the field to read */
7198         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7199         /* Read the field, zero-extended to a u64 field_value */
7200         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7201                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7202                 skip_emulated_instruction(vcpu);
7203                 return 1;
7204         }
7205         /*
7206          * Now copy part of this value to register or memory, as requested.
7207          * Note that the number of bits actually copied is 32 or 64 depending
7208          * on the guest's mode (32 or 64 bit), not on the given field's length.
7209          */
7210         if (vmx_instruction_info & (1u << 10)) {
7211                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7212                         field_value);
7213         } else {
7214                 if (get_vmx_mem_address(vcpu, exit_qualification,
7215                                 vmx_instruction_info, true, &gva))
7216                         return 1;
7217                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7218                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7219                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7220         }
7221
7222         nested_vmx_succeed(vcpu);
7223         skip_emulated_instruction(vcpu);
7224         return 1;
7225 }
7226
7227
7228 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7229 {
7230         unsigned long field;
7231         gva_t gva;
7232         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7233         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7234         /* The value to write might be 32 or 64 bits, depending on L1's long
7235          * mode, and eventually we need to write that into a field of several
7236          * possible lengths. The code below first zero-extends the value to 64
7237          * bit (field_value), and then copies only the approriate number of
7238          * bits into the vmcs12 field.
7239          */
7240         u64 field_value = 0;
7241         struct x86_exception e;
7242
7243         if (!nested_vmx_check_permission(vcpu) ||
7244             !nested_vmx_check_vmcs12(vcpu))
7245                 return 1;
7246
7247         if (vmx_instruction_info & (1u << 10))
7248                 field_value = kvm_register_readl(vcpu,
7249                         (((vmx_instruction_info) >> 3) & 0xf));
7250         else {
7251                 if (get_vmx_mem_address(vcpu, exit_qualification,
7252                                 vmx_instruction_info, false, &gva))
7253                         return 1;
7254                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7255                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7256                         kvm_inject_page_fault(vcpu, &e);
7257                         return 1;
7258                 }
7259         }
7260
7261
7262         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7263         if (vmcs_field_readonly(field)) {
7264                 nested_vmx_failValid(vcpu,
7265                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7266                 skip_emulated_instruction(vcpu);
7267                 return 1;
7268         }
7269
7270         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7271                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7272                 skip_emulated_instruction(vcpu);
7273                 return 1;
7274         }
7275
7276         nested_vmx_succeed(vcpu);
7277         skip_emulated_instruction(vcpu);
7278         return 1;
7279 }
7280
7281 /* Emulate the VMPTRLD instruction */
7282 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7283 {
7284         struct vcpu_vmx *vmx = to_vmx(vcpu);
7285         gpa_t vmptr;
7286
7287         if (!nested_vmx_check_permission(vcpu))
7288                 return 1;
7289
7290         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7291                 return 1;
7292
7293         if (vmx->nested.current_vmptr != vmptr) {
7294                 struct vmcs12 *new_vmcs12;
7295                 struct page *page;
7296                 page = nested_get_page(vcpu, vmptr);
7297                 if (page == NULL) {
7298                         nested_vmx_failInvalid(vcpu);
7299                         skip_emulated_instruction(vcpu);
7300                         return 1;
7301                 }
7302                 new_vmcs12 = kmap(page);
7303                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7304                         kunmap(page);
7305                         nested_release_page_clean(page);
7306                         nested_vmx_failValid(vcpu,
7307                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7308                         skip_emulated_instruction(vcpu);
7309                         return 1;
7310                 }
7311
7312                 nested_release_vmcs12(vmx);
7313                 vmx->nested.current_vmptr = vmptr;
7314                 vmx->nested.current_vmcs12 = new_vmcs12;
7315                 vmx->nested.current_vmcs12_page = page;
7316                 if (enable_shadow_vmcs) {
7317                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7318                                       SECONDARY_EXEC_SHADOW_VMCS);
7319                         vmcs_write64(VMCS_LINK_POINTER,
7320                                      __pa(vmx->nested.current_shadow_vmcs));
7321                         vmx->nested.sync_shadow_vmcs = true;
7322                 }
7323         }
7324
7325         nested_vmx_succeed(vcpu);
7326         skip_emulated_instruction(vcpu);
7327         return 1;
7328 }
7329
7330 /* Emulate the VMPTRST instruction */
7331 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7332 {
7333         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7334         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7335         gva_t vmcs_gva;
7336         struct x86_exception e;
7337
7338         if (!nested_vmx_check_permission(vcpu))
7339                 return 1;
7340
7341         if (get_vmx_mem_address(vcpu, exit_qualification,
7342                         vmx_instruction_info, true, &vmcs_gva))
7343                 return 1;
7344         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7345         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7346                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7347                                  sizeof(u64), &e)) {
7348                 kvm_inject_page_fault(vcpu, &e);
7349                 return 1;
7350         }
7351         nested_vmx_succeed(vcpu);
7352         skip_emulated_instruction(vcpu);
7353         return 1;
7354 }
7355
7356 /* Emulate the INVEPT instruction */
7357 static int handle_invept(struct kvm_vcpu *vcpu)
7358 {
7359         struct vcpu_vmx *vmx = to_vmx(vcpu);
7360         u32 vmx_instruction_info, types;
7361         unsigned long type;
7362         gva_t gva;
7363         struct x86_exception e;
7364         struct {
7365                 u64 eptp, gpa;
7366         } operand;
7367
7368         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7369               SECONDARY_EXEC_ENABLE_EPT) ||
7370             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7371                 kvm_queue_exception(vcpu, UD_VECTOR);
7372                 return 1;
7373         }
7374
7375         if (!nested_vmx_check_permission(vcpu))
7376                 return 1;
7377
7378         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7379                 kvm_queue_exception(vcpu, UD_VECTOR);
7380                 return 1;
7381         }
7382
7383         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7384         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7385
7386         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7387
7388         if (!(types & (1UL << type))) {
7389                 nested_vmx_failValid(vcpu,
7390                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7391                 return 1;
7392         }
7393
7394         /* According to the Intel VMX instruction reference, the memory
7395          * operand is read even if it isn't needed (e.g., for type==global)
7396          */
7397         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7398                         vmx_instruction_info, false, &gva))
7399                 return 1;
7400         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7401                                 sizeof(operand), &e)) {
7402                 kvm_inject_page_fault(vcpu, &e);
7403                 return 1;
7404         }
7405
7406         switch (type) {
7407         case VMX_EPT_EXTENT_GLOBAL:
7408                 kvm_mmu_sync_roots(vcpu);
7409                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7410                 nested_vmx_succeed(vcpu);
7411                 break;
7412         default:
7413                 /* Trap single context invalidation invept calls */
7414                 BUG_ON(1);
7415                 break;
7416         }
7417
7418         skip_emulated_instruction(vcpu);
7419         return 1;
7420 }
7421
7422 static int handle_invvpid(struct kvm_vcpu *vcpu)
7423 {
7424         struct vcpu_vmx *vmx = to_vmx(vcpu);
7425         u32 vmx_instruction_info;
7426         unsigned long type, types;
7427         gva_t gva;
7428         struct x86_exception e;
7429         int vpid;
7430
7431         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7432               SECONDARY_EXEC_ENABLE_VPID) ||
7433                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7434                 kvm_queue_exception(vcpu, UD_VECTOR);
7435                 return 1;
7436         }
7437
7438         if (!nested_vmx_check_permission(vcpu))
7439                 return 1;
7440
7441         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7442         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7443
7444         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7445
7446         if (!(types & (1UL << type))) {
7447                 nested_vmx_failValid(vcpu,
7448                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7449                 return 1;
7450         }
7451
7452         /* according to the intel vmx instruction reference, the memory
7453          * operand is read even if it isn't needed (e.g., for type==global)
7454          */
7455         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7456                         vmx_instruction_info, false, &gva))
7457                 return 1;
7458         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7459                                 sizeof(u32), &e)) {
7460                 kvm_inject_page_fault(vcpu, &e);
7461                 return 1;
7462         }
7463
7464         switch (type) {
7465         case VMX_VPID_EXTENT_ALL_CONTEXT:
7466                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7467                 nested_vmx_succeed(vcpu);
7468                 break;
7469         default:
7470                 /* Trap single context invalidation invvpid calls */
7471                 BUG_ON(1);
7472                 break;
7473         }
7474
7475         skip_emulated_instruction(vcpu);
7476         return 1;
7477 }
7478
7479 static int handle_pml_full(struct kvm_vcpu *vcpu)
7480 {
7481         unsigned long exit_qualification;
7482
7483         trace_kvm_pml_full(vcpu->vcpu_id);
7484
7485         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7486
7487         /*
7488          * PML buffer FULL happened while executing iret from NMI,
7489          * "blocked by NMI" bit has to be set before next VM entry.
7490          */
7491         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7492                         cpu_has_virtual_nmis() &&
7493                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7494                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7495                                 GUEST_INTR_STATE_NMI);
7496
7497         /*
7498          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7499          * here.., and there's no userspace involvement needed for PML.
7500          */
7501         return 1;
7502 }
7503
7504 static int handle_pcommit(struct kvm_vcpu *vcpu)
7505 {
7506         /* we never catch pcommit instruct for L1 guest. */
7507         WARN_ON(1);
7508         return 1;
7509 }
7510
7511 /*
7512  * The exit handlers return 1 if the exit was handled fully and guest execution
7513  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7514  * to be done to userspace and return 0.
7515  */
7516 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7517         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7518         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7519         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7520         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7521         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7522         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7523         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7524         [EXIT_REASON_CPUID]                   = handle_cpuid,
7525         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7526         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7527         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7528         [EXIT_REASON_HLT]                     = handle_halt,
7529         [EXIT_REASON_INVD]                    = handle_invd,
7530         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7531         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7532         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7533         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7534         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7535         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7536         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7537         [EXIT_REASON_VMREAD]                  = handle_vmread,
7538         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7539         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7540         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7541         [EXIT_REASON_VMON]                    = handle_vmon,
7542         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7543         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7544         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7545         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7546         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7547         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7548         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7549         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7550         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7551         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7552         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7553         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7554         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7555         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7556         [EXIT_REASON_INVEPT]                  = handle_invept,
7557         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7558         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7559         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7560         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7561         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7562 };
7563
7564 static const int kvm_vmx_max_exit_handlers =
7565         ARRAY_SIZE(kvm_vmx_exit_handlers);
7566
7567 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7568                                        struct vmcs12 *vmcs12)
7569 {
7570         unsigned long exit_qualification;
7571         gpa_t bitmap, last_bitmap;
7572         unsigned int port;
7573         int size;
7574         u8 b;
7575
7576         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7577                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7578
7579         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7580
7581         port = exit_qualification >> 16;
7582         size = (exit_qualification & 7) + 1;
7583
7584         last_bitmap = (gpa_t)-1;
7585         b = -1;
7586
7587         while (size > 0) {
7588                 if (port < 0x8000)
7589                         bitmap = vmcs12->io_bitmap_a;
7590                 else if (port < 0x10000)
7591                         bitmap = vmcs12->io_bitmap_b;
7592                 else
7593                         return true;
7594                 bitmap += (port & 0x7fff) / 8;
7595
7596                 if (last_bitmap != bitmap)
7597                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7598                                 return true;
7599                 if (b & (1 << (port & 7)))
7600                         return true;
7601
7602                 port++;
7603                 size--;
7604                 last_bitmap = bitmap;
7605         }
7606
7607         return false;
7608 }
7609
7610 /*
7611  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7612  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7613  * disinterest in the current event (read or write a specific MSR) by using an
7614  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7615  */
7616 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7617         struct vmcs12 *vmcs12, u32 exit_reason)
7618 {
7619         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7620         gpa_t bitmap;
7621
7622         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7623                 return true;
7624
7625         /*
7626          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7627          * for the four combinations of read/write and low/high MSR numbers.
7628          * First we need to figure out which of the four to use:
7629          */
7630         bitmap = vmcs12->msr_bitmap;
7631         if (exit_reason == EXIT_REASON_MSR_WRITE)
7632                 bitmap += 2048;
7633         if (msr_index >= 0xc0000000) {
7634                 msr_index -= 0xc0000000;
7635                 bitmap += 1024;
7636         }
7637
7638         /* Then read the msr_index'th bit from this bitmap: */
7639         if (msr_index < 1024*8) {
7640                 unsigned char b;
7641                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7642                         return true;
7643                 return 1 & (b >> (msr_index & 7));
7644         } else
7645                 return true; /* let L1 handle the wrong parameter */
7646 }
7647
7648 /*
7649  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7650  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7651  * intercept (via guest_host_mask etc.) the current event.
7652  */
7653 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7654         struct vmcs12 *vmcs12)
7655 {
7656         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7657         int cr = exit_qualification & 15;
7658         int reg = (exit_qualification >> 8) & 15;
7659         unsigned long val = kvm_register_readl(vcpu, reg);
7660
7661         switch ((exit_qualification >> 4) & 3) {
7662         case 0: /* mov to cr */
7663                 switch (cr) {
7664                 case 0:
7665                         if (vmcs12->cr0_guest_host_mask &
7666                             (val ^ vmcs12->cr0_read_shadow))
7667                                 return true;
7668                         break;
7669                 case 3:
7670                         if ((vmcs12->cr3_target_count >= 1 &&
7671                                         vmcs12->cr3_target_value0 == val) ||
7672                                 (vmcs12->cr3_target_count >= 2 &&
7673                                         vmcs12->cr3_target_value1 == val) ||
7674                                 (vmcs12->cr3_target_count >= 3 &&
7675                                         vmcs12->cr3_target_value2 == val) ||
7676                                 (vmcs12->cr3_target_count >= 4 &&
7677                                         vmcs12->cr3_target_value3 == val))
7678                                 return false;
7679                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7680                                 return true;
7681                         break;
7682                 case 4:
7683                         if (vmcs12->cr4_guest_host_mask &
7684                             (vmcs12->cr4_read_shadow ^ val))
7685                                 return true;
7686                         break;
7687                 case 8:
7688                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7689                                 return true;
7690                         break;
7691                 }
7692                 break;
7693         case 2: /* clts */
7694                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7695                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7696                         return true;
7697                 break;
7698         case 1: /* mov from cr */
7699                 switch (cr) {
7700                 case 3:
7701                         if (vmcs12->cpu_based_vm_exec_control &
7702                             CPU_BASED_CR3_STORE_EXITING)
7703                                 return true;
7704                         break;
7705                 case 8:
7706                         if (vmcs12->cpu_based_vm_exec_control &
7707                             CPU_BASED_CR8_STORE_EXITING)
7708                                 return true;
7709                         break;
7710                 }
7711                 break;
7712         case 3: /* lmsw */
7713                 /*
7714                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7715                  * cr0. Other attempted changes are ignored, with no exit.
7716                  */
7717                 if (vmcs12->cr0_guest_host_mask & 0xe &
7718                     (val ^ vmcs12->cr0_read_shadow))
7719                         return true;
7720                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7721                     !(vmcs12->cr0_read_shadow & 0x1) &&
7722                     (val & 0x1))
7723                         return true;
7724                 break;
7725         }
7726         return false;
7727 }
7728
7729 /*
7730  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7731  * should handle it ourselves in L0 (and then continue L2). Only call this
7732  * when in is_guest_mode (L2).
7733  */
7734 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7735 {
7736         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7737         struct vcpu_vmx *vmx = to_vmx(vcpu);
7738         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7739         u32 exit_reason = vmx->exit_reason;
7740
7741         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7742                                 vmcs_readl(EXIT_QUALIFICATION),
7743                                 vmx->idt_vectoring_info,
7744                                 intr_info,
7745                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7746                                 KVM_ISA_VMX);
7747
7748         if (vmx->nested.nested_run_pending)
7749                 return false;
7750
7751         if (unlikely(vmx->fail)) {
7752                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7753                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7754                 return true;
7755         }
7756
7757         switch (exit_reason) {
7758         case EXIT_REASON_EXCEPTION_NMI:
7759                 if (!is_exception(intr_info))
7760                         return false;
7761                 else if (is_page_fault(intr_info))
7762                         return enable_ept;
7763                 else if (is_no_device(intr_info) &&
7764                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7765                         return false;
7766                 return vmcs12->exception_bitmap &
7767                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7768         case EXIT_REASON_EXTERNAL_INTERRUPT:
7769                 return false;
7770         case EXIT_REASON_TRIPLE_FAULT:
7771                 return true;
7772         case EXIT_REASON_PENDING_INTERRUPT:
7773                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7774         case EXIT_REASON_NMI_WINDOW:
7775                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7776         case EXIT_REASON_TASK_SWITCH:
7777                 return true;
7778         case EXIT_REASON_CPUID:
7779                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7780                         return false;
7781                 return true;
7782         case EXIT_REASON_HLT:
7783                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7784         case EXIT_REASON_INVD:
7785                 return true;
7786         case EXIT_REASON_INVLPG:
7787                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7788         case EXIT_REASON_RDPMC:
7789                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7790         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7791                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7792         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7793         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7794         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7795         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7796         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7797         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7798                 /*
7799                  * VMX instructions trap unconditionally. This allows L1 to
7800                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7801                  */
7802                 return true;
7803         case EXIT_REASON_CR_ACCESS:
7804                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7805         case EXIT_REASON_DR_ACCESS:
7806                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7807         case EXIT_REASON_IO_INSTRUCTION:
7808                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7809         case EXIT_REASON_MSR_READ:
7810         case EXIT_REASON_MSR_WRITE:
7811                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7812         case EXIT_REASON_INVALID_STATE:
7813                 return true;
7814         case EXIT_REASON_MWAIT_INSTRUCTION:
7815                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7816         case EXIT_REASON_MONITOR_TRAP_FLAG:
7817                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7818         case EXIT_REASON_MONITOR_INSTRUCTION:
7819                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7820         case EXIT_REASON_PAUSE_INSTRUCTION:
7821                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7822                         nested_cpu_has2(vmcs12,
7823                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7824         case EXIT_REASON_MCE_DURING_VMENTRY:
7825                 return false;
7826         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7827                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7828         case EXIT_REASON_APIC_ACCESS:
7829                 return nested_cpu_has2(vmcs12,
7830                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7831         case EXIT_REASON_APIC_WRITE:
7832         case EXIT_REASON_EOI_INDUCED:
7833                 /* apic_write and eoi_induced should exit unconditionally. */
7834                 return true;
7835         case EXIT_REASON_EPT_VIOLATION:
7836                 /*
7837                  * L0 always deals with the EPT violation. If nested EPT is
7838                  * used, and the nested mmu code discovers that the address is
7839                  * missing in the guest EPT table (EPT12), the EPT violation
7840                  * will be injected with nested_ept_inject_page_fault()
7841                  */
7842                 return false;
7843         case EXIT_REASON_EPT_MISCONFIG:
7844                 /*
7845                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7846                  * table (shadow on EPT) or a merged EPT table that L0 built
7847                  * (EPT on EPT). So any problems with the structure of the
7848                  * table is L0's fault.
7849                  */
7850                 return false;
7851         case EXIT_REASON_WBINVD:
7852                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7853         case EXIT_REASON_XSETBV:
7854                 return true;
7855         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7856                 /*
7857                  * This should never happen, since it is not possible to
7858                  * set XSS to a non-zero value---neither in L1 nor in L2.
7859                  * If if it were, XSS would have to be checked against
7860                  * the XSS exit bitmap in vmcs12.
7861                  */
7862                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7863         case EXIT_REASON_PCOMMIT:
7864                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7865         default:
7866                 return true;
7867         }
7868 }
7869
7870 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7871 {
7872         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7873         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7874 }
7875
7876 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7877 {
7878         struct page *pml_pg;
7879
7880         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7881         if (!pml_pg)
7882                 return -ENOMEM;
7883
7884         vmx->pml_pg = pml_pg;
7885
7886         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7887         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7888
7889         return 0;
7890 }
7891
7892 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7893 {
7894         if (vmx->pml_pg) {
7895                 __free_page(vmx->pml_pg);
7896                 vmx->pml_pg = NULL;
7897         }
7898 }
7899
7900 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7901 {
7902         struct vcpu_vmx *vmx = to_vmx(vcpu);
7903         u64 *pml_buf;
7904         u16 pml_idx;
7905
7906         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7907
7908         /* Do nothing if PML buffer is empty */
7909         if (pml_idx == (PML_ENTITY_NUM - 1))
7910                 return;
7911
7912         /* PML index always points to next available PML buffer entity */
7913         if (pml_idx >= PML_ENTITY_NUM)
7914                 pml_idx = 0;
7915         else
7916                 pml_idx++;
7917
7918         pml_buf = page_address(vmx->pml_pg);
7919         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7920                 u64 gpa;
7921
7922                 gpa = pml_buf[pml_idx];
7923                 WARN_ON(gpa & (PAGE_SIZE - 1));
7924                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7925         }
7926
7927         /* reset PML index */
7928         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7929 }
7930
7931 /*
7932  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7933  * Called before reporting dirty_bitmap to userspace.
7934  */
7935 static void kvm_flush_pml_buffers(struct kvm *kvm)
7936 {
7937         int i;
7938         struct kvm_vcpu *vcpu;
7939         /*
7940          * We only need to kick vcpu out of guest mode here, as PML buffer
7941          * is flushed at beginning of all VMEXITs, and it's obvious that only
7942          * vcpus running in guest are possible to have unflushed GPAs in PML
7943          * buffer.
7944          */
7945         kvm_for_each_vcpu(i, vcpu, kvm)
7946                 kvm_vcpu_kick(vcpu);
7947 }
7948
7949 static void vmx_dump_sel(char *name, uint32_t sel)
7950 {
7951         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7952                name, vmcs_read32(sel),
7953                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7954                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7955                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7956 }
7957
7958 static void vmx_dump_dtsel(char *name, uint32_t limit)
7959 {
7960         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7961                name, vmcs_read32(limit),
7962                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7963 }
7964
7965 static void dump_vmcs(void)
7966 {
7967         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7968         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7969         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7970         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7971         u32 secondary_exec_control = 0;
7972         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7973         u64 efer = vmcs_read64(GUEST_IA32_EFER);
7974         int i, n;
7975
7976         if (cpu_has_secondary_exec_ctrls())
7977                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7978
7979         pr_err("*** Guest State ***\n");
7980         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7981                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7982                vmcs_readl(CR0_GUEST_HOST_MASK));
7983         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7984                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7985         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7986         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7987             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7988         {
7989                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
7990                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
7991                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
7992                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
7993         }
7994         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7995                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7996         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7997                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7998         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7999                vmcs_readl(GUEST_SYSENTER_ESP),
8000                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8001         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8002         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8003         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8004         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8005         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8006         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8007         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8008         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8009         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8010         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8011         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8012             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8013                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8014                        efer, vmcs_read64(GUEST_IA32_PAT));
8015         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8016                vmcs_read64(GUEST_IA32_DEBUGCTL),
8017                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8018         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8019                 pr_err("PerfGlobCtl = 0x%016llx\n",
8020                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8021         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8022                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8023         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8024                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8025                vmcs_read32(GUEST_ACTIVITY_STATE));
8026         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8027                 pr_err("InterruptStatus = %04x\n",
8028                        vmcs_read16(GUEST_INTR_STATUS));
8029
8030         pr_err("*** Host State ***\n");
8031         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8032                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8033         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8034                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8035                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8036                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8037                vmcs_read16(HOST_TR_SELECTOR));
8038         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8039                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8040                vmcs_readl(HOST_TR_BASE));
8041         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8042                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8043         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8044                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8045                vmcs_readl(HOST_CR4));
8046         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8047                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8048                vmcs_read32(HOST_IA32_SYSENTER_CS),
8049                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8050         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8051                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8052                        vmcs_read64(HOST_IA32_EFER),
8053                        vmcs_read64(HOST_IA32_PAT));
8054         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8055                 pr_err("PerfGlobCtl = 0x%016llx\n",
8056                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8057
8058         pr_err("*** Control State ***\n");
8059         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8060                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8061         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8062         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8063                vmcs_read32(EXCEPTION_BITMAP),
8064                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8065                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8066         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8067                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8068                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8069                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8070         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8071                vmcs_read32(VM_EXIT_INTR_INFO),
8072                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8073                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8074         pr_err("        reason=%08x qualification=%016lx\n",
8075                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8076         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8077                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8078                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8079         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8080         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8081                 pr_err("TSC Multiplier = 0x%016llx\n",
8082                        vmcs_read64(TSC_MULTIPLIER));
8083         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8084                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8085         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8086                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8087         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8088                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8089         n = vmcs_read32(CR3_TARGET_COUNT);
8090         for (i = 0; i + 1 < n; i += 4)
8091                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8092                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8093                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8094         if (i < n)
8095                 pr_err("CR3 target%u=%016lx\n",
8096                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8097         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8098                 pr_err("PLE Gap=%08x Window=%08x\n",
8099                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8100         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8101                 pr_err("Virtual processor ID = 0x%04x\n",
8102                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8103 }
8104
8105 /*
8106  * The guest has exited.  See if we can fix it or if we need userspace
8107  * assistance.
8108  */
8109 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8110 {
8111         struct vcpu_vmx *vmx = to_vmx(vcpu);
8112         u32 exit_reason = vmx->exit_reason;
8113         u32 vectoring_info = vmx->idt_vectoring_info;
8114
8115         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8116
8117         /*
8118          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8119          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8120          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8121          * mode as if vcpus is in root mode, the PML buffer must has been
8122          * flushed already.
8123          */
8124         if (enable_pml)
8125                 vmx_flush_pml_buffer(vcpu);
8126
8127         /* If guest state is invalid, start emulating */
8128         if (vmx->emulation_required)
8129                 return handle_invalid_guest_state(vcpu);
8130
8131         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8132                 nested_vmx_vmexit(vcpu, exit_reason,
8133                                   vmcs_read32(VM_EXIT_INTR_INFO),
8134                                   vmcs_readl(EXIT_QUALIFICATION));
8135                 return 1;
8136         }
8137
8138         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8139                 dump_vmcs();
8140                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8141                 vcpu->run->fail_entry.hardware_entry_failure_reason
8142                         = exit_reason;
8143                 return 0;
8144         }
8145
8146         if (unlikely(vmx->fail)) {
8147                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8148                 vcpu->run->fail_entry.hardware_entry_failure_reason
8149                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8150                 return 0;
8151         }
8152
8153         /*
8154          * Note:
8155          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8156          * delivery event since it indicates guest is accessing MMIO.
8157          * The vm-exit can be triggered again after return to guest that
8158          * will cause infinite loop.
8159          */
8160         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8161                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8162                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8163                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8164                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8165                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8166                 vcpu->run->internal.ndata = 2;
8167                 vcpu->run->internal.data[0] = vectoring_info;
8168                 vcpu->run->internal.data[1] = exit_reason;
8169                 return 0;
8170         }
8171
8172         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8173             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8174                                         get_vmcs12(vcpu))))) {
8175                 if (vmx_interrupt_allowed(vcpu)) {
8176                         vmx->soft_vnmi_blocked = 0;
8177                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8178                            vcpu->arch.nmi_pending) {
8179                         /*
8180                          * This CPU don't support us in finding the end of an
8181                          * NMI-blocked window if the guest runs with IRQs
8182                          * disabled. So we pull the trigger after 1 s of
8183                          * futile waiting, but inform the user about this.
8184                          */
8185                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8186                                "state on VCPU %d after 1 s timeout\n",
8187                                __func__, vcpu->vcpu_id);
8188                         vmx->soft_vnmi_blocked = 0;
8189                 }
8190         }
8191
8192         if (exit_reason < kvm_vmx_max_exit_handlers
8193             && kvm_vmx_exit_handlers[exit_reason])
8194                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8195         else {
8196                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8197                 kvm_queue_exception(vcpu, UD_VECTOR);
8198                 return 1;
8199         }
8200 }
8201
8202 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8203 {
8204         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8205
8206         if (is_guest_mode(vcpu) &&
8207                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8208                 return;
8209
8210         if (irr == -1 || tpr < irr) {
8211                 vmcs_write32(TPR_THRESHOLD, 0);
8212                 return;
8213         }
8214
8215         vmcs_write32(TPR_THRESHOLD, irr);
8216 }
8217
8218 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8219 {
8220         u32 sec_exec_control;
8221
8222         /*
8223          * There is not point to enable virtualize x2apic without enable
8224          * apicv
8225          */
8226         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8227                                 !kvm_vcpu_apicv_active(vcpu))
8228                 return;
8229
8230         if (!cpu_need_tpr_shadow(vcpu))
8231                 return;
8232
8233         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8234
8235         if (set) {
8236                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8237                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8238         } else {
8239                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8240                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8241         }
8242         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8243
8244         vmx_set_msr_bitmap(vcpu);
8245 }
8246
8247 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8248 {
8249         struct vcpu_vmx *vmx = to_vmx(vcpu);
8250
8251         /*
8252          * Currently we do not handle the nested case where L2 has an
8253          * APIC access page of its own; that page is still pinned.
8254          * Hence, we skip the case where the VCPU is in guest mode _and_
8255          * L1 prepared an APIC access page for L2.
8256          *
8257          * For the case where L1 and L2 share the same APIC access page
8258          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8259          * in the vmcs12), this function will only update either the vmcs01
8260          * or the vmcs02.  If the former, the vmcs02 will be updated by
8261          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8262          * the next L2->L1 exit.
8263          */
8264         if (!is_guest_mode(vcpu) ||
8265             !nested_cpu_has2(vmx->nested.current_vmcs12,
8266                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8267                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8268 }
8269
8270 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8271 {
8272         u16 status;
8273         u8 old;
8274
8275         if (isr == -1)
8276                 isr = 0;
8277
8278         status = vmcs_read16(GUEST_INTR_STATUS);
8279         old = status >> 8;
8280         if (isr != old) {
8281                 status &= 0xff;
8282                 status |= isr << 8;
8283                 vmcs_write16(GUEST_INTR_STATUS, status);
8284         }
8285 }
8286
8287 static void vmx_set_rvi(int vector)
8288 {
8289         u16 status;
8290         u8 old;
8291
8292         if (vector == -1)
8293                 vector = 0;
8294
8295         status = vmcs_read16(GUEST_INTR_STATUS);
8296         old = (u8)status & 0xff;
8297         if ((u8)vector != old) {
8298                 status &= ~0xff;
8299                 status |= (u8)vector;
8300                 vmcs_write16(GUEST_INTR_STATUS, status);
8301         }
8302 }
8303
8304 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8305 {
8306         if (!is_guest_mode(vcpu)) {
8307                 vmx_set_rvi(max_irr);
8308                 return;
8309         }
8310
8311         if (max_irr == -1)
8312                 return;
8313
8314         /*
8315          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8316          * handles it.
8317          */
8318         if (nested_exit_on_intr(vcpu))
8319                 return;
8320
8321         /*
8322          * Else, fall back to pre-APICv interrupt injection since L2
8323          * is run without virtual interrupt delivery.
8324          */
8325         if (!kvm_event_needs_reinjection(vcpu) &&
8326             vmx_interrupt_allowed(vcpu)) {
8327                 kvm_queue_interrupt(vcpu, max_irr, false);
8328                 vmx_inject_irq(vcpu);
8329         }
8330 }
8331
8332 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8333 {
8334         if (!kvm_vcpu_apicv_active(vcpu))
8335                 return;
8336
8337         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8338         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8339         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8340         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8341 }
8342
8343 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8344 {
8345         u32 exit_intr_info;
8346
8347         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8348               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8349                 return;
8350
8351         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8352         exit_intr_info = vmx->exit_intr_info;
8353
8354         /* Handle machine checks before interrupts are enabled */
8355         if (is_machine_check(exit_intr_info))
8356                 kvm_machine_check();
8357
8358         /* We need to handle NMIs before interrupts are enabled */
8359         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8360             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8361                 kvm_before_handle_nmi(&vmx->vcpu);
8362                 asm("int $2");
8363                 kvm_after_handle_nmi(&vmx->vcpu);
8364         }
8365 }
8366
8367 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8368 {
8369         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8370
8371         /*
8372          * If external interrupt exists, IF bit is set in rflags/eflags on the
8373          * interrupt stack frame, and interrupt will be enabled on a return
8374          * from interrupt handler.
8375          */
8376         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8377                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8378                 unsigned int vector;
8379                 unsigned long entry;
8380                 gate_desc *desc;
8381                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8382 #ifdef CONFIG_X86_64
8383                 unsigned long tmp;
8384 #endif
8385
8386                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8387                 desc = (gate_desc *)vmx->host_idt_base + vector;
8388                 entry = gate_offset(*desc);
8389                 asm volatile(
8390 #ifdef CONFIG_X86_64
8391                         "mov %%" _ASM_SP ", %[sp]\n\t"
8392                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8393                         "push $%c[ss]\n\t"
8394                         "push %[sp]\n\t"
8395 #endif
8396                         "pushf\n\t"
8397                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8398                         __ASM_SIZE(push) " $%c[cs]\n\t"
8399                         "call *%[entry]\n\t"
8400                         :
8401 #ifdef CONFIG_X86_64
8402                         [sp]"=&r"(tmp)
8403 #endif
8404                         :
8405                         [entry]"r"(entry),
8406                         [ss]"i"(__KERNEL_DS),
8407                         [cs]"i"(__KERNEL_CS)
8408                         );
8409         } else
8410                 local_irq_enable();
8411 }
8412
8413 static bool vmx_has_high_real_mode_segbase(void)
8414 {
8415         return enable_unrestricted_guest || emulate_invalid_guest_state;
8416 }
8417
8418 static bool vmx_mpx_supported(void)
8419 {
8420         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8421                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8422 }
8423
8424 static bool vmx_xsaves_supported(void)
8425 {
8426         return vmcs_config.cpu_based_2nd_exec_ctrl &
8427                 SECONDARY_EXEC_XSAVES;
8428 }
8429
8430 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8431 {
8432         u32 exit_intr_info;
8433         bool unblock_nmi;
8434         u8 vector;
8435         bool idtv_info_valid;
8436
8437         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8438
8439         if (cpu_has_virtual_nmis()) {
8440                 if (vmx->nmi_known_unmasked)
8441                         return;
8442                 /*
8443                  * Can't use vmx->exit_intr_info since we're not sure what
8444                  * the exit reason is.
8445                  */
8446                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8447                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8448                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8449                 /*
8450                  * SDM 3: 27.7.1.2 (September 2008)
8451                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8452                  * a guest IRET fault.
8453                  * SDM 3: 23.2.2 (September 2008)
8454                  * Bit 12 is undefined in any of the following cases:
8455                  *  If the VM exit sets the valid bit in the IDT-vectoring
8456                  *   information field.
8457                  *  If the VM exit is due to a double fault.
8458                  */
8459                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8460                     vector != DF_VECTOR && !idtv_info_valid)
8461                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8462                                       GUEST_INTR_STATE_NMI);
8463                 else
8464                         vmx->nmi_known_unmasked =
8465                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8466                                   & GUEST_INTR_STATE_NMI);
8467         } else if (unlikely(vmx->soft_vnmi_blocked))
8468                 vmx->vnmi_blocked_time +=
8469                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8470 }
8471
8472 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8473                                       u32 idt_vectoring_info,
8474                                       int instr_len_field,
8475                                       int error_code_field)
8476 {
8477         u8 vector;
8478         int type;
8479         bool idtv_info_valid;
8480
8481         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8482
8483         vcpu->arch.nmi_injected = false;
8484         kvm_clear_exception_queue(vcpu);
8485         kvm_clear_interrupt_queue(vcpu);
8486
8487         if (!idtv_info_valid)
8488                 return;
8489
8490         kvm_make_request(KVM_REQ_EVENT, vcpu);
8491
8492         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8493         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8494
8495         switch (type) {
8496         case INTR_TYPE_NMI_INTR:
8497                 vcpu->arch.nmi_injected = true;
8498                 /*
8499                  * SDM 3: 27.7.1.2 (September 2008)
8500                  * Clear bit "block by NMI" before VM entry if a NMI
8501                  * delivery faulted.
8502                  */
8503                 vmx_set_nmi_mask(vcpu, false);
8504                 break;
8505         case INTR_TYPE_SOFT_EXCEPTION:
8506                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8507                 /* fall through */
8508         case INTR_TYPE_HARD_EXCEPTION:
8509                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8510                         u32 err = vmcs_read32(error_code_field);
8511                         kvm_requeue_exception_e(vcpu, vector, err);
8512                 } else
8513                         kvm_requeue_exception(vcpu, vector);
8514                 break;
8515         case INTR_TYPE_SOFT_INTR:
8516                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8517                 /* fall through */
8518         case INTR_TYPE_EXT_INTR:
8519                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8520                 break;
8521         default:
8522                 break;
8523         }
8524 }
8525
8526 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8527 {
8528         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8529                                   VM_EXIT_INSTRUCTION_LEN,
8530                                   IDT_VECTORING_ERROR_CODE);
8531 }
8532
8533 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8534 {
8535         __vmx_complete_interrupts(vcpu,
8536                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8537                                   VM_ENTRY_INSTRUCTION_LEN,
8538                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8539
8540         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8541 }
8542
8543 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8544 {
8545         int i, nr_msrs;
8546         struct perf_guest_switch_msr *msrs;
8547
8548         msrs = perf_guest_get_msrs(&nr_msrs);
8549
8550         if (!msrs)
8551                 return;
8552
8553         for (i = 0; i < nr_msrs; i++)
8554                 if (msrs[i].host == msrs[i].guest)
8555                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8556                 else
8557                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8558                                         msrs[i].host);
8559 }
8560
8561 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8562 {
8563         struct vcpu_vmx *vmx = to_vmx(vcpu);
8564         unsigned long debugctlmsr, cr4;
8565
8566         /* Record the guest's net vcpu time for enforced NMI injections. */
8567         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8568                 vmx->entry_time = ktime_get();
8569
8570         /* Don't enter VMX if guest state is invalid, let the exit handler
8571            start emulation until we arrive back to a valid state */
8572         if (vmx->emulation_required)
8573                 return;
8574
8575         if (vmx->ple_window_dirty) {
8576                 vmx->ple_window_dirty = false;
8577                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8578         }
8579
8580         if (vmx->nested.sync_shadow_vmcs) {
8581                 copy_vmcs12_to_shadow(vmx);
8582                 vmx->nested.sync_shadow_vmcs = false;
8583         }
8584
8585         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8586                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8587         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8588                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8589
8590         cr4 = cr4_read_shadow();
8591         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8592                 vmcs_writel(HOST_CR4, cr4);
8593                 vmx->host_state.vmcs_host_cr4 = cr4;
8594         }
8595
8596         /* When single-stepping over STI and MOV SS, we must clear the
8597          * corresponding interruptibility bits in the guest state. Otherwise
8598          * vmentry fails as it then expects bit 14 (BS) in pending debug
8599          * exceptions being set, but that's not correct for the guest debugging
8600          * case. */
8601         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8602                 vmx_set_interrupt_shadow(vcpu, 0);
8603
8604         atomic_switch_perf_msrs(vmx);
8605         debugctlmsr = get_debugctlmsr();
8606
8607         vmx->__launched = vmx->loaded_vmcs->launched;
8608         asm(
8609                 /* Store host registers */
8610                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8611                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8612                 "push %%" _ASM_CX " \n\t"
8613                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8614                 "je 1f \n\t"
8615                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8616                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8617                 "1: \n\t"
8618                 /* Reload cr2 if changed */
8619                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8620                 "mov %%cr2, %%" _ASM_DX " \n\t"
8621                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8622                 "je 2f \n\t"
8623                 "mov %%" _ASM_AX", %%cr2 \n\t"
8624                 "2: \n\t"
8625                 /* Check if vmlaunch of vmresume is needed */
8626                 "cmpl $0, %c[launched](%0) \n\t"
8627                 /* Load guest registers.  Don't clobber flags. */
8628                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8629                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8630                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8631                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8632                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8633                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8634 #ifdef CONFIG_X86_64
8635                 "mov %c[r8](%0),  %%r8  \n\t"
8636                 "mov %c[r9](%0),  %%r9  \n\t"
8637                 "mov %c[r10](%0), %%r10 \n\t"
8638                 "mov %c[r11](%0), %%r11 \n\t"
8639                 "mov %c[r12](%0), %%r12 \n\t"
8640                 "mov %c[r13](%0), %%r13 \n\t"
8641                 "mov %c[r14](%0), %%r14 \n\t"
8642                 "mov %c[r15](%0), %%r15 \n\t"
8643 #endif
8644                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8645
8646                 /* Enter guest mode */
8647                 "jne 1f \n\t"
8648                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8649                 "jmp 2f \n\t"
8650                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8651                 "2: "
8652                 /* Save guest registers, load host registers, keep flags */
8653                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8654                 "pop %0 \n\t"
8655                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8656                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8657                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8658                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8659                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8660                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8661                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8662 #ifdef CONFIG_X86_64
8663                 "mov %%r8,  %c[r8](%0) \n\t"
8664                 "mov %%r9,  %c[r9](%0) \n\t"
8665                 "mov %%r10, %c[r10](%0) \n\t"
8666                 "mov %%r11, %c[r11](%0) \n\t"
8667                 "mov %%r12, %c[r12](%0) \n\t"
8668                 "mov %%r13, %c[r13](%0) \n\t"
8669                 "mov %%r14, %c[r14](%0) \n\t"
8670                 "mov %%r15, %c[r15](%0) \n\t"
8671 #endif
8672                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8673                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8674
8675                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8676                 "setbe %c[fail](%0) \n\t"
8677                 ".pushsection .rodata \n\t"
8678                 ".global vmx_return \n\t"
8679                 "vmx_return: " _ASM_PTR " 2b \n\t"
8680                 ".popsection"
8681               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8682                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8683                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8684                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8685                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8686                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8687                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8688                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8689                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8690                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8691                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8692 #ifdef CONFIG_X86_64
8693                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8694                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8695                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8696                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8697                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8698                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8699                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8700                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8701 #endif
8702                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8703                 [wordsize]"i"(sizeof(ulong))
8704               : "cc", "memory"
8705 #ifdef CONFIG_X86_64
8706                 , "rax", "rbx", "rdi", "rsi"
8707                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8708 #else
8709                 , "eax", "ebx", "edi", "esi"
8710 #endif
8711               );
8712
8713         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8714         if (debugctlmsr)
8715                 update_debugctlmsr(debugctlmsr);
8716
8717 #ifndef CONFIG_X86_64
8718         /*
8719          * The sysexit path does not restore ds/es, so we must set them to
8720          * a reasonable value ourselves.
8721          *
8722          * We can't defer this to vmx_load_host_state() since that function
8723          * may be executed in interrupt context, which saves and restore segments
8724          * around it, nullifying its effect.
8725          */
8726         loadsegment(ds, __USER_DS);
8727         loadsegment(es, __USER_DS);
8728 #endif
8729
8730         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8731                                   | (1 << VCPU_EXREG_RFLAGS)
8732                                   | (1 << VCPU_EXREG_PDPTR)
8733                                   | (1 << VCPU_EXREG_SEGMENTS)
8734                                   | (1 << VCPU_EXREG_CR3));
8735         vcpu->arch.regs_dirty = 0;
8736
8737         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8738
8739         vmx->loaded_vmcs->launched = 1;
8740
8741         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8742
8743         /*
8744          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8745          * we did not inject a still-pending event to L1 now because of
8746          * nested_run_pending, we need to re-enable this bit.
8747          */
8748         if (vmx->nested.nested_run_pending)
8749                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8750
8751         vmx->nested.nested_run_pending = 0;
8752
8753         vmx_complete_atomic_exit(vmx);
8754         vmx_recover_nmi_blocking(vmx);
8755         vmx_complete_interrupts(vmx);
8756 }
8757
8758 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8759 {
8760         struct vcpu_vmx *vmx = to_vmx(vcpu);
8761         int cpu;
8762
8763         if (vmx->loaded_vmcs == &vmx->vmcs01)
8764                 return;
8765
8766         cpu = get_cpu();
8767         vmx->loaded_vmcs = &vmx->vmcs01;
8768         vmx_vcpu_put(vcpu);
8769         vmx_vcpu_load(vcpu, cpu);
8770         vcpu->cpu = cpu;
8771         put_cpu();
8772 }
8773
8774 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8775 {
8776         struct vcpu_vmx *vmx = to_vmx(vcpu);
8777
8778         if (enable_pml)
8779                 vmx_destroy_pml_buffer(vmx);
8780         free_vpid(vmx->vpid);
8781         leave_guest_mode(vcpu);
8782         vmx_load_vmcs01(vcpu);
8783         free_nested(vmx);
8784         free_loaded_vmcs(vmx->loaded_vmcs);
8785         kfree(vmx->guest_msrs);
8786         kvm_vcpu_uninit(vcpu);
8787         kmem_cache_free(kvm_vcpu_cache, vmx);
8788 }
8789
8790 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8791 {
8792         int err;
8793         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8794         int cpu;
8795
8796         if (!vmx)
8797                 return ERR_PTR(-ENOMEM);
8798
8799         vmx->vpid = allocate_vpid();
8800
8801         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8802         if (err)
8803                 goto free_vcpu;
8804
8805         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8806         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8807                      > PAGE_SIZE);
8808
8809         err = -ENOMEM;
8810         if (!vmx->guest_msrs) {
8811                 goto uninit_vcpu;
8812         }
8813
8814         vmx->loaded_vmcs = &vmx->vmcs01;
8815         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8816         if (!vmx->loaded_vmcs->vmcs)
8817                 goto free_msrs;
8818         if (!vmm_exclusive)
8819                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8820         loaded_vmcs_init(vmx->loaded_vmcs);
8821         if (!vmm_exclusive)
8822                 kvm_cpu_vmxoff();
8823
8824         cpu = get_cpu();
8825         vmx_vcpu_load(&vmx->vcpu, cpu);
8826         vmx->vcpu.cpu = cpu;
8827         err = vmx_vcpu_setup(vmx);
8828         vmx_vcpu_put(&vmx->vcpu);
8829         put_cpu();
8830         if (err)
8831                 goto free_vmcs;
8832         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8833                 err = alloc_apic_access_page(kvm);
8834                 if (err)
8835                         goto free_vmcs;
8836         }
8837
8838         if (enable_ept) {
8839                 if (!kvm->arch.ept_identity_map_addr)
8840                         kvm->arch.ept_identity_map_addr =
8841                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8842                 err = init_rmode_identity_map(kvm);
8843                 if (err)
8844                         goto free_vmcs;
8845         }
8846
8847         if (nested) {
8848                 nested_vmx_setup_ctls_msrs(vmx);
8849                 vmx->nested.vpid02 = allocate_vpid();
8850         }
8851
8852         vmx->nested.posted_intr_nv = -1;
8853         vmx->nested.current_vmptr = -1ull;
8854         vmx->nested.current_vmcs12 = NULL;
8855
8856         /*
8857          * If PML is turned on, failure on enabling PML just results in failure
8858          * of creating the vcpu, therefore we can simplify PML logic (by
8859          * avoiding dealing with cases, such as enabling PML partially on vcpus
8860          * for the guest, etc.
8861          */
8862         if (enable_pml) {
8863                 err = vmx_create_pml_buffer(vmx);
8864                 if (err)
8865                         goto free_vmcs;
8866         }
8867
8868         return &vmx->vcpu;
8869
8870 free_vmcs:
8871         free_vpid(vmx->nested.vpid02);
8872         free_loaded_vmcs(vmx->loaded_vmcs);
8873 free_msrs:
8874         kfree(vmx->guest_msrs);
8875 uninit_vcpu:
8876         kvm_vcpu_uninit(&vmx->vcpu);
8877 free_vcpu:
8878         free_vpid(vmx->vpid);
8879         kmem_cache_free(kvm_vcpu_cache, vmx);
8880         return ERR_PTR(err);
8881 }
8882
8883 static void __init vmx_check_processor_compat(void *rtn)
8884 {
8885         struct vmcs_config vmcs_conf;
8886
8887         *(int *)rtn = 0;
8888         if (setup_vmcs_config(&vmcs_conf) < 0)
8889                 *(int *)rtn = -EIO;
8890         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8891                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8892                                 smp_processor_id());
8893                 *(int *)rtn = -EIO;
8894         }
8895 }
8896
8897 static int get_ept_level(void)
8898 {
8899         return VMX_EPT_DEFAULT_GAW + 1;
8900 }
8901
8902 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8903 {
8904         u8 cache;
8905         u64 ipat = 0;
8906
8907         /* For VT-d and EPT combination
8908          * 1. MMIO: always map as UC
8909          * 2. EPT with VT-d:
8910          *   a. VT-d without snooping control feature: can't guarantee the
8911          *      result, try to trust guest.
8912          *   b. VT-d with snooping control feature: snooping control feature of
8913          *      VT-d engine can guarantee the cache correctness. Just set it
8914          *      to WB to keep consistent with host. So the same as item 3.
8915          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8916          *    consistent with host MTRR
8917          */
8918         if (is_mmio) {
8919                 cache = MTRR_TYPE_UNCACHABLE;
8920                 goto exit;
8921         }
8922
8923         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8924                 ipat = VMX_EPT_IPAT_BIT;
8925                 cache = MTRR_TYPE_WRBACK;
8926                 goto exit;
8927         }
8928
8929         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8930                 ipat = VMX_EPT_IPAT_BIT;
8931                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8932                         cache = MTRR_TYPE_WRBACK;
8933                 else
8934                         cache = MTRR_TYPE_UNCACHABLE;
8935                 goto exit;
8936         }
8937
8938         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8939
8940 exit:
8941         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8942 }
8943
8944 static int vmx_get_lpage_level(void)
8945 {
8946         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8947                 return PT_DIRECTORY_LEVEL;
8948         else
8949                 /* For shadow and EPT supported 1GB page */
8950                 return PT_PDPE_LEVEL;
8951 }
8952
8953 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8954 {
8955         /*
8956          * These bits in the secondary execution controls field
8957          * are dynamic, the others are mostly based on the hypervisor
8958          * architecture and the guest's CPUID.  Do not touch the
8959          * dynamic bits.
8960          */
8961         u32 mask =
8962                 SECONDARY_EXEC_SHADOW_VMCS |
8963                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8964                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8965
8966         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8967
8968         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8969                      (new_ctl & ~mask) | (cur_ctl & mask));
8970 }
8971
8972 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8973 {
8974         struct kvm_cpuid_entry2 *best;
8975         struct vcpu_vmx *vmx = to_vmx(vcpu);
8976         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8977
8978         if (vmx_rdtscp_supported()) {
8979                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8980                 if (!rdtscp_enabled)
8981                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8982
8983                 if (nested) {
8984                         if (rdtscp_enabled)
8985                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8986                                         SECONDARY_EXEC_RDTSCP;
8987                         else
8988                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8989                                         ~SECONDARY_EXEC_RDTSCP;
8990                 }
8991         }
8992
8993         /* Exposing INVPCID only when PCID is exposed */
8994         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8995         if (vmx_invpcid_supported() &&
8996             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8997             !guest_cpuid_has_pcid(vcpu))) {
8998                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8999
9000                 if (best)
9001                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9002         }
9003
9004         if (cpu_has_secondary_exec_ctrls())
9005                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9006
9007         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9008                 if (guest_cpuid_has_pcommit(vcpu))
9009                         vmx->nested.nested_vmx_secondary_ctls_high |=
9010                                 SECONDARY_EXEC_PCOMMIT;
9011                 else
9012                         vmx->nested.nested_vmx_secondary_ctls_high &=
9013                                 ~SECONDARY_EXEC_PCOMMIT;
9014         }
9015 }
9016
9017 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9018 {
9019         if (func == 1 && nested)
9020                 entry->ecx |= bit(X86_FEATURE_VMX);
9021 }
9022
9023 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9024                 struct x86_exception *fault)
9025 {
9026         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9027         u32 exit_reason;
9028
9029         if (fault->error_code & PFERR_RSVD_MASK)
9030                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9031         else
9032                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9033         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9034         vmcs12->guest_physical_address = fault->address;
9035 }
9036
9037 /* Callbacks for nested_ept_init_mmu_context: */
9038
9039 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9040 {
9041         /* return the page table to be shadowed - in our case, EPT12 */
9042         return get_vmcs12(vcpu)->ept_pointer;
9043 }
9044
9045 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9046 {
9047         WARN_ON(mmu_is_nested(vcpu));
9048         kvm_init_shadow_ept_mmu(vcpu,
9049                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9050                         VMX_EPT_EXECUTE_ONLY_BIT);
9051         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9052         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9053         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9054
9055         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9056 }
9057
9058 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9059 {
9060         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9061 }
9062
9063 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9064                                             u16 error_code)
9065 {
9066         bool inequality, bit;
9067
9068         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9069         inequality =
9070                 (error_code & vmcs12->page_fault_error_code_mask) !=
9071                  vmcs12->page_fault_error_code_match;
9072         return inequality ^ bit;
9073 }
9074
9075 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9076                 struct x86_exception *fault)
9077 {
9078         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9079
9080         WARN_ON(!is_guest_mode(vcpu));
9081
9082         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9083                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9084                                   vmcs_read32(VM_EXIT_INTR_INFO),
9085                                   vmcs_readl(EXIT_QUALIFICATION));
9086         else
9087                 kvm_inject_page_fault(vcpu, fault);
9088 }
9089
9090 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9091                                         struct vmcs12 *vmcs12)
9092 {
9093         struct vcpu_vmx *vmx = to_vmx(vcpu);
9094         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9095
9096         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9097                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9098                     vmcs12->apic_access_addr >> maxphyaddr)
9099                         return false;
9100
9101                 /*
9102                  * Translate L1 physical address to host physical
9103                  * address for vmcs02. Keep the page pinned, so this
9104                  * physical address remains valid. We keep a reference
9105                  * to it so we can release it later.
9106                  */
9107                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9108                         nested_release_page(vmx->nested.apic_access_page);
9109                 vmx->nested.apic_access_page =
9110                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9111         }
9112
9113         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9114                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9115                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9116                         return false;
9117
9118                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9119                         nested_release_page(vmx->nested.virtual_apic_page);
9120                 vmx->nested.virtual_apic_page =
9121                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9122
9123                 /*
9124                  * Failing the vm entry is _not_ what the processor does
9125                  * but it's basically the only possibility we have.
9126                  * We could still enter the guest if CR8 load exits are
9127                  * enabled, CR8 store exits are enabled, and virtualize APIC
9128                  * access is disabled; in this case the processor would never
9129                  * use the TPR shadow and we could simply clear the bit from
9130                  * the execution control.  But such a configuration is useless,
9131                  * so let's keep the code simple.
9132                  */
9133                 if (!vmx->nested.virtual_apic_page)
9134                         return false;
9135         }
9136
9137         if (nested_cpu_has_posted_intr(vmcs12)) {
9138                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9139                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9140                         return false;
9141
9142                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9143                         kunmap(vmx->nested.pi_desc_page);
9144                         nested_release_page(vmx->nested.pi_desc_page);
9145                 }
9146                 vmx->nested.pi_desc_page =
9147                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9148                 if (!vmx->nested.pi_desc_page)
9149                         return false;
9150
9151                 vmx->nested.pi_desc =
9152                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9153                 if (!vmx->nested.pi_desc) {
9154                         nested_release_page_clean(vmx->nested.pi_desc_page);
9155                         return false;
9156                 }
9157                 vmx->nested.pi_desc =
9158                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9159                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9160                         (PAGE_SIZE - 1)));
9161         }
9162
9163         return true;
9164 }
9165
9166 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9167 {
9168         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9169         struct vcpu_vmx *vmx = to_vmx(vcpu);
9170
9171         if (vcpu->arch.virtual_tsc_khz == 0)
9172                 return;
9173
9174         /* Make sure short timeouts reliably trigger an immediate vmexit.
9175          * hrtimer_start does not guarantee this. */
9176         if (preemption_timeout <= 1) {
9177                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9178                 return;
9179         }
9180
9181         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9182         preemption_timeout *= 1000000;
9183         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9184         hrtimer_start(&vmx->nested.preemption_timer,
9185                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9186 }
9187
9188 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9189                                                 struct vmcs12 *vmcs12)
9190 {
9191         int maxphyaddr;
9192         u64 addr;
9193
9194         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9195                 return 0;
9196
9197         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9198                 WARN_ON(1);
9199                 return -EINVAL;
9200         }
9201         maxphyaddr = cpuid_maxphyaddr(vcpu);
9202
9203         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9204            ((addr + PAGE_SIZE) >> maxphyaddr))
9205                 return -EINVAL;
9206
9207         return 0;
9208 }
9209
9210 /*
9211  * Merge L0's and L1's MSR bitmap, return false to indicate that
9212  * we do not use the hardware.
9213  */
9214 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9215                                                struct vmcs12 *vmcs12)
9216 {
9217         int msr;
9218         struct page *page;
9219         unsigned long *msr_bitmap;
9220
9221         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9222                 return false;
9223
9224         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9225         if (!page) {
9226                 WARN_ON(1);
9227                 return false;
9228         }
9229         msr_bitmap = (unsigned long *)kmap(page);
9230         if (!msr_bitmap) {
9231                 nested_release_page_clean(page);
9232                 WARN_ON(1);
9233                 return false;
9234         }
9235
9236         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9237                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9238                         for (msr = 0x800; msr <= 0x8ff; msr++)
9239                                 nested_vmx_disable_intercept_for_msr(
9240                                         msr_bitmap,
9241                                         vmx_msr_bitmap_nested,
9242                                         msr, MSR_TYPE_R);
9243                 /* TPR is allowed */
9244                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9245                                 vmx_msr_bitmap_nested,
9246                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9247                                 MSR_TYPE_R | MSR_TYPE_W);
9248                 if (nested_cpu_has_vid(vmcs12)) {
9249                         /* EOI and self-IPI are allowed */
9250                         nested_vmx_disable_intercept_for_msr(
9251                                 msr_bitmap,
9252                                 vmx_msr_bitmap_nested,
9253                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9254                                 MSR_TYPE_W);
9255                         nested_vmx_disable_intercept_for_msr(
9256                                 msr_bitmap,
9257                                 vmx_msr_bitmap_nested,
9258                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9259                                 MSR_TYPE_W);
9260                 }
9261         } else {
9262                 /*
9263                  * Enable reading intercept of all the x2apic
9264                  * MSRs. We should not rely on vmcs12 to do any
9265                  * optimizations here, it may have been modified
9266                  * by L1.
9267                  */
9268                 for (msr = 0x800; msr <= 0x8ff; msr++)
9269                         __vmx_enable_intercept_for_msr(
9270                                 vmx_msr_bitmap_nested,
9271                                 msr,
9272                                 MSR_TYPE_R);
9273
9274                 __vmx_enable_intercept_for_msr(
9275                                 vmx_msr_bitmap_nested,
9276                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9277                                 MSR_TYPE_W);
9278                 __vmx_enable_intercept_for_msr(
9279                                 vmx_msr_bitmap_nested,
9280                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9281                                 MSR_TYPE_W);
9282                 __vmx_enable_intercept_for_msr(
9283                                 vmx_msr_bitmap_nested,
9284                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9285                                 MSR_TYPE_W);
9286         }
9287         kunmap(page);
9288         nested_release_page_clean(page);
9289
9290         return true;
9291 }
9292
9293 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9294                                            struct vmcs12 *vmcs12)
9295 {
9296         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9297             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9298             !nested_cpu_has_vid(vmcs12) &&
9299             !nested_cpu_has_posted_intr(vmcs12))
9300                 return 0;
9301
9302         /*
9303          * If virtualize x2apic mode is enabled,
9304          * virtualize apic access must be disabled.
9305          */
9306         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9307             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9308                 return -EINVAL;
9309
9310         /*
9311          * If virtual interrupt delivery is enabled,
9312          * we must exit on external interrupts.
9313          */
9314         if (nested_cpu_has_vid(vmcs12) &&
9315            !nested_exit_on_intr(vcpu))
9316                 return -EINVAL;
9317
9318         /*
9319          * bits 15:8 should be zero in posted_intr_nv,
9320          * the descriptor address has been already checked
9321          * in nested_get_vmcs12_pages.
9322          */
9323         if (nested_cpu_has_posted_intr(vmcs12) &&
9324            (!nested_cpu_has_vid(vmcs12) ||
9325             !nested_exit_intr_ack_set(vcpu) ||
9326             vmcs12->posted_intr_nv & 0xff00))
9327                 return -EINVAL;
9328
9329         /* tpr shadow is needed by all apicv features. */
9330         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9331                 return -EINVAL;
9332
9333         return 0;
9334 }
9335
9336 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9337                                        unsigned long count_field,
9338                                        unsigned long addr_field)
9339 {
9340         int maxphyaddr;
9341         u64 count, addr;
9342
9343         if (vmcs12_read_any(vcpu, count_field, &count) ||
9344             vmcs12_read_any(vcpu, addr_field, &addr)) {
9345                 WARN_ON(1);
9346                 return -EINVAL;
9347         }
9348         if (count == 0)
9349                 return 0;
9350         maxphyaddr = cpuid_maxphyaddr(vcpu);
9351         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9352             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9353                 pr_warn_ratelimited(
9354                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9355                         addr_field, maxphyaddr, count, addr);
9356                 return -EINVAL;
9357         }
9358         return 0;
9359 }
9360
9361 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9362                                                 struct vmcs12 *vmcs12)
9363 {
9364         if (vmcs12->vm_exit_msr_load_count == 0 &&
9365             vmcs12->vm_exit_msr_store_count == 0 &&
9366             vmcs12->vm_entry_msr_load_count == 0)
9367                 return 0; /* Fast path */
9368         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9369                                         VM_EXIT_MSR_LOAD_ADDR) ||
9370             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9371                                         VM_EXIT_MSR_STORE_ADDR) ||
9372             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9373                                         VM_ENTRY_MSR_LOAD_ADDR))
9374                 return -EINVAL;
9375         return 0;
9376 }
9377
9378 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9379                                        struct vmx_msr_entry *e)
9380 {
9381         /* x2APIC MSR accesses are not allowed */
9382         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9383                 return -EINVAL;
9384         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9385             e->index == MSR_IA32_UCODE_REV)
9386                 return -EINVAL;
9387         if (e->reserved != 0)
9388                 return -EINVAL;
9389         return 0;
9390 }
9391
9392 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9393                                      struct vmx_msr_entry *e)
9394 {
9395         if (e->index == MSR_FS_BASE ||
9396             e->index == MSR_GS_BASE ||
9397             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9398             nested_vmx_msr_check_common(vcpu, e))
9399                 return -EINVAL;
9400         return 0;
9401 }
9402
9403 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9404                                       struct vmx_msr_entry *e)
9405 {
9406         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9407             nested_vmx_msr_check_common(vcpu, e))
9408                 return -EINVAL;
9409         return 0;
9410 }
9411
9412 /*
9413  * Load guest's/host's msr at nested entry/exit.
9414  * return 0 for success, entry index for failure.
9415  */
9416 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9417 {
9418         u32 i;
9419         struct vmx_msr_entry e;
9420         struct msr_data msr;
9421
9422         msr.host_initiated = false;
9423         for (i = 0; i < count; i++) {
9424                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9425                                         &e, sizeof(e))) {
9426                         pr_warn_ratelimited(
9427                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9428                                 __func__, i, gpa + i * sizeof(e));
9429                         goto fail;
9430                 }
9431                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9432                         pr_warn_ratelimited(
9433                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9434                                 __func__, i, e.index, e.reserved);
9435                         goto fail;
9436                 }
9437                 msr.index = e.index;
9438                 msr.data = e.value;
9439                 if (kvm_set_msr(vcpu, &msr)) {
9440                         pr_warn_ratelimited(
9441                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9442                                 __func__, i, e.index, e.value);
9443                         goto fail;
9444                 }
9445         }
9446         return 0;
9447 fail:
9448         return i + 1;
9449 }
9450
9451 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9452 {
9453         u32 i;
9454         struct vmx_msr_entry e;
9455
9456         for (i = 0; i < count; i++) {
9457                 struct msr_data msr_info;
9458                 if (kvm_vcpu_read_guest(vcpu,
9459                                         gpa + i * sizeof(e),
9460                                         &e, 2 * sizeof(u32))) {
9461                         pr_warn_ratelimited(
9462                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9463                                 __func__, i, gpa + i * sizeof(e));
9464                         return -EINVAL;
9465                 }
9466                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9467                         pr_warn_ratelimited(
9468                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9469                                 __func__, i, e.index, e.reserved);
9470                         return -EINVAL;
9471                 }
9472                 msr_info.host_initiated = false;
9473                 msr_info.index = e.index;
9474                 if (kvm_get_msr(vcpu, &msr_info)) {
9475                         pr_warn_ratelimited(
9476                                 "%s cannot read MSR (%u, 0x%x)\n",
9477                                 __func__, i, e.index);
9478                         return -EINVAL;
9479                 }
9480                 if (kvm_vcpu_write_guest(vcpu,
9481                                          gpa + i * sizeof(e) +
9482                                              offsetof(struct vmx_msr_entry, value),
9483                                          &msr_info.data, sizeof(msr_info.data))) {
9484                         pr_warn_ratelimited(
9485                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9486                                 __func__, i, e.index, msr_info.data);
9487                         return -EINVAL;
9488                 }
9489         }
9490         return 0;
9491 }
9492
9493 /*
9494  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9495  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9496  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9497  * guest in a way that will both be appropriate to L1's requests, and our
9498  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9499  * function also has additional necessary side-effects, like setting various
9500  * vcpu->arch fields.
9501  */
9502 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9503 {
9504         struct vcpu_vmx *vmx = to_vmx(vcpu);
9505         u32 exec_control;
9506
9507         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9508         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9509         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9510         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9511         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9512         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9513         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9514         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9515         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9516         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9517         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9518         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9519         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9520         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9521         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9522         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9523         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9524         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9525         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9526         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9527         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9528         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9529         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9530         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9531         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9532         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9533         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9534         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9535         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9536         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9537         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9538         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9539         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9540         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9541         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9542         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9543
9544         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9545                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9546                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9547         } else {
9548                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9549                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9550         }
9551         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9552                 vmcs12->vm_entry_intr_info_field);
9553         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9554                 vmcs12->vm_entry_exception_error_code);
9555         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9556                 vmcs12->vm_entry_instruction_len);
9557         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9558                 vmcs12->guest_interruptibility_info);
9559         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9560         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9561         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9562                 vmcs12->guest_pending_dbg_exceptions);
9563         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9564         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9565
9566         if (nested_cpu_has_xsaves(vmcs12))
9567                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9568         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9569
9570         exec_control = vmcs12->pin_based_vm_exec_control;
9571         exec_control |= vmcs_config.pin_based_exec_ctrl;
9572         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9573
9574         if (nested_cpu_has_posted_intr(vmcs12)) {
9575                 /*
9576                  * Note that we use L0's vector here and in
9577                  * vmx_deliver_nested_posted_interrupt.
9578                  */
9579                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9580                 vmx->nested.pi_pending = false;
9581                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9582                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9583                         page_to_phys(vmx->nested.pi_desc_page) +
9584                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9585                         (PAGE_SIZE - 1)));
9586         } else
9587                 exec_control &= ~PIN_BASED_POSTED_INTR;
9588
9589         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9590
9591         vmx->nested.preemption_timer_expired = false;
9592         if (nested_cpu_has_preemption_timer(vmcs12))
9593                 vmx_start_preemption_timer(vcpu);
9594
9595         /*
9596          * Whether page-faults are trapped is determined by a combination of
9597          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9598          * If enable_ept, L0 doesn't care about page faults and we should
9599          * set all of these to L1's desires. However, if !enable_ept, L0 does
9600          * care about (at least some) page faults, and because it is not easy
9601          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9602          * to exit on each and every L2 page fault. This is done by setting
9603          * MASK=MATCH=0 and (see below) EB.PF=1.
9604          * Note that below we don't need special code to set EB.PF beyond the
9605          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9606          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9607          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9608          *
9609          * A problem with this approach (when !enable_ept) is that L1 may be
9610          * injected with more page faults than it asked for. This could have
9611          * caused problems, but in practice existing hypervisors don't care.
9612          * To fix this, we will need to emulate the PFEC checking (on the L1
9613          * page tables), using walk_addr(), when injecting PFs to L1.
9614          */
9615         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9616                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9617         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9618                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9619
9620         if (cpu_has_secondary_exec_ctrls()) {
9621                 exec_control = vmx_secondary_exec_control(vmx);
9622
9623                 /* Take the following fields only from vmcs12 */
9624                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9625                                   SECONDARY_EXEC_RDTSCP |
9626                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9627                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9628                                   SECONDARY_EXEC_PCOMMIT);
9629                 if (nested_cpu_has(vmcs12,
9630                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9631                         exec_control |= vmcs12->secondary_vm_exec_control;
9632
9633                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9634                         /*
9635                          * If translation failed, no matter: This feature asks
9636                          * to exit when accessing the given address, and if it
9637                          * can never be accessed, this feature won't do
9638                          * anything anyway.
9639                          */
9640                         if (!vmx->nested.apic_access_page)
9641                                 exec_control &=
9642                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9643                         else
9644                                 vmcs_write64(APIC_ACCESS_ADDR,
9645                                   page_to_phys(vmx->nested.apic_access_page));
9646                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9647                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9648                         exec_control |=
9649                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9650                         kvm_vcpu_reload_apic_access_page(vcpu);
9651                 }
9652
9653                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9654                         vmcs_write64(EOI_EXIT_BITMAP0,
9655                                 vmcs12->eoi_exit_bitmap0);
9656                         vmcs_write64(EOI_EXIT_BITMAP1,
9657                                 vmcs12->eoi_exit_bitmap1);
9658                         vmcs_write64(EOI_EXIT_BITMAP2,
9659                                 vmcs12->eoi_exit_bitmap2);
9660                         vmcs_write64(EOI_EXIT_BITMAP3,
9661                                 vmcs12->eoi_exit_bitmap3);
9662                         vmcs_write16(GUEST_INTR_STATUS,
9663                                 vmcs12->guest_intr_status);
9664                 }
9665
9666                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9667         }
9668
9669
9670         /*
9671          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9672          * Some constant fields are set here by vmx_set_constant_host_state().
9673          * Other fields are different per CPU, and will be set later when
9674          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9675          */
9676         vmx_set_constant_host_state(vmx);
9677
9678         /*
9679          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9680          * entry, but only if the current (host) sp changed from the value
9681          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9682          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9683          * here we just force the write to happen on entry.
9684          */
9685         vmx->host_rsp = 0;
9686
9687         exec_control = vmx_exec_control(vmx); /* L0's desires */
9688         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9689         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9690         exec_control &= ~CPU_BASED_TPR_SHADOW;
9691         exec_control |= vmcs12->cpu_based_vm_exec_control;
9692
9693         if (exec_control & CPU_BASED_TPR_SHADOW) {
9694                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9695                                 page_to_phys(vmx->nested.virtual_apic_page));
9696                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9697         }
9698
9699         if (cpu_has_vmx_msr_bitmap() &&
9700             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9701                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9702                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9703         } else
9704                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9705
9706         /*
9707          * Merging of IO bitmap not currently supported.
9708          * Rather, exit every time.
9709          */
9710         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9711         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9712
9713         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9714
9715         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9716          * bitwise-or of what L1 wants to trap for L2, and what we want to
9717          * trap. Note that CR0.TS also needs updating - we do this later.
9718          */
9719         update_exception_bitmap(vcpu);
9720         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9721         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9722
9723         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9724          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9725          * bits are further modified by vmx_set_efer() below.
9726          */
9727         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9728
9729         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9730          * emulated by vmx_set_efer(), below.
9731          */
9732         vm_entry_controls_init(vmx,
9733                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9734                         ~VM_ENTRY_IA32E_MODE) |
9735                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9736
9737         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9738                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9739                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9740         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9741                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9742
9743
9744         set_cr4_guest_host_mask(vmx);
9745
9746         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9747                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9748
9749         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9750                 vmcs_write64(TSC_OFFSET,
9751                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9752         else
9753                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9754
9755         if (enable_vpid) {
9756                 /*
9757                  * There is no direct mapping between vpid02 and vpid12, the
9758                  * vpid02 is per-vCPU for L0 and reused while the value of
9759                  * vpid12 is changed w/ one invvpid during nested vmentry.
9760                  * The vpid12 is allocated by L1 for L2, so it will not
9761                  * influence global bitmap(for vpid01 and vpid02 allocation)
9762                  * even if spawn a lot of nested vCPUs.
9763                  */
9764                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9765                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9766                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9767                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9768                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9769                         }
9770                 } else {
9771                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9772                         vmx_flush_tlb(vcpu);
9773                 }
9774
9775         }
9776
9777         if (nested_cpu_has_ept(vmcs12)) {
9778                 kvm_mmu_unload(vcpu);
9779                 nested_ept_init_mmu_context(vcpu);
9780         }
9781
9782         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9783                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9784         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9785                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9786         else
9787                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9788         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9789         vmx_set_efer(vcpu, vcpu->arch.efer);
9790
9791         /*
9792          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9793          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9794          * The CR0_READ_SHADOW is what L2 should have expected to read given
9795          * the specifications by L1; It's not enough to take
9796          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9797          * have more bits than L1 expected.
9798          */
9799         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9800         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9801
9802         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9803         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9804
9805         /* shadow page tables on either EPT or shadow page tables */
9806         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9807         kvm_mmu_reset_context(vcpu);
9808
9809         if (!enable_ept)
9810                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9811
9812         /*
9813          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9814          */
9815         if (enable_ept) {
9816                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9817                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9818                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9819                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9820         }
9821
9822         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9823         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9824 }
9825
9826 /*
9827  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9828  * for running an L2 nested guest.
9829  */
9830 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9831 {
9832         struct vmcs12 *vmcs12;
9833         struct vcpu_vmx *vmx = to_vmx(vcpu);
9834         int cpu;
9835         struct loaded_vmcs *vmcs02;
9836         bool ia32e;
9837         u32 msr_entry_idx;
9838
9839         if (!nested_vmx_check_permission(vcpu) ||
9840             !nested_vmx_check_vmcs12(vcpu))
9841                 return 1;
9842
9843         skip_emulated_instruction(vcpu);
9844         vmcs12 = get_vmcs12(vcpu);
9845
9846         if (enable_shadow_vmcs)
9847                 copy_shadow_to_vmcs12(vmx);
9848
9849         /*
9850          * The nested entry process starts with enforcing various prerequisites
9851          * on vmcs12 as required by the Intel SDM, and act appropriately when
9852          * they fail: As the SDM explains, some conditions should cause the
9853          * instruction to fail, while others will cause the instruction to seem
9854          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9855          * To speed up the normal (success) code path, we should avoid checking
9856          * for misconfigurations which will anyway be caught by the processor
9857          * when using the merged vmcs02.
9858          */
9859         if (vmcs12->launch_state == launch) {
9860                 nested_vmx_failValid(vcpu,
9861                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9862                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9863                 return 1;
9864         }
9865
9866         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9867             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9868                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9869                 return 1;
9870         }
9871
9872         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9873                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9874                 return 1;
9875         }
9876
9877         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9878                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9879                 return 1;
9880         }
9881
9882         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9883                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9884                 return 1;
9885         }
9886
9887         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9888                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9889                 return 1;
9890         }
9891
9892         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9893                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9894                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9895             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9896                                 vmx->nested.nested_vmx_secondary_ctls_low,
9897                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9898             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9899                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9900                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9901             !vmx_control_verify(vmcs12->vm_exit_controls,
9902                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9903                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9904             !vmx_control_verify(vmcs12->vm_entry_controls,
9905                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9906                                 vmx->nested.nested_vmx_entry_ctls_high))
9907         {
9908                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9909                 return 1;
9910         }
9911
9912         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9913             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9914                 nested_vmx_failValid(vcpu,
9915                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9916                 return 1;
9917         }
9918
9919         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9920             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9921                 nested_vmx_entry_failure(vcpu, vmcs12,
9922                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9923                 return 1;
9924         }
9925         if (vmcs12->vmcs_link_pointer != -1ull) {
9926                 nested_vmx_entry_failure(vcpu, vmcs12,
9927                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9928                 return 1;
9929         }
9930
9931         /*
9932          * If the load IA32_EFER VM-entry control is 1, the following checks
9933          * are performed on the field for the IA32_EFER MSR:
9934          * - Bits reserved in the IA32_EFER MSR must be 0.
9935          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9936          *   the IA-32e mode guest VM-exit control. It must also be identical
9937          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9938          *   CR0.PG) is 1.
9939          */
9940         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9941                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9942                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9943                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9944                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9945                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9946                         nested_vmx_entry_failure(vcpu, vmcs12,
9947                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9948                         return 1;
9949                 }
9950         }
9951
9952         /*
9953          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9954          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9955          * the values of the LMA and LME bits in the field must each be that of
9956          * the host address-space size VM-exit control.
9957          */
9958         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9959                 ia32e = (vmcs12->vm_exit_controls &
9960                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9961                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9962                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9963                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9964                         nested_vmx_entry_failure(vcpu, vmcs12,
9965                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9966                         return 1;
9967                 }
9968         }
9969
9970         /*
9971          * We're finally done with prerequisite checking, and can start with
9972          * the nested entry.
9973          */
9974
9975         vmcs02 = nested_get_current_vmcs02(vmx);
9976         if (!vmcs02)
9977                 return -ENOMEM;
9978
9979         enter_guest_mode(vcpu);
9980
9981         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9982
9983         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9984                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9985
9986         cpu = get_cpu();
9987         vmx->loaded_vmcs = vmcs02;
9988         vmx_vcpu_put(vcpu);
9989         vmx_vcpu_load(vcpu, cpu);
9990         vcpu->cpu = cpu;
9991         put_cpu();
9992
9993         vmx_segment_cache_clear(vmx);
9994
9995         prepare_vmcs02(vcpu, vmcs12);
9996
9997         msr_entry_idx = nested_vmx_load_msr(vcpu,
9998                                             vmcs12->vm_entry_msr_load_addr,
9999                                             vmcs12->vm_entry_msr_load_count);
10000         if (msr_entry_idx) {
10001                 leave_guest_mode(vcpu);
10002                 vmx_load_vmcs01(vcpu);
10003                 nested_vmx_entry_failure(vcpu, vmcs12,
10004                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10005                 return 1;
10006         }
10007
10008         vmcs12->launch_state = 1;
10009
10010         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10011                 return kvm_vcpu_halt(vcpu);
10012
10013         vmx->nested.nested_run_pending = 1;
10014
10015         /*
10016          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10017          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10018          * returned as far as L1 is concerned. It will only return (and set
10019          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10020          */
10021         return 1;
10022 }
10023
10024 /*
10025  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10026  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10027  * This function returns the new value we should put in vmcs12.guest_cr0.
10028  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10029  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10030  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10031  *     didn't trap the bit, because if L1 did, so would L0).
10032  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10033  *     been modified by L2, and L1 knows it. So just leave the old value of
10034  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10035  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10036  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10037  *     changed these bits, and therefore they need to be updated, but L0
10038  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10039  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10040  */
10041 static inline unsigned long
10042 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10043 {
10044         return
10045         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10046         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10047         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10048                         vcpu->arch.cr0_guest_owned_bits));
10049 }
10050
10051 static inline unsigned long
10052 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10053 {
10054         return
10055         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10056         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10057         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10058                         vcpu->arch.cr4_guest_owned_bits));
10059 }
10060
10061 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10062                                        struct vmcs12 *vmcs12)
10063 {
10064         u32 idt_vectoring;
10065         unsigned int nr;
10066
10067         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10068                 nr = vcpu->arch.exception.nr;
10069                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10070
10071                 if (kvm_exception_is_soft(nr)) {
10072                         vmcs12->vm_exit_instruction_len =
10073                                 vcpu->arch.event_exit_inst_len;
10074                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10075                 } else
10076                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10077
10078                 if (vcpu->arch.exception.has_error_code) {
10079                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10080                         vmcs12->idt_vectoring_error_code =
10081                                 vcpu->arch.exception.error_code;
10082                 }
10083
10084                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10085         } else if (vcpu->arch.nmi_injected) {
10086                 vmcs12->idt_vectoring_info_field =
10087                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10088         } else if (vcpu->arch.interrupt.pending) {
10089                 nr = vcpu->arch.interrupt.nr;
10090                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10091
10092                 if (vcpu->arch.interrupt.soft) {
10093                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10094                         vmcs12->vm_entry_instruction_len =
10095                                 vcpu->arch.event_exit_inst_len;
10096                 } else
10097                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10098
10099                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10100         }
10101 }
10102
10103 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10104 {
10105         struct vcpu_vmx *vmx = to_vmx(vcpu);
10106
10107         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10108             vmx->nested.preemption_timer_expired) {
10109                 if (vmx->nested.nested_run_pending)
10110                         return -EBUSY;
10111                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10112                 return 0;
10113         }
10114
10115         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10116                 if (vmx->nested.nested_run_pending ||
10117                     vcpu->arch.interrupt.pending)
10118                         return -EBUSY;
10119                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10120                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10121                                   INTR_INFO_VALID_MASK, 0);
10122                 /*
10123                  * The NMI-triggered VM exit counts as injection:
10124                  * clear this one and block further NMIs.
10125                  */
10126                 vcpu->arch.nmi_pending = 0;
10127                 vmx_set_nmi_mask(vcpu, true);
10128                 return 0;
10129         }
10130
10131         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10132             nested_exit_on_intr(vcpu)) {
10133                 if (vmx->nested.nested_run_pending)
10134                         return -EBUSY;
10135                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10136                 return 0;
10137         }
10138
10139         return vmx_complete_nested_posted_interrupt(vcpu);
10140 }
10141
10142 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10143 {
10144         ktime_t remaining =
10145                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10146         u64 value;
10147
10148         if (ktime_to_ns(remaining) <= 0)
10149                 return 0;
10150
10151         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10152         do_div(value, 1000000);
10153         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10154 }
10155
10156 /*
10157  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10158  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10159  * and this function updates it to reflect the changes to the guest state while
10160  * L2 was running (and perhaps made some exits which were handled directly by L0
10161  * without going back to L1), and to reflect the exit reason.
10162  * Note that we do not have to copy here all VMCS fields, just those that
10163  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10164  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10165  * which already writes to vmcs12 directly.
10166  */
10167 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10168                            u32 exit_reason, u32 exit_intr_info,
10169                            unsigned long exit_qualification)
10170 {
10171         /* update guest state fields: */
10172         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10173         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10174
10175         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10176         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10177         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10178
10179         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10180         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10181         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10182         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10183         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10184         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10185         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10186         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10187         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10188         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10189         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10190         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10191         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10192         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10193         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10194         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10195         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10196         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10197         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10198         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10199         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10200         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10201         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10202         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10203         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10204         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10205         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10206         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10207         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10208         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10209         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10210         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10211         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10212         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10213         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10214         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10215
10216         vmcs12->guest_interruptibility_info =
10217                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10218         vmcs12->guest_pending_dbg_exceptions =
10219                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10220         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10221                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10222         else
10223                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10224
10225         if (nested_cpu_has_preemption_timer(vmcs12)) {
10226                 if (vmcs12->vm_exit_controls &
10227                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10228                         vmcs12->vmx_preemption_timer_value =
10229                                 vmx_get_preemption_timer_value(vcpu);
10230                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10231         }
10232
10233         /*
10234          * In some cases (usually, nested EPT), L2 is allowed to change its
10235          * own CR3 without exiting. If it has changed it, we must keep it.
10236          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10237          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10238          *
10239          * Additionally, restore L2's PDPTR to vmcs12.
10240          */
10241         if (enable_ept) {
10242                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10243                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10244                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10245                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10246                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10247         }
10248
10249         if (nested_cpu_has_vid(vmcs12))
10250                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10251
10252         vmcs12->vm_entry_controls =
10253                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10254                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10255
10256         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10257                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10258                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10259         }
10260
10261         /* TODO: These cannot have changed unless we have MSR bitmaps and
10262          * the relevant bit asks not to trap the change */
10263         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10264                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10265         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10266                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10267         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10268         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10269         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10270         if (vmx_mpx_supported())
10271                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10272         if (nested_cpu_has_xsaves(vmcs12))
10273                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10274
10275         /* update exit information fields: */
10276
10277         vmcs12->vm_exit_reason = exit_reason;
10278         vmcs12->exit_qualification = exit_qualification;
10279
10280         vmcs12->vm_exit_intr_info = exit_intr_info;
10281         if ((vmcs12->vm_exit_intr_info &
10282              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10283             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10284                 vmcs12->vm_exit_intr_error_code =
10285                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10286         vmcs12->idt_vectoring_info_field = 0;
10287         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10288         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10289
10290         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10291                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10292                  * instead of reading the real value. */
10293                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10294
10295                 /*
10296                  * Transfer the event that L0 or L1 may wanted to inject into
10297                  * L2 to IDT_VECTORING_INFO_FIELD.
10298                  */
10299                 vmcs12_save_pending_event(vcpu, vmcs12);
10300         }
10301
10302         /*
10303          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10304          * preserved above and would only end up incorrectly in L1.
10305          */
10306         vcpu->arch.nmi_injected = false;
10307         kvm_clear_exception_queue(vcpu);
10308         kvm_clear_interrupt_queue(vcpu);
10309 }
10310
10311 /*
10312  * A part of what we need to when the nested L2 guest exits and we want to
10313  * run its L1 parent, is to reset L1's guest state to the host state specified
10314  * in vmcs12.
10315  * This function is to be called not only on normal nested exit, but also on
10316  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10317  * Failures During or After Loading Guest State").
10318  * This function should be called when the active VMCS is L1's (vmcs01).
10319  */
10320 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10321                                    struct vmcs12 *vmcs12)
10322 {
10323         struct kvm_segment seg;
10324
10325         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10326                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10327         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10328                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10329         else
10330                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10331         vmx_set_efer(vcpu, vcpu->arch.efer);
10332
10333         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10334         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10335         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10336         /*
10337          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10338          * actually changed, because it depends on the current state of
10339          * fpu_active (which may have changed).
10340          * Note that vmx_set_cr0 refers to efer set above.
10341          */
10342         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10343         /*
10344          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10345          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10346          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10347          */
10348         update_exception_bitmap(vcpu);
10349         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10350         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10351
10352         /*
10353          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10354          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10355          */
10356         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10357         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10358
10359         nested_ept_uninit_mmu_context(vcpu);
10360
10361         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10362         kvm_mmu_reset_context(vcpu);
10363
10364         if (!enable_ept)
10365                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10366
10367         if (enable_vpid) {
10368                 /*
10369                  * Trivially support vpid by letting L2s share their parent
10370                  * L1's vpid. TODO: move to a more elaborate solution, giving
10371                  * each L2 its own vpid and exposing the vpid feature to L1.
10372                  */
10373                 vmx_flush_tlb(vcpu);
10374         }
10375
10376
10377         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10378         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10379         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10380         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10381         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10382
10383         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10384         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10385                 vmcs_write64(GUEST_BNDCFGS, 0);
10386
10387         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10388                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10389                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10390         }
10391         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10392                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10393                         vmcs12->host_ia32_perf_global_ctrl);
10394
10395         /* Set L1 segment info according to Intel SDM
10396             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10397         seg = (struct kvm_segment) {
10398                 .base = 0,
10399                 .limit = 0xFFFFFFFF,
10400                 .selector = vmcs12->host_cs_selector,
10401                 .type = 11,
10402                 .present = 1,
10403                 .s = 1,
10404                 .g = 1
10405         };
10406         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10407                 seg.l = 1;
10408         else
10409                 seg.db = 1;
10410         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10411         seg = (struct kvm_segment) {
10412                 .base = 0,
10413                 .limit = 0xFFFFFFFF,
10414                 .type = 3,
10415                 .present = 1,
10416                 .s = 1,
10417                 .db = 1,
10418                 .g = 1
10419         };
10420         seg.selector = vmcs12->host_ds_selector;
10421         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10422         seg.selector = vmcs12->host_es_selector;
10423         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10424         seg.selector = vmcs12->host_ss_selector;
10425         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10426         seg.selector = vmcs12->host_fs_selector;
10427         seg.base = vmcs12->host_fs_base;
10428         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10429         seg.selector = vmcs12->host_gs_selector;
10430         seg.base = vmcs12->host_gs_base;
10431         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10432         seg = (struct kvm_segment) {
10433                 .base = vmcs12->host_tr_base,
10434                 .limit = 0x67,
10435                 .selector = vmcs12->host_tr_selector,
10436                 .type = 11,
10437                 .present = 1
10438         };
10439         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10440
10441         kvm_set_dr(vcpu, 7, 0x400);
10442         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10443
10444         if (cpu_has_vmx_msr_bitmap())
10445                 vmx_set_msr_bitmap(vcpu);
10446
10447         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10448                                 vmcs12->vm_exit_msr_load_count))
10449                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10450 }
10451
10452 /*
10453  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10454  * and modify vmcs12 to make it see what it would expect to see there if
10455  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10456  */
10457 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10458                               u32 exit_intr_info,
10459                               unsigned long exit_qualification)
10460 {
10461         struct vcpu_vmx *vmx = to_vmx(vcpu);
10462         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10463
10464         /* trying to cancel vmlaunch/vmresume is a bug */
10465         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10466
10467         leave_guest_mode(vcpu);
10468         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10469                        exit_qualification);
10470
10471         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10472                                  vmcs12->vm_exit_msr_store_count))
10473                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10474
10475         vmx_load_vmcs01(vcpu);
10476
10477         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10478             && nested_exit_intr_ack_set(vcpu)) {
10479                 int irq = kvm_cpu_get_interrupt(vcpu);
10480                 WARN_ON(irq < 0);
10481                 vmcs12->vm_exit_intr_info = irq |
10482                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10483         }
10484
10485         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10486                                        vmcs12->exit_qualification,
10487                                        vmcs12->idt_vectoring_info_field,
10488                                        vmcs12->vm_exit_intr_info,
10489                                        vmcs12->vm_exit_intr_error_code,
10490                                        KVM_ISA_VMX);
10491
10492         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10493         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10494         vmx_segment_cache_clear(vmx);
10495
10496         /* if no vmcs02 cache requested, remove the one we used */
10497         if (VMCS02_POOL_SIZE == 0)
10498                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10499
10500         load_vmcs12_host_state(vcpu, vmcs12);
10501
10502         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10503         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10504
10505         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10506         vmx->host_rsp = 0;
10507
10508         /* Unpin physical memory we referred to in vmcs02 */
10509         if (vmx->nested.apic_access_page) {
10510                 nested_release_page(vmx->nested.apic_access_page);
10511                 vmx->nested.apic_access_page = NULL;
10512         }
10513         if (vmx->nested.virtual_apic_page) {
10514                 nested_release_page(vmx->nested.virtual_apic_page);
10515                 vmx->nested.virtual_apic_page = NULL;
10516         }
10517         if (vmx->nested.pi_desc_page) {
10518                 kunmap(vmx->nested.pi_desc_page);
10519                 nested_release_page(vmx->nested.pi_desc_page);
10520                 vmx->nested.pi_desc_page = NULL;
10521                 vmx->nested.pi_desc = NULL;
10522         }
10523
10524         /*
10525          * We are now running in L2, mmu_notifier will force to reload the
10526          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10527          */
10528         kvm_vcpu_reload_apic_access_page(vcpu);
10529
10530         /*
10531          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10532          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10533          * success or failure flag accordingly.
10534          */
10535         if (unlikely(vmx->fail)) {
10536                 vmx->fail = 0;
10537                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10538         } else
10539                 nested_vmx_succeed(vcpu);
10540         if (enable_shadow_vmcs)
10541                 vmx->nested.sync_shadow_vmcs = true;
10542
10543         /* in case we halted in L2 */
10544         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10545 }
10546
10547 /*
10548  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10549  */
10550 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10551 {
10552         if (is_guest_mode(vcpu))
10553                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10554         free_nested(to_vmx(vcpu));
10555 }
10556
10557 /*
10558  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10559  * 23.7 "VM-entry failures during or after loading guest state" (this also
10560  * lists the acceptable exit-reason and exit-qualification parameters).
10561  * It should only be called before L2 actually succeeded to run, and when
10562  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10563  */
10564 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10565                         struct vmcs12 *vmcs12,
10566                         u32 reason, unsigned long qualification)
10567 {
10568         load_vmcs12_host_state(vcpu, vmcs12);
10569         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10570         vmcs12->exit_qualification = qualification;
10571         nested_vmx_succeed(vcpu);
10572         if (enable_shadow_vmcs)
10573                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10574 }
10575
10576 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10577                                struct x86_instruction_info *info,
10578                                enum x86_intercept_stage stage)
10579 {
10580         return X86EMUL_CONTINUE;
10581 }
10582
10583 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10584 {
10585         if (ple_gap)
10586                 shrink_ple_window(vcpu);
10587 }
10588
10589 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10590                                      struct kvm_memory_slot *slot)
10591 {
10592         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10593         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10594 }
10595
10596 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10597                                        struct kvm_memory_slot *slot)
10598 {
10599         kvm_mmu_slot_set_dirty(kvm, slot);
10600 }
10601
10602 static void vmx_flush_log_dirty(struct kvm *kvm)
10603 {
10604         kvm_flush_pml_buffers(kvm);
10605 }
10606
10607 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10608                                            struct kvm_memory_slot *memslot,
10609                                            gfn_t offset, unsigned long mask)
10610 {
10611         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10612 }
10613
10614 /*
10615  * This routine does the following things for vCPU which is going
10616  * to be blocked if VT-d PI is enabled.
10617  * - Store the vCPU to the wakeup list, so when interrupts happen
10618  *   we can find the right vCPU to wake up.
10619  * - Change the Posted-interrupt descriptor as below:
10620  *      'NDST' <-- vcpu->pre_pcpu
10621  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10622  * - If 'ON' is set during this process, which means at least one
10623  *   interrupt is posted for this vCPU, we cannot block it, in
10624  *   this case, return 1, otherwise, return 0.
10625  *
10626  */
10627 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10628 {
10629         unsigned long flags;
10630         unsigned int dest;
10631         struct pi_desc old, new;
10632         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10633
10634         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10635                 !irq_remapping_cap(IRQ_POSTING_CAP))
10636                 return 0;
10637
10638         vcpu->pre_pcpu = vcpu->cpu;
10639         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10640                           vcpu->pre_pcpu), flags);
10641         list_add_tail(&vcpu->blocked_vcpu_list,
10642                       &per_cpu(blocked_vcpu_on_cpu,
10643                       vcpu->pre_pcpu));
10644         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10645                                vcpu->pre_pcpu), flags);
10646
10647         do {
10648                 old.control = new.control = pi_desc->control;
10649
10650                 /*
10651                  * We should not block the vCPU if
10652                  * an interrupt is posted for it.
10653                  */
10654                 if (pi_test_on(pi_desc) == 1) {
10655                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10656                                           vcpu->pre_pcpu), flags);
10657                         list_del(&vcpu->blocked_vcpu_list);
10658                         spin_unlock_irqrestore(
10659                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10660                                         vcpu->pre_pcpu), flags);
10661                         vcpu->pre_pcpu = -1;
10662
10663                         return 1;
10664                 }
10665
10666                 WARN((pi_desc->sn == 1),
10667                      "Warning: SN field of posted-interrupts "
10668                      "is set before blocking\n");
10669
10670                 /*
10671                  * Since vCPU can be preempted during this process,
10672                  * vcpu->cpu could be different with pre_pcpu, we
10673                  * need to set pre_pcpu as the destination of wakeup
10674                  * notification event, then we can find the right vCPU
10675                  * to wakeup in wakeup handler if interrupts happen
10676                  * when the vCPU is in blocked state.
10677                  */
10678                 dest = cpu_physical_id(vcpu->pre_pcpu);
10679
10680                 if (x2apic_enabled())
10681                         new.ndst = dest;
10682                 else
10683                         new.ndst = (dest << 8) & 0xFF00;
10684
10685                 /* set 'NV' to 'wakeup vector' */
10686                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10687         } while (cmpxchg(&pi_desc->control, old.control,
10688                         new.control) != old.control);
10689
10690         return 0;
10691 }
10692
10693 static void vmx_post_block(struct kvm_vcpu *vcpu)
10694 {
10695         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10696         struct pi_desc old, new;
10697         unsigned int dest;
10698         unsigned long flags;
10699
10700         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10701                 !irq_remapping_cap(IRQ_POSTING_CAP))
10702                 return;
10703
10704         do {
10705                 old.control = new.control = pi_desc->control;
10706
10707                 dest = cpu_physical_id(vcpu->cpu);
10708
10709                 if (x2apic_enabled())
10710                         new.ndst = dest;
10711                 else
10712                         new.ndst = (dest << 8) & 0xFF00;
10713
10714                 /* Allow posting non-urgent interrupts */
10715                 new.sn = 0;
10716
10717                 /* set 'NV' to 'notification vector' */
10718                 new.nv = POSTED_INTR_VECTOR;
10719         } while (cmpxchg(&pi_desc->control, old.control,
10720                         new.control) != old.control);
10721
10722         if(vcpu->pre_pcpu != -1) {
10723                 spin_lock_irqsave(
10724                         &per_cpu(blocked_vcpu_on_cpu_lock,
10725                         vcpu->pre_pcpu), flags);
10726                 list_del(&vcpu->blocked_vcpu_list);
10727                 spin_unlock_irqrestore(
10728                         &per_cpu(blocked_vcpu_on_cpu_lock,
10729                         vcpu->pre_pcpu), flags);
10730                 vcpu->pre_pcpu = -1;
10731         }
10732 }
10733
10734 /*
10735  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10736  *
10737  * @kvm: kvm
10738  * @host_irq: host irq of the interrupt
10739  * @guest_irq: gsi of the interrupt
10740  * @set: set or unset PI
10741  * returns 0 on success, < 0 on failure
10742  */
10743 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10744                               uint32_t guest_irq, bool set)
10745 {
10746         struct kvm_kernel_irq_routing_entry *e;
10747         struct kvm_irq_routing_table *irq_rt;
10748         struct kvm_lapic_irq irq;
10749         struct kvm_vcpu *vcpu;
10750         struct vcpu_data vcpu_info;
10751         int idx, ret = -EINVAL;
10752
10753         if (!kvm_arch_has_assigned_device(kvm) ||
10754                 !irq_remapping_cap(IRQ_POSTING_CAP))
10755                 return 0;
10756
10757         idx = srcu_read_lock(&kvm->irq_srcu);
10758         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10759         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10760
10761         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10762                 if (e->type != KVM_IRQ_ROUTING_MSI)
10763                         continue;
10764                 /*
10765                  * VT-d PI cannot support posting multicast/broadcast
10766                  * interrupts to a vCPU, we still use interrupt remapping
10767                  * for these kind of interrupts.
10768                  *
10769                  * For lowest-priority interrupts, we only support
10770                  * those with single CPU as the destination, e.g. user
10771                  * configures the interrupts via /proc/irq or uses
10772                  * irqbalance to make the interrupts single-CPU.
10773                  *
10774                  * We will support full lowest-priority interrupt later.
10775                  */
10776
10777                 kvm_set_msi_irq(e, &irq);
10778                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10779                         continue;
10780
10781                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10782                 vcpu_info.vector = irq.vector;
10783
10784                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10785                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10786
10787                 if (set)
10788                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10789                 else {
10790                         /* suppress notification event before unposting */
10791                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10792                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10793                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10794                 }
10795
10796                 if (ret < 0) {
10797                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10798                                         __func__);
10799                         goto out;
10800                 }
10801         }
10802
10803         ret = 0;
10804 out:
10805         srcu_read_unlock(&kvm->irq_srcu, idx);
10806         return ret;
10807 }
10808
10809 static struct kvm_x86_ops vmx_x86_ops = {
10810         .cpu_has_kvm_support = cpu_has_kvm_support,
10811         .disabled_by_bios = vmx_disabled_by_bios,
10812         .hardware_setup = hardware_setup,
10813         .hardware_unsetup = hardware_unsetup,
10814         .check_processor_compatibility = vmx_check_processor_compat,
10815         .hardware_enable = hardware_enable,
10816         .hardware_disable = hardware_disable,
10817         .cpu_has_accelerated_tpr = report_flexpriority,
10818         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10819
10820         .vcpu_create = vmx_create_vcpu,
10821         .vcpu_free = vmx_free_vcpu,
10822         .vcpu_reset = vmx_vcpu_reset,
10823
10824         .prepare_guest_switch = vmx_save_host_state,
10825         .vcpu_load = vmx_vcpu_load,
10826         .vcpu_put = vmx_vcpu_put,
10827
10828         .update_bp_intercept = update_exception_bitmap,
10829         .get_msr = vmx_get_msr,
10830         .set_msr = vmx_set_msr,
10831         .get_segment_base = vmx_get_segment_base,
10832         .get_segment = vmx_get_segment,
10833         .set_segment = vmx_set_segment,
10834         .get_cpl = vmx_get_cpl,
10835         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10836         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10837         .decache_cr3 = vmx_decache_cr3,
10838         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10839         .set_cr0 = vmx_set_cr0,
10840         .set_cr3 = vmx_set_cr3,
10841         .set_cr4 = vmx_set_cr4,
10842         .set_efer = vmx_set_efer,
10843         .get_idt = vmx_get_idt,
10844         .set_idt = vmx_set_idt,
10845         .get_gdt = vmx_get_gdt,
10846         .set_gdt = vmx_set_gdt,
10847         .get_dr6 = vmx_get_dr6,
10848         .set_dr6 = vmx_set_dr6,
10849         .set_dr7 = vmx_set_dr7,
10850         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10851         .cache_reg = vmx_cache_reg,
10852         .get_rflags = vmx_get_rflags,
10853         .set_rflags = vmx_set_rflags,
10854         .fpu_activate = vmx_fpu_activate,
10855         .fpu_deactivate = vmx_fpu_deactivate,
10856
10857         .tlb_flush = vmx_flush_tlb,
10858
10859         .run = vmx_vcpu_run,
10860         .handle_exit = vmx_handle_exit,
10861         .skip_emulated_instruction = skip_emulated_instruction,
10862         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10863         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10864         .patch_hypercall = vmx_patch_hypercall,
10865         .set_irq = vmx_inject_irq,
10866         .set_nmi = vmx_inject_nmi,
10867         .queue_exception = vmx_queue_exception,
10868         .cancel_injection = vmx_cancel_injection,
10869         .interrupt_allowed = vmx_interrupt_allowed,
10870         .nmi_allowed = vmx_nmi_allowed,
10871         .get_nmi_mask = vmx_get_nmi_mask,
10872         .set_nmi_mask = vmx_set_nmi_mask,
10873         .enable_nmi_window = enable_nmi_window,
10874         .enable_irq_window = enable_irq_window,
10875         .update_cr8_intercept = update_cr8_intercept,
10876         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10877         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10878         .get_enable_apicv = vmx_get_enable_apicv,
10879         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10880         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10881         .hwapic_irr_update = vmx_hwapic_irr_update,
10882         .hwapic_isr_update = vmx_hwapic_isr_update,
10883         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10884         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10885
10886         .set_tss_addr = vmx_set_tss_addr,
10887         .get_tdp_level = get_ept_level,
10888         .get_mt_mask = vmx_get_mt_mask,
10889
10890         .get_exit_info = vmx_get_exit_info,
10891
10892         .get_lpage_level = vmx_get_lpage_level,
10893
10894         .cpuid_update = vmx_cpuid_update,
10895
10896         .rdtscp_supported = vmx_rdtscp_supported,
10897         .invpcid_supported = vmx_invpcid_supported,
10898
10899         .set_supported_cpuid = vmx_set_supported_cpuid,
10900
10901         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10902
10903         .read_tsc_offset = vmx_read_tsc_offset,
10904         .write_tsc_offset = vmx_write_tsc_offset,
10905         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10906         .read_l1_tsc = vmx_read_l1_tsc,
10907
10908         .set_tdp_cr3 = vmx_set_cr3,
10909
10910         .check_intercept = vmx_check_intercept,
10911         .handle_external_intr = vmx_handle_external_intr,
10912         .mpx_supported = vmx_mpx_supported,
10913         .xsaves_supported = vmx_xsaves_supported,
10914
10915         .check_nested_events = vmx_check_nested_events,
10916
10917         .sched_in = vmx_sched_in,
10918
10919         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10920         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10921         .flush_log_dirty = vmx_flush_log_dirty,
10922         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10923
10924         .pre_block = vmx_pre_block,
10925         .post_block = vmx_post_block,
10926
10927         .pmu_ops = &intel_pmu_ops,
10928
10929         .update_pi_irte = vmx_update_pi_irte,
10930 };
10931
10932 static int __init vmx_init(void)
10933 {
10934         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10935                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10936         if (r)
10937                 return r;
10938
10939 #ifdef CONFIG_KEXEC_CORE
10940         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10941                            crash_vmclear_local_loaded_vmcss);
10942 #endif
10943
10944         return 0;
10945 }
10946
10947 static void __exit vmx_exit(void)
10948 {
10949 #ifdef CONFIG_KEXEC_CORE
10950         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10951         synchronize_rcu();
10952 #endif
10953
10954         kvm_exit();
10955 }
10956
10957 module_init(vmx_init)
10958 module_exit(vmx_exit)