1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/export.h>
37 #include <linux/moduleparam.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <linux/kvm_irqfd.h>
53 #include <linux/irqbypass.h>
54 #include <linux/sched/stat.h>
55 #include <linux/sched/isolation.h>
56 #include <linux/mem_encrypt.h>
58 #include <trace/events/kvm.h>
60 #include <asm/debugreg.h>
64 #include <linux/kernel_stat.h>
65 #include <asm/fpu/internal.h> /* Ugh! */
66 #include <asm/pvclock.h>
67 #include <asm/div64.h>
68 #include <asm/irq_remapping.h>
69 #include <asm/mshyperv.h>
70 #include <asm/hypervisor.h>
71 #include <asm/intel_pt.h>
72 #include <asm/emulate_prefix.h>
73 #include <clocksource/hyperv_timer.h>
75 #define CREATE_TRACE_POINTS
78 #define MAX_IO_MSRS 256
79 #define KVM_MAX_MCE_BANKS 32
80 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
81 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
83 #define emul_to_vcpu(ctxt) \
84 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
87 * - enable syscall per default because its emulated by KVM
88 * - enable LME and LMA per default on 64 bit KVM
92 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
94 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
97 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
99 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
100 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
103 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
106 static void process_nmi(struct kvm_vcpu *vcpu);
107 static void enter_smm(struct kvm_vcpu *vcpu);
108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
109 static void store_regs(struct kvm_vcpu *vcpu);
110 static int sync_regs(struct kvm_vcpu *vcpu);
112 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
113 EXPORT_SYMBOL_GPL(kvm_x86_ops);
115 static bool __read_mostly ignore_msrs = 0;
116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
118 static bool __read_mostly report_ignored_msrs = true;
119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
121 unsigned int min_timer_period_us = 200;
122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
124 static bool __read_mostly kvmclock_periodic_sync = true;
125 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
127 bool __read_mostly kvm_has_tsc_control;
128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
129 u32 __read_mostly kvm_max_guest_tsc_khz;
130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
131 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
133 u64 __read_mostly kvm_max_tsc_scaling_ratio;
134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
135 u64 __read_mostly kvm_default_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
139 static u32 __read_mostly tsc_tolerance_ppm = 250;
140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
143 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
144 * adaptive tuning starting from default advancment of 1000ns. '0' disables
145 * advancement entirely. Any other value is used as-is and disables adaptive
146 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
148 static int __read_mostly lapic_timer_advance_ns = -1;
149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
151 static bool __read_mostly vector_hashing = true;
152 module_param(vector_hashing, bool, S_IRUGO);
154 bool __read_mostly enable_vmware_backdoor = false;
155 module_param(enable_vmware_backdoor, bool, S_IRUGO);
156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
158 static bool __read_mostly force_emulation_prefix = false;
159 module_param(force_emulation_prefix, bool, S_IRUGO);
161 int __read_mostly pi_inject_timer = -1;
162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
164 #define KVM_NR_SHARED_MSRS 16
166 struct kvm_shared_msrs_global {
168 u32 msrs[KVM_NR_SHARED_MSRS];
171 struct kvm_shared_msrs {
172 struct user_return_notifier urn;
174 struct kvm_shared_msr_values {
177 } values[KVM_NR_SHARED_MSRS];
180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
181 static struct kvm_shared_msrs __percpu *shared_msrs;
183 static u64 __read_mostly host_xss;
185 struct kvm_stats_debugfs_item debugfs_entries[] = {
186 { "pf_fixed", VCPU_STAT(pf_fixed) },
187 { "pf_guest", VCPU_STAT(pf_guest) },
188 { "tlb_flush", VCPU_STAT(tlb_flush) },
189 { "invlpg", VCPU_STAT(invlpg) },
190 { "exits", VCPU_STAT(exits) },
191 { "io_exits", VCPU_STAT(io_exits) },
192 { "mmio_exits", VCPU_STAT(mmio_exits) },
193 { "signal_exits", VCPU_STAT(signal_exits) },
194 { "irq_window", VCPU_STAT(irq_window_exits) },
195 { "nmi_window", VCPU_STAT(nmi_window_exits) },
196 { "halt_exits", VCPU_STAT(halt_exits) },
197 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
198 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
199 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
200 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
201 { "hypercalls", VCPU_STAT(hypercalls) },
202 { "request_irq", VCPU_STAT(request_irq_exits) },
203 { "irq_exits", VCPU_STAT(irq_exits) },
204 { "host_state_reload", VCPU_STAT(host_state_reload) },
205 { "fpu_reload", VCPU_STAT(fpu_reload) },
206 { "insn_emulation", VCPU_STAT(insn_emulation) },
207 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
208 { "irq_injections", VCPU_STAT(irq_injections) },
209 { "nmi_injections", VCPU_STAT(nmi_injections) },
210 { "req_event", VCPU_STAT(req_event) },
211 { "l1d_flush", VCPU_STAT(l1d_flush) },
212 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
213 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
214 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
215 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
216 { "mmu_flooded", VM_STAT(mmu_flooded) },
217 { "mmu_recycled", VM_STAT(mmu_recycled) },
218 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
219 { "mmu_unsync", VM_STAT(mmu_unsync) },
220 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
221 { "largepages", VM_STAT(lpages, .mode = 0444) },
222 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
223 { "max_mmu_page_hash_collisions",
224 VM_STAT(max_mmu_page_hash_collisions) },
228 u64 __read_mostly host_xcr0;
230 struct kmem_cache *x86_fpu_cache;
231 EXPORT_SYMBOL_GPL(x86_fpu_cache);
233 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
235 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
238 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
239 vcpu->arch.apf.gfns[i] = ~0;
242 static void kvm_on_user_return(struct user_return_notifier *urn)
245 struct kvm_shared_msrs *locals
246 = container_of(urn, struct kvm_shared_msrs, urn);
247 struct kvm_shared_msr_values *values;
251 * Disabling irqs at this point since the following code could be
252 * interrupted and executed through kvm_arch_hardware_disable()
254 local_irq_save(flags);
255 if (locals->registered) {
256 locals->registered = false;
257 user_return_notifier_unregister(urn);
259 local_irq_restore(flags);
260 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
261 values = &locals->values[slot];
262 if (values->host != values->curr) {
263 wrmsrl(shared_msrs_global.msrs[slot], values->host);
264 values->curr = values->host;
269 void kvm_define_shared_msr(unsigned slot, u32 msr)
271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
272 shared_msrs_global.msrs[slot] = msr;
273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
276 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
278 static void kvm_shared_msr_cpu_online(void)
280 unsigned int cpu = smp_processor_id();
281 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
285 for (i = 0; i < shared_msrs_global.nr; ++i) {
286 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
287 smsr->values[i].host = value;
288 smsr->values[i].curr = value;
292 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
298 value = (value & mask) | (smsr->values[slot].host & ~mask);
299 if (value == smsr->values[slot].curr)
301 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
305 smsr->values[slot].curr = value;
306 if (!smsr->registered) {
307 smsr->urn.on_user_return = kvm_on_user_return;
308 user_return_notifier_register(&smsr->urn);
309 smsr->registered = true;
313 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
315 static void drop_user_return_notifiers(void)
317 unsigned int cpu = smp_processor_id();
318 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
320 if (smsr->registered)
321 kvm_on_user_return(&smsr->urn);
324 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
326 return vcpu->arch.apic_base;
328 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
330 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
332 return kvm_apic_mode(kvm_get_apic_base(vcpu));
334 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
336 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
338 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
339 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
340 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
341 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
343 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
345 if (!msr_info->host_initiated) {
346 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
348 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 kvm_lapic_set_base(vcpu, msr_info->data);
355 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
357 asmlinkage __visible void kvm_spurious_fault(void)
359 /* Fault while not rebooting. We want the trace. */
360 BUG_ON(!kvm_rebooting);
362 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
364 #define EXCPT_BENIGN 0
365 #define EXCPT_CONTRIBUTORY 1
368 static int exception_class(int vector)
378 return EXCPT_CONTRIBUTORY;
385 #define EXCPT_FAULT 0
387 #define EXCPT_ABORT 2
388 #define EXCPT_INTERRUPT 3
390 static int exception_type(int vector)
394 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
395 return EXCPT_INTERRUPT;
399 /* #DB is trap, as instruction watchpoints are handled elsewhere */
400 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
403 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
406 /* Reserved exceptions will result in fault */
410 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
412 unsigned nr = vcpu->arch.exception.nr;
413 bool has_payload = vcpu->arch.exception.has_payload;
414 unsigned long payload = vcpu->arch.exception.payload;
422 * "Certain debug exceptions may clear bit 0-3. The
423 * remaining contents of the DR6 register are never
424 * cleared by the processor".
426 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
428 * DR6.RTM is set by all #DB exceptions that don't clear it.
430 vcpu->arch.dr6 |= DR6_RTM;
431 vcpu->arch.dr6 |= payload;
433 * Bit 16 should be set in the payload whenever the #DB
434 * exception should clear DR6.RTM. This makes the payload
435 * compatible with the pending debug exceptions under VMX.
436 * Though not currently documented in the SDM, this also
437 * makes the payload compatible with the exit qualification
438 * for #DB exceptions under VMX.
440 vcpu->arch.dr6 ^= payload & DR6_RTM;
443 * The #DB payload is defined as compatible with the 'pending
444 * debug exceptions' field under VMX, not DR6. While bit 12 is
445 * defined in the 'pending debug exceptions' field (enabled
446 * breakpoint), it is reserved and must be zero in DR6.
448 vcpu->arch.dr6 &= ~BIT(12);
451 vcpu->arch.cr2 = payload;
455 vcpu->arch.exception.has_payload = false;
456 vcpu->arch.exception.payload = 0;
458 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
460 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
461 unsigned nr, bool has_error, u32 error_code,
462 bool has_payload, unsigned long payload, bool reinject)
467 kvm_make_request(KVM_REQ_EVENT, vcpu);
469 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
471 if (has_error && !is_protmode(vcpu))
475 * On vmentry, vcpu->arch.exception.pending is only
476 * true if an event injection was blocked by
477 * nested_run_pending. In that case, however,
478 * vcpu_enter_guest requests an immediate exit,
479 * and the guest shouldn't proceed far enough to
482 WARN_ON_ONCE(vcpu->arch.exception.pending);
483 vcpu->arch.exception.injected = true;
484 if (WARN_ON_ONCE(has_payload)) {
486 * A reinjected event has already
487 * delivered its payload.
493 vcpu->arch.exception.pending = true;
494 vcpu->arch.exception.injected = false;
496 vcpu->arch.exception.has_error_code = has_error;
497 vcpu->arch.exception.nr = nr;
498 vcpu->arch.exception.error_code = error_code;
499 vcpu->arch.exception.has_payload = has_payload;
500 vcpu->arch.exception.payload = payload;
501 if (!is_guest_mode(vcpu))
502 kvm_deliver_exception_payload(vcpu);
506 /* to check exception */
507 prev_nr = vcpu->arch.exception.nr;
508 if (prev_nr == DF_VECTOR) {
509 /* triple fault -> shutdown */
510 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
513 class1 = exception_class(prev_nr);
514 class2 = exception_class(nr);
515 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
516 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
518 * Generate double fault per SDM Table 5-5. Set
519 * exception.pending = true so that the double fault
520 * can trigger a nested vmexit.
522 vcpu->arch.exception.pending = true;
523 vcpu->arch.exception.injected = false;
524 vcpu->arch.exception.has_error_code = true;
525 vcpu->arch.exception.nr = DF_VECTOR;
526 vcpu->arch.exception.error_code = 0;
527 vcpu->arch.exception.has_payload = false;
528 vcpu->arch.exception.payload = 0;
530 /* replace previous exception with a new one in a hope
531 that instruction re-execution will regenerate lost
536 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
538 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
540 EXPORT_SYMBOL_GPL(kvm_queue_exception);
542 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
546 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
548 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
549 unsigned long payload)
551 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
554 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
555 u32 error_code, unsigned long payload)
557 kvm_multiple_exception(vcpu, nr, true, error_code,
558 true, payload, false);
561 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
564 kvm_inject_gp(vcpu, 0);
566 return kvm_skip_emulated_instruction(vcpu);
570 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
572 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
574 ++vcpu->stat.pf_guest;
575 vcpu->arch.exception.nested_apf =
576 is_guest_mode(vcpu) && fault->async_page_fault;
577 if (vcpu->arch.exception.nested_apf) {
578 vcpu->arch.apf.nested_apf_token = fault->address;
579 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
581 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
585 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
587 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
589 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
590 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
592 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
594 return fault->nested_page_fault;
597 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
599 atomic_inc(&vcpu->arch.nmi_queued);
600 kvm_make_request(KVM_REQ_NMI, vcpu);
602 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
604 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
606 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
608 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
610 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
614 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
617 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
618 * a #GP and return false.
620 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
622 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
624 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
627 EXPORT_SYMBOL_GPL(kvm_require_cpl);
629 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
631 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
634 kvm_queue_exception(vcpu, UD_VECTOR);
637 EXPORT_SYMBOL_GPL(kvm_require_dr);
640 * This function will be used to read from the physical memory of the currently
641 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
642 * can read from guest physical or from the guest's guest physical memory.
644 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
645 gfn_t ngfn, void *data, int offset, int len,
648 struct x86_exception exception;
652 ngpa = gfn_to_gpa(ngfn);
653 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
654 if (real_gfn == UNMAPPED_GVA)
657 real_gfn = gpa_to_gfn(real_gfn);
659 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
661 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
663 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
664 void *data, int offset, int len, u32 access)
666 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
667 data, offset, len, access);
670 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
672 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
677 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
679 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
681 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
682 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
685 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
687 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
688 offset * sizeof(u64), sizeof(pdpte),
689 PFERR_USER_MASK|PFERR_WRITE_MASK);
694 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
695 if ((pdpte[i] & PT_PRESENT_MASK) &&
696 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
704 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
710 EXPORT_SYMBOL_GPL(load_pdptrs);
712 bool pdptrs_changed(struct kvm_vcpu *vcpu)
714 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
719 if (!is_pae_paging(vcpu))
722 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
732 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
734 EXPORT_SYMBOL_GPL(pdptrs_changed);
736 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
738 unsigned long old_cr0 = kvm_read_cr0(vcpu);
739 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
744 if (cr0 & 0xffffffff00000000UL)
748 cr0 &= ~CR0_RESERVED_BITS;
750 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
753 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
756 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
758 if ((vcpu->arch.efer & EFER_LME)) {
763 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
768 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
773 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
776 kvm_x86_ops->set_cr0(vcpu, cr0);
778 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
779 kvm_clear_async_pf_completion_queue(vcpu);
780 kvm_async_pf_hash_reset(vcpu);
783 if ((cr0 ^ old_cr0) & update_bits)
784 kvm_mmu_reset_context(vcpu);
786 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
787 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
788 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
789 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
793 EXPORT_SYMBOL_GPL(kvm_set_cr0);
795 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
797 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
799 EXPORT_SYMBOL_GPL(kvm_lmsw);
801 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
803 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
805 if (vcpu->arch.xcr0 != host_xcr0)
806 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
808 if (vcpu->arch.xsaves_enabled &&
809 vcpu->arch.ia32_xss != host_xss)
810 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
813 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
815 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
817 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
822 if (vcpu->arch.xsaves_enabled &&
823 vcpu->arch.ia32_xss != host_xss)
824 wrmsrl(MSR_IA32_XSS, host_xss);
828 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
830 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
833 u64 old_xcr0 = vcpu->arch.xcr0;
836 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
837 if (index != XCR_XFEATURE_ENABLED_MASK)
839 if (!(xcr0 & XFEATURE_MASK_FP))
841 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
845 * Do not allow the guest to set bits that we do not support
846 * saving. However, xcr0 bit 0 is always set, even if the
847 * emulated CPU does not support XSAVE (see fx_init).
849 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
850 if (xcr0 & ~valid_bits)
853 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
854 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
857 if (xcr0 & XFEATURE_MASK_AVX512) {
858 if (!(xcr0 & XFEATURE_MASK_YMM))
860 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
863 vcpu->arch.xcr0 = xcr0;
865 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
866 kvm_update_cpuid(vcpu);
870 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
872 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
873 __kvm_set_xcr(vcpu, index, xcr)) {
874 kvm_inject_gp(vcpu, 0);
879 EXPORT_SYMBOL_GPL(kvm_set_xcr);
881 #define __cr4_reserved_bits(__cpu_has, __c) \
883 u64 __reserved_bits = CR4_RESERVED_BITS; \
885 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
886 __reserved_bits |= X86_CR4_OSXSAVE; \
887 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
888 __reserved_bits |= X86_CR4_SMEP; \
889 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
890 __reserved_bits |= X86_CR4_SMAP; \
891 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
892 __reserved_bits |= X86_CR4_FSGSBASE; \
893 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
894 __reserved_bits |= X86_CR4_PKE; \
895 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
896 __reserved_bits |= X86_CR4_LA57; \
897 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
898 __reserved_bits |= X86_CR4_UMIP; \
902 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
904 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
906 if (cpuid_ecx(0x7) & feature_bit(LA57))
907 reserved_bits &= ~X86_CR4_LA57;
909 if (kvm_x86_ops->umip_emulated())
910 reserved_bits &= ~X86_CR4_UMIP;
912 return reserved_bits;
915 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
917 if (cr4 & cr4_reserved_bits)
920 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
926 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
928 unsigned long old_cr4 = kvm_read_cr4(vcpu);
929 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
930 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
932 if (kvm_valid_cr4(vcpu, cr4))
935 if (is_long_mode(vcpu)) {
936 if (!(cr4 & X86_CR4_PAE))
938 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
939 && ((cr4 ^ old_cr4) & pdptr_bits)
940 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
944 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
945 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
948 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
949 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
953 if (kvm_x86_ops->set_cr4(vcpu, cr4))
956 if (((cr4 ^ old_cr4) & pdptr_bits) ||
957 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
958 kvm_mmu_reset_context(vcpu);
960 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
961 kvm_update_cpuid(vcpu);
965 EXPORT_SYMBOL_GPL(kvm_set_cr4);
967 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
969 bool skip_tlb_flush = false;
971 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
974 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
975 cr3 &= ~X86_CR3_PCID_NOFLUSH;
979 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
980 if (!skip_tlb_flush) {
981 kvm_mmu_sync_roots(vcpu);
982 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
987 if (is_long_mode(vcpu) &&
988 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
990 else if (is_pae_paging(vcpu) &&
991 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
994 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
995 vcpu->arch.cr3 = cr3;
996 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1000 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1002 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1004 if (cr8 & CR8_RESERVED_BITS)
1006 if (lapic_in_kernel(vcpu))
1007 kvm_lapic_set_tpr(vcpu, cr8);
1009 vcpu->arch.cr8 = cr8;
1012 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1014 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1016 if (lapic_in_kernel(vcpu))
1017 return kvm_lapic_get_cr8(vcpu);
1019 return vcpu->arch.cr8;
1021 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1023 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1027 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1028 for (i = 0; i < KVM_NR_DB_REGS; i++)
1029 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1030 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1034 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1036 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1037 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1040 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1044 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1045 dr7 = vcpu->arch.guest_debug_dr7;
1047 dr7 = vcpu->arch.dr7;
1048 kvm_x86_ops->set_dr7(vcpu, dr7);
1049 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1050 if (dr7 & DR7_BP_EN_MASK)
1051 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1054 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1056 u64 fixed = DR6_FIXED_1;
1058 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1063 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1065 size_t size = ARRAY_SIZE(vcpu->arch.db);
1069 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1070 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1071 vcpu->arch.eff_db[dr] = val;
1076 if (val & 0xffffffff00000000ULL)
1077 return -1; /* #GP */
1078 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1079 kvm_update_dr6(vcpu);
1084 if (!kvm_dr7_valid(val))
1085 return -1; /* #GP */
1086 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1087 kvm_update_dr7(vcpu);
1094 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1096 if (__kvm_set_dr(vcpu, dr, val)) {
1097 kvm_inject_gp(vcpu, 0);
1102 EXPORT_SYMBOL_GPL(kvm_set_dr);
1104 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1106 size_t size = ARRAY_SIZE(vcpu->arch.db);
1110 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1115 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116 *val = vcpu->arch.dr6;
1118 *val = kvm_x86_ops->get_dr6(vcpu);
1123 *val = vcpu->arch.dr7;
1128 EXPORT_SYMBOL_GPL(kvm_get_dr);
1130 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1132 u32 ecx = kvm_rcx_read(vcpu);
1136 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1139 kvm_rax_write(vcpu, (u32)data);
1140 kvm_rdx_write(vcpu, data >> 32);
1143 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1146 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1147 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1149 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1150 * extract the supported MSRs from the related const lists.
1151 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1152 * capabilities of the host cpu. This capabilities test skips MSRs that are
1153 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1154 * may depend on host virtualization features rather than host cpu features.
1157 static const u32 msrs_to_save_all[] = {
1158 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1160 #ifdef CONFIG_X86_64
1161 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1163 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1164 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1166 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1167 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1168 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1169 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1170 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1171 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1172 MSR_IA32_UMWAIT_CONTROL,
1174 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1175 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1176 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1177 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1178 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1179 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1180 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1181 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1182 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1183 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1184 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1185 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1186 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1187 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1188 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1195 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1198 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1199 static unsigned num_msrs_to_save;
1201 static const u32 emulated_msrs_all[] = {
1202 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1203 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1204 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1205 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1206 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1207 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1208 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1210 HV_X64_MSR_VP_INDEX,
1211 HV_X64_MSR_VP_RUNTIME,
1212 HV_X64_MSR_SCONTROL,
1213 HV_X64_MSR_STIMER0_CONFIG,
1214 HV_X64_MSR_VP_ASSIST_PAGE,
1215 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1216 HV_X64_MSR_TSC_EMULATION_STATUS,
1218 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1221 MSR_IA32_TSC_ADJUST,
1222 MSR_IA32_TSCDEADLINE,
1223 MSR_IA32_ARCH_CAPABILITIES,
1224 MSR_IA32_MISC_ENABLE,
1225 MSR_IA32_MCG_STATUS,
1227 MSR_IA32_MCG_EXT_CTL,
1231 MSR_MISC_FEATURES_ENABLES,
1232 MSR_AMD64_VIRT_SPEC_CTRL,
1237 * The following list leaves out MSRs whose values are determined
1238 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1239 * We always support the "true" VMX control MSRs, even if the host
1240 * processor does not, so I am putting these registers here rather
1241 * than in msrs_to_save_all.
1244 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1245 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1246 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1247 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1249 MSR_IA32_VMX_CR0_FIXED0,
1250 MSR_IA32_VMX_CR4_FIXED0,
1251 MSR_IA32_VMX_VMCS_ENUM,
1252 MSR_IA32_VMX_PROCBASED_CTLS2,
1253 MSR_IA32_VMX_EPT_VPID_CAP,
1254 MSR_IA32_VMX_VMFUNC,
1257 MSR_KVM_POLL_CONTROL,
1260 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1261 static unsigned num_emulated_msrs;
1264 * List of msr numbers which are used to expose MSR-based features that
1265 * can be used by a hypervisor to validate requested CPU features.
1267 static const u32 msr_based_features_all[] = {
1269 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1270 MSR_IA32_VMX_PINBASED_CTLS,
1271 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1272 MSR_IA32_VMX_PROCBASED_CTLS,
1273 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1274 MSR_IA32_VMX_EXIT_CTLS,
1275 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1276 MSR_IA32_VMX_ENTRY_CTLS,
1278 MSR_IA32_VMX_CR0_FIXED0,
1279 MSR_IA32_VMX_CR0_FIXED1,
1280 MSR_IA32_VMX_CR4_FIXED0,
1281 MSR_IA32_VMX_CR4_FIXED1,
1282 MSR_IA32_VMX_VMCS_ENUM,
1283 MSR_IA32_VMX_PROCBASED_CTLS2,
1284 MSR_IA32_VMX_EPT_VPID_CAP,
1285 MSR_IA32_VMX_VMFUNC,
1289 MSR_IA32_ARCH_CAPABILITIES,
1292 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1293 static unsigned int num_msr_based_features;
1295 static u64 kvm_get_arch_capabilities(void)
1299 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1300 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1303 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1304 * the nested hypervisor runs with NX huge pages. If it is not,
1305 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1306 * L1 guests, so it need not worry about its own (L2) guests.
1308 data |= ARCH_CAP_PSCHANGE_MC_NO;
1311 * If we're doing cache flushes (either "always" or "cond")
1312 * we will do one whenever the guest does a vmlaunch/vmresume.
1313 * If an outer hypervisor is doing the cache flush for us
1314 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1315 * capability to the guest too, and if EPT is disabled we're not
1316 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1317 * require a nested hypervisor to do a flush of its own.
1319 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1320 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1322 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1323 data |= ARCH_CAP_RDCL_NO;
1324 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1325 data |= ARCH_CAP_SSB_NO;
1326 if (!boot_cpu_has_bug(X86_BUG_MDS))
1327 data |= ARCH_CAP_MDS_NO;
1330 * On TAA affected systems:
1331 * - nothing to do if TSX is disabled on the host.
1332 * - we emulate TSX_CTRL if present on the host.
1333 * This lets the guest use VERW to clear CPU buffers.
1335 if (!boot_cpu_has(X86_FEATURE_RTM))
1336 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1337 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1338 data |= ARCH_CAP_TAA_NO;
1343 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1345 switch (msr->index) {
1346 case MSR_IA32_ARCH_CAPABILITIES:
1347 msr->data = kvm_get_arch_capabilities();
1349 case MSR_IA32_UCODE_REV:
1350 rdmsrl_safe(msr->index, &msr->data);
1353 if (kvm_x86_ops->get_msr_feature(msr))
1359 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1361 struct kvm_msr_entry msr;
1365 r = kvm_get_msr_feature(&msr);
1374 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1376 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1379 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1382 if (efer & (EFER_LME | EFER_LMA) &&
1383 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1386 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1392 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1394 if (efer & efer_reserved_bits)
1397 return __kvm_valid_efer(vcpu, efer);
1399 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1401 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1403 u64 old_efer = vcpu->arch.efer;
1404 u64 efer = msr_info->data;
1406 if (efer & efer_reserved_bits)
1409 if (!msr_info->host_initiated) {
1410 if (!__kvm_valid_efer(vcpu, efer))
1413 if (is_paging(vcpu) &&
1414 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1419 efer |= vcpu->arch.efer & EFER_LMA;
1421 kvm_x86_ops->set_efer(vcpu, efer);
1423 /* Update reserved bits */
1424 if ((efer ^ old_efer) & EFER_NX)
1425 kvm_mmu_reset_context(vcpu);
1430 void kvm_enable_efer_bits(u64 mask)
1432 efer_reserved_bits &= ~mask;
1434 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1437 * Write @data into the MSR specified by @index. Select MSR specific fault
1438 * checks are bypassed if @host_initiated is %true.
1439 * Returns 0 on success, non-0 otherwise.
1440 * Assumes vcpu_load() was already called.
1442 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1443 bool host_initiated)
1445 struct msr_data msr;
1450 case MSR_KERNEL_GS_BASE:
1453 if (is_noncanonical_address(data, vcpu))
1456 case MSR_IA32_SYSENTER_EIP:
1457 case MSR_IA32_SYSENTER_ESP:
1459 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1460 * non-canonical address is written on Intel but not on
1461 * AMD (which ignores the top 32-bits, because it does
1462 * not implement 64-bit SYSENTER).
1464 * 64-bit code should hence be able to write a non-canonical
1465 * value on AMD. Making the address canonical ensures that
1466 * vmentry does not fail on Intel after writing a non-canonical
1467 * value, and that something deterministic happens if the guest
1468 * invokes 64-bit SYSENTER.
1470 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1475 msr.host_initiated = host_initiated;
1477 return kvm_x86_ops->set_msr(vcpu, &msr);
1481 * Read the MSR specified by @index into @data. Select MSR specific fault
1482 * checks are bypassed if @host_initiated is %true.
1483 * Returns 0 on success, non-0 otherwise.
1484 * Assumes vcpu_load() was already called.
1486 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1487 bool host_initiated)
1489 struct msr_data msr;
1493 msr.host_initiated = host_initiated;
1495 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1501 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1503 return __kvm_get_msr(vcpu, index, data, false);
1505 EXPORT_SYMBOL_GPL(kvm_get_msr);
1507 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1509 return __kvm_set_msr(vcpu, index, data, false);
1511 EXPORT_SYMBOL_GPL(kvm_set_msr);
1513 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1515 u32 ecx = kvm_rcx_read(vcpu);
1518 if (kvm_get_msr(vcpu, ecx, &data)) {
1519 trace_kvm_msr_read_ex(ecx);
1520 kvm_inject_gp(vcpu, 0);
1524 trace_kvm_msr_read(ecx, data);
1526 kvm_rax_write(vcpu, data & -1u);
1527 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1528 return kvm_skip_emulated_instruction(vcpu);
1530 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1532 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1534 u32 ecx = kvm_rcx_read(vcpu);
1535 u64 data = kvm_read_edx_eax(vcpu);
1537 if (kvm_set_msr(vcpu, ecx, data)) {
1538 trace_kvm_msr_write_ex(ecx, data);
1539 kvm_inject_gp(vcpu, 0);
1543 trace_kvm_msr_write(ecx, data);
1544 return kvm_skip_emulated_instruction(vcpu);
1546 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1549 * The fast path for frequent and performance sensitive wrmsr emulation,
1550 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1551 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1552 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1553 * other cases which must be called after interrupts are enabled on the host.
1555 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1557 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1558 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1559 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1561 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1562 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data);
1568 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1570 u32 msr = kvm_rcx_read(vcpu);
1571 u64 data = kvm_read_edx_eax(vcpu);
1575 case APIC_BASE_MSR + (APIC_ICR >> 4):
1576 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1579 return EXIT_FASTPATH_NONE;
1583 trace_kvm_msr_write(msr, data);
1584 return EXIT_FASTPATH_SKIP_EMUL_INS;
1587 return EXIT_FASTPATH_NONE;
1589 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1592 * Adapt set_msr() to msr_io()'s calling convention
1594 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1596 return __kvm_get_msr(vcpu, index, data, true);
1599 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1601 return __kvm_set_msr(vcpu, index, *data, true);
1604 #ifdef CONFIG_X86_64
1605 struct pvclock_clock {
1615 struct pvclock_gtod_data {
1618 struct pvclock_clock clock; /* extract of a clocksource struct */
1619 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1625 static struct pvclock_gtod_data pvclock_gtod_data;
1627 static void update_pvclock_gtod(struct timekeeper *tk)
1629 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1631 write_seqcount_begin(&vdata->seq);
1633 /* copy pvclock gtod data */
1634 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1635 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1636 vdata->clock.mask = tk->tkr_mono.mask;
1637 vdata->clock.mult = tk->tkr_mono.mult;
1638 vdata->clock.shift = tk->tkr_mono.shift;
1639 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1640 vdata->clock.offset = tk->tkr_mono.base;
1642 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode;
1643 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1644 vdata->raw_clock.mask = tk->tkr_raw.mask;
1645 vdata->raw_clock.mult = tk->tkr_raw.mult;
1646 vdata->raw_clock.shift = tk->tkr_raw.shift;
1647 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1648 vdata->raw_clock.offset = tk->tkr_raw.base;
1650 vdata->wall_time_sec = tk->xtime_sec;
1652 vdata->offs_boot = tk->offs_boot;
1654 write_seqcount_end(&vdata->seq);
1657 static s64 get_kvmclock_base_ns(void)
1659 /* Count up from boot time, but with the frequency of the raw clock. */
1660 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1663 static s64 get_kvmclock_base_ns(void)
1665 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1666 return ktime_get_boottime_ns();
1670 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1672 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1673 kvm_vcpu_kick(vcpu);
1676 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1680 struct pvclock_wall_clock wc;
1686 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1691 ++version; /* first time write, random junk */
1695 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1699 * The guest calculates current wall clock time by adding
1700 * system time (updated by kvm_guest_time_update below) to the
1701 * wall clock specified here. We do the reverse here.
1703 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1705 wc.nsec = do_div(wall_nsec, 1000000000);
1706 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1707 wc.version = version;
1709 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1712 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1715 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1717 do_shl32_div32(dividend, divisor);
1721 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1722 s8 *pshift, u32 *pmultiplier)
1730 scaled64 = scaled_hz;
1731 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1736 tps32 = (uint32_t)tps64;
1737 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1738 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1746 *pmultiplier = div_frac(scaled64, tps32);
1749 #ifdef CONFIG_X86_64
1750 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1753 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1754 static unsigned long max_tsc_khz;
1756 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1758 u64 v = (u64)khz * (1000000 + ppm);
1763 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1767 /* Guest TSC same frequency as host TSC? */
1769 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1773 /* TSC scaling supported? */
1774 if (!kvm_has_tsc_control) {
1775 if (user_tsc_khz > tsc_khz) {
1776 vcpu->arch.tsc_catchup = 1;
1777 vcpu->arch.tsc_always_catchup = 1;
1780 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1785 /* TSC scaling required - calculate ratio */
1786 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1787 user_tsc_khz, tsc_khz);
1789 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1790 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1795 vcpu->arch.tsc_scaling_ratio = ratio;
1799 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1801 u32 thresh_lo, thresh_hi;
1802 int use_scaling = 0;
1804 /* tsc_khz can be zero if TSC calibration fails */
1805 if (user_tsc_khz == 0) {
1806 /* set tsc_scaling_ratio to a safe value */
1807 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1811 /* Compute a scale to convert nanoseconds in TSC cycles */
1812 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1813 &vcpu->arch.virtual_tsc_shift,
1814 &vcpu->arch.virtual_tsc_mult);
1815 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1818 * Compute the variation in TSC rate which is acceptable
1819 * within the range of tolerance and decide if the
1820 * rate being applied is within that bounds of the hardware
1821 * rate. If so, no scaling or compensation need be done.
1823 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1824 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1825 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1826 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1829 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1832 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1834 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1835 vcpu->arch.virtual_tsc_mult,
1836 vcpu->arch.virtual_tsc_shift);
1837 tsc += vcpu->arch.this_tsc_write;
1841 static inline int gtod_is_based_on_tsc(int mode)
1843 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1846 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1848 #ifdef CONFIG_X86_64
1850 struct kvm_arch *ka = &vcpu->kvm->arch;
1851 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1853 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1854 atomic_read(&vcpu->kvm->online_vcpus));
1857 * Once the masterclock is enabled, always perform request in
1858 * order to update it.
1860 * In order to enable masterclock, the host clocksource must be TSC
1861 * and the vcpus need to have matched TSCs. When that happens,
1862 * perform request to enable masterclock.
1864 if (ka->use_master_clock ||
1865 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1866 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1868 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1869 atomic_read(&vcpu->kvm->online_vcpus),
1870 ka->use_master_clock, gtod->clock.vclock_mode);
1874 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1876 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1877 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1881 * Multiply tsc by a fixed point number represented by ratio.
1883 * The most significant 64-N bits (mult) of ratio represent the
1884 * integral part of the fixed point number; the remaining N bits
1885 * (frac) represent the fractional part, ie. ratio represents a fixed
1886 * point number (mult + frac * 2^(-N)).
1888 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1890 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1892 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1895 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1898 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1900 if (ratio != kvm_default_tsc_scaling_ratio)
1901 _tsc = __scale_tsc(ratio, tsc);
1905 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1907 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1911 tsc = kvm_scale_tsc(vcpu, rdtsc());
1913 return target_tsc - tsc;
1916 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1918 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1920 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1922 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1924 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1926 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1929 static inline bool kvm_check_tsc_unstable(void)
1931 #ifdef CONFIG_X86_64
1933 * TSC is marked unstable when we're running on Hyper-V,
1934 * 'TSC page' clocksource is good.
1936 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1939 return check_tsc_unstable();
1942 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1944 struct kvm *kvm = vcpu->kvm;
1945 u64 offset, ns, elapsed;
1946 unsigned long flags;
1948 bool already_matched;
1949 u64 data = msr->data;
1950 bool synchronizing = false;
1952 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1953 offset = kvm_compute_tsc_offset(vcpu, data);
1954 ns = get_kvmclock_base_ns();
1955 elapsed = ns - kvm->arch.last_tsc_nsec;
1957 if (vcpu->arch.virtual_tsc_khz) {
1958 if (data == 0 && msr->host_initiated) {
1960 * detection of vcpu initialization -- need to sync
1961 * with other vCPUs. This particularly helps to keep
1962 * kvm_clock stable after CPU hotplug
1964 synchronizing = true;
1966 u64 tsc_exp = kvm->arch.last_tsc_write +
1967 nsec_to_cycles(vcpu, elapsed);
1968 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1970 * Special case: TSC write with a small delta (1 second)
1971 * of virtual cycle time against real time is
1972 * interpreted as an attempt to synchronize the CPU.
1974 synchronizing = data < tsc_exp + tsc_hz &&
1975 data + tsc_hz > tsc_exp;
1980 * For a reliable TSC, we can match TSC offsets, and for an unstable
1981 * TSC, we add elapsed time in this computation. We could let the
1982 * compensation code attempt to catch up if we fall behind, but
1983 * it's better to try to match offsets from the beginning.
1985 if (synchronizing &&
1986 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1987 if (!kvm_check_tsc_unstable()) {
1988 offset = kvm->arch.cur_tsc_offset;
1990 u64 delta = nsec_to_cycles(vcpu, elapsed);
1992 offset = kvm_compute_tsc_offset(vcpu, data);
1995 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1998 * We split periods of matched TSC writes into generations.
1999 * For each generation, we track the original measured
2000 * nanosecond time, offset, and write, so if TSCs are in
2001 * sync, we can match exact offset, and if not, we can match
2002 * exact software computation in compute_guest_tsc()
2004 * These values are tracked in kvm->arch.cur_xxx variables.
2006 kvm->arch.cur_tsc_generation++;
2007 kvm->arch.cur_tsc_nsec = ns;
2008 kvm->arch.cur_tsc_write = data;
2009 kvm->arch.cur_tsc_offset = offset;
2014 * We also track th most recent recorded KHZ, write and time to
2015 * allow the matching interval to be extended at each write.
2017 kvm->arch.last_tsc_nsec = ns;
2018 kvm->arch.last_tsc_write = data;
2019 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2021 vcpu->arch.last_guest_tsc = data;
2023 /* Keep track of which generation this VCPU has synchronized to */
2024 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2025 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2026 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2028 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2029 update_ia32_tsc_adjust_msr(vcpu, offset);
2031 kvm_vcpu_write_tsc_offset(vcpu, offset);
2032 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2034 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2036 kvm->arch.nr_vcpus_matched_tsc = 0;
2037 } else if (!already_matched) {
2038 kvm->arch.nr_vcpus_matched_tsc++;
2041 kvm_track_tsc_matching(vcpu);
2042 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2045 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2047 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2050 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2051 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2054 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2056 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2057 WARN_ON(adjustment < 0);
2058 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2059 adjust_tsc_offset_guest(vcpu, adjustment);
2062 #ifdef CONFIG_X86_64
2064 static u64 read_tsc(void)
2066 u64 ret = (u64)rdtsc_ordered();
2067 u64 last = pvclock_gtod_data.clock.cycle_last;
2069 if (likely(ret >= last))
2073 * GCC likes to generate cmov here, but this branch is extremely
2074 * predictable (it's just a function of time and the likely is
2075 * very likely) and there's a data dependence, so force GCC
2076 * to generate a branch instead. I don't barrier() because
2077 * we don't actually need a barrier, and if this function
2078 * ever gets inlined it will generate worse code.
2084 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2090 switch (clock->vclock_mode) {
2091 case VCLOCK_HVCLOCK:
2092 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2094 if (tsc_pg_val != U64_MAX) {
2095 /* TSC page valid */
2096 *mode = VCLOCK_HVCLOCK;
2097 v = (tsc_pg_val - clock->cycle_last) &
2100 /* TSC page invalid */
2101 *mode = VCLOCK_NONE;
2106 *tsc_timestamp = read_tsc();
2107 v = (*tsc_timestamp - clock->cycle_last) &
2111 *mode = VCLOCK_NONE;
2114 if (*mode == VCLOCK_NONE)
2115 *tsc_timestamp = v = 0;
2117 return v * clock->mult;
2120 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2122 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2128 seq = read_seqcount_begin(>od->seq);
2129 ns = gtod->raw_clock.base_cycles;
2130 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2131 ns >>= gtod->raw_clock.shift;
2132 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2133 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2139 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2141 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2147 seq = read_seqcount_begin(>od->seq);
2148 ts->tv_sec = gtod->wall_time_sec;
2149 ns = gtod->clock.base_cycles;
2150 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2151 ns >>= gtod->clock.shift;
2152 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2154 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2160 /* returns true if host is using TSC based clocksource */
2161 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2163 /* checked again under seqlock below */
2164 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2167 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2171 /* returns true if host is using TSC based clocksource */
2172 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2175 /* checked again under seqlock below */
2176 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2179 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2185 * Assuming a stable TSC across physical CPUS, and a stable TSC
2186 * across virtual CPUs, the following condition is possible.
2187 * Each numbered line represents an event visible to both
2188 * CPUs at the next numbered event.
2190 * "timespecX" represents host monotonic time. "tscX" represents
2193 * VCPU0 on CPU0 | VCPU1 on CPU1
2195 * 1. read timespec0,tsc0
2196 * 2. | timespec1 = timespec0 + N
2198 * 3. transition to guest | transition to guest
2199 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2200 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2201 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2203 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2206 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2208 * - 0 < N - M => M < N
2210 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2211 * always the case (the difference between two distinct xtime instances
2212 * might be smaller then the difference between corresponding TSC reads,
2213 * when updating guest vcpus pvclock areas).
2215 * To avoid that problem, do not allow visibility of distinct
2216 * system_timestamp/tsc_timestamp values simultaneously: use a master
2217 * copy of host monotonic time values. Update that master copy
2220 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2224 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2226 #ifdef CONFIG_X86_64
2227 struct kvm_arch *ka = &kvm->arch;
2229 bool host_tsc_clocksource, vcpus_matched;
2231 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2232 atomic_read(&kvm->online_vcpus));
2235 * If the host uses TSC clock, then passthrough TSC as stable
2238 host_tsc_clocksource = kvm_get_time_and_clockread(
2239 &ka->master_kernel_ns,
2240 &ka->master_cycle_now);
2242 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2243 && !ka->backwards_tsc_observed
2244 && !ka->boot_vcpu_runs_old_kvmclock;
2246 if (ka->use_master_clock)
2247 atomic_set(&kvm_guest_has_master_clock, 1);
2249 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2250 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2255 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2257 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2260 static void kvm_gen_update_masterclock(struct kvm *kvm)
2262 #ifdef CONFIG_X86_64
2264 struct kvm_vcpu *vcpu;
2265 struct kvm_arch *ka = &kvm->arch;
2267 spin_lock(&ka->pvclock_gtod_sync_lock);
2268 kvm_make_mclock_inprogress_request(kvm);
2269 /* no guest entries from this point */
2270 pvclock_update_vm_gtod_copy(kvm);
2272 kvm_for_each_vcpu(i, vcpu, kvm)
2273 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2275 /* guest entries allowed */
2276 kvm_for_each_vcpu(i, vcpu, kvm)
2277 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2279 spin_unlock(&ka->pvclock_gtod_sync_lock);
2283 u64 get_kvmclock_ns(struct kvm *kvm)
2285 struct kvm_arch *ka = &kvm->arch;
2286 struct pvclock_vcpu_time_info hv_clock;
2289 spin_lock(&ka->pvclock_gtod_sync_lock);
2290 if (!ka->use_master_clock) {
2291 spin_unlock(&ka->pvclock_gtod_sync_lock);
2292 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2295 hv_clock.tsc_timestamp = ka->master_cycle_now;
2296 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2297 spin_unlock(&ka->pvclock_gtod_sync_lock);
2299 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2302 if (__this_cpu_read(cpu_tsc_khz)) {
2303 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2304 &hv_clock.tsc_shift,
2305 &hv_clock.tsc_to_system_mul);
2306 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2308 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2315 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2317 struct kvm_vcpu_arch *vcpu = &v->arch;
2318 struct pvclock_vcpu_time_info guest_hv_clock;
2320 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2321 &guest_hv_clock, sizeof(guest_hv_clock))))
2324 /* This VCPU is paused, but it's legal for a guest to read another
2325 * VCPU's kvmclock, so we really have to follow the specification where
2326 * it says that version is odd if data is being modified, and even after
2329 * Version field updates must be kept separate. This is because
2330 * kvm_write_guest_cached might use a "rep movs" instruction, and
2331 * writes within a string instruction are weakly ordered. So there
2332 * are three writes overall.
2334 * As a small optimization, only write the version field in the first
2335 * and third write. The vcpu->pv_time cache is still valid, because the
2336 * version field is the first in the struct.
2338 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2340 if (guest_hv_clock.version & 1)
2341 ++guest_hv_clock.version; /* first time write, random junk */
2343 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2344 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2346 sizeof(vcpu->hv_clock.version));
2350 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2351 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2353 if (vcpu->pvclock_set_guest_stopped_request) {
2354 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2355 vcpu->pvclock_set_guest_stopped_request = false;
2358 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2360 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2362 sizeof(vcpu->hv_clock));
2366 vcpu->hv_clock.version++;
2367 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2369 sizeof(vcpu->hv_clock.version));
2372 static int kvm_guest_time_update(struct kvm_vcpu *v)
2374 unsigned long flags, tgt_tsc_khz;
2375 struct kvm_vcpu_arch *vcpu = &v->arch;
2376 struct kvm_arch *ka = &v->kvm->arch;
2378 u64 tsc_timestamp, host_tsc;
2380 bool use_master_clock;
2386 * If the host uses TSC clock, then passthrough TSC as stable
2389 spin_lock(&ka->pvclock_gtod_sync_lock);
2390 use_master_clock = ka->use_master_clock;
2391 if (use_master_clock) {
2392 host_tsc = ka->master_cycle_now;
2393 kernel_ns = ka->master_kernel_ns;
2395 spin_unlock(&ka->pvclock_gtod_sync_lock);
2397 /* Keep irq disabled to prevent changes to the clock */
2398 local_irq_save(flags);
2399 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2400 if (unlikely(tgt_tsc_khz == 0)) {
2401 local_irq_restore(flags);
2402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2405 if (!use_master_clock) {
2407 kernel_ns = get_kvmclock_base_ns();
2410 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2413 * We may have to catch up the TSC to match elapsed wall clock
2414 * time for two reasons, even if kvmclock is used.
2415 * 1) CPU could have been running below the maximum TSC rate
2416 * 2) Broken TSC compensation resets the base at each VCPU
2417 * entry to avoid unknown leaps of TSC even when running
2418 * again on the same CPU. This may cause apparent elapsed
2419 * time to disappear, and the guest to stand still or run
2422 if (vcpu->tsc_catchup) {
2423 u64 tsc = compute_guest_tsc(v, kernel_ns);
2424 if (tsc > tsc_timestamp) {
2425 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2426 tsc_timestamp = tsc;
2430 local_irq_restore(flags);
2432 /* With all the info we got, fill in the values */
2434 if (kvm_has_tsc_control)
2435 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2437 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2438 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2439 &vcpu->hv_clock.tsc_shift,
2440 &vcpu->hv_clock.tsc_to_system_mul);
2441 vcpu->hw_tsc_khz = tgt_tsc_khz;
2444 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2445 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2446 vcpu->last_guest_tsc = tsc_timestamp;
2447 WARN_ON((s64)vcpu->hv_clock.system_time < 0);
2449 /* If the host uses TSC clocksource, then it is stable */
2451 if (use_master_clock)
2452 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2454 vcpu->hv_clock.flags = pvclock_flags;
2456 if (vcpu->pv_time_enabled)
2457 kvm_setup_pvclock_page(v);
2458 if (v == kvm_get_vcpu(v->kvm, 0))
2459 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2464 * kvmclock updates which are isolated to a given vcpu, such as
2465 * vcpu->cpu migration, should not allow system_timestamp from
2466 * the rest of the vcpus to remain static. Otherwise ntp frequency
2467 * correction applies to one vcpu's system_timestamp but not
2470 * So in those cases, request a kvmclock update for all vcpus.
2471 * We need to rate-limit these requests though, as they can
2472 * considerably slow guests that have a large number of vcpus.
2473 * The time for a remote vcpu to update its kvmclock is bound
2474 * by the delay we use to rate-limit the updates.
2477 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2479 static void kvmclock_update_fn(struct work_struct *work)
2482 struct delayed_work *dwork = to_delayed_work(work);
2483 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2484 kvmclock_update_work);
2485 struct kvm *kvm = container_of(ka, struct kvm, arch);
2486 struct kvm_vcpu *vcpu;
2488 kvm_for_each_vcpu(i, vcpu, kvm) {
2489 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2490 kvm_vcpu_kick(vcpu);
2494 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2496 struct kvm *kvm = v->kvm;
2498 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2499 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2500 KVMCLOCK_UPDATE_DELAY);
2503 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2505 static void kvmclock_sync_fn(struct work_struct *work)
2507 struct delayed_work *dwork = to_delayed_work(work);
2508 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2509 kvmclock_sync_work);
2510 struct kvm *kvm = container_of(ka, struct kvm, arch);
2512 if (!kvmclock_periodic_sync)
2515 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2516 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2517 KVMCLOCK_SYNC_PERIOD);
2521 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2523 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2525 /* McStatusWrEn enabled? */
2526 if (guest_cpuid_is_amd(vcpu))
2527 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2532 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2534 u64 mcg_cap = vcpu->arch.mcg_cap;
2535 unsigned bank_num = mcg_cap & 0xff;
2536 u32 msr = msr_info->index;
2537 u64 data = msr_info->data;
2540 case MSR_IA32_MCG_STATUS:
2541 vcpu->arch.mcg_status = data;
2543 case MSR_IA32_MCG_CTL:
2544 if (!(mcg_cap & MCG_CTL_P) &&
2545 (data || !msr_info->host_initiated))
2547 if (data != 0 && data != ~(u64)0)
2549 vcpu->arch.mcg_ctl = data;
2552 if (msr >= MSR_IA32_MC0_CTL &&
2553 msr < MSR_IA32_MCx_CTL(bank_num)) {
2554 u32 offset = array_index_nospec(
2555 msr - MSR_IA32_MC0_CTL,
2556 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2558 /* only 0 or all 1s can be written to IA32_MCi_CTL
2559 * some Linux kernels though clear bit 10 in bank 4 to
2560 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2561 * this to avoid an uncatched #GP in the guest
2563 if ((offset & 0x3) == 0 &&
2564 data != 0 && (data | (1 << 10)) != ~(u64)0)
2568 if (!msr_info->host_initiated &&
2569 (offset & 0x3) == 1 && data != 0) {
2570 if (!can_set_mci_status(vcpu))
2574 vcpu->arch.mce_banks[offset] = data;
2582 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2584 struct kvm *kvm = vcpu->kvm;
2585 int lm = is_long_mode(vcpu);
2586 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2587 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2588 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2589 : kvm->arch.xen_hvm_config.blob_size_32;
2590 u32 page_num = data & ~PAGE_MASK;
2591 u64 page_addr = data & PAGE_MASK;
2596 if (page_num >= blob_size)
2599 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2604 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2613 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2615 gpa_t gpa = data & ~0x3f;
2617 /* Bits 3:5 are reserved, Should be zero */
2621 vcpu->arch.apf.msr_val = data;
2623 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2624 kvm_clear_async_pf_completion_queue(vcpu);
2625 kvm_async_pf_hash_reset(vcpu);
2629 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2633 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2634 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2635 kvm_async_pf_wakeup_all(vcpu);
2639 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2641 vcpu->arch.pv_time_enabled = false;
2642 vcpu->arch.time = 0;
2645 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2647 ++vcpu->stat.tlb_flush;
2648 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2651 static void record_steal_time(struct kvm_vcpu *vcpu)
2653 struct kvm_host_map map;
2654 struct kvm_steal_time *st;
2656 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2659 /* -EAGAIN is returned in atomic context so we can just return. */
2660 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2661 &map, &vcpu->arch.st.cache, false))
2665 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2668 * Doing a TLB flush here, on the guest's behalf, can avoid
2671 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2672 st->preempted & KVM_VCPU_FLUSH_TLB);
2673 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2674 kvm_vcpu_flush_tlb(vcpu, false);
2676 vcpu->arch.st.preempted = 0;
2678 if (st->version & 1)
2679 st->version += 1; /* first time write, random junk */
2685 st->steal += current->sched_info.run_delay -
2686 vcpu->arch.st.last_steal;
2687 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2693 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2696 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2699 u32 msr = msr_info->index;
2700 u64 data = msr_info->data;
2703 case MSR_AMD64_NB_CFG:
2704 case MSR_IA32_UCODE_WRITE:
2705 case MSR_VM_HSAVE_PA:
2706 case MSR_AMD64_PATCH_LOADER:
2707 case MSR_AMD64_BU_CFG2:
2708 case MSR_AMD64_DC_CFG:
2709 case MSR_F15H_EX_CFG:
2712 case MSR_IA32_UCODE_REV:
2713 if (msr_info->host_initiated)
2714 vcpu->arch.microcode_version = data;
2716 case MSR_IA32_ARCH_CAPABILITIES:
2717 if (!msr_info->host_initiated)
2719 vcpu->arch.arch_capabilities = data;
2722 return set_efer(vcpu, msr_info);
2724 data &= ~(u64)0x40; /* ignore flush filter disable */
2725 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2726 data &= ~(u64)0x8; /* ignore TLB cache disable */
2728 /* Handle McStatusWrEn */
2729 if (data == BIT_ULL(18)) {
2730 vcpu->arch.msr_hwcr = data;
2731 } else if (data != 0) {
2732 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2737 case MSR_FAM10H_MMIO_CONF_BASE:
2739 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2744 case MSR_IA32_DEBUGCTLMSR:
2746 /* We support the non-activated case already */
2748 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2749 /* Values other than LBR and BTF are vendor-specific,
2750 thus reserved and should throw a #GP */
2753 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2756 case 0x200 ... 0x2ff:
2757 return kvm_mtrr_set_msr(vcpu, msr, data);
2758 case MSR_IA32_APICBASE:
2759 return kvm_set_apic_base(vcpu, msr_info);
2760 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2761 return kvm_x2apic_msr_write(vcpu, msr, data);
2762 case MSR_IA32_TSCDEADLINE:
2763 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2765 case MSR_IA32_TSC_ADJUST:
2766 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2767 if (!msr_info->host_initiated) {
2768 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2769 adjust_tsc_offset_guest(vcpu, adj);
2771 vcpu->arch.ia32_tsc_adjust_msr = data;
2774 case MSR_IA32_MISC_ENABLE:
2775 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2776 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2777 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2779 vcpu->arch.ia32_misc_enable_msr = data;
2780 kvm_update_cpuid(vcpu);
2782 vcpu->arch.ia32_misc_enable_msr = data;
2785 case MSR_IA32_SMBASE:
2786 if (!msr_info->host_initiated)
2788 vcpu->arch.smbase = data;
2790 case MSR_IA32_POWER_CTL:
2791 vcpu->arch.msr_ia32_power_ctl = data;
2794 kvm_write_tsc(vcpu, msr_info);
2797 if (!msr_info->host_initiated &&
2798 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2801 * We do support PT if kvm_x86_ops->pt_supported(), but we do
2802 * not support IA32_XSS[bit 8]. Guests will have to use
2803 * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT
2808 vcpu->arch.ia32_xss = data;
2811 if (!msr_info->host_initiated)
2813 vcpu->arch.smi_count = data;
2815 case MSR_KVM_WALL_CLOCK_NEW:
2816 case MSR_KVM_WALL_CLOCK:
2817 vcpu->kvm->arch.wall_clock = data;
2818 kvm_write_wall_clock(vcpu->kvm, data);
2820 case MSR_KVM_SYSTEM_TIME_NEW:
2821 case MSR_KVM_SYSTEM_TIME: {
2822 struct kvm_arch *ka = &vcpu->kvm->arch;
2824 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2825 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2827 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2828 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2830 ka->boot_vcpu_runs_old_kvmclock = tmp;
2833 vcpu->arch.time = data;
2834 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2836 /* we verify if the enable bit is set... */
2837 vcpu->arch.pv_time_enabled = false;
2841 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2842 &vcpu->arch.pv_time, data & ~1ULL,
2843 sizeof(struct pvclock_vcpu_time_info)))
2844 vcpu->arch.pv_time_enabled = true;
2848 case MSR_KVM_ASYNC_PF_EN:
2849 if (kvm_pv_enable_async_pf(vcpu, data))
2852 case MSR_KVM_STEAL_TIME:
2854 if (unlikely(!sched_info_on()))
2857 if (data & KVM_STEAL_RESERVED_MASK)
2860 vcpu->arch.st.msr_val = data;
2862 if (!(data & KVM_MSR_ENABLED))
2865 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2868 case MSR_KVM_PV_EOI_EN:
2869 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2873 case MSR_KVM_POLL_CONTROL:
2874 /* only enable bit supported */
2875 if (data & (-1ULL << 1))
2878 vcpu->arch.msr_kvm_poll_control = data;
2881 case MSR_IA32_MCG_CTL:
2882 case MSR_IA32_MCG_STATUS:
2883 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2884 return set_msr_mce(vcpu, msr_info);
2886 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2887 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2888 pr = true; /* fall through */
2889 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2890 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2891 if (kvm_pmu_is_valid_msr(vcpu, msr))
2892 return kvm_pmu_set_msr(vcpu, msr_info);
2894 if (pr || data != 0)
2895 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2896 "0x%x data 0x%llx\n", msr, data);
2898 case MSR_K7_CLK_CTL:
2900 * Ignore all writes to this no longer documented MSR.
2901 * Writes are only relevant for old K7 processors,
2902 * all pre-dating SVM, but a recommended workaround from
2903 * AMD for these chips. It is possible to specify the
2904 * affected processor models on the command line, hence
2905 * the need to ignore the workaround.
2908 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2909 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2910 case HV_X64_MSR_CRASH_CTL:
2911 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2912 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2913 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2914 case HV_X64_MSR_TSC_EMULATION_STATUS:
2915 return kvm_hv_set_msr_common(vcpu, msr, data,
2916 msr_info->host_initiated);
2917 case MSR_IA32_BBL_CR_CTL3:
2918 /* Drop writes to this legacy MSR -- see rdmsr
2919 * counterpart for further detail.
2921 if (report_ignored_msrs)
2922 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2925 case MSR_AMD64_OSVW_ID_LENGTH:
2926 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2928 vcpu->arch.osvw.length = data;
2930 case MSR_AMD64_OSVW_STATUS:
2931 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2933 vcpu->arch.osvw.status = data;
2935 case MSR_PLATFORM_INFO:
2936 if (!msr_info->host_initiated ||
2937 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2938 cpuid_fault_enabled(vcpu)))
2940 vcpu->arch.msr_platform_info = data;
2942 case MSR_MISC_FEATURES_ENABLES:
2943 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2944 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2945 !supports_cpuid_fault(vcpu)))
2947 vcpu->arch.msr_misc_features_enables = data;
2950 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2951 return xen_hvm_config(vcpu, data);
2952 if (kvm_pmu_is_valid_msr(vcpu, msr))
2953 return kvm_pmu_set_msr(vcpu, msr_info);
2955 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2959 if (report_ignored_msrs)
2961 "ignored wrmsr: 0x%x data 0x%llx\n",
2968 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2970 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2973 u64 mcg_cap = vcpu->arch.mcg_cap;
2974 unsigned bank_num = mcg_cap & 0xff;
2977 case MSR_IA32_P5_MC_ADDR:
2978 case MSR_IA32_P5_MC_TYPE:
2981 case MSR_IA32_MCG_CAP:
2982 data = vcpu->arch.mcg_cap;
2984 case MSR_IA32_MCG_CTL:
2985 if (!(mcg_cap & MCG_CTL_P) && !host)
2987 data = vcpu->arch.mcg_ctl;
2989 case MSR_IA32_MCG_STATUS:
2990 data = vcpu->arch.mcg_status;
2993 if (msr >= MSR_IA32_MC0_CTL &&
2994 msr < MSR_IA32_MCx_CTL(bank_num)) {
2995 u32 offset = array_index_nospec(
2996 msr - MSR_IA32_MC0_CTL,
2997 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2999 data = vcpu->arch.mce_banks[offset];
3008 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3010 switch (msr_info->index) {
3011 case MSR_IA32_PLATFORM_ID:
3012 case MSR_IA32_EBL_CR_POWERON:
3013 case MSR_IA32_DEBUGCTLMSR:
3014 case MSR_IA32_LASTBRANCHFROMIP:
3015 case MSR_IA32_LASTBRANCHTOIP:
3016 case MSR_IA32_LASTINTFROMIP:
3017 case MSR_IA32_LASTINTTOIP:
3019 case MSR_K8_TSEG_ADDR:
3020 case MSR_K8_TSEG_MASK:
3021 case MSR_VM_HSAVE_PA:
3022 case MSR_K8_INT_PENDING_MSG:
3023 case MSR_AMD64_NB_CFG:
3024 case MSR_FAM10H_MMIO_CONF_BASE:
3025 case MSR_AMD64_BU_CFG2:
3026 case MSR_IA32_PERF_CTL:
3027 case MSR_AMD64_DC_CFG:
3028 case MSR_F15H_EX_CFG:
3031 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3032 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3033 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3034 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3035 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3036 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3037 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3040 case MSR_IA32_UCODE_REV:
3041 msr_info->data = vcpu->arch.microcode_version;
3043 case MSR_IA32_ARCH_CAPABILITIES:
3044 if (!msr_info->host_initiated &&
3045 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3047 msr_info->data = vcpu->arch.arch_capabilities;
3049 case MSR_IA32_POWER_CTL:
3050 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3053 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3056 case 0x200 ... 0x2ff:
3057 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3058 case 0xcd: /* fsb frequency */
3062 * MSR_EBC_FREQUENCY_ID
3063 * Conservative value valid for even the basic CPU models.
3064 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3065 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3066 * and 266MHz for model 3, or 4. Set Core Clock
3067 * Frequency to System Bus Frequency Ratio to 1 (bits
3068 * 31:24) even though these are only valid for CPU
3069 * models > 2, however guests may end up dividing or
3070 * multiplying by zero otherwise.
3072 case MSR_EBC_FREQUENCY_ID:
3073 msr_info->data = 1 << 24;
3075 case MSR_IA32_APICBASE:
3076 msr_info->data = kvm_get_apic_base(vcpu);
3078 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3079 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3081 case MSR_IA32_TSCDEADLINE:
3082 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3084 case MSR_IA32_TSC_ADJUST:
3085 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3087 case MSR_IA32_MISC_ENABLE:
3088 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3090 case MSR_IA32_SMBASE:
3091 if (!msr_info->host_initiated)
3093 msr_info->data = vcpu->arch.smbase;
3096 msr_info->data = vcpu->arch.smi_count;
3098 case MSR_IA32_PERF_STATUS:
3099 /* TSC increment by tick */
3100 msr_info->data = 1000ULL;
3101 /* CPU multiplier */
3102 msr_info->data |= (((uint64_t)4ULL) << 40);
3105 msr_info->data = vcpu->arch.efer;
3107 case MSR_KVM_WALL_CLOCK:
3108 case MSR_KVM_WALL_CLOCK_NEW:
3109 msr_info->data = vcpu->kvm->arch.wall_clock;
3111 case MSR_KVM_SYSTEM_TIME:
3112 case MSR_KVM_SYSTEM_TIME_NEW:
3113 msr_info->data = vcpu->arch.time;
3115 case MSR_KVM_ASYNC_PF_EN:
3116 msr_info->data = vcpu->arch.apf.msr_val;
3118 case MSR_KVM_STEAL_TIME:
3119 msr_info->data = vcpu->arch.st.msr_val;
3121 case MSR_KVM_PV_EOI_EN:
3122 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3124 case MSR_KVM_POLL_CONTROL:
3125 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3127 case MSR_IA32_P5_MC_ADDR:
3128 case MSR_IA32_P5_MC_TYPE:
3129 case MSR_IA32_MCG_CAP:
3130 case MSR_IA32_MCG_CTL:
3131 case MSR_IA32_MCG_STATUS:
3132 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3133 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3134 msr_info->host_initiated);
3136 if (!msr_info->host_initiated &&
3137 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3139 msr_info->data = vcpu->arch.ia32_xss;
3141 case MSR_K7_CLK_CTL:
3143 * Provide expected ramp-up count for K7. All other
3144 * are set to zero, indicating minimum divisors for
3147 * This prevents guest kernels on AMD host with CPU
3148 * type 6, model 8 and higher from exploding due to
3149 * the rdmsr failing.
3151 msr_info->data = 0x20000000;
3153 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3154 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3155 case HV_X64_MSR_CRASH_CTL:
3156 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3157 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3158 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3159 case HV_X64_MSR_TSC_EMULATION_STATUS:
3160 return kvm_hv_get_msr_common(vcpu,
3161 msr_info->index, &msr_info->data,
3162 msr_info->host_initiated);
3164 case MSR_IA32_BBL_CR_CTL3:
3165 /* This legacy MSR exists but isn't fully documented in current
3166 * silicon. It is however accessed by winxp in very narrow
3167 * scenarios where it sets bit #19, itself documented as
3168 * a "reserved" bit. Best effort attempt to source coherent
3169 * read data here should the balance of the register be
3170 * interpreted by the guest:
3172 * L2 cache control register 3: 64GB range, 256KB size,
3173 * enabled, latency 0x1, configured
3175 msr_info->data = 0xbe702111;
3177 case MSR_AMD64_OSVW_ID_LENGTH:
3178 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3180 msr_info->data = vcpu->arch.osvw.length;
3182 case MSR_AMD64_OSVW_STATUS:
3183 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3185 msr_info->data = vcpu->arch.osvw.status;
3187 case MSR_PLATFORM_INFO:
3188 if (!msr_info->host_initiated &&
3189 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3191 msr_info->data = vcpu->arch.msr_platform_info;
3193 case MSR_MISC_FEATURES_ENABLES:
3194 msr_info->data = vcpu->arch.msr_misc_features_enables;
3197 msr_info->data = vcpu->arch.msr_hwcr;
3200 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3201 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3203 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3207 if (report_ignored_msrs)
3208 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3216 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3219 * Read or write a bunch of msrs. All parameters are kernel addresses.
3221 * @return number of msrs set successfully.
3223 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3224 struct kvm_msr_entry *entries,
3225 int (*do_msr)(struct kvm_vcpu *vcpu,
3226 unsigned index, u64 *data))
3230 for (i = 0; i < msrs->nmsrs; ++i)
3231 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3238 * Read or write a bunch of msrs. Parameters are user addresses.
3240 * @return number of msrs set successfully.
3242 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3243 int (*do_msr)(struct kvm_vcpu *vcpu,
3244 unsigned index, u64 *data),
3247 struct kvm_msrs msrs;
3248 struct kvm_msr_entry *entries;
3253 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3257 if (msrs.nmsrs >= MAX_IO_MSRS)
3260 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3261 entries = memdup_user(user_msrs->entries, size);
3262 if (IS_ERR(entries)) {
3263 r = PTR_ERR(entries);
3267 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3272 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3283 static inline bool kvm_can_mwait_in_guest(void)
3285 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3286 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3287 boot_cpu_has(X86_FEATURE_ARAT);
3290 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3295 case KVM_CAP_IRQCHIP:
3297 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3298 case KVM_CAP_SET_TSS_ADDR:
3299 case KVM_CAP_EXT_CPUID:
3300 case KVM_CAP_EXT_EMUL_CPUID:
3301 case KVM_CAP_CLOCKSOURCE:
3303 case KVM_CAP_NOP_IO_DELAY:
3304 case KVM_CAP_MP_STATE:
3305 case KVM_CAP_SYNC_MMU:
3306 case KVM_CAP_USER_NMI:
3307 case KVM_CAP_REINJECT_CONTROL:
3308 case KVM_CAP_IRQ_INJECT_STATUS:
3309 case KVM_CAP_IOEVENTFD:
3310 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3312 case KVM_CAP_PIT_STATE2:
3313 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3314 case KVM_CAP_XEN_HVM:
3315 case KVM_CAP_VCPU_EVENTS:
3316 case KVM_CAP_HYPERV:
3317 case KVM_CAP_HYPERV_VAPIC:
3318 case KVM_CAP_HYPERV_SPIN:
3319 case KVM_CAP_HYPERV_SYNIC:
3320 case KVM_CAP_HYPERV_SYNIC2:
3321 case KVM_CAP_HYPERV_VP_INDEX:
3322 case KVM_CAP_HYPERV_EVENTFD:
3323 case KVM_CAP_HYPERV_TLBFLUSH:
3324 case KVM_CAP_HYPERV_SEND_IPI:
3325 case KVM_CAP_HYPERV_CPUID:
3326 case KVM_CAP_PCI_SEGMENT:
3327 case KVM_CAP_DEBUGREGS:
3328 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3330 case KVM_CAP_ASYNC_PF:
3331 case KVM_CAP_GET_TSC_KHZ:
3332 case KVM_CAP_KVMCLOCK_CTRL:
3333 case KVM_CAP_READONLY_MEM:
3334 case KVM_CAP_HYPERV_TIME:
3335 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3336 case KVM_CAP_TSC_DEADLINE_TIMER:
3337 case KVM_CAP_DISABLE_QUIRKS:
3338 case KVM_CAP_SET_BOOT_CPU_ID:
3339 case KVM_CAP_SPLIT_IRQCHIP:
3340 case KVM_CAP_IMMEDIATE_EXIT:
3341 case KVM_CAP_PMU_EVENT_FILTER:
3342 case KVM_CAP_GET_MSR_FEATURES:
3343 case KVM_CAP_MSR_PLATFORM_INFO:
3344 case KVM_CAP_EXCEPTION_PAYLOAD:
3347 case KVM_CAP_SYNC_REGS:
3348 r = KVM_SYNC_X86_VALID_FIELDS;
3350 case KVM_CAP_ADJUST_CLOCK:
3351 r = KVM_CLOCK_TSC_STABLE;
3353 case KVM_CAP_X86_DISABLE_EXITS:
3354 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3355 KVM_X86_DISABLE_EXITS_CSTATE;
3356 if(kvm_can_mwait_in_guest())
3357 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3359 case KVM_CAP_X86_SMM:
3360 /* SMBASE is usually relocated above 1M on modern chipsets,
3361 * and SMM handlers might indeed rely on 4G segment limits,
3362 * so do not report SMM to be available if real mode is
3363 * emulated via vm86 mode. Still, do not go to great lengths
3364 * to avoid userspace's usage of the feature, because it is a
3365 * fringe case that is not enabled except via specific settings
3366 * of the module parameters.
3368 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3371 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3373 case KVM_CAP_NR_VCPUS:
3374 r = KVM_SOFT_MAX_VCPUS;
3376 case KVM_CAP_MAX_VCPUS:
3379 case KVM_CAP_MAX_VCPU_ID:
3380 r = KVM_MAX_VCPU_ID;
3382 case KVM_CAP_PV_MMU: /* obsolete */
3386 r = KVM_MAX_MCE_BANKS;
3389 r = boot_cpu_has(X86_FEATURE_XSAVE);
3391 case KVM_CAP_TSC_CONTROL:
3392 r = kvm_has_tsc_control;
3394 case KVM_CAP_X2APIC_API:
3395 r = KVM_X2APIC_API_VALID_FLAGS;
3397 case KVM_CAP_NESTED_STATE:
3398 r = kvm_x86_ops->get_nested_state ?
3399 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3401 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3402 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3404 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3405 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3414 long kvm_arch_dev_ioctl(struct file *filp,
3415 unsigned int ioctl, unsigned long arg)
3417 void __user *argp = (void __user *)arg;
3421 case KVM_GET_MSR_INDEX_LIST: {
3422 struct kvm_msr_list __user *user_msr_list = argp;
3423 struct kvm_msr_list msr_list;
3427 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3430 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3431 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3434 if (n < msr_list.nmsrs)
3437 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3438 num_msrs_to_save * sizeof(u32)))
3440 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3442 num_emulated_msrs * sizeof(u32)))
3447 case KVM_GET_SUPPORTED_CPUID:
3448 case KVM_GET_EMULATED_CPUID: {
3449 struct kvm_cpuid2 __user *cpuid_arg = argp;
3450 struct kvm_cpuid2 cpuid;
3453 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3456 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3462 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3467 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3469 if (copy_to_user(argp, &kvm_mce_cap_supported,
3470 sizeof(kvm_mce_cap_supported)))
3474 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3475 struct kvm_msr_list __user *user_msr_list = argp;
3476 struct kvm_msr_list msr_list;
3480 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3483 msr_list.nmsrs = num_msr_based_features;
3484 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3487 if (n < msr_list.nmsrs)
3490 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3491 num_msr_based_features * sizeof(u32)))
3497 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3507 static void wbinvd_ipi(void *garbage)
3512 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3514 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3517 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3519 /* Address WBINVD may be executed by guest */
3520 if (need_emulate_wbinvd(vcpu)) {
3521 if (kvm_x86_ops->has_wbinvd_exit())
3522 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3523 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3524 smp_call_function_single(vcpu->cpu,
3525 wbinvd_ipi, NULL, 1);
3528 kvm_x86_ops->vcpu_load(vcpu, cpu);
3530 /* Apply any externally detected TSC adjustments (due to suspend) */
3531 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3532 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3533 vcpu->arch.tsc_offset_adjustment = 0;
3534 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3537 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3538 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3539 rdtsc() - vcpu->arch.last_host_tsc;
3541 mark_tsc_unstable("KVM discovered backwards TSC");
3543 if (kvm_check_tsc_unstable()) {
3544 u64 offset = kvm_compute_tsc_offset(vcpu,
3545 vcpu->arch.last_guest_tsc);
3546 kvm_vcpu_write_tsc_offset(vcpu, offset);
3547 vcpu->arch.tsc_catchup = 1;
3550 if (kvm_lapic_hv_timer_in_use(vcpu))
3551 kvm_lapic_restart_hv_timer(vcpu);
3554 * On a host with synchronized TSC, there is no need to update
3555 * kvmclock on vcpu->cpu migration
3557 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3558 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3559 if (vcpu->cpu != cpu)
3560 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3564 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3567 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3569 struct kvm_host_map map;
3570 struct kvm_steal_time *st;
3572 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3575 if (vcpu->arch.st.preempted)
3578 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3579 &vcpu->arch.st.cache, true))
3583 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3585 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3587 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3590 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3594 if (vcpu->preempted)
3595 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3598 * Disable page faults because we're in atomic context here.
3599 * kvm_write_guest_offset_cached() would call might_fault()
3600 * that relies on pagefault_disable() to tell if there's a
3601 * bug. NOTE: the write to guest memory may not go through if
3602 * during postcopy live migration or if there's heavy guest
3605 pagefault_disable();
3607 * kvm_memslots() will be called by
3608 * kvm_write_guest_offset_cached() so take the srcu lock.
3610 idx = srcu_read_lock(&vcpu->kvm->srcu);
3611 kvm_steal_time_set_preempted(vcpu);
3612 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3614 kvm_x86_ops->vcpu_put(vcpu);
3615 vcpu->arch.last_host_tsc = rdtsc();
3617 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3618 * on every vmexit, but if not, we might have a stale dr6 from the
3619 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3624 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3625 struct kvm_lapic_state *s)
3627 if (vcpu->arch.apicv_active)
3628 kvm_x86_ops->sync_pir_to_irr(vcpu);
3630 return kvm_apic_get_state(vcpu, s);
3633 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3634 struct kvm_lapic_state *s)
3638 r = kvm_apic_set_state(vcpu, s);
3641 update_cr8_intercept(vcpu);
3646 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3648 return (!lapic_in_kernel(vcpu) ||
3649 kvm_apic_accept_pic_intr(vcpu));
3653 * if userspace requested an interrupt window, check that the
3654 * interrupt window is open.
3656 * No need to exit to userspace if we already have an interrupt queued.
3658 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3660 return kvm_arch_interrupt_allowed(vcpu) &&
3661 !kvm_cpu_has_interrupt(vcpu) &&
3662 !kvm_event_needs_reinjection(vcpu) &&
3663 kvm_cpu_accept_dm_intr(vcpu);
3666 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3667 struct kvm_interrupt *irq)
3669 if (irq->irq >= KVM_NR_INTERRUPTS)
3672 if (!irqchip_in_kernel(vcpu->kvm)) {
3673 kvm_queue_interrupt(vcpu, irq->irq, false);
3674 kvm_make_request(KVM_REQ_EVENT, vcpu);
3679 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3680 * fail for in-kernel 8259.
3682 if (pic_in_kernel(vcpu->kvm))
3685 if (vcpu->arch.pending_external_vector != -1)
3688 vcpu->arch.pending_external_vector = irq->irq;
3689 kvm_make_request(KVM_REQ_EVENT, vcpu);
3693 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3695 kvm_inject_nmi(vcpu);
3700 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3702 kvm_make_request(KVM_REQ_SMI, vcpu);
3707 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3708 struct kvm_tpr_access_ctl *tac)
3712 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3716 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3720 unsigned bank_num = mcg_cap & 0xff, bank;
3723 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3725 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3728 vcpu->arch.mcg_cap = mcg_cap;
3729 /* Init IA32_MCG_CTL to all 1s */
3730 if (mcg_cap & MCG_CTL_P)
3731 vcpu->arch.mcg_ctl = ~(u64)0;
3732 /* Init IA32_MCi_CTL to all 1s */
3733 for (bank = 0; bank < bank_num; bank++)
3734 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3736 kvm_x86_ops->setup_mce(vcpu);
3741 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3742 struct kvm_x86_mce *mce)
3744 u64 mcg_cap = vcpu->arch.mcg_cap;
3745 unsigned bank_num = mcg_cap & 0xff;
3746 u64 *banks = vcpu->arch.mce_banks;
3748 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3751 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3752 * reporting is disabled
3754 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3755 vcpu->arch.mcg_ctl != ~(u64)0)
3757 banks += 4 * mce->bank;
3759 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3760 * reporting is disabled for the bank
3762 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3764 if (mce->status & MCI_STATUS_UC) {
3765 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3766 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3767 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3770 if (banks[1] & MCI_STATUS_VAL)
3771 mce->status |= MCI_STATUS_OVER;
3772 banks[2] = mce->addr;
3773 banks[3] = mce->misc;
3774 vcpu->arch.mcg_status = mce->mcg_status;
3775 banks[1] = mce->status;
3776 kvm_queue_exception(vcpu, MC_VECTOR);
3777 } else if (!(banks[1] & MCI_STATUS_VAL)
3778 || !(banks[1] & MCI_STATUS_UC)) {
3779 if (banks[1] & MCI_STATUS_VAL)
3780 mce->status |= MCI_STATUS_OVER;
3781 banks[2] = mce->addr;
3782 banks[3] = mce->misc;
3783 banks[1] = mce->status;
3785 banks[1] |= MCI_STATUS_OVER;
3789 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3790 struct kvm_vcpu_events *events)
3795 * In guest mode, payload delivery should be deferred,
3796 * so that the L1 hypervisor can intercept #PF before
3797 * CR2 is modified (or intercept #DB before DR6 is
3798 * modified under nVMX). Unless the per-VM capability,
3799 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3800 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3801 * opportunistically defer the exception payload, deliver it if the
3802 * capability hasn't been requested before processing a
3803 * KVM_GET_VCPU_EVENTS.
3805 if (!vcpu->kvm->arch.exception_payload_enabled &&
3806 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3807 kvm_deliver_exception_payload(vcpu);
3810 * The API doesn't provide the instruction length for software
3811 * exceptions, so don't report them. As long as the guest RIP
3812 * isn't advanced, we should expect to encounter the exception
3815 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3816 events->exception.injected = 0;
3817 events->exception.pending = 0;
3819 events->exception.injected = vcpu->arch.exception.injected;
3820 events->exception.pending = vcpu->arch.exception.pending;
3822 * For ABI compatibility, deliberately conflate
3823 * pending and injected exceptions when
3824 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3826 if (!vcpu->kvm->arch.exception_payload_enabled)
3827 events->exception.injected |=
3828 vcpu->arch.exception.pending;
3830 events->exception.nr = vcpu->arch.exception.nr;
3831 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3832 events->exception.error_code = vcpu->arch.exception.error_code;
3833 events->exception_has_payload = vcpu->arch.exception.has_payload;
3834 events->exception_payload = vcpu->arch.exception.payload;
3836 events->interrupt.injected =
3837 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3838 events->interrupt.nr = vcpu->arch.interrupt.nr;
3839 events->interrupt.soft = 0;
3840 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3842 events->nmi.injected = vcpu->arch.nmi_injected;
3843 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3844 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3845 events->nmi.pad = 0;
3847 events->sipi_vector = 0; /* never valid when reporting to user space */
3849 events->smi.smm = is_smm(vcpu);
3850 events->smi.pending = vcpu->arch.smi_pending;
3851 events->smi.smm_inside_nmi =
3852 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3853 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3855 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3856 | KVM_VCPUEVENT_VALID_SHADOW
3857 | KVM_VCPUEVENT_VALID_SMM);
3858 if (vcpu->kvm->arch.exception_payload_enabled)
3859 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3861 memset(&events->reserved, 0, sizeof(events->reserved));
3864 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3866 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3867 struct kvm_vcpu_events *events)
3869 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3870 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3871 | KVM_VCPUEVENT_VALID_SHADOW
3872 | KVM_VCPUEVENT_VALID_SMM
3873 | KVM_VCPUEVENT_VALID_PAYLOAD))
3876 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3877 if (!vcpu->kvm->arch.exception_payload_enabled)
3879 if (events->exception.pending)
3880 events->exception.injected = 0;
3882 events->exception_has_payload = 0;
3884 events->exception.pending = 0;
3885 events->exception_has_payload = 0;
3888 if ((events->exception.injected || events->exception.pending) &&
3889 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3892 /* INITs are latched while in SMM */
3893 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3894 (events->smi.smm || events->smi.pending) &&
3895 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3899 vcpu->arch.exception.injected = events->exception.injected;
3900 vcpu->arch.exception.pending = events->exception.pending;
3901 vcpu->arch.exception.nr = events->exception.nr;
3902 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3903 vcpu->arch.exception.error_code = events->exception.error_code;
3904 vcpu->arch.exception.has_payload = events->exception_has_payload;
3905 vcpu->arch.exception.payload = events->exception_payload;
3907 vcpu->arch.interrupt.injected = events->interrupt.injected;
3908 vcpu->arch.interrupt.nr = events->interrupt.nr;
3909 vcpu->arch.interrupt.soft = events->interrupt.soft;
3910 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3911 kvm_x86_ops->set_interrupt_shadow(vcpu,
3912 events->interrupt.shadow);
3914 vcpu->arch.nmi_injected = events->nmi.injected;
3915 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3916 vcpu->arch.nmi_pending = events->nmi.pending;
3917 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3919 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3920 lapic_in_kernel(vcpu))
3921 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3923 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3924 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3925 if (events->smi.smm)
3926 vcpu->arch.hflags |= HF_SMM_MASK;
3928 vcpu->arch.hflags &= ~HF_SMM_MASK;
3929 kvm_smm_changed(vcpu);
3932 vcpu->arch.smi_pending = events->smi.pending;
3934 if (events->smi.smm) {
3935 if (events->smi.smm_inside_nmi)
3936 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3938 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3941 if (lapic_in_kernel(vcpu)) {
3942 if (events->smi.latched_init)
3943 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3945 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3949 kvm_make_request(KVM_REQ_EVENT, vcpu);
3954 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3955 struct kvm_debugregs *dbgregs)
3959 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3960 kvm_get_dr(vcpu, 6, &val);
3962 dbgregs->dr7 = vcpu->arch.dr7;
3964 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3967 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3968 struct kvm_debugregs *dbgregs)
3973 if (dbgregs->dr6 & ~0xffffffffull)
3975 if (dbgregs->dr7 & ~0xffffffffull)
3978 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3979 kvm_update_dr0123(vcpu);
3980 vcpu->arch.dr6 = dbgregs->dr6;
3981 kvm_update_dr6(vcpu);
3982 vcpu->arch.dr7 = dbgregs->dr7;
3983 kvm_update_dr7(vcpu);
3988 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3990 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3992 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3993 u64 xstate_bv = xsave->header.xfeatures;
3997 * Copy legacy XSAVE area, to avoid complications with CPUID
3998 * leaves 0 and 1 in the loop below.
4000 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4003 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4004 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4007 * Copy each region from the possibly compacted offset to the
4008 * non-compacted offset.
4010 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4012 u64 xfeature_mask = valid & -valid;
4013 int xfeature_nr = fls64(xfeature_mask) - 1;
4014 void *src = get_xsave_addr(xsave, xfeature_nr);
4017 u32 size, offset, ecx, edx;
4018 cpuid_count(XSTATE_CPUID, xfeature_nr,
4019 &size, &offset, &ecx, &edx);
4020 if (xfeature_nr == XFEATURE_PKRU)
4021 memcpy(dest + offset, &vcpu->arch.pkru,
4022 sizeof(vcpu->arch.pkru));
4024 memcpy(dest + offset, src, size);
4028 valid -= xfeature_mask;
4032 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4034 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4035 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4039 * Copy legacy XSAVE area, to avoid complications with CPUID
4040 * leaves 0 and 1 in the loop below.
4042 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4044 /* Set XSTATE_BV and possibly XCOMP_BV. */
4045 xsave->header.xfeatures = xstate_bv;
4046 if (boot_cpu_has(X86_FEATURE_XSAVES))
4047 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4050 * Copy each region from the non-compacted offset to the
4051 * possibly compacted offset.
4053 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4055 u64 xfeature_mask = valid & -valid;
4056 int xfeature_nr = fls64(xfeature_mask) - 1;
4057 void *dest = get_xsave_addr(xsave, xfeature_nr);
4060 u32 size, offset, ecx, edx;
4061 cpuid_count(XSTATE_CPUID, xfeature_nr,
4062 &size, &offset, &ecx, &edx);
4063 if (xfeature_nr == XFEATURE_PKRU)
4064 memcpy(&vcpu->arch.pkru, src + offset,
4065 sizeof(vcpu->arch.pkru));
4067 memcpy(dest, src + offset, size);
4070 valid -= xfeature_mask;
4074 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4075 struct kvm_xsave *guest_xsave)
4077 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4078 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4079 fill_xsave((u8 *) guest_xsave->region, vcpu);
4081 memcpy(guest_xsave->region,
4082 &vcpu->arch.guest_fpu->state.fxsave,
4083 sizeof(struct fxregs_state));
4084 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4085 XFEATURE_MASK_FPSSE;
4089 #define XSAVE_MXCSR_OFFSET 24
4091 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4092 struct kvm_xsave *guest_xsave)
4095 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4096 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4098 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4100 * Here we allow setting states that are not present in
4101 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4102 * with old userspace.
4104 if (xstate_bv & ~kvm_supported_xcr0() ||
4105 mxcsr & ~mxcsr_feature_mask)
4107 load_xsave(vcpu, (u8 *)guest_xsave->region);
4109 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4110 mxcsr & ~mxcsr_feature_mask)
4112 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4113 guest_xsave->region, sizeof(struct fxregs_state));
4118 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4119 struct kvm_xcrs *guest_xcrs)
4121 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4122 guest_xcrs->nr_xcrs = 0;
4126 guest_xcrs->nr_xcrs = 1;
4127 guest_xcrs->flags = 0;
4128 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4129 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4132 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4133 struct kvm_xcrs *guest_xcrs)
4137 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4140 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4143 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4144 /* Only support XCR0 currently */
4145 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4146 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4147 guest_xcrs->xcrs[i].value);
4156 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4157 * stopped by the hypervisor. This function will be called from the host only.
4158 * EINVAL is returned when the host attempts to set the flag for a guest that
4159 * does not support pv clocks.
4161 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4163 if (!vcpu->arch.pv_time_enabled)
4165 vcpu->arch.pvclock_set_guest_stopped_request = true;
4166 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4170 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4171 struct kvm_enable_cap *cap)
4174 uint16_t vmcs_version;
4175 void __user *user_ptr;
4181 case KVM_CAP_HYPERV_SYNIC2:
4186 case KVM_CAP_HYPERV_SYNIC:
4187 if (!irqchip_in_kernel(vcpu->kvm))
4189 return kvm_hv_activate_synic(vcpu, cap->cap ==
4190 KVM_CAP_HYPERV_SYNIC2);
4191 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4192 if (!kvm_x86_ops->nested_enable_evmcs)
4194 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4196 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4197 if (copy_to_user(user_ptr, &vmcs_version,
4198 sizeof(vmcs_version)))
4202 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4203 if (!kvm_x86_ops->enable_direct_tlbflush)
4206 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4213 long kvm_arch_vcpu_ioctl(struct file *filp,
4214 unsigned int ioctl, unsigned long arg)
4216 struct kvm_vcpu *vcpu = filp->private_data;
4217 void __user *argp = (void __user *)arg;
4220 struct kvm_lapic_state *lapic;
4221 struct kvm_xsave *xsave;
4222 struct kvm_xcrs *xcrs;
4230 case KVM_GET_LAPIC: {
4232 if (!lapic_in_kernel(vcpu))
4234 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4235 GFP_KERNEL_ACCOUNT);
4240 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4244 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4249 case KVM_SET_LAPIC: {
4251 if (!lapic_in_kernel(vcpu))
4253 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4254 if (IS_ERR(u.lapic)) {
4255 r = PTR_ERR(u.lapic);
4259 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4262 case KVM_INTERRUPT: {
4263 struct kvm_interrupt irq;
4266 if (copy_from_user(&irq, argp, sizeof(irq)))
4268 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4272 r = kvm_vcpu_ioctl_nmi(vcpu);
4276 r = kvm_vcpu_ioctl_smi(vcpu);
4279 case KVM_SET_CPUID: {
4280 struct kvm_cpuid __user *cpuid_arg = argp;
4281 struct kvm_cpuid cpuid;
4284 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4286 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4289 case KVM_SET_CPUID2: {
4290 struct kvm_cpuid2 __user *cpuid_arg = argp;
4291 struct kvm_cpuid2 cpuid;
4294 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4296 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4297 cpuid_arg->entries);
4300 case KVM_GET_CPUID2: {
4301 struct kvm_cpuid2 __user *cpuid_arg = argp;
4302 struct kvm_cpuid2 cpuid;
4305 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4307 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4308 cpuid_arg->entries);
4312 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4317 case KVM_GET_MSRS: {
4318 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4319 r = msr_io(vcpu, argp, do_get_msr, 1);
4320 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4323 case KVM_SET_MSRS: {
4324 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4325 r = msr_io(vcpu, argp, do_set_msr, 0);
4326 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4329 case KVM_TPR_ACCESS_REPORTING: {
4330 struct kvm_tpr_access_ctl tac;
4333 if (copy_from_user(&tac, argp, sizeof(tac)))
4335 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4339 if (copy_to_user(argp, &tac, sizeof(tac)))
4344 case KVM_SET_VAPIC_ADDR: {
4345 struct kvm_vapic_addr va;
4349 if (!lapic_in_kernel(vcpu))
4352 if (copy_from_user(&va, argp, sizeof(va)))
4354 idx = srcu_read_lock(&vcpu->kvm->srcu);
4355 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4356 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4359 case KVM_X86_SETUP_MCE: {
4363 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4365 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4368 case KVM_X86_SET_MCE: {
4369 struct kvm_x86_mce mce;
4372 if (copy_from_user(&mce, argp, sizeof(mce)))
4374 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4377 case KVM_GET_VCPU_EVENTS: {
4378 struct kvm_vcpu_events events;
4380 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4383 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4388 case KVM_SET_VCPU_EVENTS: {
4389 struct kvm_vcpu_events events;
4392 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4395 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4398 case KVM_GET_DEBUGREGS: {
4399 struct kvm_debugregs dbgregs;
4401 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4404 if (copy_to_user(argp, &dbgregs,
4405 sizeof(struct kvm_debugregs)))
4410 case KVM_SET_DEBUGREGS: {
4411 struct kvm_debugregs dbgregs;
4414 if (copy_from_user(&dbgregs, argp,
4415 sizeof(struct kvm_debugregs)))
4418 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4421 case KVM_GET_XSAVE: {
4422 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4427 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4430 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4435 case KVM_SET_XSAVE: {
4436 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4437 if (IS_ERR(u.xsave)) {
4438 r = PTR_ERR(u.xsave);
4442 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4445 case KVM_GET_XCRS: {
4446 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4451 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4454 if (copy_to_user(argp, u.xcrs,
4455 sizeof(struct kvm_xcrs)))
4460 case KVM_SET_XCRS: {
4461 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4462 if (IS_ERR(u.xcrs)) {
4463 r = PTR_ERR(u.xcrs);
4467 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4470 case KVM_SET_TSC_KHZ: {
4474 user_tsc_khz = (u32)arg;
4476 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4479 if (user_tsc_khz == 0)
4480 user_tsc_khz = tsc_khz;
4482 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4487 case KVM_GET_TSC_KHZ: {
4488 r = vcpu->arch.virtual_tsc_khz;
4491 case KVM_KVMCLOCK_CTRL: {
4492 r = kvm_set_guest_paused(vcpu);
4495 case KVM_ENABLE_CAP: {
4496 struct kvm_enable_cap cap;
4499 if (copy_from_user(&cap, argp, sizeof(cap)))
4501 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4504 case KVM_GET_NESTED_STATE: {
4505 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4509 if (!kvm_x86_ops->get_nested_state)
4512 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4514 if (get_user(user_data_size, &user_kvm_nested_state->size))
4517 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4522 if (r > user_data_size) {
4523 if (put_user(r, &user_kvm_nested_state->size))
4533 case KVM_SET_NESTED_STATE: {
4534 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4535 struct kvm_nested_state kvm_state;
4539 if (!kvm_x86_ops->set_nested_state)
4543 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4547 if (kvm_state.size < sizeof(kvm_state))
4550 if (kvm_state.flags &
4551 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4552 | KVM_STATE_NESTED_EVMCS))
4555 /* nested_run_pending implies guest_mode. */
4556 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4557 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4560 idx = srcu_read_lock(&vcpu->kvm->srcu);
4561 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4562 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4565 case KVM_GET_SUPPORTED_HV_CPUID: {
4566 struct kvm_cpuid2 __user *cpuid_arg = argp;
4567 struct kvm_cpuid2 cpuid;
4570 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4573 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4574 cpuid_arg->entries);
4579 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4594 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4596 return VM_FAULT_SIGBUS;
4599 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4603 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4605 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4609 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4612 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4615 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4616 unsigned long kvm_nr_mmu_pages)
4618 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4621 mutex_lock(&kvm->slots_lock);
4623 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4624 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4626 mutex_unlock(&kvm->slots_lock);
4630 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4632 return kvm->arch.n_max_mmu_pages;
4635 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4637 struct kvm_pic *pic = kvm->arch.vpic;
4641 switch (chip->chip_id) {
4642 case KVM_IRQCHIP_PIC_MASTER:
4643 memcpy(&chip->chip.pic, &pic->pics[0],
4644 sizeof(struct kvm_pic_state));
4646 case KVM_IRQCHIP_PIC_SLAVE:
4647 memcpy(&chip->chip.pic, &pic->pics[1],
4648 sizeof(struct kvm_pic_state));
4650 case KVM_IRQCHIP_IOAPIC:
4651 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4660 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4662 struct kvm_pic *pic = kvm->arch.vpic;
4666 switch (chip->chip_id) {
4667 case KVM_IRQCHIP_PIC_MASTER:
4668 spin_lock(&pic->lock);
4669 memcpy(&pic->pics[0], &chip->chip.pic,
4670 sizeof(struct kvm_pic_state));
4671 spin_unlock(&pic->lock);
4673 case KVM_IRQCHIP_PIC_SLAVE:
4674 spin_lock(&pic->lock);
4675 memcpy(&pic->pics[1], &chip->chip.pic,
4676 sizeof(struct kvm_pic_state));
4677 spin_unlock(&pic->lock);
4679 case KVM_IRQCHIP_IOAPIC:
4680 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4686 kvm_pic_update_irq(pic);
4690 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4692 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4694 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4696 mutex_lock(&kps->lock);
4697 memcpy(ps, &kps->channels, sizeof(*ps));
4698 mutex_unlock(&kps->lock);
4702 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4705 struct kvm_pit *pit = kvm->arch.vpit;
4707 mutex_lock(&pit->pit_state.lock);
4708 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4709 for (i = 0; i < 3; i++)
4710 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4711 mutex_unlock(&pit->pit_state.lock);
4715 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4717 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4718 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4719 sizeof(ps->channels));
4720 ps->flags = kvm->arch.vpit->pit_state.flags;
4721 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4722 memset(&ps->reserved, 0, sizeof(ps->reserved));
4726 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4730 u32 prev_legacy, cur_legacy;
4731 struct kvm_pit *pit = kvm->arch.vpit;
4733 mutex_lock(&pit->pit_state.lock);
4734 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4735 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4736 if (!prev_legacy && cur_legacy)
4738 memcpy(&pit->pit_state.channels, &ps->channels,
4739 sizeof(pit->pit_state.channels));
4740 pit->pit_state.flags = ps->flags;
4741 for (i = 0; i < 3; i++)
4742 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4744 mutex_unlock(&pit->pit_state.lock);
4748 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4749 struct kvm_reinject_control *control)
4751 struct kvm_pit *pit = kvm->arch.vpit;
4753 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4754 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4755 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4757 mutex_lock(&pit->pit_state.lock);
4758 kvm_pit_set_reinject(pit, control->pit_reinject);
4759 mutex_unlock(&pit->pit_state.lock);
4765 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4766 * @kvm: kvm instance
4767 * @log: slot id and address to which we copy the log
4769 * Steps 1-4 below provide general overview of dirty page logging. See
4770 * kvm_get_dirty_log_protect() function description for additional details.
4772 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4773 * always flush the TLB (step 4) even if previous step failed and the dirty
4774 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4775 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4776 * writes will be marked dirty for next log read.
4778 * 1. Take a snapshot of the bit and clear it if needed.
4779 * 2. Write protect the corresponding page.
4780 * 3. Copy the snapshot to the userspace.
4781 * 4. Flush TLB's if needed.
4783 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4788 mutex_lock(&kvm->slots_lock);
4791 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4793 if (kvm_x86_ops->flush_log_dirty)
4794 kvm_x86_ops->flush_log_dirty(kvm);
4796 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4799 * All the TLBs can be flushed out of mmu lock, see the comments in
4800 * kvm_mmu_slot_remove_write_access().
4802 lockdep_assert_held(&kvm->slots_lock);
4804 kvm_flush_remote_tlbs(kvm);
4806 mutex_unlock(&kvm->slots_lock);
4810 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4815 mutex_lock(&kvm->slots_lock);
4818 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4820 if (kvm_x86_ops->flush_log_dirty)
4821 kvm_x86_ops->flush_log_dirty(kvm);
4823 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4826 * All the TLBs can be flushed out of mmu lock, see the comments in
4827 * kvm_mmu_slot_remove_write_access().
4829 lockdep_assert_held(&kvm->slots_lock);
4831 kvm_flush_remote_tlbs(kvm);
4833 mutex_unlock(&kvm->slots_lock);
4837 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4840 if (!irqchip_in_kernel(kvm))
4843 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4844 irq_event->irq, irq_event->level,
4849 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4850 struct kvm_enable_cap *cap)
4858 case KVM_CAP_DISABLE_QUIRKS:
4859 kvm->arch.disabled_quirks = cap->args[0];
4862 case KVM_CAP_SPLIT_IRQCHIP: {
4863 mutex_lock(&kvm->lock);
4865 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4866 goto split_irqchip_unlock;
4868 if (irqchip_in_kernel(kvm))
4869 goto split_irqchip_unlock;
4870 if (kvm->created_vcpus)
4871 goto split_irqchip_unlock;
4872 r = kvm_setup_empty_irq_routing(kvm);
4874 goto split_irqchip_unlock;
4875 /* Pairs with irqchip_in_kernel. */
4877 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4878 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4880 split_irqchip_unlock:
4881 mutex_unlock(&kvm->lock);
4884 case KVM_CAP_X2APIC_API:
4886 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4889 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4890 kvm->arch.x2apic_format = true;
4891 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4892 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4896 case KVM_CAP_X86_DISABLE_EXITS:
4898 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4901 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4902 kvm_can_mwait_in_guest())
4903 kvm->arch.mwait_in_guest = true;
4904 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4905 kvm->arch.hlt_in_guest = true;
4906 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4907 kvm->arch.pause_in_guest = true;
4908 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4909 kvm->arch.cstate_in_guest = true;
4912 case KVM_CAP_MSR_PLATFORM_INFO:
4913 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4916 case KVM_CAP_EXCEPTION_PAYLOAD:
4917 kvm->arch.exception_payload_enabled = cap->args[0];
4927 long kvm_arch_vm_ioctl(struct file *filp,
4928 unsigned int ioctl, unsigned long arg)
4930 struct kvm *kvm = filp->private_data;
4931 void __user *argp = (void __user *)arg;
4934 * This union makes it completely explicit to gcc-3.x
4935 * that these two variables' stack usage should be
4936 * combined, not added together.
4939 struct kvm_pit_state ps;
4940 struct kvm_pit_state2 ps2;
4941 struct kvm_pit_config pit_config;
4945 case KVM_SET_TSS_ADDR:
4946 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4948 case KVM_SET_IDENTITY_MAP_ADDR: {
4951 mutex_lock(&kvm->lock);
4953 if (kvm->created_vcpus)
4954 goto set_identity_unlock;
4956 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4957 goto set_identity_unlock;
4958 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4959 set_identity_unlock:
4960 mutex_unlock(&kvm->lock);
4963 case KVM_SET_NR_MMU_PAGES:
4964 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4966 case KVM_GET_NR_MMU_PAGES:
4967 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4969 case KVM_CREATE_IRQCHIP: {
4970 mutex_lock(&kvm->lock);
4973 if (irqchip_in_kernel(kvm))
4974 goto create_irqchip_unlock;
4977 if (kvm->created_vcpus)
4978 goto create_irqchip_unlock;
4980 r = kvm_pic_init(kvm);
4982 goto create_irqchip_unlock;
4984 r = kvm_ioapic_init(kvm);
4986 kvm_pic_destroy(kvm);
4987 goto create_irqchip_unlock;
4990 r = kvm_setup_default_irq_routing(kvm);
4992 kvm_ioapic_destroy(kvm);
4993 kvm_pic_destroy(kvm);
4994 goto create_irqchip_unlock;
4996 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4998 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4999 create_irqchip_unlock:
5000 mutex_unlock(&kvm->lock);
5003 case KVM_CREATE_PIT:
5004 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5006 case KVM_CREATE_PIT2:
5008 if (copy_from_user(&u.pit_config, argp,
5009 sizeof(struct kvm_pit_config)))
5012 mutex_lock(&kvm->lock);
5015 goto create_pit_unlock;
5017 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5021 mutex_unlock(&kvm->lock);
5023 case KVM_GET_IRQCHIP: {
5024 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5025 struct kvm_irqchip *chip;
5027 chip = memdup_user(argp, sizeof(*chip));
5034 if (!irqchip_kernel(kvm))
5035 goto get_irqchip_out;
5036 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5038 goto get_irqchip_out;
5040 if (copy_to_user(argp, chip, sizeof(*chip)))
5041 goto get_irqchip_out;
5047 case KVM_SET_IRQCHIP: {
5048 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5049 struct kvm_irqchip *chip;
5051 chip = memdup_user(argp, sizeof(*chip));
5058 if (!irqchip_kernel(kvm))
5059 goto set_irqchip_out;
5060 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5067 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5070 if (!kvm->arch.vpit)
5072 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5076 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5083 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5086 if (!kvm->arch.vpit)
5088 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5091 case KVM_GET_PIT2: {
5093 if (!kvm->arch.vpit)
5095 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5099 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5104 case KVM_SET_PIT2: {
5106 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5109 if (!kvm->arch.vpit)
5111 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5114 case KVM_REINJECT_CONTROL: {
5115 struct kvm_reinject_control control;
5117 if (copy_from_user(&control, argp, sizeof(control)))
5120 if (!kvm->arch.vpit)
5122 r = kvm_vm_ioctl_reinject(kvm, &control);
5125 case KVM_SET_BOOT_CPU_ID:
5127 mutex_lock(&kvm->lock);
5128 if (kvm->created_vcpus)
5131 kvm->arch.bsp_vcpu_id = arg;
5132 mutex_unlock(&kvm->lock);
5134 case KVM_XEN_HVM_CONFIG: {
5135 struct kvm_xen_hvm_config xhc;
5137 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5142 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5146 case KVM_SET_CLOCK: {
5147 struct kvm_clock_data user_ns;
5151 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5160 * TODO: userspace has to take care of races with VCPU_RUN, so
5161 * kvm_gen_update_masterclock() can be cut down to locked
5162 * pvclock_update_vm_gtod_copy().
5164 kvm_gen_update_masterclock(kvm);
5165 now_ns = get_kvmclock_ns(kvm);
5166 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5167 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5170 case KVM_GET_CLOCK: {
5171 struct kvm_clock_data user_ns;
5174 now_ns = get_kvmclock_ns(kvm);
5175 user_ns.clock = now_ns;
5176 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5177 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5180 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5185 case KVM_MEMORY_ENCRYPT_OP: {
5187 if (kvm_x86_ops->mem_enc_op)
5188 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5191 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5192 struct kvm_enc_region region;
5195 if (copy_from_user(®ion, argp, sizeof(region)))
5199 if (kvm_x86_ops->mem_enc_reg_region)
5200 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
5203 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5204 struct kvm_enc_region region;
5207 if (copy_from_user(®ion, argp, sizeof(region)))
5211 if (kvm_x86_ops->mem_enc_unreg_region)
5212 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
5215 case KVM_HYPERV_EVENTFD: {
5216 struct kvm_hyperv_eventfd hvevfd;
5219 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5221 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5224 case KVM_SET_PMU_EVENT_FILTER:
5225 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5234 static void kvm_init_msr_list(void)
5236 struct x86_pmu_capability x86_pmu;
5240 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5241 "Please update the fixed PMCs in msrs_to_saved_all[]");
5243 perf_get_x86_pmu_capability(&x86_pmu);
5245 num_msrs_to_save = 0;
5246 num_emulated_msrs = 0;
5247 num_msr_based_features = 0;
5249 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5250 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5254 * Even MSRs that are valid in the host may not be exposed
5255 * to the guests in some cases.
5257 switch (msrs_to_save_all[i]) {
5258 case MSR_IA32_BNDCFGS:
5259 if (!kvm_mpx_supported())
5263 if (!kvm_x86_ops->rdtscp_supported())
5266 case MSR_IA32_RTIT_CTL:
5267 case MSR_IA32_RTIT_STATUS:
5268 if (!kvm_x86_ops->pt_supported())
5271 case MSR_IA32_RTIT_CR3_MATCH:
5272 if (!kvm_x86_ops->pt_supported() ||
5273 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5276 case MSR_IA32_RTIT_OUTPUT_BASE:
5277 case MSR_IA32_RTIT_OUTPUT_MASK:
5278 if (!kvm_x86_ops->pt_supported() ||
5279 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5280 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5283 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5284 if (!kvm_x86_ops->pt_supported() ||
5285 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5286 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5289 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5290 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5291 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5294 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5295 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5296 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5303 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5306 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5307 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
5310 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5313 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5314 struct kvm_msr_entry msr;
5316 msr.index = msr_based_features_all[i];
5317 if (kvm_get_msr_feature(&msr))
5320 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5324 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5332 if (!(lapic_in_kernel(vcpu) &&
5333 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5334 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5345 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5352 if (!(lapic_in_kernel(vcpu) &&
5353 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5355 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5357 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5367 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5368 struct kvm_segment *var, int seg)
5370 kvm_x86_ops->set_segment(vcpu, var, seg);
5373 void kvm_get_segment(struct kvm_vcpu *vcpu,
5374 struct kvm_segment *var, int seg)
5376 kvm_x86_ops->get_segment(vcpu, var, seg);
5379 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5380 struct x86_exception *exception)
5384 BUG_ON(!mmu_is_nested(vcpu));
5386 /* NPT walks are always user-walks */
5387 access |= PFERR_USER_MASK;
5388 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5393 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5394 struct x86_exception *exception)
5396 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5397 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5400 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5401 struct x86_exception *exception)
5403 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5404 access |= PFERR_FETCH_MASK;
5405 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5408 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5409 struct x86_exception *exception)
5411 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5412 access |= PFERR_WRITE_MASK;
5413 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5416 /* uses this to access any guest's mapped memory without checking CPL */
5417 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5418 struct x86_exception *exception)
5420 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5423 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5424 struct kvm_vcpu *vcpu, u32 access,
5425 struct x86_exception *exception)
5428 int r = X86EMUL_CONTINUE;
5431 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5433 unsigned offset = addr & (PAGE_SIZE-1);
5434 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5437 if (gpa == UNMAPPED_GVA)
5438 return X86EMUL_PROPAGATE_FAULT;
5439 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5442 r = X86EMUL_IO_NEEDED;
5454 /* used for instruction fetching */
5455 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5456 gva_t addr, void *val, unsigned int bytes,
5457 struct x86_exception *exception)
5459 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5460 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5464 /* Inline kvm_read_guest_virt_helper for speed. */
5465 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5467 if (unlikely(gpa == UNMAPPED_GVA))
5468 return X86EMUL_PROPAGATE_FAULT;
5470 offset = addr & (PAGE_SIZE-1);
5471 if (WARN_ON(offset + bytes > PAGE_SIZE))
5472 bytes = (unsigned)PAGE_SIZE - offset;
5473 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5475 if (unlikely(ret < 0))
5476 return X86EMUL_IO_NEEDED;
5478 return X86EMUL_CONTINUE;
5481 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5482 gva_t addr, void *val, unsigned int bytes,
5483 struct x86_exception *exception)
5485 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5488 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5489 * is returned, but our callers are not ready for that and they blindly
5490 * call kvm_inject_page_fault. Ensure that they at least do not leak
5491 * uninitialized kernel stack memory into cr2 and error code.
5493 memset(exception, 0, sizeof(*exception));
5494 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5497 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5499 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5500 gva_t addr, void *val, unsigned int bytes,
5501 struct x86_exception *exception, bool system)
5503 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5506 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5507 access |= PFERR_USER_MASK;
5509 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5512 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5513 unsigned long addr, void *val, unsigned int bytes)
5515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5516 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5518 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5521 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5522 struct kvm_vcpu *vcpu, u32 access,
5523 struct x86_exception *exception)
5526 int r = X86EMUL_CONTINUE;
5529 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5532 unsigned offset = addr & (PAGE_SIZE-1);
5533 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5536 if (gpa == UNMAPPED_GVA)
5537 return X86EMUL_PROPAGATE_FAULT;
5538 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5540 r = X86EMUL_IO_NEEDED;
5552 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5553 unsigned int bytes, struct x86_exception *exception,
5556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5557 u32 access = PFERR_WRITE_MASK;
5559 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5560 access |= PFERR_USER_MASK;
5562 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5566 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5567 unsigned int bytes, struct x86_exception *exception)
5569 /* kvm_write_guest_virt_system can pull in tons of pages. */
5570 vcpu->arch.l1tf_flush_l1d = true;
5573 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5574 * is returned, but our callers are not ready for that and they blindly
5575 * call kvm_inject_page_fault. Ensure that they at least do not leak
5576 * uninitialized kernel stack memory into cr2 and error code.
5578 memset(exception, 0, sizeof(*exception));
5579 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5580 PFERR_WRITE_MASK, exception);
5582 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5584 int handle_ud(struct kvm_vcpu *vcpu)
5586 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5587 int emul_type = EMULTYPE_TRAP_UD;
5588 char sig[5]; /* ud2; .ascii "kvm" */
5589 struct x86_exception e;
5591 if (force_emulation_prefix &&
5592 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5593 sig, sizeof(sig), &e) == 0 &&
5594 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5595 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5596 emul_type = EMULTYPE_TRAP_UD_FORCED;
5599 return kvm_emulate_instruction(vcpu, emul_type);
5601 EXPORT_SYMBOL_GPL(handle_ud);
5603 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5604 gpa_t gpa, bool write)
5606 /* For APIC access vmexit */
5607 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5610 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5611 trace_vcpu_match_mmio(gva, gpa, write, true);
5618 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5619 gpa_t *gpa, struct x86_exception *exception,
5622 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5623 | (write ? PFERR_WRITE_MASK : 0);
5626 * currently PKRU is only applied to ept enabled guest so
5627 * there is no pkey in EPT page table for L1 guest or EPT
5628 * shadow page table for L2 guest.
5630 if (vcpu_match_mmio_gva(vcpu, gva)
5631 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5632 vcpu->arch.mmio_access, 0, access)) {
5633 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5634 (gva & (PAGE_SIZE - 1));
5635 trace_vcpu_match_mmio(gva, *gpa, write, false);
5639 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5641 if (*gpa == UNMAPPED_GVA)
5644 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5647 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5648 const void *val, int bytes)
5652 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5655 kvm_page_track_write(vcpu, gpa, val, bytes);
5659 struct read_write_emulator_ops {
5660 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5662 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5663 void *val, int bytes);
5664 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5665 int bytes, void *val);
5666 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5667 void *val, int bytes);
5671 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5673 if (vcpu->mmio_read_completed) {
5674 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5675 vcpu->mmio_fragments[0].gpa, val);
5676 vcpu->mmio_read_completed = 0;
5683 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5684 void *val, int bytes)
5686 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5689 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5690 void *val, int bytes)
5692 return emulator_write_phys(vcpu, gpa, val, bytes);
5695 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5697 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5698 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5701 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5702 void *val, int bytes)
5704 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5705 return X86EMUL_IO_NEEDED;
5708 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5709 void *val, int bytes)
5711 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5713 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5714 return X86EMUL_CONTINUE;
5717 static const struct read_write_emulator_ops read_emultor = {
5718 .read_write_prepare = read_prepare,
5719 .read_write_emulate = read_emulate,
5720 .read_write_mmio = vcpu_mmio_read,
5721 .read_write_exit_mmio = read_exit_mmio,
5724 static const struct read_write_emulator_ops write_emultor = {
5725 .read_write_emulate = write_emulate,
5726 .read_write_mmio = write_mmio,
5727 .read_write_exit_mmio = write_exit_mmio,
5731 static int emulator_read_write_onepage(unsigned long addr, void *val,
5733 struct x86_exception *exception,
5734 struct kvm_vcpu *vcpu,
5735 const struct read_write_emulator_ops *ops)
5739 bool write = ops->write;
5740 struct kvm_mmio_fragment *frag;
5741 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5744 * If the exit was due to a NPF we may already have a GPA.
5745 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5746 * Note, this cannot be used on string operations since string
5747 * operation using rep will only have the initial GPA from the NPF
5750 if (vcpu->arch.gpa_available &&
5751 emulator_can_use_gpa(ctxt) &&
5752 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5753 gpa = vcpu->arch.gpa_val;
5754 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5756 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5758 return X86EMUL_PROPAGATE_FAULT;
5761 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5762 return X86EMUL_CONTINUE;
5765 * Is this MMIO handled locally?
5767 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5768 if (handled == bytes)
5769 return X86EMUL_CONTINUE;
5775 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5776 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5780 return X86EMUL_CONTINUE;
5783 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5785 void *val, unsigned int bytes,
5786 struct x86_exception *exception,
5787 const struct read_write_emulator_ops *ops)
5789 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5793 if (ops->read_write_prepare &&
5794 ops->read_write_prepare(vcpu, val, bytes))
5795 return X86EMUL_CONTINUE;
5797 vcpu->mmio_nr_fragments = 0;
5799 /* Crossing a page boundary? */
5800 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5803 now = -addr & ~PAGE_MASK;
5804 rc = emulator_read_write_onepage(addr, val, now, exception,
5807 if (rc != X86EMUL_CONTINUE)
5810 if (ctxt->mode != X86EMUL_MODE_PROT64)
5816 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5818 if (rc != X86EMUL_CONTINUE)
5821 if (!vcpu->mmio_nr_fragments)
5824 gpa = vcpu->mmio_fragments[0].gpa;
5826 vcpu->mmio_needed = 1;
5827 vcpu->mmio_cur_fragment = 0;
5829 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5830 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5831 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5832 vcpu->run->mmio.phys_addr = gpa;
5834 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5837 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5841 struct x86_exception *exception)
5843 return emulator_read_write(ctxt, addr, val, bytes,
5844 exception, &read_emultor);
5847 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5851 struct x86_exception *exception)
5853 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5854 exception, &write_emultor);
5857 #define CMPXCHG_TYPE(t, ptr, old, new) \
5858 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5860 #ifdef CONFIG_X86_64
5861 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5863 # define CMPXCHG64(ptr, old, new) \
5864 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5867 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5872 struct x86_exception *exception)
5874 struct kvm_host_map map;
5875 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5880 /* guests cmpxchg8b have to be emulated atomically */
5881 if (bytes > 8 || (bytes & (bytes - 1)))
5884 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5886 if (gpa == UNMAPPED_GVA ||
5887 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5890 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5893 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5896 kaddr = map.hva + offset_in_page(gpa);
5900 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5903 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5906 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5909 exchanged = CMPXCHG64(kaddr, old, new);
5915 kvm_vcpu_unmap(vcpu, &map, true);
5918 return X86EMUL_CMPXCHG_FAILED;
5920 kvm_page_track_write(vcpu, gpa, new, bytes);
5922 return X86EMUL_CONTINUE;
5925 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5927 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5930 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5934 for (i = 0; i < vcpu->arch.pio.count; i++) {
5935 if (vcpu->arch.pio.in)
5936 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5937 vcpu->arch.pio.size, pd);
5939 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5940 vcpu->arch.pio.port, vcpu->arch.pio.size,
5944 pd += vcpu->arch.pio.size;
5949 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5950 unsigned short port, void *val,
5951 unsigned int count, bool in)
5953 vcpu->arch.pio.port = port;
5954 vcpu->arch.pio.in = in;
5955 vcpu->arch.pio.count = count;
5956 vcpu->arch.pio.size = size;
5958 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5959 vcpu->arch.pio.count = 0;
5963 vcpu->run->exit_reason = KVM_EXIT_IO;
5964 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5965 vcpu->run->io.size = size;
5966 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5967 vcpu->run->io.count = count;
5968 vcpu->run->io.port = port;
5973 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5974 int size, unsigned short port, void *val,
5977 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5980 if (vcpu->arch.pio.count)
5983 memset(vcpu->arch.pio_data, 0, size * count);
5985 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5988 memcpy(val, vcpu->arch.pio_data, size * count);
5989 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5990 vcpu->arch.pio.count = 0;
5997 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5998 int size, unsigned short port,
5999 const void *val, unsigned int count)
6001 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6003 memcpy(vcpu->arch.pio_data, val, size * count);
6004 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6005 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6008 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6010 return kvm_x86_ops->get_segment_base(vcpu, seg);
6013 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6015 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6018 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6020 if (!need_emulate_wbinvd(vcpu))
6021 return X86EMUL_CONTINUE;
6023 if (kvm_x86_ops->has_wbinvd_exit()) {
6024 int cpu = get_cpu();
6026 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6027 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6028 wbinvd_ipi, NULL, 1);
6030 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6033 return X86EMUL_CONTINUE;
6036 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6038 kvm_emulate_wbinvd_noskip(vcpu);
6039 return kvm_skip_emulated_instruction(vcpu);
6041 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6045 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6047 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6050 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6051 unsigned long *dest)
6053 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6056 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6057 unsigned long value)
6060 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6063 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6065 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6068 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6070 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6071 unsigned long value;
6075 value = kvm_read_cr0(vcpu);
6078 value = vcpu->arch.cr2;
6081 value = kvm_read_cr3(vcpu);
6084 value = kvm_read_cr4(vcpu);
6087 value = kvm_get_cr8(vcpu);
6090 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6097 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6099 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6104 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6107 vcpu->arch.cr2 = val;
6110 res = kvm_set_cr3(vcpu, val);
6113 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6116 res = kvm_set_cr8(vcpu, val);
6119 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6126 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6128 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
6131 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6133 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
6136 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6138 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6141 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6143 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6146 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6148 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6151 static unsigned long emulator_get_cached_segment_base(
6152 struct x86_emulate_ctxt *ctxt, int seg)
6154 return get_segment_base(emul_to_vcpu(ctxt), seg);
6157 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6158 struct desc_struct *desc, u32 *base3,
6161 struct kvm_segment var;
6163 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6164 *selector = var.selector;
6167 memset(desc, 0, sizeof(*desc));
6175 set_desc_limit(desc, var.limit);
6176 set_desc_base(desc, (unsigned long)var.base);
6177 #ifdef CONFIG_X86_64
6179 *base3 = var.base >> 32;
6181 desc->type = var.type;
6183 desc->dpl = var.dpl;
6184 desc->p = var.present;
6185 desc->avl = var.avl;
6193 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6194 struct desc_struct *desc, u32 base3,
6197 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6198 struct kvm_segment var;
6200 var.selector = selector;
6201 var.base = get_desc_base(desc);
6202 #ifdef CONFIG_X86_64
6203 var.base |= ((u64)base3) << 32;
6205 var.limit = get_desc_limit(desc);
6207 var.limit = (var.limit << 12) | 0xfff;
6208 var.type = desc->type;
6209 var.dpl = desc->dpl;
6214 var.avl = desc->avl;
6215 var.present = desc->p;
6216 var.unusable = !var.present;
6219 kvm_set_segment(vcpu, &var, seg);
6223 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6224 u32 msr_index, u64 *pdata)
6226 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6229 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6230 u32 msr_index, u64 data)
6232 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6235 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6237 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6239 return vcpu->arch.smbase;
6242 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6246 vcpu->arch.smbase = smbase;
6249 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6252 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6255 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6256 u32 pmc, u64 *pdata)
6258 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6261 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6263 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6266 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6267 struct x86_instruction_info *info,
6268 enum x86_intercept_stage stage)
6270 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6273 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6274 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6276 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6279 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6281 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6284 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6286 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6289 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6291 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6294 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6296 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6299 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6301 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6304 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6306 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6309 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6311 return emul_to_vcpu(ctxt)->arch.hflags;
6314 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6316 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6319 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6320 const char *smstate)
6322 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6325 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6327 kvm_smm_changed(emul_to_vcpu(ctxt));
6330 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6332 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6335 static const struct x86_emulate_ops emulate_ops = {
6336 .read_gpr = emulator_read_gpr,
6337 .write_gpr = emulator_write_gpr,
6338 .read_std = emulator_read_std,
6339 .write_std = emulator_write_std,
6340 .read_phys = kvm_read_guest_phys_system,
6341 .fetch = kvm_fetch_guest_virt,
6342 .read_emulated = emulator_read_emulated,
6343 .write_emulated = emulator_write_emulated,
6344 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6345 .invlpg = emulator_invlpg,
6346 .pio_in_emulated = emulator_pio_in_emulated,
6347 .pio_out_emulated = emulator_pio_out_emulated,
6348 .get_segment = emulator_get_segment,
6349 .set_segment = emulator_set_segment,
6350 .get_cached_segment_base = emulator_get_cached_segment_base,
6351 .get_gdt = emulator_get_gdt,
6352 .get_idt = emulator_get_idt,
6353 .set_gdt = emulator_set_gdt,
6354 .set_idt = emulator_set_idt,
6355 .get_cr = emulator_get_cr,
6356 .set_cr = emulator_set_cr,
6357 .cpl = emulator_get_cpl,
6358 .get_dr = emulator_get_dr,
6359 .set_dr = emulator_set_dr,
6360 .get_smbase = emulator_get_smbase,
6361 .set_smbase = emulator_set_smbase,
6362 .set_msr = emulator_set_msr,
6363 .get_msr = emulator_get_msr,
6364 .check_pmc = emulator_check_pmc,
6365 .read_pmc = emulator_read_pmc,
6366 .halt = emulator_halt,
6367 .wbinvd = emulator_wbinvd,
6368 .fix_hypercall = emulator_fix_hypercall,
6369 .intercept = emulator_intercept,
6370 .get_cpuid = emulator_get_cpuid,
6371 .guest_has_long_mode = emulator_guest_has_long_mode,
6372 .guest_has_movbe = emulator_guest_has_movbe,
6373 .guest_has_fxsr = emulator_guest_has_fxsr,
6374 .set_nmi_mask = emulator_set_nmi_mask,
6375 .get_hflags = emulator_get_hflags,
6376 .set_hflags = emulator_set_hflags,
6377 .pre_leave_smm = emulator_pre_leave_smm,
6378 .post_leave_smm = emulator_post_leave_smm,
6379 .set_xcr = emulator_set_xcr,
6382 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6384 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6386 * an sti; sti; sequence only disable interrupts for the first
6387 * instruction. So, if the last instruction, be it emulated or
6388 * not, left the system with the INT_STI flag enabled, it
6389 * means that the last instruction is an sti. We should not
6390 * leave the flag on in this case. The same goes for mov ss
6392 if (int_shadow & mask)
6394 if (unlikely(int_shadow || mask)) {
6395 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6397 kvm_make_request(KVM_REQ_EVENT, vcpu);
6401 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6403 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6404 if (ctxt->exception.vector == PF_VECTOR)
6405 return kvm_propagate_fault(vcpu, &ctxt->exception);
6407 if (ctxt->exception.error_code_valid)
6408 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6409 ctxt->exception.error_code);
6411 kvm_queue_exception(vcpu, ctxt->exception.vector);
6415 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6417 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6420 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6422 ctxt->eflags = kvm_get_rflags(vcpu);
6423 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6425 ctxt->eip = kvm_rip_read(vcpu);
6426 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6427 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6428 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6429 cs_db ? X86EMUL_MODE_PROT32 :
6430 X86EMUL_MODE_PROT16;
6431 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6432 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6433 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6435 init_decode_cache(ctxt);
6436 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6439 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6441 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6444 init_emulate_ctxt(vcpu);
6448 ctxt->_eip = ctxt->eip + inc_eip;
6449 ret = emulate_int_real(ctxt, irq);
6451 if (ret != X86EMUL_CONTINUE) {
6452 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6454 ctxt->eip = ctxt->_eip;
6455 kvm_rip_write(vcpu, ctxt->eip);
6456 kvm_set_rflags(vcpu, ctxt->eflags);
6459 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6461 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6463 ++vcpu->stat.insn_emulation_fail;
6464 trace_kvm_emulate_insn_failed(vcpu);
6466 if (emulation_type & EMULTYPE_VMWARE_GP) {
6467 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6471 if (emulation_type & EMULTYPE_SKIP) {
6472 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6473 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6474 vcpu->run->internal.ndata = 0;
6478 kvm_queue_exception(vcpu, UD_VECTOR);
6480 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6481 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6482 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6483 vcpu->run->internal.ndata = 0;
6490 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6491 bool write_fault_to_shadow_pgtable,
6494 gpa_t gpa = cr2_or_gpa;
6497 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6500 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6503 if (!vcpu->arch.mmu->direct_map) {
6505 * Write permission should be allowed since only
6506 * write access need to be emulated.
6508 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6511 * If the mapping is invalid in guest, let cpu retry
6512 * it to generate fault.
6514 if (gpa == UNMAPPED_GVA)
6519 * Do not retry the unhandleable instruction if it faults on the
6520 * readonly host memory, otherwise it will goto a infinite loop:
6521 * retry instruction -> write #PF -> emulation fail -> retry
6522 * instruction -> ...
6524 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6527 * If the instruction failed on the error pfn, it can not be fixed,
6528 * report the error to userspace.
6530 if (is_error_noslot_pfn(pfn))
6533 kvm_release_pfn_clean(pfn);
6535 /* The instructions are well-emulated on direct mmu. */
6536 if (vcpu->arch.mmu->direct_map) {
6537 unsigned int indirect_shadow_pages;
6539 spin_lock(&vcpu->kvm->mmu_lock);
6540 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6541 spin_unlock(&vcpu->kvm->mmu_lock);
6543 if (indirect_shadow_pages)
6544 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6550 * if emulation was due to access to shadowed page table
6551 * and it failed try to unshadow page and re-enter the
6552 * guest to let CPU execute the instruction.
6554 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6557 * If the access faults on its page table, it can not
6558 * be fixed by unprotecting shadow page and it should
6559 * be reported to userspace.
6561 return !write_fault_to_shadow_pgtable;
6564 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6565 gpa_t cr2_or_gpa, int emulation_type)
6567 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6568 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6570 last_retry_eip = vcpu->arch.last_retry_eip;
6571 last_retry_addr = vcpu->arch.last_retry_addr;
6574 * If the emulation is caused by #PF and it is non-page_table
6575 * writing instruction, it means the VM-EXIT is caused by shadow
6576 * page protected, we can zap the shadow page and retry this
6577 * instruction directly.
6579 * Note: if the guest uses a non-page-table modifying instruction
6580 * on the PDE that points to the instruction, then we will unmap
6581 * the instruction and go to an infinite loop. So, we cache the
6582 * last retried eip and the last fault address, if we meet the eip
6583 * and the address again, we can break out of the potential infinite
6586 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6588 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6591 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6594 if (x86_page_table_writing_insn(ctxt))
6597 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6600 vcpu->arch.last_retry_eip = ctxt->eip;
6601 vcpu->arch.last_retry_addr = cr2_or_gpa;
6603 if (!vcpu->arch.mmu->direct_map)
6604 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6606 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6611 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6612 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6614 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6616 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6617 /* This is a good place to trace that we are exiting SMM. */
6618 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6620 /* Process a latched INIT or SMI, if any. */
6621 kvm_make_request(KVM_REQ_EVENT, vcpu);
6624 kvm_mmu_reset_context(vcpu);
6627 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6636 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6637 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6642 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6644 struct kvm_run *kvm_run = vcpu->run;
6646 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6647 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6648 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6649 kvm_run->debug.arch.exception = DB_VECTOR;
6650 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6653 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6657 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6659 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6662 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6667 * rflags is the old, "raw" value of the flags. The new value has
6668 * not been saved yet.
6670 * This is correct even for TF set by the guest, because "the
6671 * processor will not generate this exception after the instruction
6672 * that sets the TF flag".
6674 if (unlikely(rflags & X86_EFLAGS_TF))
6675 r = kvm_vcpu_do_singlestep(vcpu);
6678 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6680 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6682 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6683 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6684 struct kvm_run *kvm_run = vcpu->run;
6685 unsigned long eip = kvm_get_linear_rip(vcpu);
6686 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6687 vcpu->arch.guest_debug_dr7,
6691 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6692 kvm_run->debug.arch.pc = eip;
6693 kvm_run->debug.arch.exception = DB_VECTOR;
6694 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6700 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6701 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6702 unsigned long eip = kvm_get_linear_rip(vcpu);
6703 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6708 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6709 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6710 kvm_queue_exception(vcpu, DB_VECTOR);
6719 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6721 switch (ctxt->opcode_len) {
6728 case 0xe6: /* OUT */
6732 case 0x6c: /* INS */
6734 case 0x6e: /* OUTS */
6741 case 0x33: /* RDPMC */
6750 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6751 int emulation_type, void *insn, int insn_len)
6754 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6755 bool writeback = true;
6756 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6758 vcpu->arch.l1tf_flush_l1d = true;
6761 * Clear write_fault_to_shadow_pgtable here to ensure it is
6764 vcpu->arch.write_fault_to_shadow_pgtable = false;
6765 kvm_clear_exception_queue(vcpu);
6767 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6768 init_emulate_ctxt(vcpu);
6771 * We will reenter on the same instruction since
6772 * we do not set complete_userspace_io. This does not
6773 * handle watchpoints yet, those would be handled in
6776 if (!(emulation_type & EMULTYPE_SKIP) &&
6777 kvm_vcpu_check_breakpoint(vcpu, &r))
6780 ctxt->interruptibility = 0;
6781 ctxt->have_exception = false;
6782 ctxt->exception.vector = -1;
6783 ctxt->perm_ok = false;
6785 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6787 r = x86_decode_insn(ctxt, insn, insn_len);
6789 trace_kvm_emulate_insn_start(vcpu);
6790 ++vcpu->stat.insn_emulation;
6791 if (r != EMULATION_OK) {
6792 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6793 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6794 kvm_queue_exception(vcpu, UD_VECTOR);
6797 if (reexecute_instruction(vcpu, cr2_or_gpa,
6801 if (ctxt->have_exception) {
6803 * #UD should result in just EMULATION_FAILED, and trap-like
6804 * exception should not be encountered during decode.
6806 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6807 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6808 inject_emulated_exception(vcpu);
6811 return handle_emulation_failure(vcpu, emulation_type);
6815 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6816 !is_vmware_backdoor_opcode(ctxt)) {
6817 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6822 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6823 * for kvm_skip_emulated_instruction(). The caller is responsible for
6824 * updating interruptibility state and injecting single-step #DBs.
6826 if (emulation_type & EMULTYPE_SKIP) {
6827 kvm_rip_write(vcpu, ctxt->_eip);
6828 if (ctxt->eflags & X86_EFLAGS_RF)
6829 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6833 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6836 /* this is needed for vmware backdoor interface to work since it
6837 changes registers values during IO operation */
6838 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6839 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6840 emulator_invalidate_register_cache(ctxt);
6844 /* Save the faulting GPA (cr2) in the address field */
6845 ctxt->exception.address = cr2_or_gpa;
6847 r = x86_emulate_insn(ctxt);
6849 if (r == EMULATION_INTERCEPTED)
6852 if (r == EMULATION_FAILED) {
6853 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6857 return handle_emulation_failure(vcpu, emulation_type);
6860 if (ctxt->have_exception) {
6862 if (inject_emulated_exception(vcpu))
6864 } else if (vcpu->arch.pio.count) {
6865 if (!vcpu->arch.pio.in) {
6866 /* FIXME: return into emulator if single-stepping. */
6867 vcpu->arch.pio.count = 0;
6870 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6873 } else if (vcpu->mmio_needed) {
6874 ++vcpu->stat.mmio_exits;
6876 if (!vcpu->mmio_is_write)
6879 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6880 } else if (r == EMULATION_RESTART)
6886 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6887 toggle_interruptibility(vcpu, ctxt->interruptibility);
6888 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6889 if (!ctxt->have_exception ||
6890 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6891 kvm_rip_write(vcpu, ctxt->eip);
6893 r = kvm_vcpu_do_singlestep(vcpu);
6894 __kvm_set_rflags(vcpu, ctxt->eflags);
6898 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6899 * do nothing, and it will be requested again as soon as
6900 * the shadow expires. But we still need to check here,
6901 * because POPF has no interrupt shadow.
6903 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6904 kvm_make_request(KVM_REQ_EVENT, vcpu);
6906 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6911 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6913 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6915 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6917 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6918 void *insn, int insn_len)
6920 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6922 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6924 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6926 vcpu->arch.pio.count = 0;
6930 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6932 vcpu->arch.pio.count = 0;
6934 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6937 return kvm_skip_emulated_instruction(vcpu);
6940 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6941 unsigned short port)
6943 unsigned long val = kvm_rax_read(vcpu);
6944 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6945 size, port, &val, 1);
6950 * Workaround userspace that relies on old KVM behavior of %rip being
6951 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6954 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6955 vcpu->arch.complete_userspace_io =
6956 complete_fast_pio_out_port_0x7e;
6957 kvm_skip_emulated_instruction(vcpu);
6959 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6960 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6965 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6969 /* We should only ever be called with arch.pio.count equal to 1 */
6970 BUG_ON(vcpu->arch.pio.count != 1);
6972 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6973 vcpu->arch.pio.count = 0;
6977 /* For size less than 4 we merge, else we zero extend */
6978 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6981 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6982 * the copy and tracing
6984 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6985 vcpu->arch.pio.port, &val, 1);
6986 kvm_rax_write(vcpu, val);
6988 return kvm_skip_emulated_instruction(vcpu);
6991 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6992 unsigned short port)
6997 /* For size less than 4 we merge, else we zero extend */
6998 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7000 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
7003 kvm_rax_write(vcpu, val);
7007 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7008 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7013 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7018 ret = kvm_fast_pio_in(vcpu, size, port);
7020 ret = kvm_fast_pio_out(vcpu, size, port);
7021 return ret && kvm_skip_emulated_instruction(vcpu);
7023 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7025 static int kvmclock_cpu_down_prep(unsigned int cpu)
7027 __this_cpu_write(cpu_tsc_khz, 0);
7031 static void tsc_khz_changed(void *data)
7033 struct cpufreq_freqs *freq = data;
7034 unsigned long khz = 0;
7038 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7039 khz = cpufreq_quick_get(raw_smp_processor_id());
7042 __this_cpu_write(cpu_tsc_khz, khz);
7045 #ifdef CONFIG_X86_64
7046 static void kvm_hyperv_tsc_notifier(void)
7049 struct kvm_vcpu *vcpu;
7052 mutex_lock(&kvm_lock);
7053 list_for_each_entry(kvm, &vm_list, vm_list)
7054 kvm_make_mclock_inprogress_request(kvm);
7056 hyperv_stop_tsc_emulation();
7058 /* TSC frequency always matches when on Hyper-V */
7059 for_each_present_cpu(cpu)
7060 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7061 kvm_max_guest_tsc_khz = tsc_khz;
7063 list_for_each_entry(kvm, &vm_list, vm_list) {
7064 struct kvm_arch *ka = &kvm->arch;
7066 spin_lock(&ka->pvclock_gtod_sync_lock);
7068 pvclock_update_vm_gtod_copy(kvm);
7070 kvm_for_each_vcpu(cpu, vcpu, kvm)
7071 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7073 kvm_for_each_vcpu(cpu, vcpu, kvm)
7074 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7076 spin_unlock(&ka->pvclock_gtod_sync_lock);
7078 mutex_unlock(&kvm_lock);
7082 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7085 struct kvm_vcpu *vcpu;
7086 int i, send_ipi = 0;
7089 * We allow guests to temporarily run on slowing clocks,
7090 * provided we notify them after, or to run on accelerating
7091 * clocks, provided we notify them before. Thus time never
7094 * However, we have a problem. We can't atomically update
7095 * the frequency of a given CPU from this function; it is
7096 * merely a notifier, which can be called from any CPU.
7097 * Changing the TSC frequency at arbitrary points in time
7098 * requires a recomputation of local variables related to
7099 * the TSC for each VCPU. We must flag these local variables
7100 * to be updated and be sure the update takes place with the
7101 * new frequency before any guests proceed.
7103 * Unfortunately, the combination of hotplug CPU and frequency
7104 * change creates an intractable locking scenario; the order
7105 * of when these callouts happen is undefined with respect to
7106 * CPU hotplug, and they can race with each other. As such,
7107 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7108 * undefined; you can actually have a CPU frequency change take
7109 * place in between the computation of X and the setting of the
7110 * variable. To protect against this problem, all updates of
7111 * the per_cpu tsc_khz variable are done in an interrupt
7112 * protected IPI, and all callers wishing to update the value
7113 * must wait for a synchronous IPI to complete (which is trivial
7114 * if the caller is on the CPU already). This establishes the
7115 * necessary total order on variable updates.
7117 * Note that because a guest time update may take place
7118 * anytime after the setting of the VCPU's request bit, the
7119 * correct TSC value must be set before the request. However,
7120 * to ensure the update actually makes it to any guest which
7121 * starts running in hardware virtualization between the set
7122 * and the acquisition of the spinlock, we must also ping the
7123 * CPU after setting the request bit.
7127 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7129 mutex_lock(&kvm_lock);
7130 list_for_each_entry(kvm, &vm_list, vm_list) {
7131 kvm_for_each_vcpu(i, vcpu, kvm) {
7132 if (vcpu->cpu != cpu)
7134 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7135 if (vcpu->cpu != raw_smp_processor_id())
7139 mutex_unlock(&kvm_lock);
7141 if (freq->old < freq->new && send_ipi) {
7143 * We upscale the frequency. Must make the guest
7144 * doesn't see old kvmclock values while running with
7145 * the new frequency, otherwise we risk the guest sees
7146 * time go backwards.
7148 * In case we update the frequency for another cpu
7149 * (which might be in guest context) send an interrupt
7150 * to kick the cpu out of guest context. Next time
7151 * guest context is entered kvmclock will be updated,
7152 * so the guest will not see stale values.
7154 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7158 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7161 struct cpufreq_freqs *freq = data;
7164 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7166 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7169 for_each_cpu(cpu, freq->policy->cpus)
7170 __kvmclock_cpufreq_notifier(freq, cpu);
7175 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7176 .notifier_call = kvmclock_cpufreq_notifier
7179 static int kvmclock_cpu_online(unsigned int cpu)
7181 tsc_khz_changed(NULL);
7185 static void kvm_timer_init(void)
7187 max_tsc_khz = tsc_khz;
7189 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7190 #ifdef CONFIG_CPU_FREQ
7191 struct cpufreq_policy policy;
7194 memset(&policy, 0, sizeof(policy));
7196 cpufreq_get_policy(&policy, cpu);
7197 if (policy.cpuinfo.max_freq)
7198 max_tsc_khz = policy.cpuinfo.max_freq;
7201 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7202 CPUFREQ_TRANSITION_NOTIFIER);
7205 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7206 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7209 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7210 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7212 int kvm_is_in_guest(void)
7214 return __this_cpu_read(current_vcpu) != NULL;
7217 static int kvm_is_user_mode(void)
7221 if (__this_cpu_read(current_vcpu))
7222 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7224 return user_mode != 0;
7227 static unsigned long kvm_get_guest_ip(void)
7229 unsigned long ip = 0;
7231 if (__this_cpu_read(current_vcpu))
7232 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7237 static void kvm_handle_intel_pt_intr(void)
7239 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7241 kvm_make_request(KVM_REQ_PMI, vcpu);
7242 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7243 (unsigned long *)&vcpu->arch.pmu.global_status);
7246 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7247 .is_in_guest = kvm_is_in_guest,
7248 .is_user_mode = kvm_is_user_mode,
7249 .get_guest_ip = kvm_get_guest_ip,
7250 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7253 #ifdef CONFIG_X86_64
7254 static void pvclock_gtod_update_fn(struct work_struct *work)
7258 struct kvm_vcpu *vcpu;
7261 mutex_lock(&kvm_lock);
7262 list_for_each_entry(kvm, &vm_list, vm_list)
7263 kvm_for_each_vcpu(i, vcpu, kvm)
7264 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7265 atomic_set(&kvm_guest_has_master_clock, 0);
7266 mutex_unlock(&kvm_lock);
7269 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7272 * Notification about pvclock gtod data update.
7274 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7277 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7278 struct timekeeper *tk = priv;
7280 update_pvclock_gtod(tk);
7282 /* disable master clock if host does not trust, or does not
7283 * use, TSC based clocksource.
7285 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7286 atomic_read(&kvm_guest_has_master_clock) != 0)
7287 queue_work(system_long_wq, &pvclock_gtod_work);
7292 static struct notifier_block pvclock_gtod_notifier = {
7293 .notifier_call = pvclock_gtod_notify,
7297 int kvm_arch_init(void *opaque)
7300 struct kvm_x86_ops *ops = opaque;
7303 printk(KERN_ERR "kvm: already loaded the other module\n");
7308 if (!ops->cpu_has_kvm_support()) {
7309 printk(KERN_ERR "kvm: no hardware support\n");
7313 if (ops->disabled_by_bios()) {
7314 printk(KERN_ERR "kvm: disabled by bios\n");
7320 * KVM explicitly assumes that the guest has an FPU and
7321 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7322 * vCPU's FPU state as a fxregs_state struct.
7324 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7325 printk(KERN_ERR "kvm: inadequate fpu\n");
7331 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7332 __alignof__(struct fpu), SLAB_ACCOUNT,
7334 if (!x86_fpu_cache) {
7335 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7339 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7341 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7342 goto out_free_x86_fpu_cache;
7345 r = kvm_mmu_module_init();
7347 goto out_free_percpu;
7351 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7352 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7353 PT_PRESENT_MASK, 0, sme_me_mask);
7356 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7358 if (boot_cpu_has(X86_FEATURE_XSAVE))
7359 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7362 if (pi_inject_timer == -1)
7363 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7364 #ifdef CONFIG_X86_64
7365 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7367 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7368 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7374 free_percpu(shared_msrs);
7375 out_free_x86_fpu_cache:
7376 kmem_cache_destroy(x86_fpu_cache);
7381 void kvm_arch_exit(void)
7383 #ifdef CONFIG_X86_64
7384 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7385 clear_hv_tscchange_cb();
7388 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7390 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7391 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7392 CPUFREQ_TRANSITION_NOTIFIER);
7393 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7394 #ifdef CONFIG_X86_64
7395 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7398 kvm_mmu_module_exit();
7399 free_percpu(shared_msrs);
7400 kmem_cache_destroy(x86_fpu_cache);
7403 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7405 ++vcpu->stat.halt_exits;
7406 if (lapic_in_kernel(vcpu)) {
7407 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7410 vcpu->run->exit_reason = KVM_EXIT_HLT;
7414 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7416 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7418 int ret = kvm_skip_emulated_instruction(vcpu);
7420 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7421 * KVM_EXIT_DEBUG here.
7423 return kvm_vcpu_halt(vcpu) && ret;
7425 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7427 #ifdef CONFIG_X86_64
7428 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7429 unsigned long clock_type)
7431 struct kvm_clock_pairing clock_pairing;
7432 struct timespec64 ts;
7436 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7437 return -KVM_EOPNOTSUPP;
7439 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7440 return -KVM_EOPNOTSUPP;
7442 clock_pairing.sec = ts.tv_sec;
7443 clock_pairing.nsec = ts.tv_nsec;
7444 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7445 clock_pairing.flags = 0;
7446 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7449 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7450 sizeof(struct kvm_clock_pairing)))
7458 * kvm_pv_kick_cpu_op: Kick a vcpu.
7460 * @apicid - apicid of vcpu to be kicked.
7462 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7464 struct kvm_lapic_irq lapic_irq;
7466 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7467 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7468 lapic_irq.level = 0;
7469 lapic_irq.dest_id = apicid;
7470 lapic_irq.msi_redir_hint = false;
7472 lapic_irq.delivery_mode = APIC_DM_REMRD;
7473 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7476 bool kvm_apicv_activated(struct kvm *kvm)
7478 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7480 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7482 void kvm_apicv_init(struct kvm *kvm, bool enable)
7485 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7486 &kvm->arch.apicv_inhibit_reasons);
7488 set_bit(APICV_INHIBIT_REASON_DISABLE,
7489 &kvm->arch.apicv_inhibit_reasons);
7491 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7493 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7495 struct kvm_vcpu *target = NULL;
7496 struct kvm_apic_map *map;
7499 map = rcu_dereference(kvm->arch.apic_map);
7501 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7502 target = map->phys_map[dest_id]->vcpu;
7506 if (target && READ_ONCE(target->ready))
7507 kvm_vcpu_yield_to(target);
7510 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7512 unsigned long nr, a0, a1, a2, a3, ret;
7515 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7516 return kvm_hv_hypercall(vcpu);
7518 nr = kvm_rax_read(vcpu);
7519 a0 = kvm_rbx_read(vcpu);
7520 a1 = kvm_rcx_read(vcpu);
7521 a2 = kvm_rdx_read(vcpu);
7522 a3 = kvm_rsi_read(vcpu);
7524 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7526 op_64_bit = is_64_bit_mode(vcpu);
7535 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7541 case KVM_HC_VAPIC_POLL_IRQ:
7544 case KVM_HC_KICK_CPU:
7545 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7546 kvm_sched_yield(vcpu->kvm, a1);
7549 #ifdef CONFIG_X86_64
7550 case KVM_HC_CLOCK_PAIRING:
7551 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7554 case KVM_HC_SEND_IPI:
7555 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7557 case KVM_HC_SCHED_YIELD:
7558 kvm_sched_yield(vcpu->kvm, a0);
7568 kvm_rax_write(vcpu, ret);
7570 ++vcpu->stat.hypercalls;
7571 return kvm_skip_emulated_instruction(vcpu);
7573 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7575 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7577 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7578 char instruction[3];
7579 unsigned long rip = kvm_rip_read(vcpu);
7581 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7583 return emulator_write_emulated(ctxt, rip, instruction, 3,
7587 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7589 return vcpu->run->request_interrupt_window &&
7590 likely(!pic_in_kernel(vcpu->kvm));
7593 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7595 struct kvm_run *kvm_run = vcpu->run;
7597 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7598 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7599 kvm_run->cr8 = kvm_get_cr8(vcpu);
7600 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7601 kvm_run->ready_for_interrupt_injection =
7602 pic_in_kernel(vcpu->kvm) ||
7603 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7606 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7610 if (!kvm_x86_ops->update_cr8_intercept)
7613 if (!lapic_in_kernel(vcpu))
7616 if (vcpu->arch.apicv_active)
7619 if (!vcpu->arch.apic->vapic_addr)
7620 max_irr = kvm_lapic_find_highest_irr(vcpu);
7627 tpr = kvm_lapic_get_cr8(vcpu);
7629 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7632 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7636 /* try to reinject previous events if any */
7638 if (vcpu->arch.exception.injected)
7639 kvm_x86_ops->queue_exception(vcpu);
7641 * Do not inject an NMI or interrupt if there is a pending
7642 * exception. Exceptions and interrupts are recognized at
7643 * instruction boundaries, i.e. the start of an instruction.
7644 * Trap-like exceptions, e.g. #DB, have higher priority than
7645 * NMIs and interrupts, i.e. traps are recognized before an
7646 * NMI/interrupt that's pending on the same instruction.
7647 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7648 * priority, but are only generated (pended) during instruction
7649 * execution, i.e. a pending fault-like exception means the
7650 * fault occurred on the *previous* instruction and must be
7651 * serviced prior to recognizing any new events in order to
7652 * fully complete the previous instruction.
7654 else if (!vcpu->arch.exception.pending) {
7655 if (vcpu->arch.nmi_injected)
7656 kvm_x86_ops->set_nmi(vcpu);
7657 else if (vcpu->arch.interrupt.injected)
7658 kvm_x86_ops->set_irq(vcpu);
7662 * Call check_nested_events() even if we reinjected a previous event
7663 * in order for caller to determine if it should require immediate-exit
7664 * from L2 to L1 due to pending L1 events which require exit
7667 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7668 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7673 /* try to inject new event if pending */
7674 if (vcpu->arch.exception.pending) {
7675 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7676 vcpu->arch.exception.has_error_code,
7677 vcpu->arch.exception.error_code);
7679 WARN_ON_ONCE(vcpu->arch.exception.injected);
7680 vcpu->arch.exception.pending = false;
7681 vcpu->arch.exception.injected = true;
7683 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7684 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7687 if (vcpu->arch.exception.nr == DB_VECTOR) {
7689 * This code assumes that nSVM doesn't use
7690 * check_nested_events(). If it does, the
7691 * DR6/DR7 changes should happen before L1
7692 * gets a #VMEXIT for an intercepted #DB in
7693 * L2. (Under VMX, on the other hand, the
7694 * DR6/DR7 changes should not happen in the
7695 * event of a VM-exit to L1 for an intercepted
7698 kvm_deliver_exception_payload(vcpu);
7699 if (vcpu->arch.dr7 & DR7_GD) {
7700 vcpu->arch.dr7 &= ~DR7_GD;
7701 kvm_update_dr7(vcpu);
7705 kvm_x86_ops->queue_exception(vcpu);
7708 /* Don't consider new event if we re-injected an event */
7709 if (kvm_event_needs_reinjection(vcpu))
7712 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7713 kvm_x86_ops->smi_allowed(vcpu)) {
7714 vcpu->arch.smi_pending = false;
7715 ++vcpu->arch.smi_count;
7717 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7718 --vcpu->arch.nmi_pending;
7719 vcpu->arch.nmi_injected = true;
7720 kvm_x86_ops->set_nmi(vcpu);
7721 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7723 * Because interrupts can be injected asynchronously, we are
7724 * calling check_nested_events again here to avoid a race condition.
7725 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7726 * proposal and current concerns. Perhaps we should be setting
7727 * KVM_REQ_EVENT only on certain events and not unconditionally?
7729 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7730 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7734 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7735 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7737 kvm_x86_ops->set_irq(vcpu);
7744 static void process_nmi(struct kvm_vcpu *vcpu)
7749 * x86 is limited to one NMI running, and one NMI pending after it.
7750 * If an NMI is already in progress, limit further NMIs to just one.
7751 * Otherwise, allow two (and we'll inject the first one immediately).
7753 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7756 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7757 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7758 kvm_make_request(KVM_REQ_EVENT, vcpu);
7761 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7764 flags |= seg->g << 23;
7765 flags |= seg->db << 22;
7766 flags |= seg->l << 21;
7767 flags |= seg->avl << 20;
7768 flags |= seg->present << 15;
7769 flags |= seg->dpl << 13;
7770 flags |= seg->s << 12;
7771 flags |= seg->type << 8;
7775 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7777 struct kvm_segment seg;
7780 kvm_get_segment(vcpu, &seg, n);
7781 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7784 offset = 0x7f84 + n * 12;
7786 offset = 0x7f2c + (n - 3) * 12;
7788 put_smstate(u32, buf, offset + 8, seg.base);
7789 put_smstate(u32, buf, offset + 4, seg.limit);
7790 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7793 #ifdef CONFIG_X86_64
7794 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7796 struct kvm_segment seg;
7800 kvm_get_segment(vcpu, &seg, n);
7801 offset = 0x7e00 + n * 16;
7803 flags = enter_smm_get_segment_flags(&seg) >> 8;
7804 put_smstate(u16, buf, offset, seg.selector);
7805 put_smstate(u16, buf, offset + 2, flags);
7806 put_smstate(u32, buf, offset + 4, seg.limit);
7807 put_smstate(u64, buf, offset + 8, seg.base);
7811 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7814 struct kvm_segment seg;
7818 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7819 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7820 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7821 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7823 for (i = 0; i < 8; i++)
7824 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7826 kvm_get_dr(vcpu, 6, &val);
7827 put_smstate(u32, buf, 0x7fcc, (u32)val);
7828 kvm_get_dr(vcpu, 7, &val);
7829 put_smstate(u32, buf, 0x7fc8, (u32)val);
7831 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7832 put_smstate(u32, buf, 0x7fc4, seg.selector);
7833 put_smstate(u32, buf, 0x7f64, seg.base);
7834 put_smstate(u32, buf, 0x7f60, seg.limit);
7835 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7837 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7838 put_smstate(u32, buf, 0x7fc0, seg.selector);
7839 put_smstate(u32, buf, 0x7f80, seg.base);
7840 put_smstate(u32, buf, 0x7f7c, seg.limit);
7841 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7843 kvm_x86_ops->get_gdt(vcpu, &dt);
7844 put_smstate(u32, buf, 0x7f74, dt.address);
7845 put_smstate(u32, buf, 0x7f70, dt.size);
7847 kvm_x86_ops->get_idt(vcpu, &dt);
7848 put_smstate(u32, buf, 0x7f58, dt.address);
7849 put_smstate(u32, buf, 0x7f54, dt.size);
7851 for (i = 0; i < 6; i++)
7852 enter_smm_save_seg_32(vcpu, buf, i);
7854 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7857 put_smstate(u32, buf, 0x7efc, 0x00020000);
7858 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7861 #ifdef CONFIG_X86_64
7862 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7865 struct kvm_segment seg;
7869 for (i = 0; i < 16; i++)
7870 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7872 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7873 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7875 kvm_get_dr(vcpu, 6, &val);
7876 put_smstate(u64, buf, 0x7f68, val);
7877 kvm_get_dr(vcpu, 7, &val);
7878 put_smstate(u64, buf, 0x7f60, val);
7880 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7881 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7882 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7884 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7887 put_smstate(u32, buf, 0x7efc, 0x00020064);
7889 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7891 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7892 put_smstate(u16, buf, 0x7e90, seg.selector);
7893 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7894 put_smstate(u32, buf, 0x7e94, seg.limit);
7895 put_smstate(u64, buf, 0x7e98, seg.base);
7897 kvm_x86_ops->get_idt(vcpu, &dt);
7898 put_smstate(u32, buf, 0x7e84, dt.size);
7899 put_smstate(u64, buf, 0x7e88, dt.address);
7901 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7902 put_smstate(u16, buf, 0x7e70, seg.selector);
7903 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7904 put_smstate(u32, buf, 0x7e74, seg.limit);
7905 put_smstate(u64, buf, 0x7e78, seg.base);
7907 kvm_x86_ops->get_gdt(vcpu, &dt);
7908 put_smstate(u32, buf, 0x7e64, dt.size);
7909 put_smstate(u64, buf, 0x7e68, dt.address);
7911 for (i = 0; i < 6; i++)
7912 enter_smm_save_seg_64(vcpu, buf, i);
7916 static void enter_smm(struct kvm_vcpu *vcpu)
7918 struct kvm_segment cs, ds;
7923 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7924 memset(buf, 0, 512);
7925 #ifdef CONFIG_X86_64
7926 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7927 enter_smm_save_state_64(vcpu, buf);
7930 enter_smm_save_state_32(vcpu, buf);
7933 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7934 * vCPU state (e.g. leave guest mode) after we've saved the state into
7935 * the SMM state-save area.
7937 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7939 vcpu->arch.hflags |= HF_SMM_MASK;
7940 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7942 if (kvm_x86_ops->get_nmi_mask(vcpu))
7943 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7945 kvm_x86_ops->set_nmi_mask(vcpu, true);
7947 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7948 kvm_rip_write(vcpu, 0x8000);
7950 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7951 kvm_x86_ops->set_cr0(vcpu, cr0);
7952 vcpu->arch.cr0 = cr0;
7954 kvm_x86_ops->set_cr4(vcpu, 0);
7956 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7957 dt.address = dt.size = 0;
7958 kvm_x86_ops->set_idt(vcpu, &dt);
7960 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7962 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7963 cs.base = vcpu->arch.smbase;
7968 cs.limit = ds.limit = 0xffffffff;
7969 cs.type = ds.type = 0x3;
7970 cs.dpl = ds.dpl = 0;
7975 cs.avl = ds.avl = 0;
7976 cs.present = ds.present = 1;
7977 cs.unusable = ds.unusable = 0;
7978 cs.padding = ds.padding = 0;
7980 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7981 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7982 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7983 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7984 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7985 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7987 #ifdef CONFIG_X86_64
7988 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7989 kvm_x86_ops->set_efer(vcpu, 0);
7992 kvm_update_cpuid(vcpu);
7993 kvm_mmu_reset_context(vcpu);
7996 static void process_smi(struct kvm_vcpu *vcpu)
7998 vcpu->arch.smi_pending = true;
7999 kvm_make_request(KVM_REQ_EVENT, vcpu);
8002 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8003 unsigned long *vcpu_bitmap)
8007 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8009 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8012 free_cpumask_var(cpus);
8015 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8017 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8020 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8022 if (!lapic_in_kernel(vcpu))
8025 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8026 kvm_apic_update_apicv(vcpu);
8027 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
8029 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8032 * NOTE: Do not hold any lock prior to calling this.
8034 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8035 * locked, because it calls __x86_set_memory_region() which does
8036 * synchronize_srcu(&kvm->srcu).
8038 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8040 if (!kvm_x86_ops->check_apicv_inhibit_reasons ||
8041 !kvm_x86_ops->check_apicv_inhibit_reasons(bit))
8045 if (!test_and_clear_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
8046 !kvm_apicv_activated(kvm))
8049 if (test_and_set_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
8050 kvm_apicv_activated(kvm))
8054 trace_kvm_apicv_update_request(activate, bit);
8055 if (kvm_x86_ops->pre_update_apicv_exec_ctrl)
8056 kvm_x86_ops->pre_update_apicv_exec_ctrl(kvm, activate);
8057 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8059 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8061 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8063 if (!kvm_apic_present(vcpu))
8066 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8068 if (irqchip_split(vcpu->kvm))
8069 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8071 if (vcpu->arch.apicv_active)
8072 kvm_x86_ops->sync_pir_to_irr(vcpu);
8073 if (ioapic_in_kernel(vcpu->kvm))
8074 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8077 if (is_guest_mode(vcpu))
8078 vcpu->arch.load_eoi_exitmap_pending = true;
8080 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8083 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8085 u64 eoi_exit_bitmap[4];
8087 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8090 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8091 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8092 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8095 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8096 unsigned long start, unsigned long end,
8099 unsigned long apic_address;
8102 * The physical address of apic access page is stored in the VMCS.
8103 * Update it when it becomes invalid.
8105 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8106 if (start <= apic_address && apic_address < end)
8107 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8112 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8114 struct page *page = NULL;
8116 if (!lapic_in_kernel(vcpu))
8119 if (!kvm_x86_ops->set_apic_access_page_addr)
8122 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8123 if (is_error_page(page))
8125 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8128 * Do not pin apic access page in memory, the MMU notifier
8129 * will call us again if it is migrated or swapped out.
8134 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8136 smp_send_reschedule(vcpu->cpu);
8138 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8141 * Returns 1 to let vcpu_run() continue the guest execution loop without
8142 * exiting to the userspace. Otherwise, the value will be returned to the
8145 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8149 dm_request_for_irq_injection(vcpu) &&
8150 kvm_cpu_accept_dm_intr(vcpu);
8151 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8153 bool req_immediate_exit = false;
8155 if (kvm_request_pending(vcpu)) {
8156 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8157 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8162 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8163 kvm_mmu_unload(vcpu);
8164 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8165 __kvm_migrate_timers(vcpu);
8166 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8167 kvm_gen_update_masterclock(vcpu->kvm);
8168 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8169 kvm_gen_kvmclock_update(vcpu);
8170 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8171 r = kvm_guest_time_update(vcpu);
8175 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8176 kvm_mmu_sync_roots(vcpu);
8177 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
8178 kvm_mmu_load_cr3(vcpu);
8179 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8180 kvm_vcpu_flush_tlb(vcpu, true);
8181 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8182 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8186 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8187 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8188 vcpu->mmio_needed = 0;
8192 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8193 /* Page is swapped out. Do synthetic halt */
8194 vcpu->arch.apf.halted = true;
8198 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8199 record_steal_time(vcpu);
8200 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8202 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8204 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8205 kvm_pmu_handle_event(vcpu);
8206 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8207 kvm_pmu_deliver_pmi(vcpu);
8208 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8209 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8210 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8211 vcpu->arch.ioapic_handled_vectors)) {
8212 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8213 vcpu->run->eoi.vector =
8214 vcpu->arch.pending_ioapic_eoi;
8219 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8220 vcpu_scan_ioapic(vcpu);
8221 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8222 vcpu_load_eoi_exitmap(vcpu);
8223 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8224 kvm_vcpu_reload_apic_access_page(vcpu);
8225 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8226 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8227 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8231 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8232 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8233 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8237 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8238 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8239 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8245 * KVM_REQ_HV_STIMER has to be processed after
8246 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8247 * depend on the guest clock being up-to-date
8249 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8250 kvm_hv_process_stimers(vcpu);
8251 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8252 kvm_vcpu_update_apicv(vcpu);
8255 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8256 ++vcpu->stat.req_event;
8257 kvm_apic_accept_events(vcpu);
8258 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8263 if (inject_pending_event(vcpu, req_int_win) != 0)
8264 req_immediate_exit = true;
8266 /* Enable SMI/NMI/IRQ window open exits if needed.
8268 * SMIs have three cases:
8269 * 1) They can be nested, and then there is nothing to
8270 * do here because RSM will cause a vmexit anyway.
8271 * 2) There is an ISA-specific reason why SMI cannot be
8272 * injected, and the moment when this changes can be
8274 * 3) Or the SMI can be pending because
8275 * inject_pending_event has completed the injection
8276 * of an IRQ or NMI from the previous vmexit, and
8277 * then we request an immediate exit to inject the
8280 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8281 if (!kvm_x86_ops->enable_smi_window(vcpu))
8282 req_immediate_exit = true;
8283 if (vcpu->arch.nmi_pending)
8284 kvm_x86_ops->enable_nmi_window(vcpu);
8285 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8286 kvm_x86_ops->enable_irq_window(vcpu);
8287 WARN_ON(vcpu->arch.exception.pending);
8290 if (kvm_lapic_enabled(vcpu)) {
8291 update_cr8_intercept(vcpu);
8292 kvm_lapic_sync_to_vapic(vcpu);
8296 r = kvm_mmu_reload(vcpu);
8298 goto cancel_injection;
8303 kvm_x86_ops->prepare_guest_switch(vcpu);
8306 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8307 * IPI are then delayed after guest entry, which ensures that they
8308 * result in virtual interrupt delivery.
8310 local_irq_disable();
8311 vcpu->mode = IN_GUEST_MODE;
8313 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8316 * 1) We should set ->mode before checking ->requests. Please see
8317 * the comment in kvm_vcpu_exiting_guest_mode().
8319 * 2) For APICv, we should set ->mode before checking PID.ON. This
8320 * pairs with the memory barrier implicit in pi_test_and_set_on
8321 * (see vmx_deliver_posted_interrupt).
8323 * 3) This also orders the write to mode from any reads to the page
8324 * tables done while the VCPU is running. Please see the comment
8325 * in kvm_flush_remote_tlbs.
8327 smp_mb__after_srcu_read_unlock();
8330 * This handles the case where a posted interrupt was
8331 * notified with kvm_vcpu_kick.
8333 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8334 kvm_x86_ops->sync_pir_to_irr(vcpu);
8336 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8337 || need_resched() || signal_pending(current)) {
8338 vcpu->mode = OUTSIDE_GUEST_MODE;
8342 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8344 goto cancel_injection;
8347 if (req_immediate_exit) {
8348 kvm_make_request(KVM_REQ_EVENT, vcpu);
8349 kvm_x86_ops->request_immediate_exit(vcpu);
8352 trace_kvm_entry(vcpu->vcpu_id);
8353 guest_enter_irqoff();
8355 fpregs_assert_state_consistent();
8356 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8357 switch_fpu_return();
8359 if (unlikely(vcpu->arch.switch_db_regs)) {
8361 set_debugreg(vcpu->arch.eff_db[0], 0);
8362 set_debugreg(vcpu->arch.eff_db[1], 1);
8363 set_debugreg(vcpu->arch.eff_db[2], 2);
8364 set_debugreg(vcpu->arch.eff_db[3], 3);
8365 set_debugreg(vcpu->arch.dr6, 6);
8366 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8369 kvm_x86_ops->run(vcpu);
8372 * Do this here before restoring debug registers on the host. And
8373 * since we do this before handling the vmexit, a DR access vmexit
8374 * can (a) read the correct value of the debug registers, (b) set
8375 * KVM_DEBUGREG_WONT_EXIT again.
8377 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8378 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8379 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8380 kvm_update_dr0123(vcpu);
8381 kvm_update_dr6(vcpu);
8382 kvm_update_dr7(vcpu);
8383 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8387 * If the guest has used debug registers, at least dr7
8388 * will be disabled while returning to the host.
8389 * If we don't have active breakpoints in the host, we don't
8390 * care about the messed up debug address registers. But if
8391 * we have some of them active, restore the old state.
8393 if (hw_breakpoint_active())
8394 hw_breakpoint_restore();
8396 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8398 vcpu->mode = OUTSIDE_GUEST_MODE;
8401 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
8404 * Consume any pending interrupts, including the possible source of
8405 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8406 * An instruction is required after local_irq_enable() to fully unblock
8407 * interrupts on processors that implement an interrupt shadow, the
8408 * stat.exits increment will do nicely.
8410 kvm_before_interrupt(vcpu);
8413 local_irq_disable();
8414 kvm_after_interrupt(vcpu);
8416 guest_exit_irqoff();
8417 if (lapic_in_kernel(vcpu)) {
8418 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8419 if (delta != S64_MIN) {
8420 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8421 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8428 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8431 * Profile KVM exit RIPs:
8433 if (unlikely(prof_on == KVM_PROFILING)) {
8434 unsigned long rip = kvm_rip_read(vcpu);
8435 profile_hit(KVM_PROFILING, (void *)rip);
8438 if (unlikely(vcpu->arch.tsc_always_catchup))
8439 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8441 if (vcpu->arch.apic_attention)
8442 kvm_lapic_sync_from_vapic(vcpu);
8444 vcpu->arch.gpa_available = false;
8445 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
8449 kvm_x86_ops->cancel_injection(vcpu);
8450 if (unlikely(vcpu->arch.apic_attention))
8451 kvm_lapic_sync_from_vapic(vcpu);
8456 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8458 if (!kvm_arch_vcpu_runnable(vcpu) &&
8459 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8460 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8461 kvm_vcpu_block(vcpu);
8462 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8464 if (kvm_x86_ops->post_block)
8465 kvm_x86_ops->post_block(vcpu);
8467 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8471 kvm_apic_accept_events(vcpu);
8472 switch(vcpu->arch.mp_state) {
8473 case KVM_MP_STATE_HALTED:
8474 vcpu->arch.pv.pv_unhalted = false;
8475 vcpu->arch.mp_state =
8476 KVM_MP_STATE_RUNNABLE;
8478 case KVM_MP_STATE_RUNNABLE:
8479 vcpu->arch.apf.halted = false;
8481 case KVM_MP_STATE_INIT_RECEIVED:
8490 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8492 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8493 kvm_x86_ops->check_nested_events(vcpu, false);
8495 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8496 !vcpu->arch.apf.halted);
8499 static int vcpu_run(struct kvm_vcpu *vcpu)
8502 struct kvm *kvm = vcpu->kvm;
8504 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8505 vcpu->arch.l1tf_flush_l1d = true;
8508 if (kvm_vcpu_running(vcpu)) {
8509 r = vcpu_enter_guest(vcpu);
8511 r = vcpu_block(kvm, vcpu);
8517 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8518 if (kvm_cpu_has_pending_timer(vcpu))
8519 kvm_inject_pending_timer_irqs(vcpu);
8521 if (dm_request_for_irq_injection(vcpu) &&
8522 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8524 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8525 ++vcpu->stat.request_irq_exits;
8529 kvm_check_async_pf_completion(vcpu);
8531 if (signal_pending(current)) {
8533 vcpu->run->exit_reason = KVM_EXIT_INTR;
8534 ++vcpu->stat.signal_exits;
8537 if (need_resched()) {
8538 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8540 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8544 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8549 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8553 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8554 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8555 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8559 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8561 BUG_ON(!vcpu->arch.pio.count);
8563 return complete_emulated_io(vcpu);
8567 * Implements the following, as a state machine:
8571 * for each mmio piece in the fragment
8579 * for each mmio piece in the fragment
8584 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8586 struct kvm_run *run = vcpu->run;
8587 struct kvm_mmio_fragment *frag;
8590 BUG_ON(!vcpu->mmio_needed);
8592 /* Complete previous fragment */
8593 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8594 len = min(8u, frag->len);
8595 if (!vcpu->mmio_is_write)
8596 memcpy(frag->data, run->mmio.data, len);
8598 if (frag->len <= 8) {
8599 /* Switch to the next fragment. */
8601 vcpu->mmio_cur_fragment++;
8603 /* Go forward to the next mmio piece. */
8609 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8610 vcpu->mmio_needed = 0;
8612 /* FIXME: return into emulator if single-stepping. */
8613 if (vcpu->mmio_is_write)
8615 vcpu->mmio_read_completed = 1;
8616 return complete_emulated_io(vcpu);
8619 run->exit_reason = KVM_EXIT_MMIO;
8620 run->mmio.phys_addr = frag->gpa;
8621 if (vcpu->mmio_is_write)
8622 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8623 run->mmio.len = min(8u, frag->len);
8624 run->mmio.is_write = vcpu->mmio_is_write;
8625 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8629 static void kvm_save_current_fpu(struct fpu *fpu)
8632 * If the target FPU state is not resident in the CPU registers, just
8633 * memcpy() from current, else save CPU state directly to the target.
8635 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8636 memcpy(&fpu->state, ¤t->thread.fpu.state,
8637 fpu_kernel_xstate_size);
8639 copy_fpregs_to_fpstate(fpu);
8642 /* Swap (qemu) user FPU context for the guest FPU context. */
8643 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8647 kvm_save_current_fpu(vcpu->arch.user_fpu);
8649 /* PKRU is separately restored in kvm_x86_ops->run. */
8650 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8651 ~XFEATURE_MASK_PKRU);
8653 fpregs_mark_activate();
8659 /* When vcpu_run ends, restore user space FPU context. */
8660 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8664 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8666 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8668 fpregs_mark_activate();
8671 ++vcpu->stat.fpu_reload;
8675 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8680 kvm_sigset_activate(vcpu);
8681 kvm_load_guest_fpu(vcpu);
8683 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8684 if (kvm_run->immediate_exit) {
8688 kvm_vcpu_block(vcpu);
8689 kvm_apic_accept_events(vcpu);
8690 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8692 if (signal_pending(current)) {
8694 vcpu->run->exit_reason = KVM_EXIT_INTR;
8695 ++vcpu->stat.signal_exits;
8700 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8705 if (vcpu->run->kvm_dirty_regs) {
8706 r = sync_regs(vcpu);
8711 /* re-sync apic's tpr */
8712 if (!lapic_in_kernel(vcpu)) {
8713 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8719 if (unlikely(vcpu->arch.complete_userspace_io)) {
8720 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8721 vcpu->arch.complete_userspace_io = NULL;
8726 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8728 if (kvm_run->immediate_exit)
8734 kvm_put_guest_fpu(vcpu);
8735 if (vcpu->run->kvm_valid_regs)
8737 post_kvm_run_save(vcpu);
8738 kvm_sigset_deactivate(vcpu);
8744 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8746 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8748 * We are here if userspace calls get_regs() in the middle of
8749 * instruction emulation. Registers state needs to be copied
8750 * back from emulation context to vcpu. Userspace shouldn't do
8751 * that usually, but some bad designed PV devices (vmware
8752 * backdoor interface) need this to work
8754 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8755 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8757 regs->rax = kvm_rax_read(vcpu);
8758 regs->rbx = kvm_rbx_read(vcpu);
8759 regs->rcx = kvm_rcx_read(vcpu);
8760 regs->rdx = kvm_rdx_read(vcpu);
8761 regs->rsi = kvm_rsi_read(vcpu);
8762 regs->rdi = kvm_rdi_read(vcpu);
8763 regs->rsp = kvm_rsp_read(vcpu);
8764 regs->rbp = kvm_rbp_read(vcpu);
8765 #ifdef CONFIG_X86_64
8766 regs->r8 = kvm_r8_read(vcpu);
8767 regs->r9 = kvm_r9_read(vcpu);
8768 regs->r10 = kvm_r10_read(vcpu);
8769 regs->r11 = kvm_r11_read(vcpu);
8770 regs->r12 = kvm_r12_read(vcpu);
8771 regs->r13 = kvm_r13_read(vcpu);
8772 regs->r14 = kvm_r14_read(vcpu);
8773 regs->r15 = kvm_r15_read(vcpu);
8776 regs->rip = kvm_rip_read(vcpu);
8777 regs->rflags = kvm_get_rflags(vcpu);
8780 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8783 __get_regs(vcpu, regs);
8788 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8790 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8791 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8793 kvm_rax_write(vcpu, regs->rax);
8794 kvm_rbx_write(vcpu, regs->rbx);
8795 kvm_rcx_write(vcpu, regs->rcx);
8796 kvm_rdx_write(vcpu, regs->rdx);
8797 kvm_rsi_write(vcpu, regs->rsi);
8798 kvm_rdi_write(vcpu, regs->rdi);
8799 kvm_rsp_write(vcpu, regs->rsp);
8800 kvm_rbp_write(vcpu, regs->rbp);
8801 #ifdef CONFIG_X86_64
8802 kvm_r8_write(vcpu, regs->r8);
8803 kvm_r9_write(vcpu, regs->r9);
8804 kvm_r10_write(vcpu, regs->r10);
8805 kvm_r11_write(vcpu, regs->r11);
8806 kvm_r12_write(vcpu, regs->r12);
8807 kvm_r13_write(vcpu, regs->r13);
8808 kvm_r14_write(vcpu, regs->r14);
8809 kvm_r15_write(vcpu, regs->r15);
8812 kvm_rip_write(vcpu, regs->rip);
8813 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8815 vcpu->arch.exception.pending = false;
8817 kvm_make_request(KVM_REQ_EVENT, vcpu);
8820 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8823 __set_regs(vcpu, regs);
8828 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8830 struct kvm_segment cs;
8832 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8836 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8838 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8842 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8843 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8844 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8845 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8846 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8847 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8849 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8850 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8852 kvm_x86_ops->get_idt(vcpu, &dt);
8853 sregs->idt.limit = dt.size;
8854 sregs->idt.base = dt.address;
8855 kvm_x86_ops->get_gdt(vcpu, &dt);
8856 sregs->gdt.limit = dt.size;
8857 sregs->gdt.base = dt.address;
8859 sregs->cr0 = kvm_read_cr0(vcpu);
8860 sregs->cr2 = vcpu->arch.cr2;
8861 sregs->cr3 = kvm_read_cr3(vcpu);
8862 sregs->cr4 = kvm_read_cr4(vcpu);
8863 sregs->cr8 = kvm_get_cr8(vcpu);
8864 sregs->efer = vcpu->arch.efer;
8865 sregs->apic_base = kvm_get_apic_base(vcpu);
8867 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8869 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8870 set_bit(vcpu->arch.interrupt.nr,
8871 (unsigned long *)sregs->interrupt_bitmap);
8874 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8875 struct kvm_sregs *sregs)
8878 __get_sregs(vcpu, sregs);
8883 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8884 struct kvm_mp_state *mp_state)
8887 if (kvm_mpx_supported())
8888 kvm_load_guest_fpu(vcpu);
8890 kvm_apic_accept_events(vcpu);
8891 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8892 vcpu->arch.pv.pv_unhalted)
8893 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8895 mp_state->mp_state = vcpu->arch.mp_state;
8897 if (kvm_mpx_supported())
8898 kvm_put_guest_fpu(vcpu);
8903 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8904 struct kvm_mp_state *mp_state)
8910 if (!lapic_in_kernel(vcpu) &&
8911 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8915 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8916 * INIT state; latched init should be reported using
8917 * KVM_SET_VCPU_EVENTS, so reject it here.
8919 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8920 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8921 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8924 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8925 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8926 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8928 vcpu->arch.mp_state = mp_state->mp_state;
8929 kvm_make_request(KVM_REQ_EVENT, vcpu);
8937 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8938 int reason, bool has_error_code, u32 error_code)
8940 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8943 init_emulate_ctxt(vcpu);
8945 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8946 has_error_code, error_code);
8948 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8949 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8950 vcpu->run->internal.ndata = 0;
8954 kvm_rip_write(vcpu, ctxt->eip);
8955 kvm_set_rflags(vcpu, ctxt->eflags);
8958 EXPORT_SYMBOL_GPL(kvm_task_switch);
8960 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8962 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8964 * When EFER.LME and CR0.PG are set, the processor is in
8965 * 64-bit mode (though maybe in a 32-bit code segment).
8966 * CR4.PAE and EFER.LMA must be set.
8968 if (!(sregs->cr4 & X86_CR4_PAE)
8969 || !(sregs->efer & EFER_LMA))
8973 * Not in 64-bit mode: EFER.LMA is clear and the code
8974 * segment cannot be 64-bit.
8976 if (sregs->efer & EFER_LMA || sregs->cs.l)
8980 return kvm_valid_cr4(vcpu, sregs->cr4);
8983 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8985 struct msr_data apic_base_msr;
8986 int mmu_reset_needed = 0;
8987 int cpuid_update_needed = 0;
8988 int pending_vec, max_bits, idx;
8992 if (kvm_valid_sregs(vcpu, sregs))
8995 apic_base_msr.data = sregs->apic_base;
8996 apic_base_msr.host_initiated = true;
8997 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9000 dt.size = sregs->idt.limit;
9001 dt.address = sregs->idt.base;
9002 kvm_x86_ops->set_idt(vcpu, &dt);
9003 dt.size = sregs->gdt.limit;
9004 dt.address = sregs->gdt.base;
9005 kvm_x86_ops->set_gdt(vcpu, &dt);
9007 vcpu->arch.cr2 = sregs->cr2;
9008 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9009 vcpu->arch.cr3 = sregs->cr3;
9010 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9012 kvm_set_cr8(vcpu, sregs->cr8);
9014 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9015 kvm_x86_ops->set_efer(vcpu, sregs->efer);
9017 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9018 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
9019 vcpu->arch.cr0 = sregs->cr0;
9021 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9022 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9023 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9024 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
9025 if (cpuid_update_needed)
9026 kvm_update_cpuid(vcpu);
9028 idx = srcu_read_lock(&vcpu->kvm->srcu);
9029 if (is_pae_paging(vcpu)) {
9030 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9031 mmu_reset_needed = 1;
9033 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9035 if (mmu_reset_needed)
9036 kvm_mmu_reset_context(vcpu);
9038 max_bits = KVM_NR_INTERRUPTS;
9039 pending_vec = find_first_bit(
9040 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9041 if (pending_vec < max_bits) {
9042 kvm_queue_interrupt(vcpu, pending_vec, false);
9043 pr_debug("Set back pending irq %d\n", pending_vec);
9046 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9047 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9048 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9049 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9050 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9051 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9053 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9054 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9056 update_cr8_intercept(vcpu);
9058 /* Older userspace won't unhalt the vcpu on reset. */
9059 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9060 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9062 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9064 kvm_make_request(KVM_REQ_EVENT, vcpu);
9071 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9072 struct kvm_sregs *sregs)
9077 ret = __set_sregs(vcpu, sregs);
9082 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9083 struct kvm_guest_debug *dbg)
9085 unsigned long rflags;
9090 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9092 if (vcpu->arch.exception.pending)
9094 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9095 kvm_queue_exception(vcpu, DB_VECTOR);
9097 kvm_queue_exception(vcpu, BP_VECTOR);
9101 * Read rflags as long as potentially injected trace flags are still
9104 rflags = kvm_get_rflags(vcpu);
9106 vcpu->guest_debug = dbg->control;
9107 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9108 vcpu->guest_debug = 0;
9110 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9111 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9112 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9113 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9115 for (i = 0; i < KVM_NR_DB_REGS; i++)
9116 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9118 kvm_update_dr7(vcpu);
9120 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9121 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9122 get_segment_base(vcpu, VCPU_SREG_CS);
9125 * Trigger an rflags update that will inject or remove the trace
9128 kvm_set_rflags(vcpu, rflags);
9130 kvm_x86_ops->update_bp_intercept(vcpu);
9140 * Translate a guest virtual address to a guest physical address.
9142 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9143 struct kvm_translation *tr)
9145 unsigned long vaddr = tr->linear_address;
9151 idx = srcu_read_lock(&vcpu->kvm->srcu);
9152 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9153 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9154 tr->physical_address = gpa;
9155 tr->valid = gpa != UNMAPPED_GVA;
9163 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9165 struct fxregs_state *fxsave;
9169 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9170 memcpy(fpu->fpr, fxsave->st_space, 128);
9171 fpu->fcw = fxsave->cwd;
9172 fpu->fsw = fxsave->swd;
9173 fpu->ftwx = fxsave->twd;
9174 fpu->last_opcode = fxsave->fop;
9175 fpu->last_ip = fxsave->rip;
9176 fpu->last_dp = fxsave->rdp;
9177 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9183 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9185 struct fxregs_state *fxsave;
9189 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9191 memcpy(fxsave->st_space, fpu->fpr, 128);
9192 fxsave->cwd = fpu->fcw;
9193 fxsave->swd = fpu->fsw;
9194 fxsave->twd = fpu->ftwx;
9195 fxsave->fop = fpu->last_opcode;
9196 fxsave->rip = fpu->last_ip;
9197 fxsave->rdp = fpu->last_dp;
9198 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9204 static void store_regs(struct kvm_vcpu *vcpu)
9206 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9208 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9209 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9211 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9212 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9214 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9215 kvm_vcpu_ioctl_x86_get_vcpu_events(
9216 vcpu, &vcpu->run->s.regs.events);
9219 static int sync_regs(struct kvm_vcpu *vcpu)
9221 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9224 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9225 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9226 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9228 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9229 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9231 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9233 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9234 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9235 vcpu, &vcpu->run->s.regs.events))
9237 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9243 static void fx_init(struct kvm_vcpu *vcpu)
9245 fpstate_init(&vcpu->arch.guest_fpu->state);
9246 if (boot_cpu_has(X86_FEATURE_XSAVES))
9247 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9248 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9251 * Ensure guest xcr0 is valid for loading
9253 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9255 vcpu->arch.cr0 |= X86_CR0_ET;
9258 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9260 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9261 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9262 "guest TSC will not be reliable\n");
9267 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9272 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9273 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9274 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9276 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9278 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9280 r = kvm_mmu_create(vcpu);
9284 if (irqchip_in_kernel(vcpu->kvm)) {
9285 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9287 goto fail_mmu_destroy;
9288 if (kvm_apicv_activated(vcpu->kvm))
9289 vcpu->arch.apicv_active = true;
9291 static_key_slow_inc(&kvm_no_apic_vcpu);
9295 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9297 goto fail_free_lapic;
9298 vcpu->arch.pio_data = page_address(page);
9300 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9301 GFP_KERNEL_ACCOUNT);
9302 if (!vcpu->arch.mce_banks)
9303 goto fail_free_pio_data;
9304 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9306 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9307 GFP_KERNEL_ACCOUNT))
9308 goto fail_free_mce_banks;
9310 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9311 GFP_KERNEL_ACCOUNT);
9312 if (!vcpu->arch.user_fpu) {
9313 pr_err("kvm: failed to allocate userspace's fpu\n");
9314 goto free_wbinvd_dirty_mask;
9317 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9318 GFP_KERNEL_ACCOUNT);
9319 if (!vcpu->arch.guest_fpu) {
9320 pr_err("kvm: failed to allocate vcpu's fpu\n");
9325 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9327 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9329 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9331 kvm_async_pf_hash_reset(vcpu);
9334 vcpu->arch.pending_external_vector = -1;
9335 vcpu->arch.preempted_in_kernel = false;
9337 kvm_hv_vcpu_init(vcpu);
9339 r = kvm_x86_ops->vcpu_create(vcpu);
9341 goto free_guest_fpu;
9343 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9344 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9345 kvm_vcpu_mtrr_init(vcpu);
9347 kvm_vcpu_reset(vcpu, false);
9348 kvm_init_mmu(vcpu, false);
9353 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9355 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9356 free_wbinvd_dirty_mask:
9357 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9358 fail_free_mce_banks:
9359 kfree(vcpu->arch.mce_banks);
9361 free_page((unsigned long)vcpu->arch.pio_data);
9363 kvm_free_lapic(vcpu);
9365 kvm_mmu_destroy(vcpu);
9369 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9371 struct msr_data msr;
9372 struct kvm *kvm = vcpu->kvm;
9374 kvm_hv_vcpu_postcreate(vcpu);
9376 if (mutex_lock_killable(&vcpu->mutex))
9380 msr.index = MSR_IA32_TSC;
9381 msr.host_initiated = true;
9382 kvm_write_tsc(vcpu, &msr);
9385 /* poll control enabled by default */
9386 vcpu->arch.msr_kvm_poll_control = 1;
9388 mutex_unlock(&vcpu->mutex);
9390 if (!kvmclock_periodic_sync)
9393 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9394 KVMCLOCK_SYNC_PERIOD);
9397 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9399 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9402 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9404 kvmclock_reset(vcpu);
9406 kvm_x86_ops->vcpu_free(vcpu);
9408 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9409 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9410 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9412 kvm_hv_vcpu_uninit(vcpu);
9413 kvm_pmu_destroy(vcpu);
9414 kfree(vcpu->arch.mce_banks);
9415 kvm_free_lapic(vcpu);
9416 idx = srcu_read_lock(&vcpu->kvm->srcu);
9417 kvm_mmu_destroy(vcpu);
9418 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9419 free_page((unsigned long)vcpu->arch.pio_data);
9420 if (!lapic_in_kernel(vcpu))
9421 static_key_slow_dec(&kvm_no_apic_vcpu);
9424 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9426 kvm_lapic_reset(vcpu, init_event);
9428 vcpu->arch.hflags = 0;
9430 vcpu->arch.smi_pending = 0;
9431 vcpu->arch.smi_count = 0;
9432 atomic_set(&vcpu->arch.nmi_queued, 0);
9433 vcpu->arch.nmi_pending = 0;
9434 vcpu->arch.nmi_injected = false;
9435 kvm_clear_interrupt_queue(vcpu);
9436 kvm_clear_exception_queue(vcpu);
9438 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9439 kvm_update_dr0123(vcpu);
9440 vcpu->arch.dr6 = DR6_INIT;
9441 kvm_update_dr6(vcpu);
9442 vcpu->arch.dr7 = DR7_FIXED_1;
9443 kvm_update_dr7(vcpu);
9447 kvm_make_request(KVM_REQ_EVENT, vcpu);
9448 vcpu->arch.apf.msr_val = 0;
9449 vcpu->arch.st.msr_val = 0;
9451 kvmclock_reset(vcpu);
9453 kvm_clear_async_pf_completion_queue(vcpu);
9454 kvm_async_pf_hash_reset(vcpu);
9455 vcpu->arch.apf.halted = false;
9457 if (kvm_mpx_supported()) {
9458 void *mpx_state_buffer;
9461 * To avoid have the INIT path from kvm_apic_has_events() that be
9462 * called with loaded FPU and does not let userspace fix the state.
9465 kvm_put_guest_fpu(vcpu);
9466 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9468 if (mpx_state_buffer)
9469 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9470 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9472 if (mpx_state_buffer)
9473 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9475 kvm_load_guest_fpu(vcpu);
9479 kvm_pmu_reset(vcpu);
9480 vcpu->arch.smbase = 0x30000;
9482 vcpu->arch.msr_misc_features_enables = 0;
9484 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9487 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9488 vcpu->arch.regs_avail = ~0;
9489 vcpu->arch.regs_dirty = ~0;
9491 vcpu->arch.ia32_xss = 0;
9493 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9496 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9498 struct kvm_segment cs;
9500 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9501 cs.selector = vector << 8;
9502 cs.base = vector << 12;
9503 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9504 kvm_rip_write(vcpu, 0);
9507 int kvm_arch_hardware_enable(void)
9510 struct kvm_vcpu *vcpu;
9515 bool stable, backwards_tsc = false;
9517 kvm_shared_msr_cpu_online();
9518 ret = kvm_x86_ops->hardware_enable();
9522 local_tsc = rdtsc();
9523 stable = !kvm_check_tsc_unstable();
9524 list_for_each_entry(kvm, &vm_list, vm_list) {
9525 kvm_for_each_vcpu(i, vcpu, kvm) {
9526 if (!stable && vcpu->cpu == smp_processor_id())
9527 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9528 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9529 backwards_tsc = true;
9530 if (vcpu->arch.last_host_tsc > max_tsc)
9531 max_tsc = vcpu->arch.last_host_tsc;
9537 * Sometimes, even reliable TSCs go backwards. This happens on
9538 * platforms that reset TSC during suspend or hibernate actions, but
9539 * maintain synchronization. We must compensate. Fortunately, we can
9540 * detect that condition here, which happens early in CPU bringup,
9541 * before any KVM threads can be running. Unfortunately, we can't
9542 * bring the TSCs fully up to date with real time, as we aren't yet far
9543 * enough into CPU bringup that we know how much real time has actually
9544 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9545 * variables that haven't been updated yet.
9547 * So we simply find the maximum observed TSC above, then record the
9548 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9549 * the adjustment will be applied. Note that we accumulate
9550 * adjustments, in case multiple suspend cycles happen before some VCPU
9551 * gets a chance to run again. In the event that no KVM threads get a
9552 * chance to run, we will miss the entire elapsed period, as we'll have
9553 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9554 * loose cycle time. This isn't too big a deal, since the loss will be
9555 * uniform across all VCPUs (not to mention the scenario is extremely
9556 * unlikely). It is possible that a second hibernate recovery happens
9557 * much faster than a first, causing the observed TSC here to be
9558 * smaller; this would require additional padding adjustment, which is
9559 * why we set last_host_tsc to the local tsc observed here.
9561 * N.B. - this code below runs only on platforms with reliable TSC,
9562 * as that is the only way backwards_tsc is set above. Also note
9563 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9564 * have the same delta_cyc adjustment applied if backwards_tsc
9565 * is detected. Note further, this adjustment is only done once,
9566 * as we reset last_host_tsc on all VCPUs to stop this from being
9567 * called multiple times (one for each physical CPU bringup).
9569 * Platforms with unreliable TSCs don't have to deal with this, they
9570 * will be compensated by the logic in vcpu_load, which sets the TSC to
9571 * catchup mode. This will catchup all VCPUs to real time, but cannot
9572 * guarantee that they stay in perfect synchronization.
9574 if (backwards_tsc) {
9575 u64 delta_cyc = max_tsc - local_tsc;
9576 list_for_each_entry(kvm, &vm_list, vm_list) {
9577 kvm->arch.backwards_tsc_observed = true;
9578 kvm_for_each_vcpu(i, vcpu, kvm) {
9579 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9580 vcpu->arch.last_host_tsc = local_tsc;
9581 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9585 * We have to disable TSC offset matching.. if you were
9586 * booting a VM while issuing an S4 host suspend....
9587 * you may have some problem. Solving this issue is
9588 * left as an exercise to the reader.
9590 kvm->arch.last_tsc_nsec = 0;
9591 kvm->arch.last_tsc_write = 0;
9598 void kvm_arch_hardware_disable(void)
9600 kvm_x86_ops->hardware_disable();
9601 drop_user_return_notifiers();
9604 int kvm_arch_hardware_setup(void)
9608 r = kvm_x86_ops->hardware_setup();
9612 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9614 if (kvm_has_tsc_control) {
9616 * Make sure the user can only configure tsc_khz values that
9617 * fit into a signed integer.
9618 * A min value is not calculated because it will always
9619 * be 1 on all machines.
9621 u64 max = min(0x7fffffffULL,
9622 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9623 kvm_max_guest_tsc_khz = max;
9625 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9628 if (boot_cpu_has(X86_FEATURE_XSAVES))
9629 rdmsrl(MSR_IA32_XSS, host_xss);
9631 kvm_init_msr_list();
9635 void kvm_arch_hardware_unsetup(void)
9637 kvm_x86_ops->hardware_unsetup();
9640 int kvm_arch_check_processor_compat(void)
9642 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9644 WARN_ON(!irqs_disabled());
9646 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9649 return kvm_x86_ops->check_processor_compatibility();
9652 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9654 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9656 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9658 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9660 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9663 struct static_key kvm_no_apic_vcpu __read_mostly;
9664 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9666 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9668 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9670 vcpu->arch.l1tf_flush_l1d = true;
9671 if (pmu->version && unlikely(pmu->event_count)) {
9672 pmu->need_cleanup = true;
9673 kvm_make_request(KVM_REQ_PMU, vcpu);
9675 kvm_x86_ops->sched_in(vcpu, cpu);
9678 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9683 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9684 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9685 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9686 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9687 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9688 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9690 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9691 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9692 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9693 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9694 &kvm->arch.irq_sources_bitmap);
9696 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9697 mutex_init(&kvm->arch.apic_map_lock);
9698 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9700 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9701 pvclock_update_vm_gtod_copy(kvm);
9703 kvm->arch.guest_can_read_msr_platform_info = true;
9705 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9706 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9708 kvm_hv_init_vm(kvm);
9709 kvm_page_track_init(kvm);
9710 kvm_mmu_init_vm(kvm);
9712 return kvm_x86_ops->vm_init(kvm);
9715 int kvm_arch_post_init_vm(struct kvm *kvm)
9717 return kvm_mmu_post_init_vm(kvm);
9720 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9723 kvm_mmu_unload(vcpu);
9727 static void kvm_free_vcpus(struct kvm *kvm)
9730 struct kvm_vcpu *vcpu;
9733 * Unpin any mmu pages first.
9735 kvm_for_each_vcpu(i, vcpu, kvm) {
9736 kvm_clear_async_pf_completion_queue(vcpu);
9737 kvm_unload_vcpu_mmu(vcpu);
9739 kvm_for_each_vcpu(i, vcpu, kvm)
9740 kvm_vcpu_destroy(vcpu);
9742 mutex_lock(&kvm->lock);
9743 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9744 kvm->vcpus[i] = NULL;
9746 atomic_set(&kvm->online_vcpus, 0);
9747 mutex_unlock(&kvm->lock);
9750 void kvm_arch_sync_events(struct kvm *kvm)
9752 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9753 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9757 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9761 struct kvm_memslots *slots = kvm_memslots(kvm);
9762 struct kvm_memory_slot *slot, old;
9764 /* Called with kvm->slots_lock held. */
9765 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9768 slot = id_to_memslot(slots, id);
9774 * MAP_SHARED to prevent internal slot pages from being moved
9777 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9778 MAP_SHARED | MAP_ANONYMOUS, 0);
9779 if (IS_ERR((void *)hva))
9780 return PTR_ERR((void *)hva);
9789 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9790 struct kvm_userspace_memory_region m;
9792 m.slot = id | (i << 16);
9794 m.guest_phys_addr = gpa;
9795 m.userspace_addr = hva;
9796 m.memory_size = size;
9797 r = __kvm_set_memory_region(kvm, &m);
9803 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9807 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9809 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9811 kvm_mmu_pre_destroy_vm(kvm);
9814 void kvm_arch_destroy_vm(struct kvm *kvm)
9816 if (current->mm == kvm->mm) {
9818 * Free memory regions allocated on behalf of userspace,
9819 * unless the the memory map has changed due to process exit
9822 mutex_lock(&kvm->slots_lock);
9823 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9825 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9827 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9828 mutex_unlock(&kvm->slots_lock);
9830 if (kvm_x86_ops->vm_destroy)
9831 kvm_x86_ops->vm_destroy(kvm);
9832 kvm_pic_destroy(kvm);
9833 kvm_ioapic_destroy(kvm);
9834 kvm_free_vcpus(kvm);
9835 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9836 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9837 kvm_mmu_uninit_vm(kvm);
9838 kvm_page_track_cleanup(kvm);
9839 kvm_hv_destroy_vm(kvm);
9842 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9843 struct kvm_memory_slot *dont)
9847 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9848 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9849 kvfree(free->arch.rmap[i]);
9850 free->arch.rmap[i] = NULL;
9855 if (!dont || free->arch.lpage_info[i - 1] !=
9856 dont->arch.lpage_info[i - 1]) {
9857 kvfree(free->arch.lpage_info[i - 1]);
9858 free->arch.lpage_info[i - 1] = NULL;
9862 kvm_page_track_free_memslot(free, dont);
9865 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9866 unsigned long npages)
9870 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9871 struct kvm_lpage_info *linfo;
9876 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9877 slot->base_gfn, level) + 1;
9879 slot->arch.rmap[i] =
9880 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9881 GFP_KERNEL_ACCOUNT);
9882 if (!slot->arch.rmap[i])
9887 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9891 slot->arch.lpage_info[i - 1] = linfo;
9893 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9894 linfo[0].disallow_lpage = 1;
9895 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9896 linfo[lpages - 1].disallow_lpage = 1;
9897 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9899 * If the gfn and userspace address are not aligned wrt each
9900 * other, or if explicitly asked to, disable large page
9901 * support for this slot
9903 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9904 !kvm_largepages_enabled()) {
9907 for (j = 0; j < lpages; ++j)
9908 linfo[j].disallow_lpage = 1;
9912 if (kvm_page_track_create_memslot(slot, npages))
9918 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9919 kvfree(slot->arch.rmap[i]);
9920 slot->arch.rmap[i] = NULL;
9924 kvfree(slot->arch.lpage_info[i - 1]);
9925 slot->arch.lpage_info[i - 1] = NULL;
9930 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9932 struct kvm_vcpu *vcpu;
9936 * memslots->generation has been incremented.
9937 * mmio generation may have reached its maximum value.
9939 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9941 /* Force re-initialization of steal_time cache */
9942 kvm_for_each_vcpu(i, vcpu, kvm)
9943 kvm_vcpu_kick(vcpu);
9946 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9947 struct kvm_memory_slot *memslot,
9948 const struct kvm_userspace_memory_region *mem,
9949 enum kvm_mr_change change)
9954 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9955 struct kvm_memory_slot *new)
9957 /* Still write protect RO slot */
9958 if (new->flags & KVM_MEM_READONLY) {
9959 kvm_mmu_slot_remove_write_access(kvm, new);
9964 * Call kvm_x86_ops dirty logging hooks when they are valid.
9966 * kvm_x86_ops->slot_disable_log_dirty is called when:
9968 * - KVM_MR_CREATE with dirty logging is disabled
9969 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9971 * The reason is, in case of PML, we need to set D-bit for any slots
9972 * with dirty logging disabled in order to eliminate unnecessary GPA
9973 * logging in PML buffer (and potential PML buffer full VMEXIT). This
9974 * guarantees leaving PML enabled during guest's lifetime won't have
9975 * any additional overhead from PML when guest is running with dirty
9976 * logging disabled for memory slots.
9978 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9979 * to dirty logging mode.
9981 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9983 * In case of write protect:
9985 * Write protect all pages for dirty logging.
9987 * All the sptes including the large sptes which point to this
9988 * slot are set to readonly. We can not create any new large
9989 * spte on this slot until the end of the logging.
9991 * See the comments in fast_page_fault().
9993 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9994 if (kvm_x86_ops->slot_enable_log_dirty)
9995 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9997 kvm_mmu_slot_remove_write_access(kvm, new);
9999 if (kvm_x86_ops->slot_disable_log_dirty)
10000 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
10004 void kvm_arch_commit_memory_region(struct kvm *kvm,
10005 const struct kvm_userspace_memory_region *mem,
10006 const struct kvm_memory_slot *old,
10007 const struct kvm_memory_slot *new,
10008 enum kvm_mr_change change)
10010 if (!kvm->arch.n_requested_mmu_pages)
10011 kvm_mmu_change_mmu_pages(kvm,
10012 kvm_mmu_calculate_default_mmu_pages(kvm));
10015 * Dirty logging tracks sptes in 4k granularity, meaning that large
10016 * sptes have to be split. If live migration is successful, the guest
10017 * in the source machine will be destroyed and large sptes will be
10018 * created in the destination. However, if the guest continues to run
10019 * in the source machine (for example if live migration fails), small
10020 * sptes will remain around and cause bad performance.
10022 * Scan sptes if dirty logging has been stopped, dropping those
10023 * which can be collapsed into a single large-page spte. Later
10024 * page faults will create the large-page sptes.
10026 * There is no need to do this in any of the following cases:
10027 * CREATE: No dirty mappings will already exist.
10028 * MOVE/DELETE: The old mappings will already have been cleaned up by
10029 * kvm_arch_flush_shadow_memslot()
10031 if (change == KVM_MR_FLAGS_ONLY &&
10032 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10033 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10034 kvm_mmu_zap_collapsible_sptes(kvm, new);
10037 * Set up write protection and/or dirty logging for the new slot.
10039 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10040 * been zapped so no dirty logging staff is needed for old slot. For
10041 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10042 * new and it's also covered when dealing with the new slot.
10044 * FIXME: const-ify all uses of struct kvm_memory_slot.
10046 if (change != KVM_MR_DELETE)
10047 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10050 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10052 kvm_mmu_zap_all(kvm);
10055 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10056 struct kvm_memory_slot *slot)
10058 kvm_page_track_flush_slot(kvm, slot);
10061 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10063 return (is_guest_mode(vcpu) &&
10064 kvm_x86_ops->guest_apic_has_interrupt &&
10065 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
10068 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10070 if (!list_empty_careful(&vcpu->async_pf.done))
10073 if (kvm_apic_has_events(vcpu))
10076 if (vcpu->arch.pv.pv_unhalted)
10079 if (vcpu->arch.exception.pending)
10082 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10083 (vcpu->arch.nmi_pending &&
10084 kvm_x86_ops->nmi_allowed(vcpu)))
10087 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10088 (vcpu->arch.smi_pending && !is_smm(vcpu)))
10091 if (kvm_arch_interrupt_allowed(vcpu) &&
10092 (kvm_cpu_has_interrupt(vcpu) ||
10093 kvm_guest_apic_has_interrupt(vcpu)))
10096 if (kvm_hv_has_stimer_pending(vcpu))
10102 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10104 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10107 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10109 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10112 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10113 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10114 kvm_test_request(KVM_REQ_EVENT, vcpu))
10117 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10123 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10125 return vcpu->arch.preempted_in_kernel;
10128 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10130 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10133 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10135 return kvm_x86_ops->interrupt_allowed(vcpu);
10138 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10140 if (is_64_bit_mode(vcpu))
10141 return kvm_rip_read(vcpu);
10142 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10143 kvm_rip_read(vcpu));
10145 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10147 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10149 return kvm_get_linear_rip(vcpu) == linear_rip;
10151 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10153 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10155 unsigned long rflags;
10157 rflags = kvm_x86_ops->get_rflags(vcpu);
10158 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10159 rflags &= ~X86_EFLAGS_TF;
10162 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10164 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10166 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10167 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10168 rflags |= X86_EFLAGS_TF;
10169 kvm_x86_ops->set_rflags(vcpu, rflags);
10172 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10174 __kvm_set_rflags(vcpu, rflags);
10175 kvm_make_request(KVM_REQ_EVENT, vcpu);
10177 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10179 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10183 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10187 r = kvm_mmu_reload(vcpu);
10191 if (!vcpu->arch.mmu->direct_map &&
10192 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
10195 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10198 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10200 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10203 static inline u32 kvm_async_pf_next_probe(u32 key)
10205 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10208 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10210 u32 key = kvm_async_pf_hash_fn(gfn);
10212 while (vcpu->arch.apf.gfns[key] != ~0)
10213 key = kvm_async_pf_next_probe(key);
10215 vcpu->arch.apf.gfns[key] = gfn;
10218 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10221 u32 key = kvm_async_pf_hash_fn(gfn);
10223 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10224 (vcpu->arch.apf.gfns[key] != gfn &&
10225 vcpu->arch.apf.gfns[key] != ~0); i++)
10226 key = kvm_async_pf_next_probe(key);
10231 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10233 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10236 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10240 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10242 vcpu->arch.apf.gfns[i] = ~0;
10244 j = kvm_async_pf_next_probe(j);
10245 if (vcpu->arch.apf.gfns[j] == ~0)
10247 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10249 * k lies cyclically in ]i,j]
10251 * |....j i.k.| or |.k..j i...|
10253 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10254 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10259 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10262 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10266 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10269 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10273 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10275 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10278 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10279 (vcpu->arch.apf.send_user_only &&
10280 kvm_x86_ops->get_cpl(vcpu) == 0))
10286 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10288 if (unlikely(!lapic_in_kernel(vcpu) ||
10289 kvm_event_needs_reinjection(vcpu) ||
10290 vcpu->arch.exception.pending))
10293 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10297 * If interrupts are off we cannot even use an artificial
10300 return kvm_x86_ops->interrupt_allowed(vcpu);
10303 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10304 struct kvm_async_pf *work)
10306 struct x86_exception fault;
10308 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10309 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10311 if (kvm_can_deliver_async_pf(vcpu) &&
10312 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10313 fault.vector = PF_VECTOR;
10314 fault.error_code_valid = true;
10315 fault.error_code = 0;
10316 fault.nested_page_fault = false;
10317 fault.address = work->arch.token;
10318 fault.async_page_fault = true;
10319 kvm_inject_page_fault(vcpu, &fault);
10322 * It is not possible to deliver a paravirtualized asynchronous
10323 * page fault, but putting the guest in an artificial halt state
10324 * can be beneficial nevertheless: if an interrupt arrives, we
10325 * can deliver it timely and perhaps the guest will schedule
10326 * another process. When the instruction that triggered a page
10327 * fault is retried, hopefully the page will be ready in the host.
10329 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10333 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10334 struct kvm_async_pf *work)
10336 struct x86_exception fault;
10339 if (work->wakeup_all)
10340 work->arch.token = ~0; /* broadcast wakeup */
10342 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10343 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10345 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10346 !apf_get_user(vcpu, &val)) {
10347 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10348 vcpu->arch.exception.pending &&
10349 vcpu->arch.exception.nr == PF_VECTOR &&
10350 !apf_put_user(vcpu, 0)) {
10351 vcpu->arch.exception.injected = false;
10352 vcpu->arch.exception.pending = false;
10353 vcpu->arch.exception.nr = 0;
10354 vcpu->arch.exception.has_error_code = false;
10355 vcpu->arch.exception.error_code = 0;
10356 vcpu->arch.exception.has_payload = false;
10357 vcpu->arch.exception.payload = 0;
10358 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10359 fault.vector = PF_VECTOR;
10360 fault.error_code_valid = true;
10361 fault.error_code = 0;
10362 fault.nested_page_fault = false;
10363 fault.address = work->arch.token;
10364 fault.async_page_fault = true;
10365 kvm_inject_page_fault(vcpu, &fault);
10368 vcpu->arch.apf.halted = false;
10369 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10372 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10374 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10377 return kvm_can_do_async_pf(vcpu);
10380 void kvm_arch_start_assignment(struct kvm *kvm)
10382 atomic_inc(&kvm->arch.assigned_device_count);
10384 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10386 void kvm_arch_end_assignment(struct kvm *kvm)
10388 atomic_dec(&kvm->arch.assigned_device_count);
10390 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10392 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10394 return atomic_read(&kvm->arch.assigned_device_count);
10396 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10398 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10400 atomic_inc(&kvm->arch.noncoherent_dma_count);
10402 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10404 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10406 atomic_dec(&kvm->arch.noncoherent_dma_count);
10408 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10410 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10412 return atomic_read(&kvm->arch.noncoherent_dma_count);
10414 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10416 bool kvm_arch_has_irq_bypass(void)
10421 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10422 struct irq_bypass_producer *prod)
10424 struct kvm_kernel_irqfd *irqfd =
10425 container_of(cons, struct kvm_kernel_irqfd, consumer);
10427 irqfd->producer = prod;
10429 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10430 prod->irq, irqfd->gsi, 1);
10433 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10434 struct irq_bypass_producer *prod)
10437 struct kvm_kernel_irqfd *irqfd =
10438 container_of(cons, struct kvm_kernel_irqfd, consumer);
10440 WARN_ON(irqfd->producer != prod);
10441 irqfd->producer = NULL;
10444 * When producer of consumer is unregistered, we change back to
10445 * remapped mode, so we can re-use the current implementation
10446 * when the irq is masked/disabled or the consumer side (KVM
10447 * int this case doesn't want to receive the interrupts.
10449 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10451 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10452 " fails: %d\n", irqfd->consumer.token, ret);
10455 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10456 uint32_t guest_irq, bool set)
10458 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10461 bool kvm_vector_hashing_enabled(void)
10463 return vector_hashing;
10466 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10468 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10470 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10472 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10474 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10476 /* The STIBP bit doesn't fault even if it's not advertised */
10477 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10478 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10479 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10480 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10481 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10482 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10484 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10485 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10486 bits &= ~SPEC_CTRL_SSBD;
10487 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10488 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10489 bits &= ~SPEC_CTRL_SSBD;
10493 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10495 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10496 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10497 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10498 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10499 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10500 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10501 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10502 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10503 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10504 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10505 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10506 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10507 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10508 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10509 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10510 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10511 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10512 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10513 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10514 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10515 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);