arch/x86/power/cpu_32.c

   1 /*
   2  * Suspend support specific for i386.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
   7  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   8  */
   9
  10 #include <linux/suspend.h>
  11 #include <linux/smp.h>
  12
  13 #include <asm/pgtable.h>
  14 #include <asm/proto.h>
  15 #include <asm/mtrr.h>
  16 #include <asm/page.h>
  17 #include <asm/mce.h>
  18 #include <asm/xcr.h>
  19 #include <asm/suspend.h>
  20
  21 static struct saved_context saved_context;
  22
  23 unsigned long saved_context_ebx;
  24 unsigned long saved_context_esp, saved_context_ebp;
  25 unsigned long saved_context_esi, saved_context_edi;
  26 unsigned long saved_context_eflags;
  27
  28 static void __save_processor_state(struct saved_context *ctxt)
  29 {
  30         mtrr_save_fixed_ranges(NULL);
  31         kernel_fpu_begin();
  32
  33         /*
  34          * descriptor tables
  35          */
  36         store_gdt(&ctxt->gdt);
  37         store_idt(&ctxt->idt);
  38         store_tr(ctxt->tr);
  39
  40         /*
  41          * segment registers
  42          */
  43         savesegment(es, ctxt->es);
  44         savesegment(fs, ctxt->fs);
  45         savesegment(gs, ctxt->gs);
  46         savesegment(ss, ctxt->ss);
  47
  48         /*
  49          * control registers
  50          */
  51         ctxt->cr0 = read_cr0();
  52         ctxt->cr2 = read_cr2();
  53         ctxt->cr3 = read_cr3();
  54         ctxt->cr4 = read_cr4_safe();
  55 }
  56
  57 /* Needed by apm.c */
  58 void save_processor_state(void)
  59 {
  60         __save_processor_state(&saved_context);
  61 }
  62 EXPORT_SYMBOL(save_processor_state);
  63
  64 static void do_fpu_end(void)
  65 {
  66         /*
  67          * Restore FPU regs if necessary.
  68          */
  69         kernel_fpu_end();
  70 }
  71
  72 static void fix_processor_context(void)
  73 {
  74         int cpu = smp_processor_id();
  75         struct tss_struct *t = &per_cpu(init_tss, cpu);
  76
  77         set_tss_desc(cpu, t);   /*
  78                                  * This just modifies memory; should not be
  79                                  * necessary. But... This is necessary, because
  80                                  * 386 hardware has concept of busy TSS or some
  81                                  * similar stupidity.
  82                                  */
  83
  84         load_TR_desc();                         /* This does ltr */
  85         load_LDT(&current->active_mm->context); /* This does lldt */
  86
  87         /*
  88          * Now maybe reload the debug registers
  89          */
  90         if (current->thread.debugreg7) {
  91                 set_debugreg(current->thread.debugreg0, 0);
  92                 set_debugreg(current->thread.debugreg1, 1);
  93                 set_debugreg(current->thread.debugreg2, 2);
  94                 set_debugreg(current->thread.debugreg3, 3);
  95                 /* no 4 and 5 */
  96                 set_debugreg(current->thread.debugreg6, 6);
  97                 set_debugreg(current->thread.debugreg7, 7);
  98         }
  99
 100 }
 101
 102 static void __restore_processor_state(struct saved_context *ctxt)
 103 {
 104         /*
 105          * control registers
 106          */
 107         /* cr4 was introduced in the Pentium CPU */
 108         if (ctxt->cr4)
 109                 write_cr4(ctxt->cr4);
 110         write_cr3(ctxt->cr3);
 111         write_cr2(ctxt->cr2);
 112         write_cr0(ctxt->cr0);
 113
 114         /*
 115          * now restore the descriptor tables to their proper values
 116          * ltr is done i fix_processor_context().
 117          */
 118         load_gdt(&ctxt->gdt);
 119         load_idt(&ctxt->idt);
 120
 121         /*
 122          * segment registers
 123          */
 124         loadsegment(es, ctxt->es);
 125         loadsegment(fs, ctxt->fs);
 126         loadsegment(gs, ctxt->gs);
 127         loadsegment(ss, ctxt->ss);
 128
 129         /*
 130          * sysenter MSRs
 131          */
 132         if (boot_cpu_has(X86_FEATURE_SEP))
 133                 enable_sep_cpu();
 134
 135         /*
 136          * restore XCR0 for xsave capable cpu's.
 137          */
 138         if (cpu_has_xsave)
 139                 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
 140
 141         fix_processor_context();
 142         do_fpu_end();
 143         mtrr_ap_init();
 144         mcheck_init(&boot_cpu_data);
 145 }
 146
 147 /* Needed by apm.c */
 148 void restore_processor_state(void)
 149 {
 150         __restore_processor_state(&saved_context);
 151 }
 152 EXPORT_SYMBOL(restore_processor_state);