1 /* drm.h -- Header for Direct Rendering Manager -*- linux-c -*-
2 * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
31 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
38 #include <sys/ioccom.h>
39 #define DRM_IOCTL_NR(n) ((n) & 0xff)
41 #define XFREE86_VERSION(major,minor,patch,snap) \
42 ((major << 16) | (minor << 8) | patch)
44 #ifndef CONFIG_XFREE86_VERSION
45 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
48 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
49 #define DRM_PROC_DEVICES "/proc/devices"
50 #define DRM_PROC_MISC "/proc/misc"
51 #define DRM_PROC_DRM "/proc/drm"
52 #define DRM_DEV_DRM "/dev/drm"
53 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
58 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
60 #define DRM_MAX_MINOR 15
62 #define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
63 #define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
64 #define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
65 #define DRM_RAM_PERCENT 50 /* How much system ram can we lock? */
67 #define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */
68 #define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */
69 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
70 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
71 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
73 typedef unsigned long drm_handle_t;
74 typedef unsigned int drm_context_t;
75 typedef unsigned int drm_drawable_t;
76 typedef unsigned int drm_magic_t;
78 /* Warning: If you change this structure, make sure you change
79 * XF86DRIClipRectRec in the server as well */
81 typedef struct drm_clip_rect {
88 typedef struct drm_tex_region {
92 unsigned char padding;
96 typedef struct drm_version {
97 int version_major; /* Major version */
98 int version_minor; /* Minor version */
99 int version_patchlevel;/* Patch level */
100 size_t name_len; /* Length of name buffer */
101 char *name; /* Name of driver */
102 size_t date_len; /* Length of date buffer */
103 char *date; /* User-space buffer to hold date */
104 size_t desc_len; /* Length of desc buffer */
105 char *desc; /* User-space buffer to hold desc */
108 typedef struct drm_unique {
109 size_t unique_len; /* Length of unique */
110 char *unique; /* Unique name for driver instantiation */
113 typedef struct drm_list {
114 int count; /* Length of user-space structures */
115 drm_version_t *version;
118 typedef struct drm_block {
122 typedef struct drm_control {
132 typedef enum drm_map_type {
133 _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */
134 _DRM_REGISTERS = 1, /* no caching, no core dump */
135 _DRM_SHM = 2, /* shared, cached */
136 _DRM_AGP = 3, /* AGP/GART */
137 _DRM_SCATTER_GATHER = 4 /* Scatter/gather memory for PCI DMA */
140 typedef enum drm_map_flags {
141 _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */
142 _DRM_READ_ONLY = 0x02,
143 _DRM_LOCKED = 0x04, /* shared, cached, locked */
144 _DRM_KERNEL = 0x08, /* kernel requires access */
145 _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */
146 _DRM_CONTAINS_LOCK = 0x20, /* SHM page that contains lock */
147 _DRM_REMOVABLE = 0x40 /* Removable mapping */
150 typedef struct drm_ctx_priv_map {
151 unsigned int ctx_id; /* Context requesting private mapping */
152 void *handle; /* Handle of map */
153 } drm_ctx_priv_map_t;
155 typedef struct drm_map {
156 unsigned long offset; /* Requested physical address (0 for SAREA)*/
157 unsigned long size; /* Requested physical size (bytes) */
158 drm_map_type_t type; /* Type of memory to map */
159 drm_map_flags_t flags; /* Flags */
160 void *handle; /* User-space: "Handle" to pass to mmap */
161 /* Kernel-space: kernel-virtual address */
162 int mtrr; /* MTRR slot used */
166 typedef struct drm_client {
167 int idx; /* Which client desired? */
168 int auth; /* Is client authenticated? */
169 unsigned long pid; /* Process id */
170 unsigned long uid; /* User id */
171 unsigned long magic; /* Magic */
172 unsigned long iocs; /* Ioctl count */
182 _DRM_STAT_VALUE, /* Generic value */
183 _DRM_STAT_BYTE, /* Generic byte counter (1024bytes/K) */
184 _DRM_STAT_COUNT, /* Generic non-byte counter (1000/k) */
186 _DRM_STAT_IRQ, /* IRQ */
187 _DRM_STAT_PRIMARY, /* Primary DMA bytes */
188 _DRM_STAT_SECONDARY, /* Secondary DMA bytes */
189 _DRM_STAT_DMA, /* DMA */
190 _DRM_STAT_SPECIAL, /* Special DMA (e.g., priority or polled) */
191 _DRM_STAT_MISSED /* Missed DMA opportunity */
193 /* Add to the *END* of the list */
196 typedef struct drm_stats {
200 drm_stat_type_t type;
204 typedef enum drm_lock_flags {
205 _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */
206 _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */
207 _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */
208 _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */
209 /* These *HALT* flags aren't supported yet
210 -- they will be used to support the
211 full-screen DGA-like mode. */
212 _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */
213 _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */
216 typedef struct drm_lock {
218 drm_lock_flags_t flags;
221 typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */
222 /* Flags for DMA buffer dispatch */
223 _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched.
224 Note, the buffer may not yet have
225 been processed by the hardware --
226 getting a hardware lock with the
227 hardware quiescent will ensure
228 that the buffer has been
230 _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */
231 _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */
233 /* Flags for DMA buffer request */
234 _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */
235 _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */
236 _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */
239 typedef struct drm_buf_desc {
240 int count; /* Number of buffers of this size */
241 int size; /* Size in bytes */
242 int low_mark; /* Low water mark */
243 int high_mark; /* High water mark */
245 _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */
246 _DRM_AGP_BUFFER = 0x02, /* Buffer is in agp space */
247 _DRM_SG_BUFFER = 0x04 /* Scatter/gather memory buffer */
249 unsigned long agp_start; /* Start address of where the agp buffers
250 * are in the agp aperture */
253 typedef struct drm_buf_info {
254 int count; /* Entries in list */
255 drm_buf_desc_t *list;
258 typedef struct drm_buf_free {
263 typedef struct drm_buf_pub {
264 int idx; /* Index into master buflist */
265 int total; /* Buffer size */
266 int used; /* Amount of buffer in use (for DMA) */
267 void *address; /* Address of buffer */
270 typedef struct drm_buf_map {
271 int count; /* Length of buflist */
272 void *virtual; /* Mmaped area in user-virtual */
273 drm_buf_pub_t *list; /* Buffer information */
276 typedef struct drm_dma {
277 /* Indices here refer to the offset into
278 buflist in drm_buf_get_t. */
279 int context; /* Context handle */
280 int send_count; /* Number of buffers to send */
281 int *send_indices; /* List of handles to buffers */
282 int *send_sizes; /* Lengths of data to send */
283 drm_dma_flags_t flags; /* Flags */
284 int request_count; /* Number of buffers requested */
285 int request_size; /* Desired size for buffers */
286 int *request_indices; /* Buffer information */
288 int granted_count; /* Number of buffers granted */
292 _DRM_CONTEXT_PRESERVED = 0x01,
293 _DRM_CONTEXT_2DONLY = 0x02
296 typedef struct drm_ctx {
297 drm_context_t handle;
298 drm_ctx_flags_t flags;
301 typedef struct drm_ctx_res {
306 typedef struct drm_draw {
307 drm_drawable_t handle;
310 typedef struct drm_auth {
314 typedef struct drm_irq_busid {
321 typedef struct drm_agp_mode {
325 /* For drm_agp_alloc -- allocated a buffer */
326 typedef struct drm_agp_buffer {
327 unsigned long size; /* In bytes -- will round to page boundary */
328 unsigned long handle; /* Used for BIND/UNBIND ioctls */
329 unsigned long type; /* Type of memory to allocate */
330 unsigned long physical; /* Physical used by i810 */
333 /* For drm_agp_bind */
334 typedef struct drm_agp_binding {
335 unsigned long handle; /* From drm_agp_buffer */
336 unsigned long offset; /* In bytes -- will round to page boundary */
339 typedef struct drm_agp_info {
340 int agp_version_major;
341 int agp_version_minor;
343 unsigned long aperture_base; /* physical address */
344 unsigned long aperture_size; /* bytes */
345 unsigned long memory_allowed; /* bytes */
346 unsigned long memory_used;
348 /* PCI information */
349 unsigned short id_vendor;
350 unsigned short id_device;
353 typedef struct drm_scatter_gather {
354 unsigned long size; /* In bytes -- will round to page boundary */
355 unsigned long handle; /* Used for mapping / unmapping */
356 } drm_scatter_gather_t;
358 #define DRM_IOCTL_BASE 'd'
359 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
360 #define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
361 #define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
362 #define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
365 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
366 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
367 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
368 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
369 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
370 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
371 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
373 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
374 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
375 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
376 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
377 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
378 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
379 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
380 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
381 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
382 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
383 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
385 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
387 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
388 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
390 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
391 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
392 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
393 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
394 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
395 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
396 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
397 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
398 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
399 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
400 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
401 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
402 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
404 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
405 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
406 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
407 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
408 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
409 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
410 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
411 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
413 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
414 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
416 /* Device specfic ioctls should only be in their respective headers
417 * The device specific ioctl range is 0x40 to 0x79. */
418 #define DRM_COMMAND_BASE 0x40