2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Gareth Hughes <gareth@valinux.com>
29 /** @file ati_pcigart.c
30 * Implementation of ATI's PCIGART, which provides an aperture in card virtual
31 * address space with addresses remapped to system memory.
36 #define ATI_PCIGART_PAGE_SIZE 4096 /* PCI GART page size */
37 #define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
39 #define ATI_PCIE_WRITE 0x4
40 #define ATI_PCIE_READ 0x8
43 drm_ati_alloc_pcigart_table_cb(void *arg, bus_dma_segment_t *segs,
46 struct drm_dma_handle *dmah = arg;
52 ("drm_ati_alloc_pcigart_table_cb: bad dma segment count"));
54 dmah->busaddr = segs[0].ds_addr;
58 drm_ati_alloc_pcigart_table(struct drm_device *dev,
59 struct drm_ati_pcigart_info *gart_info)
61 struct drm_dma_handle *dmah;
64 dmah = malloc(sizeof(struct drm_dma_handle), DRM_MEM_DMA,
70 ret = bus_dma_tag_create(NULL, PAGE_SIZE, 0, /* tag, align, boundary */
71 gart_info->table_mask, BUS_SPACE_MAXADDR, /* lowaddr, highaddr */
72 NULL, NULL, /* filtfunc, filtfuncargs */
73 gart_info->table_size, 1, /* maxsize, nsegs */
74 gart_info->table_size, /* maxsegsize */
75 BUS_DMA_ALLOCNOW, NULL, NULL, /* flags, lockfunc, lockfuncargs */
78 free(dmah, DRM_MEM_DMA);
82 flags = BUS_DMA_NOWAIT | BUS_DMA_ZERO;
83 if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
84 flags |= BUS_DMA_NOCACHE;
86 ret = bus_dmamem_alloc(dmah->tag, &dmah->vaddr, flags, &dmah->map);
88 bus_dma_tag_destroy(dmah->tag);
89 free(dmah, DRM_MEM_DMA);
94 ret = bus_dmamap_load(dmah->tag, dmah->map, dmah->vaddr,
95 gart_info->table_size, drm_ati_alloc_pcigart_table_cb, dmah, 0);
97 bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
98 bus_dma_tag_destroy(dmah->tag);
99 free(dmah, DRM_MEM_DMA);
103 dev->sg->dmah = dmah;
109 drm_ati_free_pcigart_table(struct drm_device *dev,
110 struct drm_ati_pcigart_info *gart_info)
112 struct drm_dma_handle *dmah = dev->sg->dmah;
114 bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
115 bus_dma_tag_destroy(dmah->tag);
116 free(dmah, DRM_MEM_DMA);
117 dev->sg->dmah = NULL;
121 drm_ati_pcigart_cleanup(struct drm_device *dev,
122 struct drm_ati_pcigart_info *gart_info)
124 /* we need to support large memory configurations */
125 if (dev->sg == NULL) {
126 DRM_ERROR("no scatter/gather memory!\n");
130 if (gart_info->bus_addr) {
131 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
132 gart_info->bus_addr = 0;
134 drm_ati_free_pcigart_table(dev, gart_info);
142 drm_ati_pcigart_init(struct drm_device *dev,
143 struct drm_ati_pcigart_info *gart_info)
145 void *address = NULL;
147 u32 *pci_gart, page_base;
148 dma_addr_t bus_address = 0;
149 dma_addr_t entry_addr;
153 /* we need to support large memory configurations */
154 if (dev->sg == NULL) {
155 DRM_ERROR("no scatter/gather memory!\n");
159 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
160 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
162 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
164 DRM_ERROR("cannot allocate PCI GART page!\n");
168 address = (void *)dev->sg->dmah->vaddr;
169 bus_address = dev->sg->dmah->busaddr;
171 address = gart_info->addr;
172 bus_address = gart_info->bus_addr;
173 DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n",
174 (unsigned int)bus_address, (unsigned long)address);
177 pci_gart = (u32 *) address;
179 max_pages = (gart_info->table_size / sizeof(u32));
180 pages = (dev->sg->pages <= max_pages)
181 ? dev->sg->pages : max_pages;
183 memset(pci_gart, 0, max_pages * sizeof(u32));
185 KASSERT(PAGE_SIZE >= ATI_PCIGART_PAGE_SIZE, ("page size too small"));
187 for (i = 0; i < pages; i++) {
188 entry_addr = dev->sg->busaddr[i];
189 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
190 page_base = (u32) entry_addr & ATI_PCIGART_PAGE_MASK;
191 switch(gart_info->gart_reg_if) {
192 case DRM_ATI_GART_IGP:
194 (upper_32_bits(entry_addr) & 0xff) << 4;
197 case DRM_ATI_GART_PCIE:
200 (upper_32_bits(entry_addr) & 0xff) << 24;
201 page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
204 case DRM_ATI_GART_PCI:
207 *pci_gart = cpu_to_le32(page_base);
209 entry_addr += ATI_PCIGART_PAGE_SIZE;
216 gart_info->addr = address;
217 gart_info->bus_addr = bus_address;