1 ; cpu description for debugging and experimental purposes. -*- Scheme -*-
2 ; This file is part of CGEN.
3 ; See file COPYING.CGEN for details.
4 ; Copyright (C) 2000 Red Hat, Inc.
6 ; This file is for experimental purposes. Don't expect it to be correct
9 (include "simplify.inc")
12 (name play) ; name of cpu
13 (comment "experimental .cpu file")
21 (base-insn-bitsize 16)
22 (decode-assist (0 1 2 3))
27 (comment "experimental cpu family")
34 (comment "experimental mach")
39 (name test) (comment "test") (attrs)
41 ;(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
42 (unit u-exec "Execution Unit" () 1 1
47 ; Copies of all the variations.
49 ; little endian, lsb0? = #f
50 ;(dnf f-op1 "op1" () 0 4)
51 ;(dnf f-op2 "op2" () 4 4)
52 ;(dnf f-op3 "op3" () 8 4)
53 ;(dnf f-op4 "op4" () 12 4)
54 ;(dnf f-r1 "r1" () 8 4)
55 ;(dnf f-r2 "r2" () 12 4)
56 ;(df f-simm16 "simm16" () 16 16 INT #f #f)
57 ;(df f-simm16b "16 bit signed immediate after simm32" () 48 16 INT #f #f)
58 ;(df f-simm32 "simm32" () 16 32 INT #f #f)
59 ;(df f-simm32b "32 bit signed immediate after simm16" () 32 32 INT #f #f)
61 ; little endian, lsb0? = #t
62 (dnf f-op1 "op1" () 15 4)
63 (dnf f-op2 "op2" () 11 4)
64 (dnf f-op3 "op3" () 7 4)
65 (dnf f-op4 "op4" () 3 4)
66 (dnf f-r1 "r1" () 7 4)
67 (dnf f-r2 "r2" () 3 4)
68 (df f-simm16 "simm16" () 31 16 INT #f #f)
69 (df f-simm16b "16 bit signed immediate after simm32" () 63 16 INT #f #f)
70 (df f-simm32 "simm32" () 47 32 INT #f #f)
71 (df f-simm32b "32 bit signed immediate after simm16" () 63 32 INT #f #f)
73 ; big endian, lsb0? = #f
74 ;(dnf f-op1 "op1" () 0 4)
75 ;(dnf f-op2 "op2" () 4 4)
76 ;(dnf f-op3 "op3" () 8 4)
77 ;(dnf f-op4 "op4" () 12 4)
78 ;(dnf f-r1 "r1" () 8 4)
79 ;(dnf f-r2 "r2" () 12 4)
80 ;(df f-simm16 "simm16" () 16 16 INT #f #f)
81 ;(df f-simm16b "16 bit signed immediate after simm32" () 48 16 INT #f #f)
82 ;(df f-simm32 "simm32" () 16 32 INT #f #f)
83 ;(df f-simm32b "32 bit signed immediate after simm16" () 32 32 INT #f #f)
85 ; big endian, lsb0? = #t
86 ;(dnf f-op1 "op1" () 15 4)
87 ;(dnf f-op2 "op2" () 11 4)
88 ;(dnf f-op3 "op3" () 7 4)
89 ;(dnf f-op4 "op4" () 3 4)
90 ;(dnf f-r1 "r1" () 7 4)
91 ;(dnf f-r2 "r2" () 3 4)
92 ;(df f-simm16 "simm16" () 31 16 INT #f #f)
93 ;(df f-simm16b "16 bit signed immediate after simm32" () 63 16 INT #f #f)
94 ;(df f-simm32 "simm32" () 47 32 INT #f #f)
95 ;(df f-simm32b "32 bit signed immediate after simm16" () 63 32 INT #f #f)
97 (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
98 (.map .str (.iota 16))
101 (define-normal-insn-enum insn-op2 "insn format enums (2)" () OP2_ f-op2
102 (.map .str (.iota 16))
105 (define-normal-insn-enum insn-op3 "insn format enums (3)" () OP3_ f-op3
106 (.map .str (.iota 16))
109 (define-normal-insn-enum insn-op4 "insn format enums (4)" () OP4_ f-op4
110 (.map .str (.iota 16))
115 (dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
119 (comment "general registers")
120 (attrs PROFILE );CACHE-ADDR)
121 (type register WI (16))
123 ( (fp 13) (lr 14) (sp 15)
124 (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
125 (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)
131 (comment "status reg")
137 ; These bits are actualy part of the PS register
138 (dsh h-nbit "negative bit" () (register BI))
139 (dsh h-zbit "zero bit" () (register BI))
140 (dsh h-vbit "overflow bit" () (register BI))
141 (dsh h-cbit "carry bit" () (register BI))
143 (dsh h-df "df test" () (register DF))
144 (dsh h-tf "tf test" () (register TF))
146 ; Operand attributes.
152 (comment "immediates have a '#' prefix")
157 (dnop nbit "negative bit" (SEM-ONLY) h-nbit f-nil)
158 (dnop vbit "overflow bit" (SEM-ONLY) h-vbit f-nil)
159 (dnop zbit "zero bit" (SEM-ONLY) h-zbit f-nil)
160 (dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil)
162 (dnop dr "destination register" () h-gr f-r1)
163 (dnop sr "source register" () h-gr f-r2)
164 (dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16)
165 (dnop simm16b "16 bit signed immediate after simm32" (HASH-PREFIX) h-sint f-simm16b)
166 (dnop simm32 "32 bit signed immediate" (HASH-PREFIX) h-sint f-simm32)
167 (dnop simm32b "32 bit signed immediate after simm16" (HASH-PREFIX) h-sint f-simm32b)
169 ; Note that `df' doesn't work as that is a pmacro.
170 (dnop df-reg "df reg" () h-df f-nil)
171 (dnop tf-reg "tf reg" () h-tf f-nil)
178 ; Use (f-op1 OP1_4) to exercise it.
179 (+ (f-op1 OP1_4) OP2_0 dr sr)
181 (set vbit (add-oflag dr sr (const 0)))
182 (set cbit (add-cflag dr sr (const 0)))
184 (set zbit (zflag dr))
185 (set nbit (nflag dr)))
189 (dni addv2 "add version 2"
192 (+ OP1_4 OP2_1 dr sr)
193 (sequence ((WI tmp1))
195 (set tmp1 (add dr sr))
196 (set vbit (add-oflag dr sr (const 0)))
197 (set cbit (add-cflag dr sr (const 0))))
198 (set zbit (zflag tmp1))
199 (set nbit (nflag tmp1))
207 "addi16 $dr,$sr,$simm16"
208 (+ OP1_4 OP2_2 dr sr simm16)
209 (set dr (add sr simm16))
215 "addi32 $dr,$sr,$simm32"
216 (+ OP1_4 OP2_3 dr sr simm32)
217 (set dr (add sr simm32))
221 (define-pmacro (reg+ oprnd n)
222 (reg h-gr (add (index-of oprnd) (const n)))
228 (+ OP1_5 OP2_2 dr sr)
231 (set (reg+ dr 1) (reg+ sr 1))
236 (dni use-ifield "use-ifield"
239 (+ OP1_5 OP2_3 dr sr)
241 (set dr (ifield f-r2))
246 (dni use-index-of "index-of"
249 (+ OP1_5 OP2_4 dr sr)
250 (set dr (reg h-gr (add (index-of sr) (const 1))))
254 (dni load-df "use df"
257 (+ OP1_6 OP2_0 OP3_0 sr)
258 (set df-reg (mem DF sr))
262 (dni make-df "use df"
265 (+ OP1_6 OP2_1 OP3_0 sr)
266 (set df-reg (join DF SI (mem SI sr) (mem SI (add sr (const 4)))))
270 (dni split-df "use df"
273 (+ OP1_6 OP2_2 OP3_0 sr)
274 (sequence ((DF temp))
278 (reg h-gr (add (regno sr) (const 1))))
284 (dni load-tf "use tf"
287 (+ OP1_6 OP2_3 OP3_0 sr)
288 (set tf-reg (mem TF sr))
292 (dni make-tf "use tf"
295 (+ OP1_6 OP2_4 OP3_0 sr)
296 (set tf-reg (join TF SI
298 (reg h-gr (add (regno sr) (const 1)))
299 (reg h-gr (add (regno sr) (const 2)))
300 (reg h-gr (add (regno sr) (const 3)))))
304 (dni split-tf "use tf"
307 (+ OP1_6 OP2_5 OP3_0 sr)
308 (sequence ((TF temp))
310 (set (concat (SI SI SI SI)
312 (reg h-gr (add (regno sr) (const 1)))
313 (reg h-gr (add (regno sr) (const 2)))
314 (reg h-gr (add (regno sr) (const 3))))
320 ;;(define-pmacro (no-ext-expr mode expr) expr)
321 ;;(define-pmacro (ext-expr mode expr) (ext mode expr))
322 ;;(define-pmacro (zext-expr mode expr) (zext mode expr))
324 (define-pmacro (load-op suffix op2-op mode ext-op)
326 (no-ext-expr (.pmacro (mode expr) expr))
327 (ext-expr (.pmacro (mode expr) (ext mode expr)))
328 (zext-expr (.pmacro (mode expr) (zext mode expr)))
331 (dni (.sym ld suffix) (.str "ld" suffix)
333 (.str "ld" suffix " $dr,@@$sr")
334 (+ OP1_2 op2-op dr sr)
335 (set dr (ext-op WI (mem mode sr)))
341 (load-op "" OP2_12 WI no-ext-expr)
342 (load-op b OP2_8 QI ext-expr)
343 (load-op h OP2_10 HI ext-expr)
344 (load-op ub OP2_9 QI zext-expr)
345 (load-op uh OP2_11 HI zext-expr)