1 ; SPARC64 CPU description. -*- Scheme -*-
2 ; This file contains elements specific to sparc64.
3 ; Copyright (C) 2000 Red Hat, Inc.
4 ; This file is part of CGEN.
5 ; See file COPYING.CGEN for details.
8 ; - sparc64 support wip
10 ; - source file layout wip
11 ; - cpu family layout wip
13 ; ??? For the nonce there is one cpu family to cover all 64 bit sparcs.
14 ; It's not clear this will work, but following the goal of incremental
19 (comment "SPARC 64 bit architecture")
20 (endian big) ; ??? big insn, either data
22 ; Generated files have a "64" suffix.
36 (comment "sparc v9a (sparc-v9 + vis)")
39 (bfd-name "sparc_v9a")
46 (comment "sparc64 default")
49 ; wip (Meaning, yes I know this is inaccurate, duh ...
50 ; When I have time I'll finish this up right.
51 ; Support for some of this isn't even implemented yet and support for the
52 ; rest will be rewritten.)
53 (pipeline p-foo "" () ((fetch) (decode) (execute) (memory) (writeback)))
54 (unit u-exec "Execution Unit" ()
59 ; sparc64 instruction fields
61 (dnf f-fmt2-cc1 "cc" ((MACH64)) 21 1)
62 (dnf f-fmt2-cc0 "cc" ((MACH64)) 20 1)
63 (dnf f-p "p" ((MACH64)) 19 1)
64 (dnf f-fmt2-rcond "fmt2 rcond" ((MACH64)) 27 3)
65 (df f-disp19 "disp19" (PCREL-ADDR (MACH64)) 13 19 INT #f #f)
66 (dnf f-fmt3-rcond "fmt3 rcond" ((MACH64)) 19 3)
67 (dnf f-shcnt64 "shcnt64" ((MACH64)) 5 6)
68 (dnf f-fmt4-cond "cond" ((MACH64)) 14 4)
69 (dnf f-fmt4-ccx-hi "ccx hi" ((MACH64)) 13 1)
70 (dnf f-fmt4-ccx-lo "ccx lo" ((MACH64)) 19 2)
71 (dnf f-fmt4-rcond "fmt4 rcond" ((MACH64)) 19 3)
72 (dnf f-fmt4-cc2 "fmt4 cc2" ((MACH64)) 18 1)
73 (dnf f-fmt4-cc1-0 "fmt4 cc1,cc0" ((MACH64)) 12 2)
74 (dnf f-fmt4-res10-6 "reserved bits in movcc insns" (RESERVED (MACH64)) 10 6)
76 ; The disp16 field requires a bit of special handling as it is split in two.
77 (df f-disp16-hi "disp16 hi" ((MACH64)) 10 2 INT #f #f)
78 (dnf f-disp16-lo "disp16 lo" ((MACH64)) 18 14)
79 (dnmf f-disp16 "disp16" (PCREL-ADDR (MACH64)) INT
80 (f-disp16-hi f-disp16-lo)
82 (set (ifield f-disp16-hi) (srl (ifield f-disp16) (const 14)))
83 (set (ifield f-disp16-lo) (and (ifield f-disp16) (const #x3fff)))
85 (sequence () ; extract
86 ; ??? where will pc be added?
87 (set (ifield f-disp16) (or (sll (ifield f-disp16-hi) (const 14))
88 (ifield f-disp16-low)))
92 (dnf f-res-18-19 "reserved bits in done/retry" (RESERVED (MACH64)) 18 19)
94 ; sparc64 enums of opcodes, special insn values, etc.
96 (define-normal-insn-enum insn-rcond "rcond op values" () RCOND_ f-fmt2-rcond
107 ; sparc64 hardware pieces.
109 (dsh h-ver "version" ((MACH64)) (register UDI))
111 (dsh h-pstate "processor state" ((MACH64)) (register UDI))
113 (dsh h-tba "trap base address" ((MACH64)) (register UDI))
115 ; FIXME: These are a stack of values.
116 (dsh h-tt "trap type" ((MACH64)) (register UDI))
117 (dsh h-tpc "trap pc" ((MACH64)) (register UDI))
118 (dsh h-tnpc "trap npc" ((MACH64)) (register UDI))
119 (dsh h-tstate "trap state" ((MACH64)) (register UDI))
121 (dsh h-tl "trap level" ((MACH64)) (register UQI))
123 (dsh h-asi "address space identifier" ((MACH64)) (register UQI))
125 (dsh h-tick "tick counter" ((MACH64)) (register UDI))
127 (dsh h-cansave "savable window registers" ((MACH64)) (register UDI))
128 (dsh h-canrestore "restorable window registers" ((MACH64)) (register UDI))
129 (dsh h-otherwin "other window registers" ((MACH64)) (register UDI))
130 (dsh h-cleanwin "clean window registers" ((MACH64)) (register UDI))
132 (dsh h-wstate "window state" ((MACH64)) (register UDI))
136 (comment "condition code selector")
138 (type immediate (UINT 1))
139 (values keyword "%" (("icc" 0) ("xcc" 1)))
144 (comment "prediction bit")
146 (type immediate (UINT 1))
147 (values keyword "" (("" 0) (",pf" 0) (",pt" 1)))
152 (dnop ixcc "%icc,%xcc arg to bpcc insns" ((MACH64)) h-ixcc f-fmt2-cc1)
154 (dnop p "prediction bit" ((MACH64)) h-p f-p)
156 (dnop disp16 "16 bit displacement" ((MACH64)) h-iaddr f-disp16)
157 (dnop disp19 "19 bit displacement" ((MACH64)) h-iaddr f-disp19)
161 (dnf f-bpr-res28-1 "reserved bit 28 in bpr insn" (RESERVED (MACH64)) 28 1)
163 (define-pmacro (bpr-cbranch name comment rcond-op comp-op)
164 (dni name (.str comment ", v9 page 136")
166 (.str name "$a$p $rs1,$disp16")
167 (+ OP_0 a (f-bpr-res28-1 0) (.sym RCOND_ rcond-op)
168 OP2_BPR p rs1 disp16)
170 (if (comp-op rs1 (const 0))
175 (bpr-cbranch beqz "beqz" BRZ eq)
176 (bpr-cbranch bgez "bgez" BRGEZ ge)
177 (bpr-cbranch bgtz "bgtz" BRGZ gt)
178 (bpr-cbranch blez "blez" BRLEZ le)
179 (bpr-cbranch bltz "bltz" BRLZ lt)
180 (bpr-cbranch bnez "bnez" BRNZ ne)
182 (define-pmacro (bpcc-branch bname comment cond test br-sem)
183 (dni (.sym bpcc- bname)
184 (.str "branch with prediction %icc " comment ", v9 page 146")
186 (.str bname "$a$p %icc,$disp19")
187 (+ OP_0 a cond OP2_BPCC (f-fmt2-cc1 0) (f-fmt2-cc0 0) p disp19)
190 (dni (.sym bpcc- bname)
191 (.str "branch with prediction %xcc " comment ", v9 page 146")
193 (.str bname "$a$p %xcc,$disp19")
194 (+ OP_0 a cond OP2_BPCC (f-fmt2-cc1 1) (f-fmt2-cc0 0) p disp19)
198 ; test-*,uncond-br-sem,cond-br-sem are defined in sparc.cpu.
199 (bpcc-branch ba "always" CC_A test-always uncond-br-sem)
200 (bpcc-branch bn "never" CC_N test-never uncond-br-sem)
201 (bpcc-branch bne "ne" CC_NE test-ne cond-br-sem)
202 (bpcc-branch be "eq" CC_E test-eq cond-br-sem)
203 (bpcc-branch bg "gt" CC_G test-gt cond-br-sem)
204 (bpcc-branch ble "le" CC_LE test-le cond-br-sem)
205 (bpcc-branch bge "ge" CC_GE test-ge cond-br-sem)
206 (bpcc-branch bl "lt" CC_L test-lt cond-br-sem)
207 (bpcc-branch bgu "gtu" CC_GU test-gtu cond-br-sem)
208 (bpcc-branch bleu "leu" CC_LEU test-leu cond-br-sem)
209 (bpcc-branch bcc "geu" CC_CC test-geu cond-br-sem)
210 (bpcc-branch bcs "ltu" CC_CS test-ltu cond-br-sem)
211 (bpcc-branch bpos "pos" CC_POS test-pos cond-br-sem)
212 (bpcc-branch bneg "neg" CC_NEG test-neg cond-br-sem)
213 (bpcc-branch bvc "vc" CC_VC test-vc cond-br-sem)
214 (bpcc-branch bvs "vs" CC_VS test-vs cond-br-sem)
218 (dni done "done, v9 page 155" ((MACH64))
220 (+ OP_2 (f-fcn 0) OP3_DONE_RETRY (f-res-18-19 0))
221 (c-call "@cpu@_done" pc)
224 (dni retry "retry, v9 page 155" ((MACH64))
226 (+ OP_2 (f-fcn 1) OP3_DONE_RETRY (f-res-18-19 0))
227 (c-call "@cpu@_retry" pc)
231 (dni flush "flush instruction memory rs1+rs2, v9 page 165" ((MACH64))
233 (+ OP_2 (f-rd 0) OP3_FLUSH rs1 (f-i 0) (f-res-asi 0) rs2)
234 (c-call "@cpu@_flush" pc (add rs1 rs2))
237 (dni flush-imm "flush instruction memory rs1+simm13, v9 page 165" ((MACH64))
239 (+ OP_2 (f-rd 0) OP3_FLUSH rs1 (f-i 1) simm13)
240 (c-call "@cpu@_flush" pc (add rs1 simm13))
244 (dni flushw "flush register windows, v9 page 167" ((MACH64))
246 (+ OP_2 (f-rd 0) OP3_FLUSHW (f-rs1 0) (f-i 0) (f-simm13 0))
247 (c-call "@cpu@_flushw" pc)
251 ; On sparc64 unimp is called illtrap.
253 (dnmi illtrap "illegal instruction trap, v9 page 168" ((MACH64))
260 (dnf f-impdep5 "5 bit field in impdep insns" ((MACH64)) 29 5)
261 (dnf f-impdep19 "19 bit field in impdep insns" ((MACH64)) 18 19)
263 (dnop impdep5 "5 bit arg in impdep insns" ((MACH64)) h-uint f-impdep5)
264 (dnop impdep19 "19 bit arg in impdep insns" ((MACH64)) h-uint f-impdep19)
266 (dni impdep1 "implementation dependent instruction 1, v9 page 169"
268 "impdep1 $impdep5,$impdep19"
269 (+ OP_2 impdep5 OP3_IMPDEP1 impdep19)
270 (c-call "@cpu@_impdep1" pc impdep5 impdep19)
273 (dni impdep2 "implementation dependent instruction 1, v9 page 169"
275 "impdep2 $impdep5,$impdep19"
276 (+ OP_2 impdep5 OP3_IMPDEP2 impdep19)
277 (c-call "@cpu@_impdep2" pc impdep5 impdep19)
281 ; Memory barrier insn
283 (dnf f-membar-res12-6 "reserved bits 12-7 in membar insn"
284 (RESERVED (MACH64)) 12 6)
285 (dnf f-cmask "cmask field in membar insn" ((MACH64)) 6 3)
286 (dnf f-mmask "mmask field in membar insn" ((MACH64)) 3 4)
287 (dnf f-membarmask "cmask+mmask field in membar insn" ((MACH64)) 6 7)
291 (comment "membar mask")
293 (type immediate (UINT 7))
307 (comment "cmask+mmask arg in membar insn")
311 (handlers (parse "membar_mask")
312 (print "membar_mask"))
315 (dni membar "memory barrier, v9 page 183"
317 "member $membarmask" ; ${membar-mask}
318 (+ OP_2 (f-rd 0) OP3_MEMBAR (f-rs1 15) (f-i 1) (f-membar-res12-6 0)
320 (c-call "@cpu@_membar" pc membarmask)
324 ; Conditional move insns
326 (df f-simm11 "11 bit signed immediate field" ((MACH64)) 10 11 INT #f #f)
328 (dnop simm11 "11 bit signed immediate arg to condition move insns"
329 ((MACH64)) h-sint f-simm11)
331 (define-pmacro (cond-move-1 name comment mnemonic cc-prefix cc-name cc-opcode
332 src-name src-opcode cond test)
334 (.str "move %" cc-name " " comment ", v9 page 191")
336 (.str mnemonic " " cc-prefix cc-name ",$" src-name ",$rd")
337 (.splice + OP_2 rd OP3_MOVCC cond
338 (.unsplice cc-opcode) (.unsplice src-opcode))
344 (define-pmacro (cond-move name comment cond test)
346 (cond-move-1 (.sym name -icc) comment
347 name "%" icc ((f-fmt4-cc2 1) (f-fmt4-cc1-0 0))
348 rs2 ((f-i 0) (f-fmt4-res10-6 0) rs2)
350 (cond-move-1 (.sym name -imm-icc) comment
351 name "%" icc ((f-fmt4-cc2 1) (f-fmt4-cc1-0 0))
352 simm11 ((f-i 1) simm11)
354 (cond-move-1 (.sym name -xcc) comment
355 name "%" xcc ((f-fmt4-cc2 1) (f-fmt4-cc1-0 2))
356 rs2 ((f-i 0) (f-fmt4-res10-6 0) rs2)
358 (cond-move-1 (.sym name -imm-xcc) comment
359 name "%" xcc ((f-fmt4-cc2 1) (f-fmt4-cc1-0 2))
360 simm11 ((f-i 1) simm11)
364 ; test-* are defined in sparc.cpu.
365 (cond-move mova "always" CC_A test-always)
366 (cond-move movn "never" CC_N test-never)
367 (cond-move movne "ne" CC_NE test-ne)
368 (cond-move move "eq" CC_E test-eq)
369 (cond-move movg "gt" CC_G test-gt)
370 (cond-move movle "le" CC_LE test-le)
371 (cond-move movge "ge" CC_GE test-ge)
372 (cond-move movl "lt" CC_L test-lt)
373 (cond-move movgu "gtu" CC_GU test-gtu)
374 (cond-move movleu "leu" CC_LEU test-leu)
375 (cond-move movcc "geu" CC_CC test-geu)
376 (cond-move movcs "ltu" CC_CS test-ltu)
377 (cond-move movpos "pos" CC_POS test-pos)
378 (cond-move movneg "neg" CC_NEG test-neg)
379 (cond-move movvc "vc" CC_VC test-vc)
380 (cond-move movvs "vs" CC_VS test-vs)
382 ; Arithmetic binary ops
384 (define-pmacro (v8-addx-rename old new)
387 (.str old " in v8 is " new " in v9, v9 page 135") ()
388 (.str new " $rs1,$rs2,$rd")
389 (emit old rs1 rs2 rd))
390 (dnmi (.sym new -imm)
391 (.str old " in v8 is " new " in v9, v9 page 135") ()
392 (.str new " $rs1,$simm13,$rd")
393 (emit old rs1 simm13 rd))
396 (v8-addx-rename addx addc)
397 (v8-addx-rename addxcc addccc)
401 (define-pmacro (s64-set-bool-flags x)
403 (set icc-z (zflag (trunc SI x)))
404 (set icc-n (nflag (trunc SI x)))
405 (set icc-c (const 0))
406 (set icc-v (const 0))
407 (set xcc-z (zflag x))
408 (set xcc-n (nflag x))
409 (set xcc-c (const 0))
410 (set xcc-v (const 0))
416 ; FIXME: flags handling incomplete
417 ; FIXME: div-binop is in sparccom.cpu which is included later.
418 ;(div-binop s64-sdiv "sdiv" MACH64 SDIV div ext: (s64-set-bool-flags rd))
419 ;(div-binop s64-udiv "udiv" MACH64 UDIV div zext: (s64-set-bool-flags rd))