1 ; Generate .c/.h versions of main elements of cpu description file.
2 ; Copyright (C) 2000, 2001, 2002, 2003, 2005, 2009 Red Hat, Inc.
3 ; This file is part of CGEN.
7 (define (/gen-isa-table-defns)
8 (logit 2 "Generating isa table defns ...\n")
12 /* Instruction set variants. */
14 static const CGEN_ISA @arch@_cgen_isa_table[] = {
16 (string-list-map (lambda (isa)
20 "\"" (obj:str-name isa) "\", "
22 (isa-default-insn-bitsize isa))
25 (isa-base-insn-bitsize isa))
28 (isa-min-insn-bitsize isa))
31 (isa-max-insn-bitsize isa))
43 ; Return C code to describe the various cpu variants.
44 ; Currently this is quite simple, the various cpu names and their mach numbers
45 ; are recorded in a "keyword" table.
46 ; ??? No longer used as there is the mach attribute.
48 ;(set! mach-table (make <keyword> 'mach "machine list"
49 ; (make <attr-list> "" nil) ; FIXME: sanitization?
50 ; (map (lambda (elm) (list (obj:name elm) (mach-number elm)))
51 ; (current-mach-list))))
53 (define (/gen-mach-table-decls)
54 (logit 2 "Generating machine table decls ...\n")
55 "" ; (gen-decl mach-table)
58 (define (/gen-mach-table-defns)
59 (logit 2 "Generating machine table defns ...\n")
63 /* Machine variants. */
65 static const CGEN_MACH @arch@_cgen_mach_table[] = {
67 (string-list-map (lambda (mach)
71 "\"" (obj:str-name mach) "\", "
72 "\"" (mach-bfd-name mach) "\", "
74 (number->string (cpu-insn-chunk-bitsize (mach-cpu mach)))
84 ; Attribute support code.
86 ; Return C code to describe the various attributes.
88 (define (/gen-attr-table-decls)
89 (logit 2 "Generating attribute table decls ...\n")
92 "extern const CGEN_ATTR_TABLE @arch@_cgen_hardware_attr_table[];\n"
93 "extern const CGEN_ATTR_TABLE @arch@_cgen_ifield_attr_table[];\n"
94 "extern const CGEN_ATTR_TABLE @arch@_cgen_operand_attr_table[];\n"
95 "extern const CGEN_ATTR_TABLE @arch@_cgen_insn_attr_table[];\n"
100 ; Alternative GEN-MASK argument to gen-bool-attrs.
101 ; This uses the `A' macro to abbreviate the attribute definition.
103 (define (gen-A-attr-mask prefix name)
104 (string-append "A(" (string-upcase (gen-c-symbol name)) ")")
107 ; Instruction fields support code.
109 ; Return C code to declare various ifield bits.
111 (define (gen-ifld-decls)
112 (logit 2 "Generating instruction field decls ...\n")
114 "/* Ifield support. */\n\n"
115 "/* Ifield attribute indices. */\n\n"
116 (gen-attr-enum-decl "cgen_ifld" (current-ifld-attr-list))
117 (gen-attr-accessors "cgen_ifld" (current-ifld-attr-list))
118 (gen-enum-decl 'ifield_type "@arch@ ifield types"
120 (append (gen-obj-list-enums (non-derived-ifields (current-ifld-list)))
122 "#define MAX_IFLD ((int) @ARCH@_F_MAX)\n\n"
126 ; Return C code to define the instruction field table,
127 ; and any other ifield related definitions.
129 (define (gen-ifld-defns)
130 (logit 2 "Generating ifield table ...\n")
131 (let* ((ifld-list (current-ifld-list))
132 (all-attrs (current-ifld-attr-list))
133 (num-non-bools (attr-count-non-bools all-attrs)))
136 /* The instruction field table. */
139 (gen-define-with-symcat "A(a) (1 << CGEN_IFLD_" "a)")
141 const CGEN_IFLD @arch@_cgen_ifld_table[] =
146 (gen-obj-sanitize ifld
149 (ifld-enum ifld) ", "
150 "\"" (obj:str-name ifld) "\", "
152 (or (has-attr? ifld 'VIRTUAL)
153 (derived-ifield? ifld))
156 (number->string (ifld-word-offset ifld)) ", "
157 (number->string (ifld-word-length ifld)) ", "
158 (number->string (ifld-start ifld)) ", "
159 (number->string (ifld-length ifld)) ", "))
160 (gen-obj-attr-defn 'ifld ifld all-attrs
161 num-non-bools gen-A-attr-mask)
165 { 0, 0, 0, 0, 0, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
176 ; Return C code to declare the various hardware bits
177 ; that can be (or must be) defined before including opcode/cgen.h.
179 (define (gen-hw-decls)
180 (logit 2 "Generating hardware decls ...\n")
182 "/* Hardware attribute indices. */\n\n"
183 (gen-attr-enum-decl "cgen_hw" (current-hw-attr-list))
184 (gen-attr-accessors "cgen_hw" (current-hw-attr-list))
185 (gen-enum-decl 'cgen_hw_type "@arch@ hardware types"
186 "HW_" ; FIXME: @ARCH@_
187 (append (nub (map (lambda (hw)
188 (cons (hw-sem-name hw)
193 (lambda (elm) (car elm)))
195 "#define MAX_HW ((int) HW_MAX)\n\n"
199 ; Return declarations of variables tables used by HW.
201 (define (/gen-hw-decl hw)
204 (gen-decl (hw-indices hw))
207 (gen-decl (hw-values hw))
212 ; Return C code to declare the various hardware bits
213 ; that must be defined after including opcode/cgen.h.
215 (define (gen-hw-table-decls)
216 (logit 2 "Generating hardware table decls ...\n")
218 "/* Hardware decls. */\n\n"
219 (string-map /gen-hw-decl (current-hw-list))
221 "extern const CGEN_HW_ENTRY @arch@_cgen_hw_table[];\n"
225 ; Return definitions of variables tables used by HW.
226 ; Only do this for `PRIVATE' elements. Public ones are emitted elsewhere.
228 (define (/gen-hw-defn hw)
230 (if (and (hw-indices hw)
231 (obj-has-attr? (hw-indices hw) 'PRIVATE))
232 (gen-defn (hw-indices hw))
234 (if (and (hw-values hw)
235 (obj-has-attr? (hw-values hw) 'PRIVATE))
236 (gen-defn (hw-values hw))
241 ; Generate the tables for the various hardware bits (register names, etc.).
242 ; A table is generated for each element, and then another table is generated
243 ; which collects them all together.
244 ; Uses include looking up a particular register set so that a new reg
245 ; can be added to it [at runtime].
247 (define (gen-hw-table-defns)
248 (logit 2 "Generating hardware table ...\n")
249 (let* ((all-attrs (current-hw-attr-list))
250 (num-non-bools (attr-count-non-bools all-attrs)))
252 (string-list-map gen-defn (current-kw-list))
253 (string-list-map /gen-hw-defn (current-hw-list))
255 /* The hardware table. */
258 (gen-define-with-symcat "A(a) (1 << CGEN_HW_" "a)")
260 const CGEN_HW_ENTRY @arch@_cgen_hw_table[] =
268 "\"" (obj:str-name hw) "\", "
270 ; ??? No element currently requires both indices and
271 ; values specs so we only output the needed one.
272 (or (and (hw-indices hw)
273 (send (hw-indices hw) 'gen-table-entry))
275 (send (hw-values hw) 'gen-table-entry))
276 "CGEN_ASM_NONE, 0, ")
277 (gen-obj-attr-defn 'hw hw all-attrs
278 num-non-bools gen-A-attr-mask)
282 { 0, 0, CGEN_ASM_NONE, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
291 ; Utilities of cgen-opc.h.
293 ; Return #define's of several constants.
294 ; FIXME: Some of these to be moved into table of structs, one per cpu family.
296 (define (/gen-hash-defines)
297 (logit 2 "Generating #define's ...\n")
299 "#define CGEN_ARCH @arch@\n\n"
300 "/* Given symbol S, return @arch@_cgen_<S>. */\n"
301 (gen-define-with-symcat "CGEN_SYM(s) @arch@" "_cgen_" "s")
302 "\n\n/* Selected cpu families. */\n"
303 ; FIXME: Move to sim's arch.h.
304 (string-map (lambda (cpu)
305 (gen-obj-sanitize cpu
306 (string-append "#define HAVE_CPU_"
307 (string-upcase (gen-sym cpu))
311 "#define CGEN_INSN_LSB0_P " (if (current-arch-insn-lsb0?) "1" "0")
313 "/* Minimum size of any insn (in bytes). */\n"
314 "#define CGEN_MIN_INSN_SIZE "
315 (number->string (bits->bytes
316 (apply min (map isa-min-insn-bitsize (current-isa-list)))))
318 "/* Maximum size of any insn (in bytes). */\n"
319 "#define CGEN_MAX_INSN_SIZE "
320 (number->string (bits->bytes
321 (apply max (map isa-max-insn-bitsize (current-isa-list)))))
323 ; This tells the assembler/disassembler whether or not it can use an int to
324 ; record insns, which is faster. Since this controls the typedef of the
325 ; insn buffer, only enable this if all isas support it.
326 "#define CGEN_INT_INSN_P "
327 (if (all-true? (map isa-integral-insn? (current-isa-list))) "1" "0")
330 "/* Maximum number of syntax elements in an instruction. */\n"
331 "#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS "
332 ; The +2 account for the leading "MNEM" and trailing 0.
333 (number->string (+ 2 (apply max (map (lambda (insn)
334 (length (syntax-break-out (insn-syntax insn)
335 (obj-isa-list insn))))
336 (current-insn-list)))))
339 "/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.\n"
340 " e.g. In \"b,a foo\" the \",a\" is an operand. If mnemonics have operands\n"
341 " we can't hash on everything up to the space. */\n"
343 "/*#define CGEN_MNEMONIC_OPERANDS*/\n"
344 "#define CGEN_MNEMONIC_OPERANDS\n")
346 ; "/* Maximum number of operands any insn or macro-insn has. */\n"
347 ; FIXME: Should compute.
348 ; "#define CGEN_MAX_INSN_OPERANDS 16\n"
350 "/* Maximum number of fields in an instruction. */\n"
351 "#define CGEN_ACTUAL_MAX_IFMT_OPERANDS "
352 (number->string (apply max (map (lambda (f) (length (ifmt-ifields f)))
353 (current-ifmt-list))))
360 ; Return C code to declare various operand bits.
362 (define (gen-operand-decls)
363 (logit 2 "Generating operand decls ...\n")
365 "/* Operand attribute indices. */\n\n"
366 (gen-attr-enum-decl "cgen_operand" (current-op-attr-list))
367 (gen-attr-accessors "cgen_operand" (current-op-attr-list))
368 (gen-enum-decl 'cgen_operand_type "@arch@ operand types"
370 (nub (append (gen-obj-list-enums (current-op-list))
373 "/* Number of operands types. */\n"
374 "#define MAX_OPERANDS " (number->string (length (gen-obj-list-enums (current-op-list)))) "\n\n"
375 ; was: "#define MAX_OPERANDS ((int) @ARCH@_OPERAND_MAX)\n\n"
376 "/* Maximum number of operands referenced by any insn. */\n"
377 "#define MAX_OPERAND_INSTANCES "
378 (number->string (max-operand-instances))
383 ; Generate C code to define the operand table.
385 (define ifld-number-cache #f)
386 (define (ifld-number f)
387 (if (not ifld-number-cache)
388 (let* ((ls (find (lambda (f) (not (has-attr? f 'VIRTUAL)))
389 (non-derived-ifields (current-ifld-list))))
390 (numls (iota (length ls))))
391 (set! ifld-number-cache
392 (map (lambda (elt num) (cons (obj:name elt) num))
394 (number->string (cdr (assoc (obj:name f) ifld-number-cache))))
396 (define (gen-maybe-multi-ifld-of-op op)
397 (let* ((idx (op:index op))
398 (ty (hw-index:type idx))
399 (fld (hw-index:value idx)))
400 (gen-maybe-multi-ifld ty fld)))
402 (define (gen-maybe-multi-ifld ty fld)
403 (let* ((field-ref "0")
405 (if (equal? ty 'ifield)
406 (if (multi-ifield? fld)
408 (set! field-ref (string-append "&" (ifld-enum fld) "_MULTI_IFIELD[0]"))
409 (set! field-count (number->string (length (elm-get fld 'subfields)))))
411 (set! field-ref (string-append "&@arch@_cgen_ifld_table[" (ifld-enum fld) "]"))))
412 (string-append "{ " field-count ", { (const PTR) " field-ref " } }")))
414 (define (gen-multi-ifield-nodes)
415 (let ((multis (find multi-ifield? (current-ifld-list))))
419 '("\n\n/* multi ifield declarations */\n\n")
423 "const CGEN_MAYBE_MULTI_IFLD "
424 (ifld-enum ifld) "_MULTI_IFIELD [];\n"))
427 '("\n\n/* multi ifield definitions */\n\n")
431 "const CGEN_MAYBE_MULTI_IFLD "
432 (ifld-enum ifld) "_MULTI_IFIELD [] =\n{"
434 (map (lambda (x) (string-append "\n " (gen-maybe-multi-ifld 'ifield x) ","))
435 (elm-get ifld 'subfields)))
436 "\n { 0, { (const PTR) 0 } }\n};\n"))
439 (define (gen-operand-table)
440 (logit 2 "Generating operand table ...\n")
441 (let* ((all-attrs (current-op-attr-list))
442 (num-non-bools (attr-count-non-bools all-attrs)))
445 /* The operand table. */
448 (gen-define-with-symcat "A(a) (1 << CGEN_OPERAND_" "a)")
449 (gen-define-with-symcat "OPERAND(op) @ARCH@_OPERAND_" "op")
451 const CGEN_OPERAND @arch@_cgen_operand_table[] =
458 "/* " (obj:str-name op) ": " (obj:comment op) " */\n"
459 (if (or (derived-operand? op)
464 "\"" (obj:str-name op) "\", "
466 (hw-enum (op:hw-name op)) ", "
467 (number->string (op:start op)) ", "
468 (number->string (op:length op)) ",\n"
470 (gen-maybe-multi-ifld-of-op op) ", \n"
472 (gen-obj-attr-defn 'operand op all-attrs
473 num-non-bools gen-A-attr-mask)
478 { 0, 0, 0, 0, 0,\n { 0, { (const PTR) 0 } },\n " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
488 ; Instruction table support.
490 ; Return C code to declare various insn bits.
492 (define (gen-insn-decls)
493 (logit 2 "Generating instruction decls ...\n")
495 "/* Insn attribute indices. */\n\n"
496 (gen-attr-enum-decl "cgen_insn" (current-insn-attr-list))
497 (gen-attr-accessors "cgen_insn" (current-insn-attr-list))
501 ; Generate an insn table entry for INSN.
502 ; ALL-ATTRS is a list of all instruction attributes.
503 ; NUM-NON-BOOLS is the number of non-boolean insn attributes.
505 (define (gen-insn-table-entry insn all-attrs num-non-bools)
509 "/* " (insn-syntax insn) " */\n"
512 (if (has-attr? insn 'ALIAS) "-1" (insn-enum insn)) ", "
513 "\"" (obj:str-name insn) "\", "
514 "\"" (insn-mnemonic insn) "\", "
515 ;(if (has-attr? insn 'ALIAS) "0" (number->string (insn-length insn))) ",\n"
516 (number->string (insn-length insn)) ",\n"
517 ; ??? There is currently a problem with embedded newlines, and this might
518 ; best be put in another file [the table is already pretty big].
519 ; Might also wish to output bytecodes instead.
521 ; (if (insn-semantics insn)
522 ; (string-append "\""
523 ; (with-output-to-string
524 ; ; ??? Should we do macro expansion here?
525 ; (lambda () (display (insn-semantics insn))))
529 ; ??? Might wish to output the raw format spec here instead
530 ; (either as plain text or bytecodes).
531 ; Values could be lazily computed and cached.
533 (gen-obj-attr-defn 'insn insn all-attrs num-non-bools gen-A-attr-mask)
537 ; Generate insn table.
539 (define (gen-insn-table)
540 (logit 2 "Generating instruction table ...\n")
541 (let* ((all-attrs (current-insn-attr-list))
542 (num-non-bools (attr-count-non-bools all-attrs)))
545 /* The instruction table. */
547 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
549 (gen-define-with-symcat "A(a) (1 << CGEN_INSN_" "a)")
551 static const CGEN_IBASE @arch@_cgen_insn_table[MAX_INSNS] =
553 /* Special null first entry.
554 A `num' value of zero is thus invalid.
555 Also, the special `invalid' insn resides here. */
556 { 0, 0, 0, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " },\n"
559 (string-write-map (lambda (insn)
560 (logit 3 "Generating insn table entry for " (obj:name insn) " ...\n")
561 (gen-insn-table-entry insn all-attrs num-non-bools))
562 (non-multi-insns (current-insn-list))))
575 ; Cpu table handling support.
577 ; ??? A lot of this can live in a machine independent file, but there's
578 ; currently no place to put this file (there's no libcgen). libopcodes is the
579 ; wrong place as some simulator ports use this but they don't use libopcodes.
581 ; Return C routines to open/close a cpu description table.
582 ; This is defined here and not in cgen-opc.in because it refers to
583 ; CGEN_{ASM,DIS}_HASH and insn_table/macro_insn_table which is defined
584 ; earlier in the file. ??? Things can certainly be rearranged though
585 ; and opcodes/cgen.sh modified to insert the generated part into the middle
586 ; of the file like is done for assembler/disassembler support.
588 (define (/gen-cpu-open)
591 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
592 static void build_hw_table (CGEN_CPU_TABLE *);
593 static void build_ifield_table (CGEN_CPU_TABLE *);
594 static void build_operand_table (CGEN_CPU_TABLE *);
595 static void build_insn_table (CGEN_CPU_TABLE *);
596 static void @arch@_cgen_rebuild_tables (CGEN_CPU_TABLE *);
598 /* Subroutine of @arch@_cgen_cpu_open to look up a mach via its bfd name. */
600 static const CGEN_MACH *
601 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
605 if (strcmp (name, table->bfd_name) == 0)
612 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
615 build_hw_table (CGEN_CPU_TABLE *cd)
618 int machs = cd->machs;
619 const CGEN_HW_ENTRY *init = & @arch@_cgen_hw_table[0];
620 /* MAX_HW is only an upper bound on the number of selected entries.
621 However each entry is indexed by it's enum so there can be holes in
623 const CGEN_HW_ENTRY **selected =
624 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
626 cd->hw_table.init_entries = init;
627 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
628 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
629 /* ??? For now we just use machs to determine which ones we want. */
630 for (i = 0; init[i].name != NULL; ++i)
631 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
633 selected[init[i].type] = &init[i];
634 cd->hw_table.entries = selected;
635 cd->hw_table.num_entries = MAX_HW;
638 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
641 build_ifield_table (CGEN_CPU_TABLE *cd)
643 cd->ifld_table = & @arch@_cgen_ifld_table[0];
646 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
649 build_operand_table (CGEN_CPU_TABLE *cd)
652 int machs = cd->machs;
653 const CGEN_OPERAND *init = & @arch@_cgen_operand_table[0];
654 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
655 However each entry is indexed by it's enum so there can be holes in
657 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
659 cd->operand_table.init_entries = init;
660 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
661 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
662 /* ??? For now we just use mach to determine which ones we want. */
663 for (i = 0; init[i].name != NULL; ++i)
664 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
666 selected[init[i].type] = &init[i];
667 cd->operand_table.entries = selected;
668 cd->operand_table.num_entries = MAX_OPERANDS;
671 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table.
672 ??? This could leave out insns not supported by the specified mach/isa,
673 but that would cause errors like \"foo only supported by bar\" to become
674 \"unknown insn\", so for now we include all insns and require the app to
675 do the checking later.
676 ??? On the other hand, parsing of such insns may require their hardware or
677 operand elements to be in the table [which they mightn't be]. */
680 build_insn_table (CGEN_CPU_TABLE *cd)
683 const CGEN_IBASE *ib = & @arch@_cgen_insn_table[0];
684 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
686 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
687 for (i = 0; i < MAX_INSNS; ++i)
688 insns[i].base = &ib[i];
689 cd->insn_table.init_entries = insns;
690 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
691 cd->insn_table.num_init_entries = MAX_INSNS;
694 /* Subroutine of @arch@_cgen_cpu_open to rebuild the tables. */
697 @arch@_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
700 CGEN_BITSET *isas = cd->isas;
701 unsigned int machs = cd->machs;
703 cd->int_insn_p = CGEN_INT_INSN_P;
705 /* Data derived from the isa spec. */
706 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
707 cd->default_insn_bitsize = UNSET;
708 cd->base_insn_bitsize = UNSET;
709 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
710 cd->max_insn_bitsize = 0;
711 for (i = 0; i < MAX_ISAS; ++i)
712 if (cgen_bitset_contains (isas, i))
714 const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
716 /* Default insn sizes of all selected isas must be
717 equal or we set the result to 0, meaning \"unknown\". */
718 if (cd->default_insn_bitsize == UNSET)
719 cd->default_insn_bitsize = isa->default_insn_bitsize;
720 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
723 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
725 /* Base insn sizes of all selected isas must be equal
726 or we set the result to 0, meaning \"unknown\". */
727 if (cd->base_insn_bitsize == UNSET)
728 cd->base_insn_bitsize = isa->base_insn_bitsize;
729 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
732 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
734 /* Set min,max insn sizes. */
735 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
736 cd->min_insn_bitsize = isa->min_insn_bitsize;
737 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
738 cd->max_insn_bitsize = isa->max_insn_bitsize;
741 /* Data derived from the mach spec. */
742 for (i = 0; i < MAX_MACHS; ++i)
743 if (((1 << i) & machs) != 0)
745 const CGEN_MACH *mach = & @arch@_cgen_mach_table[i];
747 if (mach->insn_chunk_bitsize != 0)
749 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
751 fprintf (stderr, \"@arch@_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\\n\",
752 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
756 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
760 /* Determine which hw elements are used by MACH. */
763 /* Build the ifield table. */
764 build_ifield_table (cd);
766 /* Determine which operands are used by MACH/ISA. */
767 build_operand_table (cd);
769 /* Build the instruction table. */
770 build_insn_table (cd);
773 /* Initialize a cpu table and return a descriptor.
774 It's much like opening a file, and must be the first function called.
775 The arguments are a set of (type/value) pairs, terminated with
778 Currently supported values:
779 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
780 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
781 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
782 CGEN_CPU_OPEN_ENDIAN: specify endian choice
783 CGEN_CPU_OPEN_END: terminates arguments
785 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
788 ??? We only support ISO C stdargs here, not K&R.
789 Laziness, plus experiment to see if anything requires K&R - eventually
790 K&R will no longer be supported - e.g. GDB is currently trying this. */
793 @arch@_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
795 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
797 CGEN_BITSET *isas = 0; /* 0 = \"unspecified\" */
798 unsigned int machs = 0; /* 0 = \"unspecified\" */
799 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
808 memset (cd, 0, sizeof (*cd));
810 va_start (ap, arg_type);
811 while (arg_type != CGEN_CPU_OPEN_END)
815 case CGEN_CPU_OPEN_ISAS :
816 isas = va_arg (ap, CGEN_BITSET *);
818 case CGEN_CPU_OPEN_MACHS :
819 machs = va_arg (ap, unsigned int);
821 case CGEN_CPU_OPEN_BFDMACH :
823 const char *name = va_arg (ap, const char *);
824 const CGEN_MACH *mach =
825 lookup_mach_via_bfd_name (@arch@_cgen_mach_table, name);
827 machs |= 1 << mach->num;
830 case CGEN_CPU_OPEN_ENDIAN :
831 endian = va_arg (ap, enum cgen_endian);
834 fprintf (stderr, \"@arch@_cgen_cpu_open: unsupported argument `%d'\\n\",
836 abort (); /* ??? return NULL? */
838 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
842 /* Mach unspecified means \"all\". */
844 machs = (1 << MAX_MACHS) - 1;
845 /* Base mach is always selected. */
847 if (endian == CGEN_ENDIAN_UNKNOWN)
849 /* ??? If target has only one, could have a default. */
850 fprintf (stderr, \"@arch@_cgen_cpu_open: no endianness specified\\n\");
854 cd->isas = cgen_bitset_copy (isas);
857 /* FIXME: for the sparc case we can determine insn-endianness statically.
858 The worry here is where both data and insn endian can be independently
859 chosen, in which case this function will need another argument.
860 Actually, will want to allow for more arguments in the future anyway. */
861 cd->insn_endian = endian;
863 /* Table (re)builder. */
864 cd->rebuild_tables = @arch@_cgen_rebuild_tables;
865 @arch@_cgen_rebuild_tables (cd);
867 /* Default to not allowing signed overflow. */
868 cd->signed_overflow_ok_p = 0;
870 return (CGEN_CPU_DESC) cd;
873 /* Cover fn to @arch@_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
874 MACH_NAME is the bfd name of the mach. */
877 @arch@_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
879 return @arch@_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
880 CGEN_CPU_OPEN_ENDIAN, endian,
884 /* Close a cpu table.
885 ??? This can live in a machine independent file, but there's currently
886 no place to put this file (there's no libcgen). libopcodes is the wrong
887 place as some simulator ports use this but they don't use libopcodes. */
890 @arch@_cgen_cpu_close (CGEN_CPU_DESC cd)
893 const CGEN_INSN *insns;
895 if (cd->macro_insn_table.init_entries)
897 insns = cd->macro_insn_table.init_entries;
898 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
899 if (CGEN_INSN_RX ((insns)))
900 regfree (CGEN_INSN_RX (insns));
903 if (cd->insn_table.init_entries)
905 insns = cd->insn_table.init_entries;
906 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
907 if (CGEN_INSN_RX (insns))
908 regfree (CGEN_INSN_RX (insns));
911 if (cd->macro_insn_table.init_entries)
912 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
914 if (cd->insn_table.init_entries)
915 free ((CGEN_INSN *) cd->insn_table.init_entries);
917 if (cd->hw_table.entries)
918 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
920 if (cd->operand_table.entries)
921 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
929 ; General initialization C code
930 ; Code is appended during processing.
932 (define /cputab-init-code "")
933 (define (cputab-add-init! code)
934 (set! /cputab-init-code (string-append /cputab-init-code code))
937 ; Return the C code to define the various initialization functions.
938 ; This does not include assembler/disassembler specific stuff.
939 ; Generally, this function doesn't do anything.
940 ; It exists to allow a global-static-constructor kind of thing should
941 ; one ever be necessary.
943 (define (gen-init-fns)
944 (logit 2 "Generating init fns ...\n")
947 /* Initialize anything needed to be done once, before any cpu_open call. */
957 ; Top level C code generators
959 ; FIXME: Create enum objects for all the enums we explicitly declare here.
960 ; Then they'd be usable and we wouldn't have to special case them here.
962 (define (cgen-desc.h)
963 (logit 1 "Generating " (current-arch-name) "-desc.h ...\n")
965 (gen-c-copyright "CPU data header for @arch@."
966 CURRENT-COPYRIGHT CURRENT-PACKAGE)
973 ; This is defined in arch.h. It's not defined here as there is yet to
974 ; be a need for it in the assembler/disassembler.
975 ;(gen-enum-decl 'model_type "model types"
977 ; (append (map list (map obj:name (current-model-list))) '((max))))
978 ;"#define MAX_MODELS ((int) MODEL_MAX)\n\n"
980 (string-map gen-decl (current-enum-list))
981 "/* Attributes. */\n\n"
982 (string-map gen-decl (current-attr-list))
983 "/* Number of architecture variants. */\n"
984 ; If there is only 1 isa, leave out special handling. */
985 (if (= (length (current-isa-list)) 1)
986 "#define MAX_ISAS 1\n"
987 "#define MAX_ISAS ((int) ISA_MAX)\n")
988 "#define MAX_MACHS ((int) MACH_MAX)\n\n"
993 "/* cgen.h uses things we just defined. */\n"
994 "#include \"opcode/cgen.h\"\n\n"
995 "extern const struct cgen_ifld @arch@_cgen_ifld_table[];\n\n"
996 /gen-attr-table-decls
997 /gen-mach-table-decls
1001 (if (opc-file-provided?)
1002 (gen-extra-cpu.h (opc-file-path) (current-arch-name))
1006 #endif /* @ARCH@_CPU_H */
1011 ; This file contains the "top level" definitions of the cpu.
1012 ; This includes various elements of the description file, expressed in C.
1014 ; ??? A lot of this file can go in a machine-independent file! However,
1015 ; some simulators don't use the cgen opcodes support so there is currently
1016 ; no place to put this file. To be revisited when we do have such a place.
1018 (define (cgen-desc.c)
1019 (logit 1 "Generating " (current-arch-name) "-desc.c ...\n")
1021 (gen-c-copyright "CPU data for @arch@."
1022 CURRENT-COPYRIGHT CURRENT-PACKAGE)
1024 #include \"sysdep.h\"
1027 #include \"ansidecl.h\"
1029 #include \"symcat.h\"
1030 #include \"@arch@-desc.h\"
1031 #include \"@arch@-opc.h\"
1032 #include \"opintl.h\"
1033 #include \"libiberty.h\"
1034 #include \"xregex.h\"
1037 (if (opc-file-provided?)
1038 (gen-extra-cpu.c (opc-file-path) (current-arch-name))
1040 gen-attr-table-defns
1041 /gen-isa-table-defns
1042 /gen-mach-table-defns
1045 gen-multi-ifield-nodes