1 ; Generate .c/.h versions of main elements of cpu description file.
2 ; Copyright (C) 2000, 2001 Red Hat, Inc.
3 ; This file is part of CGEN.
7 (define (-gen-isa-table-defns)
8 (logit 2 "Generating isa table defns ...\n")
12 /* Instruction set variants. */
14 static const CGEN_ISA @arch@_cgen_isa_table[] = {
16 (string-list-map (lambda (isa)
20 "\"" (obj:name isa) "\", "
22 (isa-default-insn-bitsize isa))
25 (isa-base-insn-bitsize isa))
28 (isa-min-insn-bitsize isa))
31 (isa-max-insn-bitsize isa))
43 ; Return C code to describe the various cpu variants.
44 ; Currently this is quite simple, the various cpu names and their mach numbers
45 ; are recorded in a "keyword" table.
46 ; ??? No longer used as there is the mach attribute.
48 ;(set! mach-table (make <keyword> 'mach "machine list"
49 ; (make <attr-list> "" nil) ; FIXME: sanitization?
50 ; (map (lambda (elm) (list (obj:name elm) (mach-number elm)))
51 ; (current-mach-list))))
53 (define (-gen-mach-table-decls)
54 (logit 2 "Generating machine table decls ...\n")
55 "" ; (gen-decl mach-table)
58 (define (-gen-mach-table-defns)
59 (logit 2 "Generating machine table defns ...\n")
63 /* Machine variants. */
65 static const CGEN_MACH @arch@_cgen_mach_table[] = {
67 (string-list-map (lambda (mach)
71 "\"" (obj:name mach) "\", "
72 "\"" (mach-bfd-name mach) "\", "
74 (number->string (cpu-insn-chunk-bitsize (mach-cpu mach)))
84 ; Attribute support code.
86 ; Return C code to describe the various attributes.
88 (define (-gen-attr-table-decls)
89 (logit 2 "Generating attribute table decls ...\n")
92 "extern const CGEN_ATTR_TABLE @arch@_cgen_hardware_attr_table[];\n"
93 "extern const CGEN_ATTR_TABLE @arch@_cgen_ifield_attr_table[];\n"
94 "extern const CGEN_ATTR_TABLE @arch@_cgen_operand_attr_table[];\n"
95 "extern const CGEN_ATTR_TABLE @arch@_cgen_insn_attr_table[];\n"
100 ; Alternative GEN-MASK argument to gen-bool-attrs.
101 ; This uses the `A' macro to abbreviate the attribute definition.
103 (define (gen-A-attr-mask prefix name)
104 (string-append "A(" (string-upcase (gen-c-symbol name)) ")")
107 ; Instruction fields support code.
109 ; Return C code to declare various ifield bits.
111 (define (gen-ifld-decls)
112 (logit 2 "Generating instruction field decls ...\n")
114 "/* Ifield support. */\n\n"
115 "extern const struct cgen_ifld @arch@_cgen_ifld_table[];\n\n"
116 "/* Ifield attribute indices. */\n\n"
117 (gen-attr-enum-decl "cgen_ifld" (current-ifld-attr-list))
118 (gen-enum-decl 'ifield_type "@arch@ ifield types"
120 (append (gen-obj-list-enums (non-derived-ifields (current-ifld-list)))
122 "#define MAX_IFLD ((int) @ARCH@_F_MAX)\n\n"
126 ; Return C code to define the instruction field table,
127 ; and any other ifield related definitions.
129 (define (gen-ifld-defns)
130 (logit 2 "Generating ifield table ...\n")
131 (let* ((ifld-list (find (lambda (f) (not (has-attr? f 'VIRTUAL)))
132 (non-derived-ifields (current-ifld-list))))
133 (all-attrs (current-ifld-attr-list))
134 (num-non-bools (attr-count-non-bools all-attrs)))
137 /* The instruction field table. */
140 (gen-define-with-symcat "A(a) (1 << CGEN_IFLD_" "a)")
142 const CGEN_IFLD @arch@_cgen_ifld_table[] =
147 (gen-obj-sanitize ifld
150 (ifld-enum ifld) ", "
151 "\"" (obj:name ifld) "\", "
152 (number->string (ifld-word-offset ifld)) ", "
153 (number->string (ifld-word-length ifld)) ", "
154 (number->string (ifld-start ifld #f)) ", "
155 (number->string (ifld-length ifld)) ", "
156 (gen-obj-attr-defn 'ifld ifld all-attrs
157 num-non-bools gen-A-attr-mask)
161 { 0, 0, 0, 0, 0, 0, {0, {0}} }
172 ; Return C code to declare the various hardware bits
173 ; that can be (or must be) defined before including opcode/cgen.h.
175 (define (gen-hw-decls)
176 (logit 2 "Generating hardware decls ...\n")
178 "/* Hardware attribute indices. */\n\n"
179 (gen-attr-enum-decl "cgen_hw" (current-hw-attr-list))
180 (gen-enum-decl 'cgen_hw_type "@arch@ hardware types"
181 "HW_" ; FIXME: @ARCH@_
182 (append (nub (map (lambda (hw)
183 (cons (hw-sem-name hw)
188 (lambda (elm) (car elm)))
190 "#define MAX_HW ((int) HW_MAX)\n\n"
194 ; Return declarations of variables tables used by HW.
196 (define (-gen-hw-decl hw)
198 (if (and (hw-indices hw)
199 ; ??? Commented out as opcode changes are needed
200 ) ; (not (obj-has-attr? (hw-indices hw) 'PRIVATE)))
201 (gen-decl (hw-indices hw))
203 (if (and (hw-values hw)
204 ; ??? Commented out as opcode changes are needed
205 ) ; (not (obj-has-attr? (hw-values hw) 'PRIVATE)))
206 (gen-decl (hw-values hw))
211 ; Return C code to declare the various hardware bits
212 ; that must be defined after including opcode/cgen.h.
214 (define (gen-hw-table-decls)
215 (logit 2 "Generating hardware table decls ...\n")
217 "/* Hardware decls. */\n\n"
218 (string-map -gen-hw-decl (current-hw-list))
223 ; Return definitions of variables tables used by HW.
224 ; Only do this for `PRIVATE' elements. Public ones are emitted elsewhere.
226 (define (-gen-hw-defn hw)
228 (if (and (hw-indices hw)
229 (obj-has-attr? (hw-indices hw) 'PRIVATE))
230 (gen-defn (hw-indices hw))
232 (if (and (hw-values hw)
233 (obj-has-attr? (hw-values hw) 'PRIVATE))
234 (gen-defn (hw-values hw))
239 ; Generate the tables for the various hardware bits (register names, etc.).
240 ; A table is generated for each element, and then another table is generated
241 ; which collects them all together.
242 ; Uses include looking up a particular register set so that a new reg
243 ; can be added to it [at runtime].
245 (define (gen-hw-table-defns)
246 (logit 2 "Generating hardware table ...\n")
247 (let* ((all-attrs (current-hw-attr-list))
248 (num-non-bools (attr-count-non-bools all-attrs)))
250 (string-list-map gen-defn (current-kw-list))
251 (string-list-map -gen-hw-defn (current-hw-list))
253 /* The hardware table. */
256 (gen-define-with-symcat "A(a) (1 << CGEN_HW_" "a)")
258 const CGEN_HW_ENTRY @arch@_cgen_hw_table[] =
266 "\"" (obj:name hw) "\", "
268 ; ??? No element currently requires both indices and
269 ; values specs so we only output the needed one.
270 (or (and (hw-indices hw)
271 (send (hw-indices hw) 'gen-table-entry))
273 (send (hw-values hw) 'gen-table-entry))
274 "CGEN_ASM_NONE, 0, ")
275 (gen-obj-attr-defn 'hw hw all-attrs
276 num-non-bools gen-A-attr-mask)
280 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
289 ; Utilities of cgen-opc.h.
291 ; Return #define's of several constants.
292 ; FIXME: Some of these to be moved into table of structs, one per cpu family.
294 (define (-gen-hash-defines)
295 (logit 2 "Generating #define's ...\n")
297 "#define CGEN_ARCH @arch@\n\n"
298 "/* Given symbol S, return @arch@_cgen_<S>. */\n"
299 (gen-define-with-symcat "CGEN_SYM(s) @arch@" "_cgen_" "s")
300 "\n\n/* Selected cpu families. */\n"
301 ; FIXME: Move to sim's arch.h.
302 (string-map (lambda (cpu)
303 (gen-obj-sanitize cpu
304 (string-append "#define HAVE_CPU_"
305 (string-upcase (gen-sym cpu))
309 "#define CGEN_INSN_LSB0_P " (if (current-arch-insn-lsb0?) "1" "0")
311 "/* Minimum size of any insn (in bytes). */\n"
312 "#define CGEN_MIN_INSN_SIZE "
313 (number->string (bits->bytes
314 (apply min (map isa-min-insn-bitsize (current-isa-list)))))
316 "/* Maximum size of any insn (in bytes). */\n"
317 "#define CGEN_MAX_INSN_SIZE "
318 (number->string (bits->bytes
319 (apply max (map isa-max-insn-bitsize (current-isa-list)))))
321 ; This tells the assembler/disassembler whether or not it can use an int to
322 ; record insns, which is faster. Since this controls the typedef of the
323 ; insn buffer, only enable this if all isas support it.
324 "#define CGEN_INT_INSN_P "
325 (if (all-true? (map isa-integral-insn? (current-isa-list))) "1" "0")
328 "/* Maximum number of syntax elements in an instruction. */\n"
329 "#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS "
330 ; The +2 account for the leading "MNEM" and trailing 0.
331 (number->string (+ 2 (apply max (map (lambda (insn)
332 (length (syntax-break-out (insn-syntax insn))))
333 (current-insn-list)))))
336 "/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.\n"
337 " e.g. In \"b,a foo\" the \",a\" is an operand. If mnemonics have operands\n"
338 " we can't hash on everything up to the space. */\n"
340 "/*#define CGEN_MNEMONIC_OPERANDS*/\n"
341 "#define CGEN_MNEMONIC_OPERANDS\n")
343 ; "/* Maximum number of operands any insn or macro-insn has. */\n"
344 ; FIXME: Should compute.
345 ; "#define CGEN_MAX_INSN_OPERANDS 16\n"
347 "/* Maximum number of fields in an instruction. */\n"
348 "#define CGEN_ACTUAL_MAX_IFMT_OPERANDS "
349 (number->string (apply max (map (lambda (f) (length (ifmt-ifields f)))
350 (current-ifmt-list))))
357 ; Return C code to declare various operand bits.
359 (define (gen-operand-decls)
360 (logit 2 "Generating operand decls ...\n")
362 "/* Operand attribute indices. */\n\n"
363 (gen-attr-enum-decl "cgen_operand" (current-op-attr-list))
364 (gen-enum-decl 'cgen_operand_type "@arch@ operand types"
366 (nub (append (gen-obj-list-enums (current-op-list))
369 "/* Number of operands types. */\n"
370 "#define MAX_OPERANDS " (number->string (length (gen-obj-list-enums (current-op-list)))) "\n\n"
371 ; was: "#define MAX_OPERANDS ((int) @ARCH@_OPERAND_MAX)\n\n"
372 "/* Maximum number of operands referenced by any insn. */\n"
373 "#define MAX_OPERAND_INSTANCES "
374 (number->string (max-operand-instances))
379 ; Generate C code to define the operand table.
381 (define ifld-number-cache #f)
382 (define (ifld-number f)
383 (if (not ifld-number-cache)
384 (let* ((ls (find (lambda (f) (not (has-attr? f 'VIRTUAL)))
385 (non-derived-ifields (current-ifld-list))))
386 (numls (iota (length ls))))
387 (set! ifld-number-cache
388 (map (lambda (elt num) (cons (obj:name elt) num))
390 (number->string (cdr (assoc (obj:name f) ifld-number-cache))))
392 (define (gen-maybe-multi-ifld-of-op op)
393 (let* ((idx (op:index op))
394 (ty (hw-index:type idx))
395 (fld (hw-index:value idx)))
396 (gen-maybe-multi-ifld ty fld)))
398 (define (gen-maybe-multi-ifld ty fld)
399 (let* ((field-ref "0")
401 (if (equal? ty 'ifield)
402 (if (multi-ifield? fld)
404 (set! field-ref (string-append "&(" (ifld-enum fld) "_MULTI_IFIELD[0])"))
405 (set! field-count (number->string (length (elm-get fld 'subfields)))))
407 (set! field-ref (string-append "&(@arch@_cgen_ifld_table[" (ifld-number fld) "])"))))
408 (string-append "{ " field-count ", " field-ref " }")))
410 (define (gen-multi-ifield-nodes)
411 (let ((multis (find multi-ifield? (current-ifld-list))))
415 '("\n\n/* multi ifield declarations */\n\n")
419 "const CGEN_MAYBE_MULTI_IFLD "
420 (ifld-enum ifld) "_MULTI_IFIELD [];\n"))
423 '("\n\n/* multi ifield definitions */\n\n")
427 "const CGEN_MAYBE_MULTI_IFLD "
428 (ifld-enum ifld) "_MULTI_IFIELD [] =\n{"
430 (map (lambda (x) (string-append "\n " (gen-maybe-multi-ifld 'ifield x) ","))
431 (elm-get ifld 'subfields)))
435 (define (gen-operand-table)
436 (logit 2 "Generating operand table ...\n")
437 (let* ((all-attrs (current-op-attr-list))
438 (num-non-bools (attr-count-non-bools all-attrs)))
441 /* The operand table. */
444 (gen-define-with-symcat "A(a) (1 << CGEN_OPERAND_" "a)")
445 (gen-define-with-symcat "OPERAND(op) @ARCH@_OPERAND_" "op")
447 const CGEN_OPERAND @arch@_cgen_operand_table[] =
454 "/* " (obj:name op) ": " (obj:comment op) " */\n"
455 (if (or (derived-operand? op)
460 "\"" (obj:name op) "\", "
462 (hw-enum (op:hw-name op)) ", "
463 (number->string (op:start op)) ", "
464 (number->string (op:length op)) ",\n"
466 (gen-maybe-multi-ifld-of-op op) ", \n"
468 (gen-obj-attr-defn 'operand op all-attrs
469 num-non-bools gen-A-attr-mask)
474 { 0, 0, 0, 0, 0, {0, {0}} }
484 ; Instruction table support.
486 ; Return C code to declare various insn bits.
488 (define (gen-insn-decls)
489 (logit 2 "Generating instruction decls ...\n")
491 "/* Insn attribute indices. */\n\n"
492 (gen-attr-enum-decl "cgen_insn" (current-insn-attr-list))
496 ; Generate an insn table entry for INSN.
497 ; ALL-ATTRS is a list of all instruction attributes.
498 ; NUM-NON-BOOLS is the number of non-boolean insn attributes.
500 (define (gen-insn-table-entry insn all-attrs num-non-bools)
504 "/* " (insn-syntax insn) " */\n"
507 (if (has-attr? insn 'ALIAS) "-1" (insn-enum insn)) ", "
508 "\"" (obj:name insn) "\", "
509 "\"" (insn-mnemonic insn) "\", "
510 ;(if (has-attr? insn 'ALIAS) "0" (number->string (insn-length insn))) ",\n"
511 (number->string (insn-length insn)) ",\n"
512 ; ??? There is currently a problem with embedded newlines, and this might
513 ; best be put in another file [the table is already pretty big].
514 ; Might also wish to output bytecodes instead.
516 ; (if (insn-semantics insn)
517 ; (string-append "\""
518 ; (with-output-to-string
519 ; ; ??? Should we do macro expansion here?
520 ; (lambda () (display (insn-semantics insn))))
524 ; ??? Might wish to output the raw format spec here instead
525 ; (either as plain text or bytecodes).
526 ; Values could be lazily computed and cached.
528 (gen-obj-attr-defn 'insn insn all-attrs num-non-bools gen-A-attr-mask)
532 ; Generate insn table.
534 (define (gen-insn-table)
535 (logit 2 "Generating instruction table ...\n")
536 (let* ((all-attrs (current-insn-attr-list))
537 (num-non-bools (attr-count-non-bools all-attrs)))
540 /* The instruction table. */
542 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
544 (gen-define-with-symcat "A(a) (1 << CGEN_INSN_" "a)")
546 static const CGEN_IBASE @arch@_cgen_insn_table[MAX_INSNS] =
548 /* Special null first entry.
549 A `num' value of zero is thus invalid.
550 Also, the special `invalid' insn resides here. */
551 { 0, 0, 0, 0, {0, {0}} },\n"
554 (string-write-map (lambda (insn)
555 (logit 3 "Generating insn table entry for " (obj:name insn) " ...\n")
556 (gen-insn-table-entry insn all-attrs num-non-bools))
557 (non-multi-insns (current-insn-list))))
570 ; Cpu table handling support.
572 ; ??? A lot of this can live in a machine independent file, but there's
573 ; currently no place to put this file (there's no libcgen). libopcodes is the
574 ; wrong place as some simulator ports use this but they don't use libopcodes.
576 ; Return C routines to open/close a cpu description table.
577 ; This is defined here and not in cgen-opc.in because it refers to
578 ; CGEN_{ASM,DIS}_HASH and insn_table/macro_insn_table which is defined
579 ; earlier in the file. ??? Things can certainly be rearranged though
580 ; and opcodes/cgen.sh modified to insert the generated part into the middle
581 ; of the file like is done for assembler/disassembler support.
583 (define (-gen-cpu-open)
586 static const CGEN_MACH * lookup_mach_via_bfd_name
587 PARAMS ((const CGEN_MACH *, const char *));
588 static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
589 static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
590 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
591 static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
592 static void @arch@_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
594 /* Subroutine of @arch@_cgen_cpu_open to look up a mach via its bfd name. */
596 static const CGEN_MACH *
597 lookup_mach_via_bfd_name (table, name)
598 const CGEN_MACH *table;
603 if (strcmp (name, table->bfd_name) == 0)
610 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
617 int machs = cd->machs;
618 const CGEN_HW_ENTRY *init = & @arch@_cgen_hw_table[0];
619 /* MAX_HW is only an upper bound on the number of selected entries.
620 However each entry is indexed by it's enum so there can be holes in
622 const CGEN_HW_ENTRY **selected =
623 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
625 cd->hw_table.init_entries = init;
626 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
627 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
628 /* ??? For now we just use machs to determine which ones we want. */
629 for (i = 0; init[i].name != NULL; ++i)
630 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
632 selected[init[i].type] = &init[i];
633 cd->hw_table.entries = selected;
634 cd->hw_table.num_entries = MAX_HW;
637 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
640 build_ifield_table (cd)
643 cd->ifld_table = & @arch@_cgen_ifld_table[0];
646 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
649 build_operand_table (cd)
653 int machs = cd->machs;
654 const CGEN_OPERAND *init = & @arch@_cgen_operand_table[0];
655 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
656 However each entry is indexed by it's enum so there can be holes in
658 const CGEN_OPERAND **selected =
659 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
661 cd->operand_table.init_entries = init;
662 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
663 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
664 /* ??? For now we just use mach to determine which ones we want. */
665 for (i = 0; init[i].name != NULL; ++i)
666 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
668 selected[init[i].type] = &init[i];
669 cd->operand_table.entries = selected;
670 cd->operand_table.num_entries = MAX_OPERANDS;
673 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table.
674 ??? This could leave out insns not supported by the specified mach/isa,
675 but that would cause errors like \"foo only supported by bar\" to become
676 \"unknown insn\", so for now we include all insns and require the app to
677 do the checking later.
678 ??? On the other hand, parsing of such insns may require their hardware or
679 operand elements to be in the table [which they mightn't be]. */
682 build_insn_table (cd)
686 const CGEN_IBASE *ib = & @arch@_cgen_insn_table[0];
687 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
689 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
690 for (i = 0; i < MAX_INSNS; ++i)
691 insns[i].base = &ib[i];
692 cd->insn_table.init_entries = insns;
693 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
694 cd->insn_table.num_init_entries = MAX_INSNS;
697 /* Subroutine of @arch@_cgen_cpu_open to rebuild the tables. */
700 @arch@_cgen_rebuild_tables (cd)
704 unsigned int isas = cd->isas;
705 unsigned int machs = cd->machs;
707 cd->int_insn_p = CGEN_INT_INSN_P;
709 /* Data derived from the isa spec. */
710 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
711 cd->default_insn_bitsize = UNSET;
712 cd->base_insn_bitsize = UNSET;
713 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
714 cd->max_insn_bitsize = 0;
715 for (i = 0; i < MAX_ISAS; ++i)
716 if (((1 << i) & isas) != 0)
718 const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
720 /* Default insn sizes of all selected isas must be
721 equal or we set the result to 0, meaning \"unknown\". */
722 if (cd->default_insn_bitsize == UNSET)
723 cd->default_insn_bitsize = isa->default_insn_bitsize;
724 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
727 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
729 /* Base insn sizes of all selected isas must be equal
730 or we set the result to 0, meaning \"unknown\". */
731 if (cd->base_insn_bitsize == UNSET)
732 cd->base_insn_bitsize = isa->base_insn_bitsize;
733 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
736 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
738 /* Set min,max insn sizes. */
739 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
740 cd->min_insn_bitsize = isa->min_insn_bitsize;
741 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
742 cd->max_insn_bitsize = isa->max_insn_bitsize;
745 /* Data derived from the mach spec. */
746 for (i = 0; i < MAX_MACHS; ++i)
747 if (((1 << i) & machs) != 0)
749 const CGEN_MACH *mach = & @arch@_cgen_mach_table[i];
751 if (mach->insn_chunk_bitsize != 0)
753 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
755 fprintf (stderr, \"@arch@_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\\n\",
756 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
760 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
764 /* Determine which hw elements are used by MACH. */
767 /* Build the ifield table. */
768 build_ifield_table (cd);
770 /* Determine which operands are used by MACH/ISA. */
771 build_operand_table (cd);
773 /* Build the instruction table. */
774 build_insn_table (cd);
777 /* Initialize a cpu table and return a descriptor.
778 It's much like opening a file, and must be the first function called.
779 The arguments are a set of (type/value) pairs, terminated with
782 Currently supported values:
783 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
784 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
785 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
786 CGEN_CPU_OPEN_ENDIAN: specify endian choice
787 CGEN_CPU_OPEN_END: terminates arguments
789 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
792 ??? We only support ISO C stdargs here, not K&R.
793 Laziness, plus experiment to see if anything requires K&R - eventually
794 K&R will no longer be supported - e.g. GDB is currently trying this. */
797 @arch@_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
799 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
801 unsigned int isas = 0; /* 0 = \"unspecified\" */
802 unsigned int machs = 0; /* 0 = \"unspecified\" */
803 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
812 memset (cd, 0, sizeof (*cd));
814 va_start (ap, arg_type);
815 while (arg_type != CGEN_CPU_OPEN_END)
819 case CGEN_CPU_OPEN_ISAS :
820 isas = va_arg (ap, unsigned int);
822 case CGEN_CPU_OPEN_MACHS :
823 machs = va_arg (ap, unsigned int);
825 case CGEN_CPU_OPEN_BFDMACH :
827 const char *name = va_arg (ap, const char *);
828 const CGEN_MACH *mach =
829 lookup_mach_via_bfd_name (@arch@_cgen_mach_table, name);
831 machs |= 1 << mach->num;
834 case CGEN_CPU_OPEN_ENDIAN :
835 endian = va_arg (ap, enum cgen_endian);
838 fprintf (stderr, \"@arch@_cgen_cpu_open: unsupported argument `%d'\\n\",
840 abort (); /* ??? return NULL? */
842 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
846 /* mach unspecified means \"all\" */
848 machs = (1 << MAX_MACHS) - 1;
849 /* base mach is always selected */
851 /* isa unspecified means \"all\" */
853 isas = (1 << MAX_ISAS) - 1;
854 if (endian == CGEN_ENDIAN_UNKNOWN)
856 /* ??? If target has only one, could have a default. */
857 fprintf (stderr, \"@arch@_cgen_cpu_open: no endianness specified\\n\");
864 /* FIXME: for the sparc case we can determine insn-endianness statically.
865 The worry here is where both data and insn endian can be independently
866 chosen, in which case this function will need another argument.
867 Actually, will want to allow for more arguments in the future anyway. */
868 cd->insn_endian = endian;
870 /* Table (re)builder. */
871 cd->rebuild_tables = @arch@_cgen_rebuild_tables;
872 @arch@_cgen_rebuild_tables (cd);
874 /* Default to not allowing signed overflow. */
875 cd->signed_overflow_ok_p = 0;
877 return (CGEN_CPU_DESC) cd;
880 /* Cover fn to @arch@_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
881 MACH_NAME is the bfd name of the mach. */
884 @arch@_cgen_cpu_open_1 (mach_name, endian)
885 const char *mach_name;
886 enum cgen_endian endian;
888 return @arch@_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
889 CGEN_CPU_OPEN_ENDIAN, endian,
893 /* Close a cpu table.
894 ??? This can live in a machine independent file, but there's currently
895 no place to put this file (there's no libcgen). libopcodes is the wrong
896 place as some simulator ports use this but they don't use libopcodes. */
899 @arch@_cgen_cpu_close (cd)
902 if (cd->insn_table.init_entries)
903 free ((CGEN_INSN *) cd->insn_table.init_entries);
904 if (cd->hw_table.entries)
905 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
912 ; General initialization C code
913 ; Code is appended during processing.
915 (define -cputab-init-code "")
916 (define (cputab-add-init! code)
917 (set! -cputab-init-code (string-append -cputab-init-code code))
920 ; Return the C code to define the various initialization functions.
921 ; This does not include assembler/disassembler specific stuff.
922 ; Generally, this function doesn't do anything.
923 ; It exists to allow a global-static-constructor kind of thing should
924 ; one ever be necessary.
926 (define (gen-init-fns)
927 (logit 2 "Generating init fns ...\n")
930 /* Initialize anything needed to be done once, before any cpu_open call. */
931 static void init_tables PARAMS ((void));
941 ; Top level C code generators
943 ; FIXME: Create enum objects for all the enums we explicitly declare here.
944 ; Then they'd be usable and we wouldn't have to special case them here.
946 (define (cgen-desc.h)
947 (logit 1 "Generating " (current-arch-name) " desc.h ...\n")
949 (gen-copyright "CPU data header for @arch@."
950 CURRENT-COPYRIGHT CURRENT-PACKAGE)
957 ; This is defined in arch.h. It's not defined here as there is yet to
958 ; be a need for it in the assembler/disassembler.
959 ;(gen-enum-decl 'model_type "model types"
961 ; (append (map list (map obj:name (current-model-list))) '((max))))
962 ;"#define MAX_MODELS ((int) MODEL_MAX)\n\n"
964 (string-map gen-decl (current-enum-list))
965 "/* Attributes. */\n\n"
966 (string-map gen-decl (current-attr-list))
967 "/* Number of architecture variants. */\n"
968 ; If there is only 1 isa, leave out special handling. */
969 (if (= (length (current-isa-list)) 1)
970 "#define MAX_ISAS 1\n"
971 "#define MAX_ISAS ((int) ISA_MAX)\n")
972 "#define MAX_MACHS ((int) MACH_MAX)\n\n"
977 "/* cgen.h uses things we just defined. */\n"
978 "#include \"opcode/cgen.h\"\n\n"
979 -gen-attr-table-decls
980 -gen-mach-table-decls
983 (lambda () (gen-extra-cpu.h srcdir (current-arch-name))) ; from <arch>.opc
986 #endif /* @ARCH@_CPU_H */
991 ; This file contains the "top level" definitions of the cpu.
992 ; This includes various elements of the description file, expressed in C.
994 ; ??? A lot of this file can go in a machine-independent file! However,
995 ; some simulators don't use the cgen opcodes support so there is currently
996 ; no place to put this file. To be revisited when we do have such a place.
998 (define (cgen-desc.c)
999 (logit 1 "Generating " (current-arch-name) " desc.c ...\n")
1001 (gen-copyright "CPU data for @arch@."
1002 CURRENT-COPYRIGHT CURRENT-PACKAGE)
1004 #include \"sysdep.h\"
1007 #include \"ansidecl.h\"
1009 #include \"symcat.h\"
1010 #include \"@arch@-desc.h\"
1011 #include \"@arch@-opc.h\"
1012 #include \"opintl.h\"
1013 #include \"libiberty.h\"
1015 (lambda () (gen-extra-cpu.c srcdir (current-arch-name))) ; from <arch>.opc
1016 gen-attr-table-defns
1017 -gen-isa-table-defns
1018 -gen-mach-table-defns
1021 gen-multi-ifield-nodes