1 ; CPU family related simulator generator, excluding decoding and model support.
2 ; Copyright (C) 2000, 2002 Red Hat, Inc.
3 ; This file is part of CGEN.
9 (string-upcase (gen-c-symbol (caar (list-take -1
10 (gen-obj-list-enums (non-multi-insns (current-insn-list))))))))
12 ; Declare the attributes.
14 (define (-gen-attr-decls)
16 "// Insn attribute indices.\n\n"
17 (gen-attr-enum-decl "cgen_insn" (current-insn-attr-list))
19 (string-list-map gen-decl (current-attr-list))
23 ; Generate class to hold an instruction's attributes.
25 (define (-gen-insn-attr-decls)
26 (let ((attrs (current-insn-attr-list)))
28 "// Insn attributes.\n\n"
29 ; FIXME: maybe make class, but that'll require a constructor. Later.
30 "struct @arch@_insn_attr {\n"
31 " unsigned int bools;\n"
32 (string-map (lambda (attr)
38 (string-downcase (gen-sym attr))
42 (string-map (lambda (attr)
46 " get_" (string-downcase (gen-sym attr)) "_attr"
49 (string-append "(bools & "
50 (gen-attr-mask "cgen_insn" (obj:name attr))
52 (string-downcase (gen-sym attr)))
61 ; Emit a macro that specifies the word-bitsize for each machine.
62 (define (-gen-mach-params)
63 (string-map (lambda (mach)
65 "#define MACH_" (string-upcase (gen-sym mach)) "_INSN_CHUNK_BITSIZE "
66 (number->string (cpu-insn-chunk-bitsize (mach-cpu mach))) "\n"))
71 ; Generate <cpu>-desc.h.
74 (logit 1 "Generating " (gen-cpu-name) " desc.h ...\n")
77 (gen-c-copyright "Misc. entries in the @arch@ description file."
78 copyright-red-hat package-red-hat-simulators)
87 (lambda () (string-map gen-decl (current-enum-list)))
94 } // end @arch@ namespace
96 #endif /* DESC_@ARCH@_H */\n"
103 ; Print out file containing elements to add to cpu class.
105 ; Get/set fns for hardware element HW.
107 (define (-gen-reg-access-defns hw)
108 (let ((scalar? (hw-scalar? hw))
110 (getter (hw-getter hw))
111 (setter (hw-setter hw))
112 (isas (bitset-attr->list (obj-attr-value hw 'ISA)))
113 (type (gen-type hw)))
114 (let ((get-code (if getter
115 (let ((mode (hw-mode hw))
117 (expr (cadr getter)))
123 (list (list (car args) 'UINT "regno")))
127 "return this->hardware."
129 (if scalar? "" "[regno]")
132 (let ((args (car setter))
133 (expr (cadr setter)))
135 VOID ; not `mode', sets have mode VOID
138 (list (list (car args) (hw-mode hw) "newval"))
139 (list (list (car args) 'UINT "regno")
140 (list (cadr args) (hw-mode hw) "newval")))
141 #:rtl-cover-fns? #t))
145 (if scalar? "" "[regno]")
149 (gen-reg-get-fun-name hw)
151 (if scalar? "" "UINT regno")
156 (gen-reg-set-fun-name hw)
158 (if scalar? "" "UINT regno, ")
164 ; Return a boolean indicating if hardware element HW needs storage allocated
165 ; for it in the SIM_CPU struct.
167 (define (hw-need-storage? hw)
169 (not (obj-has-attr? hw 'VIRTUAL)))
172 ; Subroutine of -gen-hardware-types to generate the struct containing
173 ; hardware elements of one isa.
175 (define (-gen-hardware-struct prefix hw-list)
177 ; If struct is empty, leave it out to simplify generated code.
181 (string-append " // Hardware elements for " prefix ".\n")
182 " // Hardware elements.\n")
184 (string-list-map gen-decl hw-list)
187 (string-append prefix "_")
193 ; Return C type declarations of all of the hardware elements.
194 ; The name of the type is prepended with the cpu family name.
196 (define (-gen-hardware-types)
198 "// CPU state information.\n\n"
199 (-gen-hardware-struct #f (find hw-need-storage? (current-hw-list))))
202 ; Generate <cpu>-cpu.h
205 (logit 1 "Generating " (gen-cpu-name) " cpu.h ...\n")
208 ; Turn parallel execution support on if cpu needs it.
209 (set-with-parallel?! (state-parallel-exec?))
211 ; Initialize rtl->c generation.
212 (rtl-c-config! #:rtl-cover-fns? #t)
215 (gen-c-copyright "CPU class elements for @cpu@."
216 copyright-red-hat package-red-hat-simulators)
218 // This file is included in the middle of the cpu class struct.
225 " // C++ register access function templates\n"
226 "#define current_cpu this\n\n"
228 (string-list-map -gen-reg-access-defns
229 (find register? (current-hw-list))))
230 "#undef current_cpu\n\n"
237 ; Print various parameters of the cpu family.
238 ; A "cpu family" here is a collection of variants of a particular architecture
239 ; that share sufficient commonality that they can be handled together.
241 (define (-gen-cpu-defines)
244 /* Maximum number of instructions that are fetched at a time.
245 This is for LIW type instructions sets (e.g. m32r). */\n"
246 "#define @CPU@_MAX_LIW_INSNS " (number->string (cpu-liw-insns (current-cpu))) "\n\n"
247 "/* Maximum number of instructions that can be executed in parallel. */\n"
248 "#define @CPU@_MAX_PARALLEL_INSNS " (number->string (cpu-parallel-insns (current-cpu))) "\n"
250 ; (gen-enum-decl '@prefix@_virtual
251 ; "@prefix@ virtual insns"
252 ; "@ARCH@_INSN_" ; not @CPU@ to match CGEN_INSN_TYPE in opc.h
254 ; (x-before -1) (x-after -2)
255 ; (x-begin -3) (x-chain -4) (x-cti-chain -5)))
259 ; Generate type of struct holding model state while executing.
261 (define (-gen-model-decls)
262 (logit 2 "Generating model decls ...\n")
268 (if (null? (model:state model))
270 (string-map (lambda (var)
272 (mode:c-type (mode:lookup (cadr var)))
274 (gen-c-symbol (car var))
276 (model:state model)))
278 (if (null? (model:state model)) "BLANK" "@CPU@") "_MODEL_DATA;\n\n"
280 (current-model-list))
282 typedef int (@CPU@_MODEL_FN) (struct @cpu@_cpu*, void*);
285 /* This is an integer that identifies this insn.
286 How this works is up to the target. */
289 /* Function to handle insn-specific profiling. */
290 @CPU@_MODEL_FN *model_fn;
292 /* Array of function units used by this insn. */
293 UNIT units[MAX_UNITS];
294 } @CPU@_INSN_TIMING;"
298 ; Utility of gen-parallel-exec-type to generate the definition of one
299 ; structure in PAREXEC.
300 ; SFMT is an <sformat> object.
302 (define (gen-parallel-exec-elm sfmt)
304 " struct { /* " (obj:comment sfmt) " */\n"
306 ((if (with-parallel-write?) sfmt-out-ops sfmt-in-ops) sfmt)))
311 (logit 2 "Processing operand " (obj:name op) " of format "
312 (obj:name sfmt) " ...\n")
313 (if (with-parallel-write?)
314 (let ((index-type (and (op-save-index? op)
315 (gen-index-type op sfmt))))
316 (string-append " " (gen-type op)
317 " " (gen-sym op) ";\n"
319 (string-append " " index-type
320 " " (gen-sym op) "_idx;\n")
328 " } " (gen-sym sfmt) ";\n"
332 ; Generate the definition of the structure that holds register values, etc.
333 ; for use during parallel execution. When instructions are executed parallelly
335 ; - their inputs are read before their outputs are written. Thus we have to
336 ; fetch the input values of several instructions before executing any of them.
337 ; - or their outputs are queued here first and then written out after all insns
339 ; The fetched/queued values are stored in an array of PAREXEC structs, one
340 ; element per instruction.
342 (define (gen-parallel-exec-type)
343 (logit 2 "Generating PAREXEC type ...\n")
345 (if (with-parallel-write?)
346 "/* Queued output values of an instruction. */\n"
347 "/* Fetched input values of an instruction. */\n")
350 struct @prefix@_parexec {
352 (string-map gen-parallel-exec-elm (current-sfmt-list))
355 /* For conditionally written operands, bitmask of which ones were. */
356 unsigned long long written;
361 ; Generate the TRACE_RECORD struct definition.
363 (define (-gen-trace-record-type)
366 /* Collection of various things for the trace handler to use. */
368 typedef struct @prefix@_trace_record {
371 } @CPU@_TRACE_RECORD;
376 ; Generate <cpu>-defs.h
378 (define (cgen-defs.h)
379 (logit 1 "Generating " (gen-cpu-name) " defs.h ...\n")
382 ; Turn parallel execution support on if cpu needs it.
383 (set-with-parallel?! (state-parallel-exec?))
385 ; Initialize rtl->c generation.
386 (rtl-c-config! #:rtl-cover-fns? #t)
389 (gen-c-copyright "CPU family header for @cpu@ / @prefix@."
390 copyright-red-hat package-red-hat-simulators)
392 #ifndef DEFS_@PREFIX@_H
393 #define DEFS_@PREFIX@_H
399 gen-parallel-exec-type
403 } // end @cpu@ namespace
405 #endif /* DEFS_@PREFIX@_H */\n"
412 ; This is the other way of implementing parallel execution support.
413 ; Instead of fetching all the input operands first, write all the output
414 ; operands and their addresses to holding variables, and then run a
415 ; post-processing pass to update the cpu state.
417 ; Return C code to fetch and save all output operands to instructions with
420 (define (-gen-write-args sfmt)
421 (string-map (lambda (op) (op:write op sfmt))
425 ; Utility of gen-write-fns to generate a writer function for <sformat> SFMT.
427 (define (-gen-write-fn sfmt)
428 (logit 2 "Processing write function for \"" (obj:name sfmt) "\" ...\n")
431 (-gen-write-fn-name sfmt) " (@cpu@_cpu* current_cpu, @prefix@_scache* sem, @prefix@_parexec* par_exec)\n"
434 (gen-define-field-macro sfmt)
436 (gen-define-parallel-operand-macro sfmt)
437 " @prefix@_scache* abuf = sem;\n"
438 " unsigned long long written = abuf->written;\n"
439 " PCADDR pc = abuf->addr;\n"
440 " PCADDR npc = 0; // dummy value for branches\n"
441 " sem_status status = SEM_STATUS_NORMAL; // ditto\n"
443 (-gen-write-args sfmt)
446 (gen-undef-parallel-operand-macro sfmt)
448 (gen-undef-field-macro sfmt)
453 (define (-gen-write-fns)
454 (logit 2 "Processing writer functions ...\n")
455 (string-write-map (lambda (sfmt) (-gen-write-fn sfmt))
460 ; Generate <cpu>-write.cxx.
462 (define (cgen-write.cxx)
463 (logit 1 "Generating " (gen-cpu-name) " write.cxx ...\n")
468 ; Turn parallel execution support off.
469 (set-with-parallel?! #f)
471 ; Tell the rtx->c translator we are the simulator.
472 (rtl-c-config! #:rtl-cover-fns? #t)
475 (gen-c-copyright (string-append "Simulator instruction operand writer for "
476 (symbol->string (current-arch-name))
478 copyright-red-hat package-red-hat-simulators)
482 using namespace @cpu@;
492 ; Return C code to perform the semantics of INSN.
494 (define (gen-semantic-code insn)
495 ; Indicate generating code for INSN.
496 ; Use the compiled form if available.
497 ; The case when they're not available is for virtual insns.
499 (if (insn-compiled-semantics insn)
500 (rtl-c++-parsed VOID (insn-compiled-semantics insn) nil
503 (rtl-c++ VOID (insn-semantics insn) nil
510 ; Return definition of C function to perform INSN.
511 ; This version handles the with-scache case.
513 (define (-gen-scache-semantic-fn insn)
514 (logit 2 "Processing semantics for " (obj:name insn) ": \"" (insn-syntax insn) "\" ...\n")
515 (set! -with-profile? -with-profile-fn?)
516 (let ((cti? (insn-cti? insn))
517 (insn-len (insn-length-bytes insn)))
519 "// ********** " (obj:name insn) ": " (insn-syntax insn) "\n\n"
523 "@prefix@_sem_" (gen-sym insn)
525 " (@cpu@_cpu* current_cpu, @prefix@_scache* sem, @prefix@_parexec* par_exec)\n"
526 " (@cpu@_cpu* current_cpu, @prefix@_scache* sem)\n")
528 (gen-define-field-macro (insn-sfmt insn))
530 (gen-define-parallel-operand-macro (insn-sfmt insn))
532 " sem_status status = SEM_STATUS_NORMAL;\n"
533 " @prefix@_scache* abuf = sem;\n"
534 ; Unconditionally written operands are not recorded here.
535 (if (or (with-profile?) (with-parallel-write?))
536 " unsigned long long written = 0;\n"
538 ; The address of this insn, needed by extraction and semantic code.
539 ; Note that the address recorded in the cpu state struct is not used.
540 ; For faster engines that copy will be out of date.
541 " PCADDR pc = abuf->addr;\n"
542 " PCADDR npc = pc + " (number->string insn-len) ";\n"
544 (gen-semantic-code insn)
546 ; Only update what's been written if some are conditionally written.
547 ; Otherwise we know they're all written so there's no point in
549 (if (or (with-profile?) (with-parallel-write?))
550 (if (-any-cond-written? (insn-sfmt insn))
551 " abuf->written = written;\n"
555 " current_cpu->done_cti_insn (npc, status);\n"
556 " current_cpu->done_insn (npc, status);\n")
561 (gen-undef-parallel-operand-macro (insn-sfmt insn))
563 (gen-undef-field-macro (insn-sfmt insn))
568 (define (-gen-all-semantic-fns)
569 (logit 2 "Processing semantics ...\n")
570 (let ((insns (scache-engine-insns)))
572 (string-write-map -gen-scache-semantic-fn insns)
573 (error "must specify `with-scache'")))
576 ; Generate <cpu>-sem.cxx.
577 ; Each instruction is implemented in its own function.
579 (define (cgen-semantics.cxx)
580 (logit 1 "Generating " (gen-cpu-name) " semantics.cxx ...\n")
585 ; Turn parallel execution support on if cpu needs it.
586 (set-with-parallel?! (state-parallel-exec?))
588 ; Tell the rtx->c translator we are the simulator.
589 (rtl-c-config! #:rtl-cover-fns? #t)
591 ; Indicate we're currently not generating a pbb engine.
592 (set-current-pbb-engine?! #f)
595 (gen-c-copyright "Simulator instruction semantics for @prefix@."
596 copyright-red-hat package-red-hat-simulators)
600 #include \"config.h\"
604 using namespace @cpu@; // FIXME: namespace organization still wip
606 #define GET_ATTR(name) GET_ATTR_##name ()
610 -gen-all-semantic-fns
614 ; *******************
615 ; cgen-sem-switch.cxx
617 ; The semantic switch engine has two flavors: one case per insn, and one
618 ; case per "frag" (where each insn is split into one or more fragments).
620 ; Utility of -gen-sem-case to return the mask of operands always written
621 ; to in <sformat> SFMT.
622 ; ??? Not currently used.
624 (define (-uncond-written-mask sfmt)
625 (apply + (map (lambda (op)
628 (logsll 1 (op:num op))))
629 (sfmt-out-ops sfmt)))
632 ; Utility of -gen-sem-case to return #t if any operand in <sformat> SFMT is
633 ; conditionally written to.
635 (define (-any-cond-written? sfmt)
636 (any-true? (map op:cond? (sfmt-out-ops sfmt)))
639 ; One case per insn version.
641 ; Generate a switch case to perform INSN.
643 (define (-gen-sem-case insn parallel?)
644 (logit 2 "Processing "
645 (if parallel? "parallel " "")
646 "semantic switch case for \"" (insn-syntax insn) "\" ...\n")
647 (set! -with-profile? -with-profile-sw?)
648 (let ((cti? (insn-cti? insn))
649 (insn-len (insn-length-bytes insn)))
651 ; INSN_ is prepended here and not elsewhere to avoid name collisions
652 ; with symbols like AND, etc.
654 // ********** " (insn-syntax insn) "
656 CASE (INSN_" (if parallel? "PAR_" "") (string-upcase (gen-sym insn)) "):
658 @prefix@_scache* abuf = vpc;\n"
660 (gen-define-field-macro (insn-sfmt insn))
663 (gen-define-parallel-operand-macro (insn-sfmt insn))
665 ; Unconditionally written operands are not recorded here.
666 (if (or (with-profile?) (with-parallel-write?))
667 " unsigned long long written = 0;\n"
669 ; The address of this insn, needed by extraction and semantic code.
670 ; Note that the address recorded in the cpu state struct is not used.
671 " PCADDR pc = abuf->addr;\n"
672 (if (and cti? (not parallel?))
673 (string-append " PCADDR npc;\n"
674 " branch_status br_status = BRANCH_UNTAKEN;\n")
676 (string-list " vpc = vpc + 1;\n")
677 ; Emit setup-semantics code for real insns.
678 (if (and (insn-real? insn)
679 (isa-setup-semantics (current-isa)))
682 (rtl-c++ VOID (isa-setup-semantics (current-isa)) nil
687 (gen-semantic-code insn)
689 ; Only update what's been written if some are conditionally written.
690 ; Otherwise we know they're all written so there's no point in
692 (if (or (with-profile?) (with-parallel-write?))
693 (if (-any-cond-written? (insn-sfmt insn))
694 " abuf->written = written;\n"
697 (if (and cti? (not parallel?))
698 (string-append " pbb_br_npc = npc;\n"
699 " pbb_br_status = br_status;\n")
702 (gen-undef-parallel-operand-macro (insn-sfmt insn))
705 (gen-undef-field-macro (insn-sfmt insn))
712 (define (-gen-sem-switch)
713 (logit 2 "Processing semantic switch ...\n")
714 ; Turn parallel execution support off.
715 (set-with-parallel?! #f)
716 (string-write-map (lambda (insn) (-gen-sem-case insn #f))
717 (non-multi-insns (non-alias-insns (current-insn-list))))
720 ; Generate the guts of a C switch statement to execute parallel instructions.
721 ; This switch is included after the non-parallel instructions in the semantic
724 ; ??? We duplicate the writeback case for each insn, even though we only need
725 ; one case per insn format. The former keeps the code for each insn
726 ; together and might improve cache usage. On the other hand the latter
727 ; reduces the amount of code, though it is believed that in this particular
728 ; instance the win isn't big enough.
730 (define (-gen-parallel-sem-switch)
731 (logit 2 "Processing parallel insn semantic switch ...\n")
732 ; Turn parallel execution support on.
733 (set-with-parallel?! #t)
734 (string-write-map (lambda (insn)
735 (string-list (-gen-sem-case insn #t)
736 (-gen-write-case (insn-sfmt insn) insn)))
737 (parallel-insns (current-insn-list)))
740 ; Return computed-goto engine.
742 (define (-gen-sem-switch-engine)
746 @cpu@_cpu::@prefix@_pbb_run ()
748 @cpu@_cpu* current_cpu = this;
749 @prefix@_scache* vpc;
750 // These two are used to pass data from cti insns to the cti-chain insn.
752 branch_status pbb_br_status;
756 static const struct sem_labels
758 enum @prefix@_insn_type insn;
765 (string-write-map (lambda (insn)
768 (string-upcase (gen-sym insn))
770 (string-upcase (gen-sym insn))
772 (non-multi-insns (non-alias-insns (current-insn-list)))))
774 (if (state-parallel-exec?)
776 (string-write-map (lambda (insn)
779 (string-upcase (gen-sym insn))
780 ", && case_INSN_PAR_"
781 (string-upcase (gen-sym insn))
784 "@PREFIX@_INSN_WRITE_"
785 (string-upcase (gen-sym insn))
786 ", && case_INSN_WRITE_"
787 (string-upcase (gen-sym insn))
789 (parallel-insns (current-insn-list))))
792 " { (@prefix@_insn_type) 0, 0 }
795 if (! @prefix@_idesc::idesc_table_initialized_p)
797 for (int i=0; labels[i].label != 0; i++)
798 @prefix@_idesc::idesc_table[labels[i].insn].cgoto.label = labels[i].label;
800 // confirm that table is all filled up
801 for (int i = 0; i <= @PREFIX@_INSN_" (-last-insn) "; i++)
802 assert (@prefix@_idesc::idesc_table[i].cgoto.label != 0);
804 // Initialize the compiler virtual insn.
805 current_cpu->@prefix@_engine.compile_begin_insn (current_cpu);
807 @prefix@_idesc::idesc_table_initialized_p = true;
813 #define CASE(X) case_##X
814 // Branch to next handler without going around main loop.
815 #define NEXT(vpc) goto * vpc->execute.cgoto.label;
816 // Break out of threaded interpreter and return to \"main loop\".
817 #define BREAK(vpc) goto end_switch
819 #define CASE(X) case @PREFIX@_##X
820 #define NEXT(vpc) goto restart
821 #define BREAK(vpc) break
824 // Get next insn to execute.
825 vpc = current_cpu->@prefix@_engine.get_next_vpc (current_cpu->h_pc_get ());
829 goto * vpc->execute.cgoto.label;
831 switch (vpc->idesc->sem_index)
839 (if (state-parallel-exec?)
840 -gen-parallel-sem-switch
851 // Save vpc for next time.
852 current_cpu->@prefix@_engine.set_next_vpc (vpc);
858 ; Semantic frag version.
860 ; Return declaration of frag enum.
862 (define (-gen-sfrag-enum-decl frag-list)
863 (gen-enum-decl "@prefix@_frag_type"
864 "semantic fragments in cpu family @prefix@"
866 (append '((list-end))
870 (atlist-attrs (obj-atlist i)))))
875 ; Return header file decls for semantic frag threaded engine.
877 (define (-gen-sfrag-engine-decls)
879 "namespace @cpu@ {\n\n"
881 ; FIXME: vector->list
882 (-gen-sfrag-enum-decl (vector->list (sim-sfrag-frag-table)))
885 struct @prefix@_insn_frag {
886 @PREFIX@_INSN_TYPE itype;
887 // 4: header+middle+trailer+delimiter
888 @PREFIX@_FRAG_TYPE ftype[4];
891 struct @prefix@_pbb_label {
892 @PREFIX@_FRAG_TYPE frag;
896 } // end @cpu@ namespace
900 ; Return C code to perform the semantics of FRAG.
901 ; LOCALS is a list of sequence locals made global to all frags.
902 ; Each element is (symbol <mode> "c-var-name").
904 (define (-gen-sfrag-code frag locals)
905 ; Indicate generating code for FRAG.
906 ; Use the compiled form if available.
907 ; The case when they're not available is for virtual insns.
908 (let ((sem (sfrag-compiled-semantics frag))
909 ; If the frag has one owner, use it. Otherwise indicate the owner is
910 ; unknown. In cases where the owner is needed by the semantics, the
911 ; frag should have only one owner.
912 (owner (if (= (length (sfrag-users frag)) 1)
913 (car (sfrag-users frag))
917 (rtl-c++-parsed VOID sem locals
920 (rtl-c++ VOID (sfrag-semantics frag) locals
925 ; Generate a switch case to perform FRAG.
926 ; LOCALS is a list of sequence locals made global to all frags.
927 ; Each element is (symbol <mode> "c-var-name").
929 (define (-gen-sfrag-case frag locals)
930 (set! -with-profile? -with-profile-sw?)
931 (let ((cti? (sfmt-cti? (sfrag-sfmt frag)))
932 (parallel? (sfrag-parallel? frag)))
933 (logit 2 "Processing "
934 (if parallel? "parallel " "")
935 "semantic switch case for \"" (obj:name frag) "\" ...\n")
937 ; FRAG_ is prepended here and not elsewhere to avoid name collisions
938 ; with symbols like AND, etc.
941 (if (= (length (sfrag-users frag)) 1)
945 (string-map (lambda (user)
946 (string-append ", " (obj:str-name user)))
950 CASE (FRAG_" (string-upcase (gen-sym frag)) "):
952 (if (sfrag-header? frag)
953 (string-append " abuf = vpc;\n"
956 (gen-define-field-macro (sfrag-sfmt frag))
958 (gen-define-parallel-operand-macro (sfrag-sfmt frag))
960 ; Unconditionally written operands are not recorded here.
961 (if (or (with-profile?) (with-parallel-write?))
962 " unsigned long long written = 0;\n"
964 ; The address of this insn, needed by extraction and semantic code.
965 ; Note that the address recorded in the cpu state struct is not used.
966 " PCADDR pc = abuf->addr;\n"
969 (sfrag-header? frag))
970 (string-append ; " npc = 0;\n" ??? needed?
971 " br_status = BRANCH_UNTAKEN;\n")
973 ; Emit setup-semantics code for headers of real insns.
974 (if (and (sfrag-header? frag)
975 (not (obj-has-attr? frag 'VIRTUAL))
976 (isa-setup-semantics (current-isa)))
979 (rtl-c++ VOID (isa-setup-semantics (current-isa)) nil
984 (-gen-sfrag-code frag locals)
986 ; Only update what's been written if some are conditionally written.
987 ; Otherwise we know they're all written so there's no point in
989 (if (or (with-profile?) (with-parallel-write?))
990 (if (-any-cond-written? (sfrag-sfmt frag))
991 " abuf->written = written;\n"
996 (sfrag-trailer? frag))
997 (string-append " pbb_br_npc = npc;\n"
998 " pbb_br_status = br_status;\n")
1001 (gen-undef-parallel-operand-macro (sfrag-sfmt frag))
1003 (gen-undef-field-macro (sfrag-sfmt frag))
1005 (if (sfrag-trailer? frag)
1006 " NEXT_INSN (vpc, fragpc);\n"
1007 " NEXT_FRAG (fragpc);\n")
1012 ; Convert locals from form computed by sem-find-common-frags to that needed by
1013 ; -gen-sfrag-engine-code (and ultimately rtl-c++).
1015 (define (-frag-convert-c-locals locals)
1016 (map (lambda (local)
1017 (list (car local) (mode:lookup (cadr local))
1018 (gen-c-symbol (car local))))
1022 ; Return definition of insn frag usage table.
1024 (define (-gen-sfrag-engine-frag-table insn-list frag-table frag-usage)
1027 // Table of frags used by each insn.
1029 const @prefix@_insn_frag @prefix@_frag_usage[] = {\n"
1032 (for-each (lambda (insn frag-nums)
1035 (string-upcase (gen-sym insn))
1036 (string-map (lambda (frag-num)
1037 (string-append ", @PREFIX@_FRAG_"
1038 (string-upcase (gen-sym (vector-ref frag-table frag-num)))))
1040 ", @PREFIX@_FRAG_LIST_END },\n"))
1041 insn-list frag-usage)
1046 ; Return sfrag computed-goto engine.
1047 ; LOCALS is a list of sequence locals made global to all frags.
1048 ; Each element is (symbol <mode> "c-var-name").
1050 (define (-gen-sfrag-engine-fn frag-table locals)
1054 @cpu@_cpu::@prefix@_pbb_run ()
1056 @cpu@_cpu* current_cpu = this;
1057 @prefix@_scache* vpc;
1058 @prefix@_scache* abuf;
1062 ARM_FRAG_TYPE* fragpc;
1067 static const @prefix@_pbb_label labels[] =
1069 { @PREFIX@_FRAG_LIST_END, 0 },
1073 (string-write-map (lambda (frag)
1074 (string-append " { "
1076 (string-upcase (gen-sym frag))
1078 (string-upcase (gen-sym frag))
1080 ; FIXME: vector->list
1081 (vector->list frag-table)))
1084 { @PREFIX@_FRAG_MAX, 0 }
1087 if (! @prefix@_idesc::idesc_table_initialized_p)
1089 // Several tables are in play here:
1090 // idesc table: const table of misc things for each insn
1091 // frag usage table: const set of frags used by each insn
1092 // frag label table: same as frag usage table, but contains labels
1093 // selected insn frag table: table of pointers to either the frag usage
1094 // table (if !gnuc) or frag label table (if gnuc) for the currently
1095 // selected ISA. Insns not in the ISA are redirected to the `invalid'
1096 // insn handler. FIXME: This one isn't implemented yet.
1098 // Allocate frag label table and point idesc table entries at it.
1099 // FIXME: Temporary hack, to be redone.
1100 static void** frag_label_table;
1101 int max_insns = @PREFIX@_INSN_" (-last-insn) " + 1;
1102 int tabsize = max_insns * 4;
1103 frag_label_table = new void* [tabsize];
1104 memset (frag_label_table, 0, sizeof (void*) * tabsize);
1107 for (i = 0, v = frag_label_table; i < max_insns; ++i)
1109 @prefix@_idesc::idesc_table[@prefix@_frag_usage[i].itype].cgoto.frags = v;
1110 for (int j = 0; @prefix@_frag_usage[i].ftype[j] != @PREFIX@_FRAG_LIST_END; ++j)
1111 *v++ = labels[@prefix@_frag_usage[i].ftype[j]].label;
1114 // Initialize the compiler virtual insn.
1115 // FIXME: Also needed if !gnuc.
1116 current_cpu->@prefix@_engine.compile_begin_insn (current_cpu);
1118 @prefix@_idesc::idesc_table_initialized_p = true;
1124 #define CASE(X) case_##X
1125 // Branch to next handler without going around main loop.
1126 #define NEXT_INSN(vpc, fragpc) fragpc = vpc->execute.cgoto.frags; goto * *fragpc
1127 #define NEXT_FRAG(fragpc) ++fragpc; goto * *fragpc
1128 // Break out of threaded interpreter and return to \"main loop\".
1129 #define BREAK(vpc) goto end_switch
1131 #define CASE(X) case @PREFIX@_##X
1132 #define NEXT_INSN(vpc, fragpc) fragpc = vpc->idesc->frags; goto restart
1133 #define NEXT_FRAG(fragpc) ++fragpc; goto restart
1134 #define BREAK(vpc) break
1137 // Get next insn to execute.
1138 vpc = current_cpu->@prefix@_engine.get_next_vpc (current_cpu->h_pc_get ());
1141 // These two are used to pass data from cti insns to the cti-chain insn.
1143 branch_status pbb_br_status;
1144 // These two are used to build up values of the previous two.
1146 branch_status br_status;
1147 // Top level locals moved here so they're usable by multiple fragments.
1151 (string-write-map (lambda (local)
1153 (mode:c-type (cadr local))
1163 fragpc = vpc->execute.cgoto.frags;
1166 fragpc = vpc->idesc->frags;
1175 ; Turn parallel execution support off.
1177 (set-with-parallel?! #f)
1178 (string-write-map (lambda (frag)
1179 (-gen-sfrag-case frag locals))
1180 ; FIXME: vector->list
1181 (vector->list frag-table)))
1192 // Save vpc for next time.
1193 current_cpu->@prefix@_engine.set_next_vpc (vpc);
1198 (define (-gen-sfrag-engine)
1201 (-gen-sfrag-engine-frag-table (sim-sfrag-insn-list)
1202 (sim-sfrag-frag-table)
1203 (sim-sfrag-usage-table)))
1205 (-gen-sfrag-engine-fn (sim-sfrag-frag-table)
1206 (-frag-convert-c-locals (sim-sfrag-locals-list))))
1210 ; Generate sem-switch.cxx.
1212 (define (cgen-sem-switch.cxx)
1213 (logit 1 "Generating " (gen-cpu-name) " sem-switch.cxx ...\n")
1215 (sim-analyze-insns!)
1216 (if (with-sem-frags?)
1217 (sim-sfrag-analyze-insns!))
1219 ; Turn parallel execution support off.
1220 ; It is later turned on/off when generating the actual semantic code.
1221 (set-with-parallel?! #f)
1223 ; Tell the rtx->c translator we are the simulator.
1224 (rtl-c-config! #:rtl-cover-fns? #t)
1226 ; Indicate we're currently generating a pbb engine.
1227 (set-current-pbb-engine?! #t)
1230 (gen-c-copyright "Simulator instruction semantics for @prefix@."
1231 copyright-red-hat package-red-hat-simulators)
1234 #include \"@cpu@.h\"
1236 using namespace @cpu@; // FIXME: namespace organization still wip
1238 #define GET_ATTR(name) GET_ATTR_##name ()
1242 (if (with-sem-frags?)
1243 -gen-sfrag-engine-decls
1246 (if (with-sem-frags?)
1248 -gen-sem-switch-engine)