1 ; SPARC32 CPU description. -*- Scheme -*-
2 ; This file contains elements specific to sparc32.
3 ; Copyright (C) 2000 Red Hat, Inc.
4 ; This file is part of CGEN.
5 ; See file COPYING.CGEN for details.
8 ; - sparc64 support wip
10 ; - source file layout wip
11 ; - cpu family layout wip
13 ; ??? For the nonce there is one cpu family to cover all 32 bit sparcs.
14 ; It's not clear this will work, but following the goal of incremental
19 (comment "SPARC 32 bit architecture")
22 ; Generated files have a "32" suffix.
35 (comment "Fujitsu sparclite")
37 (bfd-name "sparc_sparclite")
44 (comment "sparc32 default")
48 (pipeline p-foo "" () ((fetch) (decode) (execute) (memory) (writeback)))
49 (unit u-exec "Execution Unit" ()
54 ; sparc32 enums of opcodes, special insn values, etc.
56 ; sparc32 hardware pieces.
58 ; ??? impl,ver are left as part of h-psr (change maybe later)
61 (comment "psr register")
63 (get () (c-call USI "@cpu@_get_h_psr_handler"))
64 (set (newval) (c-call VOID "@cpu@_set_h_psr_handler" newval))
67 (dsh h-s "supervisor bit" () (register BI))
68 (dsh h-ps "previous supervisor bit" () (register BI))
70 (dsh h-pil "processor interrupt level" () (register UQI))
72 (dsh h-et "enable traps bit" () (register BI))
76 (comment "trap base register")
78 ;CPU (h_tbr) = (CPU (h_tbr) & 0xff0) | ((newval) & 0xfffff000);
79 (set (newval) (set (raw-reg WI h-tbr)
80 (or WI (and WI (raw-reg WI h-tbr) (const #xff0))
81 (and WI newval (const #xfffff000)))))
86 (comment "current window pointer")
88 (set (newval) (c-call VOID "@cpu@_set_h_cwp_handler" newval))
93 (comment "window invalid mask")
95 ; ??? These just put ideas down so I can play with them. Ignore.
96 ;(get (value index) (and SI value (c-code SI "((1 << NWINDOWS) - 1)")))
97 ;(get (self mode index insn)
98 ; (c-code USI "(CPU (h_wim) & ((1 << NWINDOWS) - 1))"))
99 ;(set (self mode index insn newval)
100 ; (s-eval `(set SI ,self (and SI ,newval (const #xff)))))
101 (get () (and (raw-reg USI h-wim)
102 (sub (sll (const 1) (c-raw-call SI "GET_NWINDOWS")) (const 1))))
105 (dsh h-ag "alternate global indicator" () (register QI))
107 ; Coprocessor support.
109 (dsh h-ec "enable coprocessor bit" () (register BI))
111 ; Floating point support.
113 ; - currently evaluating the various possibilities
115 (dsh h-ef "enable fpu bit" () (register BI))
117 (dsh h-fsr "floating point status register" () (register USI))
119 ; sparc32 instruction definitions.
121 ; Special register move operations.
123 ; %y is handled by the asr insns
125 (dni rd-asr "read asr" ()
126 "rd $rdasr,$rd" ; note: `rdasr' is for ReaD asr, `rd' is for Reg Dest.
127 (+ OP_2 OP3_RDASR rd rdasr (f-i 0) (f-simm13 0))
130 (dni wr-asr "write asr" ()
131 "wr $rs1,$rs2,$wrasr"
132 (+ OP_2 OP3_WRASR wrasr rs1 rs2 (f-i 0) (f-res-asi 0))
133 (set wrasr (xor rs1 rs2))
135 (dni wr-asr-imm "write-imm asr" ()
136 "wr $rs1,$simm13,$wrasr"
137 (+ OP_2 OP3_WRASR wrasr rs1 (f-i 1) simm13)
138 (set wrasr (xor rs1 simm13))
141 (define-pmacro (rdwr-op name op3 asm-name reg-name)
143 (dni (.sym rd- name) (.str "read " name) ()
144 (.str "rd " asm-name ",$rd")
145 (+ OP_2 (.sym OP3_RD op3) rd (f-rs1 0) (f-i 0) (f-simm13 0))
146 (set rd (reg WI reg-name))
148 (dni (.sym wr- name) (.str "write " name) ()
149 (.str "wr $rs1,$rs2," asm-name)
150 (+ OP_2 (.sym OP3_WR op3) (f-rd 0) rs1 rs2 (f-i 0) (f-res-asi 0))
151 (set (reg WI reg-name) (xor rs1 rs2))
153 (dni (.sym wr- name -imm) (.str "write-imm " name) ()
154 (.str "wr $rs1,$simm13," asm-name)
155 (+ OP_2 (.sym OP3_WR op3) (f-rd 0) rs1 (f-i 1) simm13)
156 (set (reg WI reg-name) (xor rs1 simm13))
161 (rdwr-op psr PSR "%psr" h-psr)
162 (rdwr-op wim WIM "%wim" h-wim)
163 (rdwr-op tbr TBR "%tbr" h-tbr)
169 ; - ldc, lddc, ldcsr, stc, stdc, stcsr, stdcq