client/trunk/anago/bandai_fcg3_x24c01.ag

   1 /*\r
   2 BANDAI FCG-3 + X24C01 style cartridge\r
   3 \r
   4 SDガンダム外伝 ナイトガンダム物語\r
   5         1990-08-11 B50EEP, LZ93D50+X24C01\r
   6 ドラゴンボールZ 強襲！サイヤ人\r
   7         1990-10-27 DRAGON BALLZ, LZ93D50+X24C01\r
   8 まじかる☆タルるートくん ファンタスティックワールド\r
   9         1991-03-21 DRAGON BALLZ-B, LZ93D50+X24C01\r
  10 まじかる☆タルるートくん2\r
  11         1992-06-19 DRAGON BALLZ-B, LZ93D50+X24C01 ← 24C02 ではない\r
  12 */\r
  13 board <- {\r
  14         mappernum = 16, \r
  15         cpu_rom = {\r
  16                 size_base = 2 * mega, size_max = 2 * mega,\r
  17                 banksize = 0x4000\r
  18         }, \r
  19         cpu_ram = {\r
  20                 size_base = 0x0080, size_max = 0x0080,\r
  21                 banksize = 0x0080\r
  22         },\r
  23         ppu_rom = {\r
  24                 size_base = 1 * mega, size_max = 2 * mega,\r
  25                 banksize = 0x0400\r
  26         },\r
  27         ppu_ramfind = false,\r
  28         vram_mirrorfind = false\r
  29 };\r
  30 \r
  31 const register_offset = 0x8000;\r
  32 dofile("fcg3.ai");\r
  33 \r
  34 /*\r
  35 =====================\r
  36 X24C01 frame sequence\r
  37 =====================\r
  38 <START>[EEPROM address+RW]<A-ACK>[data]<D-ACK><STOP>\r
  39 \r
  40 <> is 1bit, [] is 8bit, A-ACK is address acknowledge, \r
  41 D-ACK is data acknowledge, R is 1, W is 0\r
  42 \r
  43 8bit data send MSB to LSB (bit7 to bit0)\r
  44 Dragon Ball Z1's program send address LSB to MSB (bug).\r
  45 \r
  46 slave address does not exist.\r
  47 \r
  48 --current address read--\r
  49 <START>[EEPROM address,R]<A-ACK>[EEPROM data]<D-ACK><STOP>\r
  50 \r
  51 --sequenctial read--\r
  52 <START>[EEPROM address,R]<A-ACK>|[EEPROM data]<D-ACK>|<STOP>\r
  53                                 |<- loop any times ->|\r
  54 \r
  55 --page write---\r
  56 |<START>[EEPROM address,W]<A-ACK>|[EEPROM data]<D-ACK>|<STOP>\r
  57 |<-     loop A-ACK is H        ->|<- loop 1to4times ->|\r
  58 */\r
  59 \r
  60 function cpu_ram_access(d, pagesize, banksize)\r
  61 {\r
  62         local I2C_WRITE = I2C_SEND_L;\r
  63         local I2C_READ = I2C_SEND_H;\r
  64 \r
  65         if(mode_is_read(d) == true){\r
  66                 //sequential read\r
  67                 i2c_address_set(d, 0, I2C_READ);\r
  68                 for(local i = 0; i < pagesize * banksize; i++){\r
  69                         for(local bit = 0; bit < 8; bit++){\r
  70                                 cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_H);\r
  71                                 cpu_write(d, 0x800d, I2C_DIR_READ | I2C_CLOCK_H | I2C_SEND_H);\r
  72                                 cpu_read_bit_msb(d, 0x6000, 4);\r
  73                         }\r
  74                         //send ack\r
  75                         send_bit(d, I2C_SEND_L);\r
  76                 }\r
  77                 i2c_stop(d);\r
  78         }else{\r
  79                 //page write (4byte)\r
  80                 for(local i = 0; i < pagesize * banksize; i+=4){\r
  81                         i2c_address_set(d, i, I2C_WRITE);\r
  82                         for(local j = 0; j < 4; j++){\r
  83                                 for(local bit = 0; bit < 8; bit++){\r
  84                                         local n = I2C_SEND_L;\r
  85                                         if(cpu_fetch_bit_msb(d) != 0){\r
  86                                                 n = I2C_SEND_H;\r
  87                                         }\r
  88                                         send_bit(d, n);\r
  89                                 }\r
  90                                 i2c_ack_wait(d);\r
  91                         }\r
  92                         i2c_stop(d);\r
  93                 }\r
  94         }\r
  95 }\r