client/trunk/hard_onajimi.h

   1 #ifndef _HARD_ONAJIMI_H_
   2 #define _HARD_ONAJIMI_H_
   3 /*
   4 STROB: CPU/PPU ADDRESS BUS control
   5 L Address reset, address = 0
   6 H Address Enable
   7 */
   8 enum{
   9         ADDRESS_RESET = 1,
  10         ADDRESS_ENABLE = 0
  11 };
  12 /*
  13 D0: CPU/PPU ADDRESS BUS increment
  14 D1: CPU/PPU DATA SHIFT
  15 D2: CPU/PPU DATA WRITE DATA
  16 D3: CPU/PPU DATA DIRECTION
  17 D4: PPU /WR + CPU ¦Õ2
  18 D5: PPU /CS
  19 D6: CPU ROM area /CS
  20 D7: CPU /WR
  21 */
  22 enum BITNUM{
  23         BITNUM_ADDRESS_INCREMENT = 0,
  24         BITNUM_DATA_SHIFT_RIGHT,
  25         BITNUM_DATA_WRITE_DATA,
  26         BITNUM_DATA_DIRECTION,
  27         BITNUM_CPU_M2,
  28         BITNUM_PPU_SELECT,
  29         BITNUM_CPU_RAMROM_SELECT,
  30         BITNUM_CPU_RW,
  31         BITNUM_PPU_RW = BITNUM_CPU_M2
  32 };
  33 /*
  34 D0: CPU/PPU ADDRESS BUS increment
  35 H->L address += 1
  36
  37 D1: CPU/PPU DATA SHIFT (¥Ð¥¹¤ÎÀÜÂ³¤¬È¿Å¾¤·¤Æ¤¤¤ë)
  38 L->H D01234567
  39
  40 D2: CPU/PPU DATA WRITE DATA
  41 LSB->MSB ºÇ²¼°Ìbit¤«¤é½ç¤Ë¡£
  42 */
  43 enum{
  44         ADDRESS_NOP = 1 << BITNUM_ADDRESS_INCREMENT,
  45         DATA_SHIFT_NOP = 0 << BITNUM_DATA_SHIFT_RIGHT
  46 };
  47 /*
  48 D3: CPU/PPU DATA DIRECTION
  49 H FC read
  50 L FC write
  51 */
  52 enum{
  53         DATA_DIRECTION_WRITE = 0,
  54         DATA_DIRECTION_READ = 1
  55 };
  56 /*
  57 D4: PPU /WE + CPU M2
  58 H PPU read + CPU bus enable (for MMC5)
  59 L PPU write + CPU bus disable
  60 */
  61 enum{
  62         PPU_WRITE__CPU_DISABLE = 0,
  63         PPU_READ__CPU_ENABLE
  64 };
  65 /*
  66 D5: PPU /RD + PPU A13
  67 H disable
  68 L enable
  69 */
  70 enum{
  71         PPU_ENABLE = 0,
  72         PPU_DISABLE
  73 };
  74 /*
  75 D6: CPU ROM select (~A15)
  76 H RAM IO select, use $0000-$7fff
  77 L ROM select, use $8000-$ffff
  78 */
  79 enum{
  80         CPU_ROM_SELECT = 0,
  81         CPU_RAM_SELECT
  82 };
  83 /*
  84 D7: CPU W/~R
  85 L write
  86 H read
  87 */
  88 enum{
  89         CPU_WRITE = 0,
  90         CPU_READ
  91 };
  92 /*
  93 BUSY: CPU/PPU DATA READ DATA
  94 LSB->MSB ºÇ²¼°Ìbit¤«¤é½ç¤Ë¡£
  95 */
  96 #endif