1 # -------------------------------------------------------------------------- #
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3 # Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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4 # Your use of Altera Corporation's design tools, logic functions
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5 # and other software and tools, and its AMPP partner logic
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6 # functions, and any output files from any of the foregoing
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7 # (including device programming or simulation files), and any
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8 # associated documentation or information are expressly subject
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9 # to the terms and conditions of the Altera Program License
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10 # Subscription Agreement, the Altera Quartus II License Agreement,
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11 # the Altera MegaCore Function License Agreement, or other
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12 # applicable license agreement, including, without limitation,
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13 # that your use is for the sole purpose of programming logic
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14 # devices manufactured by Altera and sold by Altera or its
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15 # authorized distributors. Please refer to the applicable
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16 # agreement for further details.
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18 # -------------------------------------------------------------------------- #
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21 # Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
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22 # Date created = 15:11:02 May 18, 2016
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24 # -------------------------------------------------------------------------- #
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28 # 1) The default values for assignments are stored in the file:
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29 # de0_cv_nes_assignment_defaults.qdf
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30 # If this file doesn't exist, see file:
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31 # assignment_defaults.qdf
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33 # 2) Altera recommends that you do not modify this file. This
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34 # file is updated automatically by the Quartus II software
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35 # and any changes you make may be lost or overwritten.
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37 # -------------------------------------------------------------------------- #
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40 set_global_assignment -name FAMILY "Cyclone V"
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41 set_global_assignment -name DEVICE 5CEBA4F23C7
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42 set_global_assignment -name TOP_LEVEL_ENTITY de0_cv_nes
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43 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
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44 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:11:02 MAY 18, 2016"
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45 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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46 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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47 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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48 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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49 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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50 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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51 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
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52 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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53 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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54 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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55 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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56 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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57 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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58 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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59 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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60 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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64 set_location_assignment PIN_M9 -to pi_base_clk
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68 set_location_assignment PIN_A9 -to po_r[0]
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69 set_location_assignment PIN_B10 -to po_r[1]
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70 set_location_assignment PIN_C9 -to po_r[2]
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71 set_location_assignment PIN_A5 -to po_r[3]
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72 set_location_assignment PIN_L7 -to po_g[0]
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73 set_location_assignment PIN_K7 -to po_g[1]
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74 set_location_assignment PIN_J7 -to po_g[2]
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75 set_location_assignment PIN_J8 -to po_g[3]
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76 set_location_assignment PIN_B6 -to po_b[0]
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77 set_location_assignment PIN_B7 -to po_b[1]
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78 set_location_assignment PIN_A8 -to po_b[2]
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79 set_location_assignment PIN_A7 -to po_b[3]
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80 set_location_assignment PIN_H8 -to po_h_sync_n
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81 set_location_assignment PIN_G8 -to po_v_sync_n
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84 set_location_assignment PIN_P22 -to pi_rst_n
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87 set_location_assignment PIN_AB12 -to pi_nt_v_mirror
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90 #set_location_assignment PIN_AA2 -to dbg_cpu_clk
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91 #set_location_assignment PIN_AA1 -to dbg_ppu_clk
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92 #set_location_assignment PIN_W2 -to dbg_mem_clk
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98 set_global_assignment -name VHDL_FILE mem/chr_rom.vhd
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99 set_global_assignment -name VHDL_FILE mem/ram.vhd
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100 set_global_assignment -name VHDL_FILE chip_selector.vhd
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101 set_global_assignment -name VHDL_FILE dummy-mos6502.vhd
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102 set_global_assignment -name VHDL_FILE ppu/render.vhd
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103 set_global_assignment -name VHDL_FILE ppu/ppu.vhd
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105 set_global_assignment -name VHDL_FILE de0_cv_nes.vhd
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108 ##timing definition...
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109 set_global_assignment -name SDC_FILE mos6502-timing.sdc
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110 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to base_clk
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112 ##for signal trap ii setting...
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113 #set_global_assignment -name ENABLE_SIGNALTAP ON
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114 #set_global_assignment -name USE_SIGNALTAP_FILE "de0-cv-analyze-all.stp"
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115 #set_global_assignment -name SIGNALTAP_FILE "de0-cv-analyze-all.stp"
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117 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top