2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
12 --logic analyzer reference clock
13 signal dbg_base_clk: out std_logic;
\r
16 pi_base_clk : in std_logic;
17 pi_rst_n : in std_logic;
18 pi_joypad1 : in std_logic_vector(7 downto 0);
19 pi_joypad2 : in std_logic_vector(7 downto 0);
20 po_h_sync_n : out std_logic;
21 po_v_sync_n : out std_logic;
22 po_r : out std_logic_vector(3 downto 0);
23 po_g : out std_logic_vector(3 downto 0);
24 po_b : out std_logic_vector(3 downto 0);
25 pi_nt_v_mirror : in std_logic
\r
29 architecture rtl of de0_cv_nes is
32 pi_rst_n : in std_logic;
\r
33 pi_base_clk : in std_logic;
\r
34 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
35 pi_rdy : in std_logic;
\r
36 pi_irq_n : in std_logic;
\r
37 pi_nmi_n : in std_logic;
\r
38 po_r_nw : out std_logic;
\r
39 po_addr : out std_logic_vector ( 15 downto 0);
\r
40 pio_d_io : inout std_logic_vector ( 7 downto 0)
\r
44 component clock_selector
\r
46 pi_rst_n : in std_logic;
\r
47 pi_base_clk : in std_logic;
\r
48 po_cpu_en : out std_logic_vector (7 downto 0);
\r
49 po_ppu_en : out std_logic_vector (3 downto 0)
\r
53 component chip_selector
\r
55 pi_rst_n : in std_logic;
\r
56 pi_base_clk : in std_logic;
\r
57 pi_addr : in std_logic_vector (15 downto 0);
\r
58 po_rom_ce_n : out std_logic;
\r
59 po_ram_ce_n : out std_logic;
\r
60 po_ppu_ce_n : out std_logic;
\r
61 po_apu_ce_n : out std_logic
\r
66 pi_rst_n : in std_logic;
\r
67 pi_base_clk : in std_logic;
68 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
69 pi_ce_n : in std_logic;
70 pi_r_nw : in std_logic;
71 pi_cpu_addr : in std_logic_vector (2 downto 0);
72 pio_cpu_d : inout std_logic_vector (7 downto 0);
74 po_v_rd_n : out std_logic;
\r
75 po_v_wr_n : out std_logic;
\r
76 po_v_addr : out std_logic_vector (13 downto 0);
\r
77 pio_v_data : inout std_logic_vector (7 downto 0);
\r
79 po_spr_ce_n : out std_logic;
\r
80 po_spr_rd_n : out std_logic;
\r
81 po_spr_wr_n : out std_logic;
\r
82 po_spr_addr : out std_logic_vector (7 downto 0);
\r
83 po_spr_data : out std_logic_vector (7 downto 0)
\r
88 generic (abus_size : integer := 16; dbus_size : integer := 8);
\r
90 pi_base_clk : in std_logic;
\r
91 pi_ce_n : in std_logic;
\r
92 pi_oe_n : in std_logic;
\r
93 pi_we_n : in std_logic;
\r
94 pi_addr : in std_logic_vector (abus_size - 1 downto 0);
\r
95 pio_d_io : inout std_logic_vector (dbus_size - 1 downto 0)
\r
99 component palette_ram
\r
101 pi_base_clk : in std_logic;
\r
102 pi_ce_n : in std_logic;
\r
103 pi_oe_n : in std_logic;
\r
104 pi_we_n : in std_logic;
\r
105 pi_addr : in std_logic_vector (4 downto 0);
\r
106 pio_d_io : inout std_logic_vector (7 downto 0)
\r
112 pi_base_clk : in std_logic;
\r
113 pi_ce_n : in std_logic;
\r
114 pi_addr : in std_logic_vector (12 downto 0);
\r
115 po_data : out std_logic_vector (7 downto 0)
\r
119 component v_chip_selector
\r
121 pi_rst_n : in std_logic;
\r
122 pi_base_clk : in std_logic;
\r
123 pi_v_addr : in std_logic_vector (13 downto 0);
\r
124 pi_nt_v_mirror : in std_logic;
\r
125 po_pt_ce_n : out std_logic;
\r
126 po_nt0_ce_n : out std_logic;
\r
127 po_nt1_ce_n : out std_logic;
\r
128 po_plt_ce_n : out std_logic
\r
132 constant ram_2k : integer := 11; --2k = 11 bit width.
\r
133 constant rom_32k : integer := 15; --32k = 15 bit width.
\r
134 constant vram_1k : integer := 10; --1k = 10 bit width.
\r
136 signal wr_cpu_en : std_logic_vector (7 downto 0);
\r
137 signal wr_ppu_en : std_logic_vector (3 downto 0);
\r
139 signal wr_rdy : std_logic;
\r
140 signal wr_irq_n : std_logic;
\r
141 signal wr_nmi_n : std_logic;
\r
142 signal wr_r_nw : std_logic;
\r
144 signal wr_addr : std_logic_vector ( 15 downto 0);
\r
145 signal wr_d_io : std_logic_vector ( 7 downto 0);
\r
147 signal wr_rom_ce_n : std_logic;
\r
148 signal wr_ram_ce_n : std_logic;
\r
149 signal wr_ppu_ce_n : std_logic;
\r
150 signal wr_apu_ce_n : std_logic;
\r
152 signal wr_v_rd_n : std_logic;
\r
153 signal wr_v_wr_n : std_logic;
\r
154 signal wr_v_addr : std_logic_vector (13 downto 0);
\r
155 signal wr_v_data : std_logic_vector (7 downto 0);
\r
157 signal wr_spr_ce_n : std_logic;
\r
158 signal wr_spr_rd_n : std_logic;
\r
159 signal wr_spr_wr_n : std_logic;
\r
160 signal wr_spr_addr : std_logic_vector (7 downto 0);
\r
161 signal wr_spr_data : std_logic_vector (7 downto 0);
\r
163 signal wr_pt_ce_n : std_logic;
\r
164 signal wr_nt0_ce_n : std_logic;
\r
165 signal wr_nt1_ce_n : std_logic;
\r
166 signal wr_plt_ce_n : std_logic;
\r
171 dbg_base_clk <= pi_base_clk;
\r
173 --synchronized clock generator instance
\r
174 clock_selector_inst : clock_selector port map (
\r
181 --mos 6502 cpu instance
\r
182 cpu_inst : mos6502 port map (
\r
194 --chip select (address decode)
\r
195 cs_inst : chip_selector port map (
\r
206 ppu_inst : ppu port map (
\r
212 wr_addr(2 downto 0),
\r
227 --vram chip select (address decode)
\r
228 vcs_inst : v_chip_selector port map (
\r
239 --name table/attr table #0
\r
240 vram_nt0_inst : ram generic map
\r
241 (vram_1k, 8) port map (
\r
246 wr_v_addr(vram_1k - 1 downto 0),
\r
250 --name table/attr table #1
\r
251 vram_nt1_inst : ram generic map
\r
252 (vram_1k, 8) port map (
\r
257 wr_v_addr(vram_1k - 1 downto 0),
\r
262 vram_plt_inst : palette_ram port map (
\r
267 wr_v_addr(4 downto 0),
\r
272 chr_rom_inst : chr_rom port map (
\r
275 wr_v_addr(12 downto 0),
\r
280 spr_ram_inst : ram generic map
\r
294 po_h_sync_n <= '0';
\r
295 po_v_sync_n <= '0';
\r
296 po_r <= (others => '0');
\r
297 po_g <= (others => '0');
\r
298 po_b <= (others => '0');
\r
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