2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
12 --logic analyzer reference clock
13 signal dbg_base_clk: out std_logic;
\r
16 pi_base_clk : in std_logic;
17 pi_rst_n : in std_logic;
18 pi_joypad1 : in std_logic_vector(7 downto 0);
19 pi_joypad2 : in std_logic_vector(7 downto 0);
20 po_h_sync_n : out std_logic;
21 po_v_sync_n : out std_logic;
22 po_r : out std_logic_vector(3 downto 0);
23 po_g : out std_logic_vector(3 downto 0);
24 po_b : out std_logic_vector(3 downto 0);
25 pi_nt_v_mirror : in std_logic
\r
29 architecture rtl of de0_cv_nes is
32 pi_rst_n : in std_logic;
\r
33 pi_base_clk : in std_logic;
\r
34 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
35 pi_rdy : in std_logic;
\r
36 pi_irq_n : in std_logic;
\r
37 pi_nmi_n : in std_logic;
\r
38 po_r_nw : out std_logic;
\r
39 po_addr : out std_logic_vector ( 15 downto 0);
\r
40 pio_d_io : inout std_logic_vector ( 7 downto 0)
\r
44 component clock_selector
\r
46 pi_rst_n : in std_logic;
\r
47 pi_base_clk : in std_logic;
\r
48 po_cpu_en : out std_logic_vector (7 downto 0);
\r
49 po_rnd_en : out std_logic_vector (3 downto 0)
\r
53 component chip_selector
\r
55 pi_rst_n : in std_logic;
\r
56 pi_base_clk : in std_logic;
\r
57 pi_addr : in std_logic_vector (15 downto 0);
\r
58 po_rom_ce_n : out std_logic;
\r
59 po_ram_ce_n : out std_logic;
\r
60 po_ppu_ce_n : out std_logic;
\r
61 po_apu_ce_n : out std_logic
\r
66 pi_rst_n : in std_logic;
\r
67 pi_base_clk : in std_logic;
68 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
69 pi_ce_n : in std_logic;
70 pi_r_nw : in std_logic;
71 pi_cpu_addr : in std_logic_vector (2 downto 0);
72 pio_cpu_d : inout std_logic_vector (7 downto 0);
74 po_v_rd_n : out std_logic;
\r
75 po_v_wr_n : out std_logic;
\r
76 po_v_addr : out std_logic_vector (13 downto 0);
\r
77 pio_v_data : inout std_logic_vector (7 downto 0);
\r
79 po_spr_ce_n : out std_logic;
\r
80 po_spr_rd_n : out std_logic;
\r
81 po_spr_wr_n : out std_logic;
\r
82 po_spr_addr : out std_logic_vector (7 downto 0);
\r
83 po_spr_data : out std_logic_vector (7 downto 0);
\r
85 po_ppu_ctrl : out std_logic_vector (7 downto 0);
\r
86 po_ppu_mask : out std_logic_vector (7 downto 0);
\r
87 pi_ppu_status : in std_logic_vector (7 downto 0);
\r
88 po_ppu_scroll_x : out std_logic_vector (7 downto 0);
\r
89 po_ppu_scroll_y : out std_logic_vector (7 downto 0)
\r
94 generic (abus_size : integer := 16; dbus_size : integer := 8);
\r
96 pi_base_clk : in std_logic;
\r
97 pi_ce_n : in std_logic;
\r
98 pi_oe_n : in std_logic;
\r
99 pi_we_n : in std_logic;
\r
100 pi_addr : in std_logic_vector (abus_size - 1 downto 0);
\r
101 pio_d_io : inout std_logic_vector (dbus_size - 1 downto 0)
\r
105 component palette_ram
\r
107 pi_base_clk : in std_logic;
\r
108 pi_ce_n : in std_logic;
\r
109 pi_oe_n : in std_logic;
\r
110 pi_we_n : in std_logic;
\r
111 pi_addr : in std_logic_vector (4 downto 0);
\r
112 pio_d_io : inout std_logic_vector (7 downto 0)
\r
118 pi_base_clk : in std_logic;
\r
119 pi_ce_n : in std_logic;
\r
120 pi_addr : in std_logic_vector (12 downto 0);
\r
121 po_data : out std_logic_vector (7 downto 0)
\r
125 component v_chip_selector
\r
127 pi_rst_n : in std_logic;
\r
128 pi_base_clk : in std_logic;
\r
129 pi_v_addr : in std_logic_vector (13 downto 0);
\r
130 pi_nt_v_mirror : in std_logic;
\r
131 po_pt_ce_n : out std_logic;
\r
132 po_nt0_ce_n : out std_logic;
\r
133 po_nt1_ce_n : out std_logic;
\r
134 po_plt_ce_n : out std_logic
\r
140 pi_rst_n : in std_logic;
\r
141 pi_base_clk : in std_logic;
\r
142 pi_rnd_en : in std_logic_vector (3 downto 0);
\r
145 pi_ppu_ctrl : in std_logic_vector (7 downto 0);
\r
146 pi_ppu_mask : in std_logic_vector (7 downto 0);
\r
147 po_ppu_status : out std_logic_vector (7 downto 0);
\r
148 pi_ppu_scroll_x : in std_logic_vector (7 downto 0);
\r
149 pi_ppu_scroll_y : in std_logic_vector (7 downto 0);
\r
152 po_rd_n : out std_logic;
\r
153 po_wr_n : out std_logic;
\r
154 po_v_addr : out std_logic_vector (13 downto 0);
\r
155 io_v_data : in std_logic_vector (7 downto 0);
\r
158 po_spr_ce_n : out std_logic;
\r
159 po_spr_rd_n : out std_logic;
\r
160 po_spr_wr_n : out std_logic;
\r
161 po_spr_addr : out std_logic_vector (7 downto 0);
\r
162 pi_spr_data : in std_logic_vector (7 downto 0);
\r
165 po_h_sync_n : out std_logic;
\r
166 po_v_sync_n : out std_logic;
\r
167 po_r : out std_logic_vector(3 downto 0);
\r
168 po_g : out std_logic_vector(3 downto 0);
\r
169 po_b : out std_logic_vector(3 downto 0)
\r
173 constant ram_2k : integer := 11; --2k = 11 bit width.
\r
174 constant rom_32k : integer := 15; --32k = 15 bit width.
\r
175 constant vram_1k : integer := 10; --1k = 10 bit width.
\r
177 signal wr_cpu_en : std_logic_vector (7 downto 0);
\r
178 signal wr_rnd_en : std_logic_vector (3 downto 0);
\r
180 signal wr_rdy : std_logic;
\r
181 signal wr_irq_n : std_logic;
\r
182 signal wr_nmi_n : std_logic;
\r
183 signal wr_r_nw : std_logic;
\r
185 signal wr_addr : std_logic_vector ( 15 downto 0);
\r
186 signal wr_d_io : std_logic_vector ( 7 downto 0);
\r
188 signal wr_rom_ce_n : std_logic;
\r
189 signal wr_ram_ce_n : std_logic;
\r
190 signal wr_ppu_ce_n : std_logic;
\r
191 signal wr_apu_ce_n : std_logic;
\r
193 signal wr_v_rd_n : std_logic;
\r
194 signal wr_v_wr_n : std_logic;
\r
195 signal wr_v_addr : std_logic_vector (13 downto 0);
\r
196 signal wr_v_data : std_logic_vector (7 downto 0);
\r
198 signal wr_spr_ce_n : std_logic;
\r
199 signal wr_spr_rd_n : std_logic;
\r
200 signal wr_spr_wr_n : std_logic;
\r
201 signal wr_spr_addr : std_logic_vector (7 downto 0);
\r
202 signal wr_spr_data : std_logic_vector (7 downto 0);
\r
204 signal wr_pt_ce_n : std_logic;
\r
205 signal wr_nt0_ce_n : std_logic;
\r
206 signal wr_nt1_ce_n : std_logic;
\r
207 signal wr_plt_ce_n : std_logic;
\r
209 signal wr_ppu_ctrl : std_logic_vector (7 downto 0);
\r
210 signal wr_ppu_mask : std_logic_vector (7 downto 0);
\r
211 signal wr_ppu_status : std_logic_vector (7 downto 0);
\r
212 signal wr_ppu_scroll_x : std_logic_vector (7 downto 0);
\r
213 signal wr_ppu_scroll_y : std_logic_vector (7 downto 0);
\r
217 dbg_base_clk <= pi_base_clk;
\r
219 --synchronized clock generator instance
\r
220 clock_selector_inst : clock_selector port map (
\r
227 --mos 6502 cpu instance
\r
228 cpu_inst : mos6502 port map (
\r
240 --chip select (address decode)
\r
241 cs_inst : chip_selector port map (
\r
252 ppu_inst : ppu port map (
\r
258 wr_addr(2 downto 0),
\r
280 --vram chip select (address decode)
\r
281 vcs_inst : v_chip_selector port map (
\r
292 --name table/attr table #0
\r
293 vram_nt0_inst : ram generic map
\r
294 (vram_1k, 8) port map (
\r
299 wr_v_addr(vram_1k - 1 downto 0),
\r
303 --name table/attr table #1
\r
304 vram_nt1_inst : ram generic map
\r
305 (vram_1k, 8) port map (
\r
310 wr_v_addr(vram_1k - 1 downto 0),
\r
315 vram_plt_inst : palette_ram port map (
\r
320 wr_v_addr(4 downto 0),
\r
325 chr_rom_inst : chr_rom port map (
\r
328 wr_v_addr(12 downto 0),
\r
333 spr_ram_inst : ram generic map
\r
343 --vga render instance
\r
344 render_inst : render port map (
\r
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