2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
12 --logic analyzer reference clock
13 signal dbg_base_clk: out std_logic;
\r
16 pi_base_clk : in std_logic;
17 pi_rst_n : in std_logic;
18 pi_joypad1 : in std_logic_vector(7 downto 0);
19 pi_joypad2 : in std_logic_vector(7 downto 0);
20 po_h_sync_n : out std_logic;
21 po_v_sync_n : out std_logic;
22 po_r : out std_logic_vector(3 downto 0);
23 po_g : out std_logic_vector(3 downto 0);
24 po_b : out std_logic_vector(3 downto 0);
25 pi_nt_v_mirror : in std_logic
\r
29 architecture rtl of de0_cv_nes is
32 pi_base_clk : in std_logic;
\r
33 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
34 pi_rdy : in std_logic;
\r
35 pi_rst_n : in std_logic;
\r
36 pi_irq_n : in std_logic;
\r
37 pi_nmi_n : in std_logic;
\r
38 po_r_nw : out std_logic;
\r
39 po_addr : out std_logic_vector ( 15 downto 0);
\r
40 pio_d_io : inout std_logic_vector ( 7 downto 0)
\r
44 component clock_selector
\r
46 pi_rst_n : in std_logic;
\r
47 pi_base_clk : in std_logic;
\r
48 po_cpu_en : out std_logic_vector (7 downto 0);
\r
49 po_ppu_en : out std_logic_vector (3 downto 0)
\r
54 pi_base_clk : in std_logic;
55 pi_ce_n : in std_logic;
56 pi_rst_n : in std_logic;
57 pi_r_nw : in std_logic;
58 pi_cpu_addr : in std_logic_vector (2 downto 0);
59 pio_cpu_d : inout std_logic_vector (7 downto 0);
61 po_rd_n : out std_logic;
62 po_wr_n : out std_logic;
63 po_ale_n : out std_logic;
64 po_vram_addr : out std_logic_vector (13 downto 0);
65 pio_vram_data : inout std_logic_vector (7 downto 0)
69 component chip_selector
71 pi_rst_n : in std_logic;
\r
72 pi_base_clk : in std_logic;
\r
73 pi_addr : in std_logic_vector (15 downto 0);
74 po_rom_ce_n : out std_logic;
\r
75 po_ram_ce_n : out std_logic;
\r
76 po_ppu_ce_n : out std_logic;
\r
77 po_apu_ce_n : out std_logic
\r
81 component v_chip_selector
\r
83 pi_rst_n : in std_logic;
\r
84 pi_base_clk : in std_logic;
\r
85 pi_v_addr : in std_logic_vector (13 downto 0);
\r
86 pi_nt_v_mirror : in std_logic;
\r
87 po_pt_ce_n : out std_logic;
\r
88 po_nt0_ce_n : out std_logic;
\r
89 po_nt1_ce_n : out std_logic
\r
93 signal wr_cpu_en : std_logic_vector (7 downto 0);
\r
94 signal wr_ppu_en : std_logic_vector (3 downto 0);
\r
96 signal wr_rdy : std_logic;
\r
97 signal wr_irq_n : std_logic;
\r
98 signal wr_nmi_n : std_logic;
\r
99 signal wr_r_nw : std_logic;
\r
101 signal wr_addr : std_logic_vector ( 15 downto 0);
\r
102 signal wr_d_io : std_logic_vector ( 7 downto 0);
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104 signal wr_rom_ce_n : std_logic;
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105 signal wr_ram_ce_n : std_logic;
\r
106 signal wr_ppu_ce_n : std_logic;
\r
107 signal wr_apu_ce_n : std_logic;
\r
109 --signal wr_pt_ce_n : std_logic;
\r
110 --signal wr_nt0_ce_n : std_logic;
\r
111 --signal wr_nt1_ce_n : std_logic;
\r
115 dbg_base_clk <= pi_base_clk;
\r
117 --synchronized clock generator instance
\r
118 clock_selector_inst : clock_selector port map
\r
119 (pi_rst_n, pi_base_clk, wr_cpu_en, wr_ppu_en);
\r
121 --mos 6502 cpu instance
\r
122 cpu_inst : mos6502 port map (
\r
134 --chip select (address decode)
\r
135 cs_inst : chip_selector port map (
\r
149 po_h_sync_n <= '0';
\r
150 po_v_sync_n <= '0';
\r
151 po_r <= (others => '0');
\r
152 po_g <= (others => '0');
\r
153 po_b <= (others => '0');
\r