de0_cv_nes/mos6502.vhd

   1 library ieee;\r
   2 use ieee.std_logic_1164.all;\r
   3 use ieee.std_logic_unsigned.all;\r
   4 use ieee.std_logic_arith.conv_std_logic_vector;\r
   5 \r
   6 entity mos6502 is \r
   7     port (  \r
   8             pi_rst_n       : in std_logic;\r
   9             pi_base_clk         : in std_logic;\r
  10             pi_cpu_en       : in std_logic_vector (7 downto 0);\r
  11             pi_rdy         : in std_logic;\r
  12             pi_irq_n       : in std_logic;\r
  13             pi_nmi_n       : in std_logic;\r
  14             po_r_nw        : out std_logic;\r
  15             po_addr        : out std_logic_vector ( 15 downto 0);\r
  16             pio_d_io       : inout std_logic_vector ( 7 downto 0)\r
  17     );\r
  18 end mos6502;\r
  19 \r
  20 architecture rtl of mos6502 is\r
  21 \r
  22 ---cpu main state:\r
  23 type cpu_main_state is (\r
  24     --common state. idle and inst fetch.\r
  25     ST_IDLE,\r
  26     ST_CM_T0,\r
  27 \r
  28     --single byte inst execute.\r
  29     ST_A1_T1,\r
  30 \r
  31     --mem data operation\r
  32     --imm\r
  33     ST_A21_T1,\r
  34     --zp\r
  35     ST_A22_T1, ST_A22_T2,\r
  36     --abs\r
  37     ST_A23_T1, ST_A23_T2, ST_A23_T3,\r
  38     --indir, x\r
  39     ST_A24_T1, ST_A24_T2, ST_A24_T3, ST_A24_T4, ST_A24_T5,\r
  40     --abs xy\r
  41     ST_A25_T1, ST_A25_T2, ST_A25_T3, ST_A25_T4,\r
  42     --zp xy\r
  43     ST_A26_T1, ST_A26_T2, ST_A26_T3,\r
  44     --indir, y\r
  45     ST_A27_T1, ST_A27_T2, ST_A27_T3, ST_A27_T4, ST_A27_T5,\r
  46 \r
  47     --store op.\r
  48     --zp\r
  49     ST_A31_T1, ST_A31_T2,\r
  50     --abs\r
  51     ST_A32_T1, ST_A32_T2, ST_A32_T3,\r
  52     --indir, x\r
  53     ST_A33_T1, ST_A33_T2, ST_A33_T3, ST_A33_T4, ST_A33_T5,\r
  54     --abs xy\r
  55     ST_A34_T1, ST_A34_T2, ST_A34_T3, ST_A34_T4,\r
  56     --zp xy\r
  57     ST_A35_T1, ST_A35_T2, ST_A35_T3,\r
  58     --indir, y\r
  59     ST_A36_T1, ST_A36_T2, ST_A36_T3, ST_A36_T4, ST_A36_T5,\r
  60 \r
  61     --memory to memory op.\r
  62     --zp\r
  63     ST_A41_T1, ST_A41_T2, ST_A41_T3, ST_A41_T4,\r
  64     --abs\r
  65     ST_A42_T1, ST_A42_T2, ST_A42_T3, ST_A42_T4, ST_A42_T5,\r
  66     --zp x\r
  67     ST_A43_T1, ST_A43_T2, ST_A43_T3, ST_A43_T4, ST_A43_T5,\r
  68     --abs x\r
  69     ST_A44_T1, ST_A44_T2, ST_A44_T3, ST_A44_T4, ST_A44_T5, ST_A44_T6, \r
  70 \r
  71     --misc operation.\r
  72     --push\r
  73     ST_A51_T1, ST_A51_T2,\r
  74     --pull\r
  75     ST_A52_T1, ST_A52_T2, ST_A52_T3,\r
  76     --jsr\r
  77     ST_A53_T1, ST_A53_T2, ST_A53_T3,ST_A53_T4, ST_A53_T5,\r
  78     --rti\r
  79     ST_A55_T1, ST_A55_T2, ST_A55_T3, ST_A55_T4, ST_A55_T5,\r
  80     --jmp abs\r
  81     ST_A561_T1, ST_A561_T2,\r
  82     --jmp indir\r
  83     ST_A562_T1, ST_A562_T2, ST_A562_T3, ST_A562_T4,\r
  84     --rts\r
  85     ST_A57_T1, ST_A57_T2, ST_A57_T3, ST_A57_T4, ST_A57_T5,\r
  86     --branch\r
  87     ST_A58_T1, ST_A58_T2, ST_A58_T3,\r
  88 \r
  89     --reset vector.\r
  90     ST_RS_T0, ST_RS_T1, ST_RS_T2, ST_RS_T3, ST_RS_T4, ST_RS_T5, ST_RS_T6, ST_RS_T7,\r
  91 \r
  92     --invalid state\r
  93     ST_INV\r
  94     );\r
  95 \r
  96 --cpu sub state.\r
  97 --1 cpu clock is split into 8 state.\r
  98 --1 cpu clock = 32 x base clock.\r
  99 type cpu_sub_state is (\r
 100     ST_SUB00, ST_SUB01, ST_SUB02, ST_SUB03,\r
 101     ST_SUB10, ST_SUB11, ST_SUB12, ST_SUB13,\r
 102     ST_SUB20, ST_SUB21, ST_SUB22, ST_SUB23,\r
 103     ST_SUB30, ST_SUB31, ST_SUB32, ST_SUB33,\r
 104     ST_SUB40, ST_SUB41, ST_SUB42, ST_SUB43,\r
 105     ST_SUB50, ST_SUB51, ST_SUB52, ST_SUB53,\r
 106     ST_SUB60, ST_SUB61, ST_SUB62, ST_SUB63,\r
 107     ST_SUB70, ST_SUB71, ST_SUB72, ST_SUB73\r
 108     );\r
 109 \r
 110 type cpu_state_array    is array (0 to 255) of cpu_main_state;\r
 111 constant inst_decode_rom : cpu_state_array := (\r
 112   --00          01          02          03          04          05          06          07\r
 113     ST_INV,     ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 114   --08          09          0a          0b          0c          0d          0e          0f\r
 115     ST_A51_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_INV,     ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 116   --10          11          12          13          14          15          16          17\r
 117     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 118   --18          19          1a          1b          1c          1d          1e          1f\r
 119     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 120   --20          21          22          23          24          25          26          27\r
 121     ST_A53_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 122   --28          29          2a          2b          2c          2d          2e          2f\r
 123     ST_A52_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 124   --30          31          32          33          34          35          36          37\r
 125     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 126   --38          39          3a          3b          3c          3d          3e          3f\r
 127     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 128   --40          41          42          43          44          45          46          47\r
 129     ST_A55_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 130   --48          49          4a          4b          4c          4d          4e          4f\r
 131     ST_A51_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A561_T1, ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 132   --50          51          52          53          54          55          56          57\r
 133     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_A43_T1,  ST_INV,\r
 134   --58          59          5a          5b          5c          5d          5e          5f\r
 135     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 136   --60          61          62          63          64          65          66          67\r
 137     ST_A57_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 138   --68          69          6a          6b          6c          6d          6e          6f\r
 139     ST_A52_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A562_T1, ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 140   --70          71          72          73          74          75          76          77\r
 141     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_A43_T1,  ST_INV,\r
 142   --78          79          7a          7b          7c          7d          7e          7f\r
 143     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 144   --80          81          82          83          84          85          86          87\r
 145     ST_INV,     ST_A33_T1,  ST_INV,     ST_INV,     ST_A31_T1,  ST_A31_T1,  ST_A31_T1,  ST_INV,\r
 146   --88          89          8a          8b          8c          8d          8e          8f\r
 147     ST_A1_T1,   ST_INV,     ST_A1_T1,   ST_INV,     ST_A32_T1,  ST_A32_T1,  ST_A32_T1,  ST_INV,\r
 148   --90          91          92          93          94          95          96          97\r
 149     ST_A58_T1,  ST_A36_T1,  ST_INV,     ST_INV,     ST_A35_T1,  ST_A35_T1,  ST_A35_T1,  ST_INV,\r
 150   --98          99          9a          9b          9c          9d          9e          9f\r
 151     ST_A1_T1,   ST_A34_T1,  ST_A1_T1,   ST_INV,     ST_INV,     ST_A34_T1,  ST_INV,     ST_INV,\r
 152   --a0          a1          a2          a3          a4          a5          a6          a7\r
 153     ST_A21_T1,  ST_A24_T1,  ST_A21_T1,  ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A22_T1,  ST_INV,\r
 154   --a8          a9          aa          ab          ac          ad          ae          af\r
 155     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A23_T1,  ST_INV,\r
 156   --b0          b1          b2          b3          b4          b5          b6          b7\r
 157     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A26_T1,  ST_INV,     ST_INV,\r
 158   --b8          b9          ba          bb          bc          bd          be          bf\r
 159     ST_A1_T1,   ST_A25_T1,  ST_A1_T1,   ST_INV,     ST_A25_T1,  ST_A25_T1,  ST_A25_T1,  ST_INV,\r
 160   --c0          c1          c2          c3          c4          c5          c6          c7\r
 161     ST_A21_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 162   --c8          c9          ca          cb          cc          cd          ce          cf\r
 163     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 164   --d0          d1          d2          d3          d4          d5          d6          d7\r
 165     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_A43_T1,  ST_INV,\r
 166   --d8          d9          da          db          dc          dd          de          df\r
 167     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
 168   --e0          e1          e2          e3          e4          e5          e6          e7\r
 169     ST_A21_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A41_T1,  ST_INV,\r
 170   --e8          e9          ea          eb          ec          ed          ee          ef\r
 171     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A42_T1,  ST_INV,\r
 172   --f0          f1          f2          f3          f4          f5          f6          f7\r
 173     ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A26_T1,  ST_A43_T1,  ST_INV,\r
 174   --f8          f9          fa          fb          fc          fd          fe          ff\r
 175     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV\r
 176 );\r
 177 \r
 178 --        Flags (bit 7 to bit 0):\r
 179 --        N   ....    Negative\r
 180 --        V   ....    Overflow\r
 181 --        -   ....    ignored   -- always 1 for NES 6502\r
 182 --        B   ....    Break\r
 183 --        D   ....    Decimal (use BCD for arithmetics)     -- not supported. always 0.\r
 184 --        I   ....    Interrupt (IRQ disable)\r
 185 --        Z   ....    Zero\r
 186 --        C   ....    Carry\r
 187 constant FL_N   : integer := 7;\r
 188 constant FL_V   : integer := 6;\r
 189 constant FL_I   : integer := 2;\r
 190 constant FL_Z   : integer := 1;\r
 191 constant FL_C   : integer := 0;\r
 192 \r
 193 signal reg_main_state           : cpu_main_state;\r
 194 signal reg_main_next_state      : cpu_main_state;\r
 195 signal reg_sub_state            : cpu_sub_state;\r
 196 signal reg_sub_next_state       : cpu_sub_state;\r
 197 \r
 198 --6502 register definition...\r
 199 signal reg_inst     : std_logic_vector (7 downto 0);\r
 200 signal reg_acc      : std_logic_vector (7 downto 0);\r
 201 signal reg_x        : std_logic_vector (7 downto 0);\r
 202 signal reg_y        : std_logic_vector (7 downto 0);\r
 203 signal reg_idl_l    : std_logic_vector (7 downto 0);\r
 204 signal reg_idl_h    : std_logic_vector (7 downto 0);\r
 205 signal reg_sp       : std_logic_vector (7 downto 0);\r
 206 signal reg_status   : std_logic_vector (7 downto 0);\r
 207 signal reg_pc_l     : std_logic_vector (7 downto 0);\r
 208 signal reg_pc_h     : std_logic_vector (7 downto 0);\r
 209 \r
 210 --tmp flag reg.\r
 211 signal reg_tmp_carry    : std_logic;\r
 212 signal reg_tmp_ovf      : std_logic;\r
 213 signal reg_tmp_condition    : std_logic;\r
 214 signal reg_tmp_pg_crossed   : std_logic;\r
 215 \r
 216 --tmp address reg.\r
 217 signal reg_tmp_l    : std_logic_vector (7 downto 0);\r
 218 signal reg_tmp_h    : std_logic_vector (7 downto 0);\r
 219 \r
 220 --tmp data reg.\r
 221 signal reg_tmp_data : std_logic_vector (7 downto 0);\r
 222 \r
 223 --bus i/o reg.\r
 224 signal reg_r_nw     : std_logic;\r
 225 signal reg_addr     : std_logic_vector (15 downto 0);\r
 226 signal reg_d_in     : std_logic_vector (7 downto 0);\r
 227 signal reg_d_out    : std_logic_vector (7 downto 0);\r
 228 \r
 229 \r
 230 begin\r
 231     --state transition process...\r
 232     set_stat_p : process (pi_rst_n, pi_base_clk)\r
 233     begin\r
 234         if (pi_rst_n = '0') then\r
 235             reg_main_state <= ST_IDLE;\r
 236             reg_sub_state <= ST_SUB00;\r
 237         elsif (rising_edge(pi_base_clk)) then\r
 238             reg_main_state <= reg_main_next_state;\r
 239             reg_sub_state <= reg_sub_next_state;\r
 240         end if;--if (pi_rst_n = '0') then\r
 241     end process;\r
 242 \r
 243     --fixed length sub status change (0 - 31 because cpu clock is 1/32 of base clock).\r
 244     tx_next_sub_stat_p : process (reg_sub_state, pi_cpu_en)\r
 245     begin\r
 246         case reg_sub_state is\r
 247             when ST_SUB00 =>\r
 248                 if (pi_cpu_en(0) = '1') then\r
 249                     reg_sub_next_state <= ST_SUB01;\r
 250                 else\r
 251                     reg_sub_next_state <= reg_sub_state;\r
 252                 end if;\r
 253             when ST_SUB01 =>\r
 254                 reg_sub_next_state <= ST_SUB02;\r
 255             when ST_SUB02 =>\r
 256                 reg_sub_next_state <= ST_SUB03;\r
 257             when ST_SUB03 =>\r
 258                 reg_sub_next_state <= ST_SUB10;\r
 259             when ST_SUB10 =>\r
 260                 reg_sub_next_state <= ST_SUB11;\r
 261             when ST_SUB11 =>\r
 262                 reg_sub_next_state <= ST_SUB12;\r
 263             when ST_SUB12 =>\r
 264                 reg_sub_next_state <= ST_SUB13;\r
 265             when ST_SUB13 =>\r
 266                 reg_sub_next_state <= ST_SUB20;\r
 267             when ST_SUB20 =>\r
 268                 reg_sub_next_state <= ST_SUB21;\r
 269             when ST_SUB21 =>\r
 270                 reg_sub_next_state <= ST_SUB22;\r
 271             when ST_SUB22 =>\r
 272                 reg_sub_next_state <= ST_SUB23;\r
 273             when ST_SUB23 =>\r
 274                 reg_sub_next_state <= ST_SUB30;\r
 275             when ST_SUB30 =>\r
 276                 reg_sub_next_state <= ST_SUB31;\r
 277             when ST_SUB31 =>\r
 278                 reg_sub_next_state <= ST_SUB32;\r
 279             when ST_SUB32 =>\r
 280                 reg_sub_next_state <= ST_SUB33;\r
 281             when ST_SUB33 =>\r
 282                 reg_sub_next_state <= ST_SUB40;\r
 283             when ST_SUB40 =>\r
 284                 reg_sub_next_state <= ST_SUB41;\r
 285             when ST_SUB41 =>\r
 286                 reg_sub_next_state <= ST_SUB42;\r
 287             when ST_SUB42 =>\r
 288                 reg_sub_next_state <= ST_SUB43;\r
 289             when ST_SUB43 =>\r
 290                 reg_sub_next_state <= ST_SUB50;\r
 291             when ST_SUB50 =>\r
 292                 reg_sub_next_state <= ST_SUB51;\r
 293             when ST_SUB51 =>\r
 294                 reg_sub_next_state <= ST_SUB52;\r
 295             when ST_SUB52 =>\r
 296                 reg_sub_next_state <= ST_SUB53;\r
 297             when ST_SUB53 =>\r
 298                 reg_sub_next_state <= ST_SUB60;\r
 299             when ST_SUB60 =>\r
 300                 reg_sub_next_state <= ST_SUB61;\r
 301             when ST_SUB61 =>\r
 302                 reg_sub_next_state <= ST_SUB62;\r
 303             when ST_SUB62 =>\r
 304                 reg_sub_next_state <= ST_SUB63;\r
 305             when ST_SUB63 =>\r
 306                 reg_sub_next_state <= ST_SUB70;\r
 307             when ST_SUB70 =>\r
 308                 reg_sub_next_state <= ST_SUB71;\r
 309             when ST_SUB71 =>\r
 310                 reg_sub_next_state <= ST_SUB72;\r
 311             when ST_SUB72 =>\r
 312                 reg_sub_next_state <= ST_SUB73;\r
 313             when ST_SUB73 =>\r
 314                 reg_sub_next_state <= ST_SUB00;\r
 315         end case;\r
 316     end process;\r
 317 \r
 318     --state change to next.\r
 319     tx_next_main_stat_p : process (pi_rst_n, reg_main_state, reg_sub_state,\r
 320                                    reg_inst, reg_tmp_condition, reg_tmp_pg_crossed)\r
 321 \r
 322     begin\r
 323         case reg_main_state is\r
 324             -----idle...\r
 325             when ST_IDLE =>\r
 326                 if (pi_rst_n = '0') then\r
 327                     reg_main_next_state <= reg_main_state;\r
 328                 else\r
 329                     reg_main_next_state <= ST_RS_T0;\r
 330                 end if;\r
 331             -----reset...\r
 332             when ST_RS_T0 =>\r
 333                 if (reg_sub_state = ST_SUB73) then\r
 334                     reg_main_next_state <= ST_RS_T1;\r
 335                 else\r
 336                     reg_main_next_state <= reg_main_state;\r
 337                 end if;\r
 338             when ST_RS_T1 =>\r
 339                 if (reg_sub_state = ST_SUB73) then\r
 340                     reg_main_next_state <= ST_RS_T2;\r
 341                 else\r
 342                     reg_main_next_state <= reg_main_state;\r
 343                 end if;\r
 344             when ST_RS_T2 =>\r
 345                 if (reg_sub_state = ST_SUB73) then\r
 346                     reg_main_next_state <= ST_RS_T3;\r
 347                 else\r
 348                     reg_main_next_state <= reg_main_state;\r
 349                 end if;\r
 350             when ST_RS_T3 =>\r
 351                 if (reg_sub_state = ST_SUB73) then\r
 352                     reg_main_next_state <= ST_RS_T4;\r
 353                 else\r
 354                     reg_main_next_state <= reg_main_state;\r
 355                 end if;\r
 356             when ST_RS_T4 =>\r
 357                 if (reg_sub_state = ST_SUB73) then\r
 358                     reg_main_next_state <= ST_RS_T5;\r
 359                 else\r
 360                     reg_main_next_state <= reg_main_state;\r
 361                 end if;\r
 362             when ST_RS_T5 =>\r
 363                 if (reg_sub_state = ST_SUB73) then\r
 364                     reg_main_next_state <= ST_RS_T6;\r
 365                 else\r
 366                     reg_main_next_state <= reg_main_state;\r
 367                 end if;\r
 368             when ST_RS_T6 =>\r
 369                 if (reg_sub_state = ST_SUB73) then\r
 370                     reg_main_next_state <= ST_RS_T7;\r
 371                 else\r
 372                     reg_main_next_state <= reg_main_state;\r
 373                 end if;\r
 374             when ST_RS_T7 =>\r
 375                 if (reg_sub_state = ST_SUB73) then\r
 376                     reg_main_next_state <= ST_CM_T0;\r
 377                 else\r
 378                     reg_main_next_state <= reg_main_state;\r
 379                 end if;\r
 380 \r
 381             --instruction fetch\r
 382             when ST_CM_T0 =>\r
 383                 if (reg_sub_state = ST_SUB73) then\r
 384                     ---instruction decode next state.\r
 385                     reg_main_next_state <= inst_decode_rom(conv_integer(reg_inst));\r
 386                 else\r
 387                     reg_main_next_state <= reg_main_state;\r
 388                 end if;\r
 389 \r
 390             --A1 inst.(single byte)\r
 391             when ST_A1_T1 =>\r
 392                 if (reg_sub_state = ST_SUB73) then\r
 393                     reg_main_next_state <= ST_CM_T0;\r
 394                 else\r
 395                     reg_main_next_state <= reg_main_state;\r
 396                 end if;\r
 397 \r
 398             --A2 inst.\r
 399             when ST_A21_T1 =>\r
 400                 if (reg_sub_state = ST_SUB73) then\r
 401                     reg_main_next_state <= ST_CM_T0;\r
 402                 else\r
 403                     reg_main_next_state <= reg_main_state;\r
 404                 end if;\r
 405             when ST_A22_T1 =>\r
 406                 if (reg_sub_state = ST_SUB73) then\r
 407                     reg_main_next_state <= ST_A22_T2;\r
 408                 else\r
 409                     reg_main_next_state <= reg_main_state;\r
 410                 end if;\r
 411             when ST_A22_T2 =>\r
 412                 if (reg_sub_state = ST_SUB73) then\r
 413                     reg_main_next_state <= ST_CM_T0;\r
 414                 else\r
 415                     reg_main_next_state <= reg_main_state;\r
 416                 end if;\r
 417             when ST_A23_T1 =>\r
 418                 if (reg_sub_state = ST_SUB73) then\r
 419                     reg_main_next_state <= ST_A23_T2;\r
 420                 else\r
 421                     reg_main_next_state <= reg_main_state;\r
 422                 end if;\r
 423             when ST_A23_T2 =>\r
 424                 if (reg_sub_state = ST_SUB73) then\r
 425                     reg_main_next_state <= ST_A23_T3;\r
 426                 else\r
 427                     reg_main_next_state <= reg_main_state;\r
 428                 end if;\r
 429             when ST_A23_T3 =>\r
 430                 if (reg_sub_state = ST_SUB73) then\r
 431                     reg_main_next_state <= ST_CM_T0;\r
 432                 else\r
 433                     reg_main_next_state <= reg_main_state;\r
 434                 end if;\r
 435             when ST_A24_T1 =>\r
 436                 if (reg_sub_state = ST_SUB73) then\r
 437                     reg_main_next_state <= ST_A24_T2;\r
 438                 else\r
 439                     reg_main_next_state <= reg_main_state;\r
 440                 end if;\r
 441             when ST_A24_T2 =>\r
 442                 if (reg_sub_state = ST_SUB73) then\r
 443                     reg_main_next_state <= ST_A24_T3;\r
 444                 else\r
 445                     reg_main_next_state <= reg_main_state;\r
 446                 end if;\r
 447             when ST_A24_T3 =>\r
 448                 if (reg_sub_state = ST_SUB73) then\r
 449                     reg_main_next_state <= ST_A24_T4;\r
 450                 else\r
 451                     reg_main_next_state <= reg_main_state;\r
 452                 end if;\r
 453             when ST_A24_T4 =>\r
 454                 if (reg_sub_state = ST_SUB73) then\r
 455                     reg_main_next_state <= ST_A24_T5;\r
 456                 else\r
 457                     reg_main_next_state <= reg_main_state;\r
 458                 end if;\r
 459             when ST_A24_T5 =>\r
 460                 if (reg_sub_state = ST_SUB73) then\r
 461                     reg_main_next_state <= ST_CM_T0;\r
 462                 else\r
 463                     reg_main_next_state <= reg_main_state;\r
 464                 end if;\r
 465             when ST_A25_T1 =>\r
 466                 if (reg_sub_state = ST_SUB73) then\r
 467                     reg_main_next_state <= ST_A25_T2;\r
 468                 else\r
 469                     reg_main_next_state <= reg_main_state;\r
 470                 end if;\r
 471             when ST_A25_T2 =>\r
 472                 if (reg_sub_state = ST_SUB73) then\r
 473                     reg_main_next_state <= ST_A25_T3;\r
 474                 else\r
 475                     reg_main_next_state <= reg_main_state;\r
 476                 end if;\r
 477             when ST_A25_T3 =>\r
 478                 if (reg_sub_state = ST_SUB73) then\r
 479                     --abs xy move to next only when page crossed.\r
 480                     if (reg_tmp_pg_crossed = '1') then\r
 481                         reg_main_next_state <= ST_A25_T4;\r
 482                     else\r
 483                         reg_main_next_state <= ST_CM_T0;\r
 484                     end if;\r
 485                 else\r
 486                     reg_main_next_state <= reg_main_state;\r
 487                 end if;\r
 488             when ST_A25_T4 =>\r
 489                 if (reg_sub_state = ST_SUB73) then\r
 490                     reg_main_next_state <= ST_CM_T0;\r
 491                 else\r
 492                     reg_main_next_state <= reg_main_state;\r
 493                 end if;\r
 494             when ST_A26_T1 =>\r
 495                 if (reg_sub_state = ST_SUB73) then\r
 496                     reg_main_next_state <= ST_A26_T2;\r
 497                 else\r
 498                     reg_main_next_state <= reg_main_state;\r
 499                 end if;\r
 500             when ST_A26_T2 =>\r
 501                 if (reg_sub_state = ST_SUB73) then\r
 502                     reg_main_next_state <= ST_A26_T3;\r
 503                 else\r
 504                     reg_main_next_state <= reg_main_state;\r
 505                 end if;\r
 506             when ST_A26_T3 =>\r
 507                 if (reg_sub_state = ST_SUB73) then\r
 508                     reg_main_next_state <= ST_CM_T0;\r
 509                 else\r
 510                     reg_main_next_state <= reg_main_state;\r
 511                 end if;\r
 512             when ST_A27_T1 =>\r
 513                 if (reg_sub_state = ST_SUB73) then\r
 514                     reg_main_next_state <= ST_A27_T2;\r
 515                 else\r
 516                     reg_main_next_state <= reg_main_state;\r
 517                 end if;\r
 518             when ST_A27_T2 =>\r
 519                 if (reg_sub_state = ST_SUB73) then\r
 520                     reg_main_next_state <= ST_A27_T3;\r
 521                 else\r
 522                     reg_main_next_state <= reg_main_state;\r
 523                 end if;\r
 524             when ST_A27_T3 =>\r
 525                 if (reg_sub_state = ST_SUB73) then\r
 526                     reg_main_next_state <= ST_A27_T4;\r
 527                 else\r
 528                     reg_main_next_state <= reg_main_state;\r
 529                 end if;\r
 530             when ST_A27_T4 =>\r
 531                 if (reg_sub_state = ST_SUB73) then\r
 532                     --indir, y move to next only when page crossed.\r
 533                     if (reg_tmp_pg_crossed = '1') then\r
 534                         reg_main_next_state <= ST_A27_T5;\r
 535                     else\r
 536                         reg_main_next_state <= ST_CM_T0;\r
 537                     end if;\r
 538                 else\r
 539                     reg_main_next_state <= reg_main_state;\r
 540                 end if;\r
 541             when ST_A27_T5 =>\r
 542                 if (reg_sub_state = ST_SUB73) then\r
 543                     reg_main_next_state <= ST_CM_T0;\r
 544                 else\r
 545                     reg_main_next_state <= reg_main_state;\r
 546                 end if;\r
 547 \r
 548             --A3 inst.\r
 549             when ST_A31_T1 =>\r
 550                 if (reg_sub_state = ST_SUB73) then\r
 551                     reg_main_next_state <= ST_A31_T2;\r
 552                 else\r
 553                     reg_main_next_state <= reg_main_state;\r
 554                 end if;\r
 555             when ST_A31_T2 =>\r
 556                 if (reg_sub_state = ST_SUB73) then\r
 557                     reg_main_next_state <= ST_CM_T0;\r
 558                 else\r
 559                     reg_main_next_state <= reg_main_state;\r
 560                 end if;\r
 561             when ST_A32_T1 =>\r
 562                 if (reg_sub_state = ST_SUB73) then\r
 563                     reg_main_next_state <= ST_A32_T2;\r
 564                 else\r
 565                     reg_main_next_state <= reg_main_state;\r
 566                 end if;\r
 567             when ST_A32_T2 =>\r
 568                 if (reg_sub_state = ST_SUB73) then\r
 569                     reg_main_next_state <= ST_A32_T3;\r
 570                 else\r
 571                     reg_main_next_state <= reg_main_state;\r
 572                 end if;\r
 573             when ST_A32_T3 =>\r
 574                 if (reg_sub_state = ST_SUB73) then\r
 575                     reg_main_next_state <= ST_CM_T0;\r
 576                 else\r
 577                     reg_main_next_state <= reg_main_state;\r
 578                 end if;\r
 579             when ST_A33_T1 =>\r
 580                 if (reg_sub_state = ST_SUB73) then\r
 581                     reg_main_next_state <= ST_A33_T2;\r
 582                 else\r
 583                     reg_main_next_state <= reg_main_state;\r
 584                 end if;\r
 585             when ST_A33_T2 =>\r
 586                 if (reg_sub_state = ST_SUB73) then\r
 587                     reg_main_next_state <= ST_A33_T3;\r
 588                 else\r
 589                     reg_main_next_state <= reg_main_state;\r
 590                 end if;\r
 591             when ST_A33_T3 =>\r
 592                 if (reg_sub_state = ST_SUB73) then\r
 593                     reg_main_next_state <= ST_A33_T4;\r
 594                 else\r
 595                     reg_main_next_state <= reg_main_state;\r
 596                 end if;\r
 597             when ST_A33_T4 =>\r
 598                 if (reg_sub_state = ST_SUB73) then\r
 599                     reg_main_next_state <= ST_A33_T5;\r
 600                 else\r
 601                     reg_main_next_state <= reg_main_state;\r
 602                 end if;\r
 603             when ST_A33_T5 =>\r
 604                 if (reg_sub_state = ST_SUB73) then\r
 605                     reg_main_next_state <= ST_CM_T0;\r
 606                 else\r
 607                     reg_main_next_state <= reg_main_state;\r
 608                 end if;\r
 609             when ST_A34_T1 =>\r
 610                 if (reg_sub_state = ST_SUB73) then\r
 611                     reg_main_next_state <= ST_A34_T2;\r
 612                 else\r
 613                     reg_main_next_state <= reg_main_state;\r
 614                 end if;\r
 615             when ST_A34_T2 =>\r
 616                 if (reg_sub_state = ST_SUB73) then\r
 617                     reg_main_next_state <= ST_A34_T3;\r
 618                 else\r
 619                     reg_main_next_state <= reg_main_state;\r
 620                 end if;\r
 621             when ST_A34_T3 =>\r
 622                 if (reg_sub_state = ST_SUB73) then\r
 623                     reg_main_next_state <= ST_A34_T4;\r
 624                 else\r
 625                     reg_main_next_state <= reg_main_state;\r
 626                 end if;\r
 627             when ST_A34_T4 =>\r
 628                 if (reg_sub_state = ST_SUB73) then\r
 629                     reg_main_next_state <= ST_CM_T0;\r
 630                 else\r
 631                     reg_main_next_state <= reg_main_state;\r
 632                 end if;\r
 633             when ST_A35_T1 =>\r
 634                 if (reg_sub_state = ST_SUB73) then\r
 635                     reg_main_next_state <= ST_A35_T2;\r
 636                 else\r
 637                     reg_main_next_state <= reg_main_state;\r
 638                 end if;\r
 639             when ST_A35_T2 =>\r
 640                 if (reg_sub_state = ST_SUB73) then\r
 641                     reg_main_next_state <= ST_A35_T3;\r
 642                 else\r
 643                     reg_main_next_state <= reg_main_state;\r
 644                 end if;\r
 645             when ST_A35_T3 =>\r
 646                 if (reg_sub_state = ST_SUB73) then\r
 647                     reg_main_next_state <= ST_CM_T0;\r
 648                 else\r
 649                     reg_main_next_state <= reg_main_state;\r
 650                 end if;\r
 651             when ST_A36_T1 =>\r
 652                 if (reg_sub_state = ST_SUB73) then\r
 653                     reg_main_next_state <= ST_A36_T2;\r
 654                 else\r
 655                     reg_main_next_state <= reg_main_state;\r
 656                 end if;\r
 657             when ST_A36_T2 =>\r
 658                 if (reg_sub_state = ST_SUB73) then\r
 659                     reg_main_next_state <= ST_A36_T3;\r
 660                 else\r
 661                     reg_main_next_state <= reg_main_state;\r
 662                 end if;\r
 663             when ST_A36_T3 =>\r
 664                 if (reg_sub_state = ST_SUB73) then\r
 665                     reg_main_next_state <= ST_A36_T4;\r
 666                 else\r
 667                     reg_main_next_state <= reg_main_state;\r
 668                 end if;\r
 669             when ST_A36_T4 =>\r
 670                 if (reg_sub_state = ST_SUB73) then\r
 671                     reg_main_next_state <= ST_A36_T5;\r
 672                 else\r
 673                     reg_main_next_state <= reg_main_state;\r
 674                 end if;\r
 675             when ST_A36_T5 =>\r
 676                 if (reg_sub_state = ST_SUB73) then\r
 677                     reg_main_next_state <= ST_CM_T0;\r
 678                 else\r
 679                     reg_main_next_state <= reg_main_state;\r
 680                 end if;\r
 681 \r
 682 \r
 683             --A4 inst.\r
 684             when ST_A41_T1 =>\r
 685                 if (reg_sub_state = ST_SUB73) then\r
 686                     reg_main_next_state <= ST_A41_T2;\r
 687                 else\r
 688                     reg_main_next_state <= reg_main_state;\r
 689                 end if;\r
 690             when ST_A41_T2 =>\r
 691                 if (reg_sub_state = ST_SUB73) then\r
 692                     reg_main_next_state <= ST_A41_T3;\r
 693                 else\r
 694                     reg_main_next_state <= reg_main_state;\r
 695                 end if;\r
 696             when ST_A41_T3 =>\r
 697                 if (reg_sub_state = ST_SUB73) then\r
 698                     reg_main_next_state <= ST_A41_T4;\r
 699                 else\r
 700                     reg_main_next_state <= reg_main_state;\r
 701                 end if;\r
 702             when ST_A41_T4 =>\r
 703                 if (reg_sub_state = ST_SUB73) then\r
 704                     reg_main_next_state <= ST_CM_T0;\r
 705                 else\r
 706                     reg_main_next_state <= reg_main_state;\r
 707                 end if;\r
 708             when ST_A42_T1 =>\r
 709                 if (reg_sub_state = ST_SUB73) then\r
 710                     reg_main_next_state <= ST_A42_T2;\r
 711                 else\r
 712                     reg_main_next_state <= reg_main_state;\r
 713                 end if;\r
 714             when ST_A42_T2 =>\r
 715                 if (reg_sub_state = ST_SUB73) then\r
 716                     reg_main_next_state <= ST_A42_T3;\r
 717                 else\r
 718                     reg_main_next_state <= reg_main_state;\r
 719                 end if;\r
 720             when ST_A42_T3 =>\r
 721                 if (reg_sub_state = ST_SUB73) then\r
 722                     reg_main_next_state <= ST_A42_T4;\r
 723                 else\r
 724                     reg_main_next_state <= reg_main_state;\r
 725                 end if;\r
 726             when ST_A42_T4 =>\r
 727                 if (reg_sub_state = ST_SUB73) then\r
 728                     reg_main_next_state <= ST_A42_T5;\r
 729                 else\r
 730                     reg_main_next_state <= reg_main_state;\r
 731                 end if;\r
 732             when ST_A42_T5 =>\r
 733                 if (reg_sub_state = ST_SUB73) then\r
 734                     reg_main_next_state <= ST_CM_T0;\r
 735                 else\r
 736                     reg_main_next_state <= reg_main_state;\r
 737                 end if;\r
 738             when ST_A43_T1 =>\r
 739                 if (reg_sub_state = ST_SUB73) then\r
 740                     reg_main_next_state <= ST_A43_T2;\r
 741                 else\r
 742                     reg_main_next_state <= reg_main_state;\r
 743                 end if;\r
 744             when ST_A43_T2 =>\r
 745                 if (reg_sub_state = ST_SUB73) then\r
 746                     reg_main_next_state <= ST_CM_T0;\r
 747                 else\r
 748                     reg_main_next_state <= reg_main_state;\r
 749                 end if;\r
 750             when ST_A43_T3 =>\r
 751                 if (reg_sub_state = ST_SUB73) then\r
 752                     reg_main_next_state <= ST_A43_T4;\r
 753                 else\r
 754                     reg_main_next_state <= reg_main_state;\r
 755                 end if;\r
 756             when ST_A43_T4 =>\r
 757                 if (reg_sub_state = ST_SUB73) then\r
 758                     reg_main_next_state <= ST_A43_T5;\r
 759                 else\r
 760                     reg_main_next_state <= reg_main_state;\r
 761                 end if;\r
 762             when ST_A43_T5 =>\r
 763                 if (reg_sub_state = ST_SUB73) then\r
 764                     reg_main_next_state <= ST_CM_T0;\r
 765                 else\r
 766                     reg_main_next_state <= reg_main_state;\r
 767                 end if;\r
 768             when ST_A44_T1 =>\r
 769                 if (reg_sub_state = ST_SUB73) then\r
 770                     reg_main_next_state <= ST_A44_T2;\r
 771                 else\r
 772                     reg_main_next_state <= reg_main_state;\r
 773                 end if;\r
 774             when ST_A44_T2 =>\r
 775                 if (reg_sub_state = ST_SUB73) then\r
 776                     reg_main_next_state <= ST_A44_T3;\r
 777                 else\r
 778                     reg_main_next_state <= reg_main_state;\r
 779                 end if;\r
 780             when ST_A44_T3 =>\r
 781                 if (reg_sub_state = ST_SUB73) then\r
 782                     reg_main_next_state <= ST_A44_T4;\r
 783                 else\r
 784                     reg_main_next_state <= reg_main_state;\r
 785                 end if;\r
 786             when ST_A44_T4 =>\r
 787                 if (reg_sub_state = ST_SUB73) then\r
 788                     reg_main_next_state <= ST_A44_T5;\r
 789                 else\r
 790                     reg_main_next_state <= reg_main_state;\r
 791                 end if;\r
 792             when ST_A44_T5 =>\r
 793                 if (reg_sub_state = ST_SUB73) then\r
 794                     reg_main_next_state <= ST_A44_T6;\r
 795                 else\r
 796                     reg_main_next_state <= reg_main_state;\r
 797                 end if;\r
 798             when ST_A44_T6 =>\r
 799                 if (reg_sub_state = ST_SUB73) then\r
 800                     reg_main_next_state <= ST_CM_T0;\r
 801                 else\r
 802                     reg_main_next_state <= reg_main_state;\r
 803                 end if;\r
 804 \r
 805 \r
 806             --A5 inst.\r
 807             when ST_A51_T1 =>\r
 808                 if (reg_sub_state = ST_SUB73) then\r
 809                     reg_main_next_state <= ST_A51_T2;\r
 810                 else\r
 811                     reg_main_next_state <= reg_main_state;\r
 812                 end if;\r
 813             when ST_A51_T2 =>\r
 814                 if (reg_sub_state = ST_SUB73) then\r
 815                     reg_main_next_state <= ST_CM_T0;\r
 816                 else\r
 817                     reg_main_next_state <= reg_main_state;\r
 818                 end if;\r
 819             when ST_A52_T1 =>\r
 820                 if (reg_sub_state = ST_SUB73) then\r
 821                     reg_main_next_state <= ST_A52_T2;\r
 822                 else\r
 823                     reg_main_next_state <= reg_main_state;\r
 824                 end if;\r
 825             when ST_A52_T2 =>\r
 826                 if (reg_sub_state = ST_SUB73) then\r
 827                     reg_main_next_state <= ST_A52_T3;\r
 828                 else\r
 829                     reg_main_next_state <= reg_main_state;\r
 830                 end if;\r
 831             when ST_A52_T3 =>\r
 832                 if (reg_sub_state = ST_SUB73) then\r
 833                     reg_main_next_state <= ST_CM_T0;\r
 834                 else\r
 835                     reg_main_next_state <= reg_main_state;\r
 836                 end if;\r
 837             when ST_A53_T1 =>\r
 838                 if (reg_sub_state = ST_SUB73) then\r
 839                     reg_main_next_state <= ST_A53_T2;\r
 840                 else\r
 841                     reg_main_next_state <= reg_main_state;\r
 842                 end if;\r
 843             when ST_A53_T2 =>\r
 844                 if (reg_sub_state = ST_SUB73) then\r
 845                     reg_main_next_state <= ST_A53_T3;\r
 846                 else\r
 847                     reg_main_next_state <= reg_main_state;\r
 848                 end if;\r
 849             when ST_A53_T3 =>\r
 850                 if (reg_sub_state = ST_SUB73) then\r
 851                     reg_main_next_state <= ST_A53_T4;\r
 852                 else\r
 853                     reg_main_next_state <= reg_main_state;\r
 854                 end if;\r
 855             when ST_A53_T4 =>\r
 856                 if (reg_sub_state = ST_SUB73) then\r
 857                     reg_main_next_state <= ST_A53_T5;\r
 858                 else\r
 859                     reg_main_next_state <= reg_main_state;\r
 860                 end if;\r
 861             when ST_A53_T5 =>\r
 862                 if (reg_sub_state = ST_SUB73) then\r
 863                     reg_main_next_state <= ST_CM_T0;\r
 864                 else\r
 865                     reg_main_next_state <= reg_main_state;\r
 866                 end if;\r
 867             when ST_A55_T1 =>\r
 868                 if (reg_sub_state = ST_SUB73) then\r
 869                     reg_main_next_state <= ST_A55_T2;\r
 870                 else\r
 871                     reg_main_next_state <= reg_main_state;\r
 872                 end if;\r
 873             when ST_A55_T2 =>\r
 874                 if (reg_sub_state = ST_SUB73) then\r
 875                     reg_main_next_state <= ST_A55_T3;\r
 876                 else\r
 877                     reg_main_next_state <= reg_main_state;\r
 878                 end if;\r
 879             when ST_A55_T3 =>\r
 880                 if (reg_sub_state = ST_SUB73) then\r
 881                     reg_main_next_state <= ST_A55_T4;\r
 882                 else\r
 883                     reg_main_next_state <= reg_main_state;\r
 884                 end if;\r
 885             when ST_A55_T4 =>\r
 886                 if (reg_sub_state = ST_SUB73) then\r
 887                     reg_main_next_state <= ST_A55_T5;\r
 888                 else\r
 889                     reg_main_next_state <= reg_main_state;\r
 890                 end if;\r
 891             when ST_A55_T5 =>\r
 892                 if (reg_sub_state = ST_SUB73) then\r
 893                     reg_main_next_state <= ST_CM_T0;\r
 894                 else\r
 895                     reg_main_next_state <= reg_main_state;\r
 896                 end if;\r
 897             when ST_A561_T1 =>\r
 898                 if (reg_sub_state = ST_SUB73) then\r
 899                     reg_main_next_state <= ST_A561_T2;\r
 900                 else\r
 901                     reg_main_next_state <= reg_main_state;\r
 902                 end if;\r
 903             when ST_A561_T2 =>\r
 904                 if (reg_sub_state = ST_SUB73) then\r
 905                     reg_main_next_state <= ST_CM_T0;\r
 906                 else\r
 907                     reg_main_next_state <= reg_main_state;\r
 908                 end if;\r
 909             when ST_A562_T1 =>\r
 910                 if (reg_sub_state = ST_SUB73) then\r
 911                     reg_main_next_state <= ST_A562_T2;\r
 912                 else\r
 913                     reg_main_next_state <= reg_main_state;\r
 914                 end if;\r
 915             when ST_A562_T2 =>\r
 916                 if (reg_sub_state = ST_SUB73) then\r
 917                     reg_main_next_state <= ST_A562_T3;\r
 918                 else\r
 919                     reg_main_next_state <= reg_main_state;\r
 920                 end if;\r
 921             when ST_A562_T3 =>\r
 922                 if (reg_sub_state = ST_SUB73) then\r
 923                     reg_main_next_state <= ST_A562_T4;\r
 924                 else\r
 925                     reg_main_next_state <= reg_main_state;\r
 926                 end if;\r
 927             when ST_A562_T4 =>\r
 928                 if (reg_sub_state = ST_SUB73) then\r
 929                     reg_main_next_state <= ST_CM_T0;\r
 930                 else\r
 931                     reg_main_next_state <= reg_main_state;\r
 932                 end if;\r
 933             when ST_A57_T1 =>\r
 934                 if (reg_sub_state = ST_SUB73) then\r
 935                     reg_main_next_state <= ST_A57_T2;\r
 936                 else\r
 937                     reg_main_next_state <= reg_main_state;\r
 938                 end if;\r
 939             when ST_A57_T2 =>\r
 940                 if (reg_sub_state = ST_SUB73) then\r
 941                     reg_main_next_state <= ST_A57_T3;\r
 942                 else\r
 943                     reg_main_next_state <= reg_main_state;\r
 944                 end if;\r
 945             when ST_A57_T3 =>\r
 946                 if (reg_sub_state = ST_SUB73) then\r
 947                     reg_main_next_state <= ST_A57_T4;\r
 948                 else\r
 949                     reg_main_next_state <= reg_main_state;\r
 950                 end if;\r
 951             when ST_A57_T4 =>\r
 952                 if (reg_sub_state = ST_SUB73) then\r
 953                     reg_main_next_state <= ST_A57_T5;\r
 954                 else\r
 955                     reg_main_next_state <= reg_main_state;\r
 956                 end if;\r
 957             when ST_A57_T5 =>\r
 958                 if (reg_sub_state = ST_SUB73) then\r
 959                     reg_main_next_state <= ST_CM_T0;\r
 960                 else\r
 961                     reg_main_next_state <= reg_main_state;\r
 962                 end if;\r
 963             when ST_A58_T1 =>\r
 964                 if (reg_sub_state = ST_SUB73) then\r
 965                     if (reg_tmp_condition = '1') then\r
 966                         --condition met. move to branch state.\r
 967                         reg_main_next_state <= ST_A58_T2;\r
 968                     else\r
 969                         --condition not met. goto next inst fetch.\r
 970                         reg_main_next_state <= ST_CM_T0;\r
 971                     end if;\r
 972                 else\r
 973                     reg_main_next_state <= reg_main_state;\r
 974                 end if;\r
 975             when ST_A58_T2 =>\r
 976                 if (reg_sub_state = ST_SUB73) then\r
 977                     if (reg_tmp_pg_crossed = '1') then\r
 978                         --page crossed. move to next.\r
 979                         reg_main_next_state <= ST_A58_T2;\r
 980                     else\r
 981                         --page not crossed. move to next inst fetch.\r
 982                         reg_main_next_state <= ST_CM_T0;\r
 983                     end if;\r
 984                 else\r
 985                     reg_main_next_state <= reg_main_state;\r
 986                 end if;\r
 987             when ST_A58_T3 =>\r
 988                 if (reg_sub_state = ST_SUB73) then\r
 989                     reg_main_next_state <= ST_CM_T0;\r
 990                 else\r
 991                     reg_main_next_state <= reg_main_state;\r
 992                 end if;\r
 993 \r
 994             when ST_INV =>\r
 995                 ---failed to decode next...\r
 996                     reg_main_next_state <= reg_main_state;\r
 997 --            ---not ready yet...\r
 998 --            when others =>\r
 999 --                reg_main_next_state <= reg_main_state;\r
1000         end case;\r
1001     end process;\r
1002 \r
1003 \r
1004     po_r_nw     <= reg_r_nw;\r
1005     po_addr     <= reg_addr;\r
1006     pio_d_io    <= reg_d_out;\r
1007 \r
1008     --addressing general process...\r
1009     --pc, io bus, r/w, instruction regs...\r
1010     ad_general_p : process (pi_rst_n, pi_base_clk)\r
1011 \r
1012     --address calcuratin w/ carry.\r
1013     variable calc_adl   : std_logic_vector(8 downto 0);\r
1014 \r
1015 procedure pc_inc is\r
1016 begin\r
1017     if (reg_pc_l = "11111111") then\r
1018         --pch page next.\r
1019         reg_pc_l    <= "00000000";\r
1020         reg_pc_h    <= reg_pc_h + 1;\r
1021     else\r
1022         reg_pc_l    <= reg_pc_l + 1;\r
1023     end if;\r
1024 end;\r
1025 \r
1026     begin\r
1027         if (pi_rst_n = '0') then\r
1028             reg_pc_l    <= (others => '0');\r
1029             reg_pc_h    <= (others => '0');\r
1030             reg_inst    <= (others => '0');\r
1031             reg_addr    <= (others => 'Z');\r
1032             reg_d_out   <= (others => 'Z');\r
1033             reg_d_in    <= (others => '0');\r
1034             reg_r_nw    <= 'Z';\r
1035             reg_tmp_pg_crossed  <= '0';\r
1036             calc_adl    := (others => '0');\r
1037         elsif (rising_edge(pi_base_clk)) then\r
1038 \r
1039             --general input data register.\r
1040             reg_d_in    <= pio_d_io;\r
1041             \r
1042             --i/o data bus state change.\r
1043             if (reg_main_state = ST_RS_T0) then\r
1044                 reg_pc_l    <= (others => '0');\r
1045                 reg_pc_h    <= (others => '0');\r
1046                 reg_inst    <= (others => '0');\r
1047                 reg_addr    <= (others => '0');\r
1048                 reg_d_out   <= (others => 'Z');\r
1049                 reg_r_nw    <= '1';\r
1050             elsif (reg_main_state = ST_RS_T3) then\r
1051                 --dummy sp out 1.\r
1052                 reg_addr    <= "11111111" & reg_sp;\r
1053                 reg_d_out   <= (others => 'Z');\r
1054                 reg_r_nw    <= '0';\r
1055             elsif (reg_main_state = ST_RS_T4) then\r
1056                 --dummy sp out 2.\r
1057                 reg_addr    <= "11111111" & (reg_sp - 1);\r
1058                 reg_d_out   <= (others => 'Z');\r
1059                 reg_r_nw    <= '0';\r
1060             elsif (reg_main_state = ST_RS_T5) then\r
1061                 --dummy sp out 3.\r
1062                 reg_addr    <= "11111111" & (reg_sp - 2);\r
1063                 reg_d_out   <= (others => 'Z');\r
1064                 reg_r_nw    <= '0';\r
1065             elsif (reg_main_state = ST_RS_T6) then\r
1066                 --reset vector low...\r
1067                 reg_addr    <= "1111111111111100";\r
1068                 reg_d_out   <= (others => 'Z');\r
1069                 reg_r_nw    <= '1';\r
1070                 reg_pc_l    <= reg_d_in;\r
1071             elsif (reg_main_state = ST_RS_T7) then\r
1072                 --reset vector high...\r
1073                 reg_addr    <= "1111111111111101";\r
1074                 reg_d_out   <= (others => 'Z');\r
1075                 reg_r_nw    <= '1';\r
1076                 reg_pc_h    <= reg_d_in;\r
1077             elsif (reg_main_state = ST_CM_T0) then\r
1078                 --init pg crossing flag.\r
1079                 reg_tmp_pg_crossed <= '0';\r
1080                 calc_adl    := (others => '0');\r
1081 \r
1082                 if (reg_sub_state = ST_SUB00) then\r
1083                     --fetch next.\r
1084                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1085                     reg_d_out   <= (others => 'Z');\r
1086                     reg_r_nw    <= '1';\r
1087                 elsif (reg_sub_state = ST_SUB30) then\r
1088                     --update instruction register.\r
1089                     reg_inst    <= reg_d_in;\r
1090                 elsif (reg_sub_state = ST_SUB70) then\r
1091                     --pc move next.\r
1092                     pc_inc;\r
1093                 end if;\r
1094             --fetch and move next case.\r
1095             elsif (reg_main_state = ST_A21_T1 or\r
1096                 reg_main_state = ST_A22_T1 or\r
1097                 reg_main_state = ST_A23_T1 or\r
1098                 reg_main_state = ST_A23_T2 or\r
1099                 reg_main_state = ST_A24_T1 or\r
1100                 reg_main_state = ST_A25_T1 or\r
1101                 reg_main_state = ST_A25_T2 or\r
1102                 reg_main_state = ST_A26_T1 or\r
1103                 reg_main_state = ST_A27_T1 or\r
1104                 reg_main_state = ST_A31_T1 or\r
1105                 reg_main_state = ST_A32_T1 or\r
1106                 reg_main_state = ST_A32_T2 or\r
1107                 reg_main_state = ST_A33_T1 or\r
1108                 reg_main_state = ST_A34_T1 or\r
1109                 reg_main_state = ST_A34_T2 or\r
1110                 reg_main_state = ST_A35_T1 or\r
1111                 reg_main_state = ST_A36_T1 or\r
1112                 reg_main_state = ST_A41_T1 or\r
1113                 reg_main_state = ST_A42_T1 or\r
1114                 reg_main_state = ST_A42_T2 or\r
1115                 reg_main_state = ST_A43_T1 or\r
1116                 reg_main_state = ST_A44_T1 or\r
1117                 reg_main_state = ST_A44_T2 or\r
1118                 reg_main_state = ST_A53_T1 or\r
1119                 reg_main_state = ST_A561_T1 or\r
1120                 reg_main_state = ST_A562_T1 or\r
1121                 reg_main_state = ST_A57_T1 or\r
1122                 reg_main_state = ST_A58_T1) then\r
1123                 if (reg_sub_state = ST_SUB00) then\r
1124                     --fetch next.\r
1125                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1126                     reg_d_out   <= (others => 'Z');\r
1127                     reg_r_nw    <= '1';\r
1128                 elsif (reg_sub_state = ST_SUB70) then\r
1129                     --pc move next.\r
1130                     pc_inc;\r
1131                 end if;\r
1132 \r
1133             --intermediate cycles..\r
1134             elsif (reg_main_state = ST_A24_T2 or\r
1135                 reg_main_state = ST_A26_T2 or\r
1136                 reg_main_state = ST_A33_T2 or\r
1137                 reg_main_state = ST_A35_T2 or\r
1138                 reg_main_state = ST_A27_T2 or\r
1139                 reg_main_state = ST_A36_T2 or\r
1140                 reg_main_state = ST_A43_T2\r
1141                 ) then\r
1142                 --zp xy\r
1143                 --ind, x\r
1144                 -->>discarded cycle.\r
1145                 --ind, y\r
1146                 --ial cycle.\r
1147                 reg_addr    <= "00000000" & reg_idl_l;\r
1148                 reg_d_out   <= (others => 'Z');\r
1149                 reg_r_nw    <= '1';\r
1150             elsif (reg_main_state = ST_A24_T3 or\r
1151                 reg_main_state = ST_A33_T3\r
1152                 ) then\r
1153                 --ind, x\r
1154                 --bal + x cycle.\r
1155                 reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1156                 reg_d_out   <= (others => 'Z');\r
1157                 reg_r_nw    <= '1';\r
1158             elsif (reg_main_state = ST_A24_T4 or\r
1159                 reg_main_state = ST_A33_T4) then\r
1160                 --ind, x\r
1161                 --bal + x + 1 cycle.\r
1162                 reg_addr    <= "00000000" & (reg_idl_l + reg_x + 1);\r
1163                 reg_d_out   <= (others => 'Z');\r
1164                 reg_r_nw    <= '1';\r
1165             elsif (reg_main_state = ST_A25_T3 or\r
1166                 reg_main_state = ST_A34_T3 or\r
1167                 reg_main_state = ST_A44_T3\r
1168                 ) then\r
1169                 --abs xy\r
1170                 --(discarded cycle for store inst..)\r
1171                 if (reg_inst(1 downto 0) = "01") then\r
1172                     if (reg_inst(4 downto 2) = "110") then\r
1173                         --abs y\r
1174                         reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
1175                     elsif (reg_inst(4 downto 2) = "111") then\r
1176                         --abs x\r
1177                         reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1178                     end if; \r
1179                 elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then\r
1180                     --abs y\r
1181                     --ldx\r
1182                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
1183                 elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then\r
1184                     --abs x\r
1185                     --ldy\r
1186                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1187                 elsif (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
1188                     --sta, x\r
1189                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1190                     calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
1191                 elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then\r
1192                     --sta, y\r
1193                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
1194                     calc_adl    := ("0" & reg_idl_l) + ("0" & reg_y);\r
1195                 elsif (reg_inst(1 downto 0) = "10") then\r
1196                     --a4 inst.\r
1197                     if (reg_inst(4 downto 2) = "111") then\r
1198                         --abs x\r
1199                         reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
1200                         calc_adl    := ("0" & reg_idl_l) + ("0" & reg_y);\r
1201                     end if; \r
1202                 end if;\r
1203                 reg_d_out   <= (others => 'Z');\r
1204                 reg_r_nw    <= '1';\r
1205 \r
1206                 reg_tmp_pg_crossed <= calc_adl(8);\r
1207             elsif (reg_main_state = ST_A27_T3 or\r
1208                 reg_main_state = ST_A36_T3) then\r
1209                 --ind, y\r
1210                 --ial + 1 cycle.\r
1211                 reg_addr    <= "00000000" & (reg_idl_l + 1);\r
1212                 reg_d_out   <= (others => 'Z');\r
1213                 reg_r_nw    <= '1';\r
1214             elsif (reg_main_state = ST_A27_T4 or\r
1215                 reg_main_state = ST_A36_T4) then\r
1216                 --ind, y\r
1217                 --bal + y cycle.\r
1218                 reg_addr    <= reg_tmp_h & (reg_tmp_l + reg_y);\r
1219                 reg_d_out   <= (others => 'Z');\r
1220                 reg_r_nw    <= '1';\r
1221                 calc_adl    := ("0" & reg_tmp_l) + ("0" & reg_y);\r
1222                 reg_tmp_pg_crossed <= calc_adl(8);\r
1223 \r
1224 \r
1225            --a2 instructions.\r
1226             elsif (reg_main_state = ST_A22_T2 or\r
1227                 reg_main_state = ST_A23_T3 or\r
1228                 reg_main_state = ST_A24_T5 or\r
1229                 reg_main_state = ST_A25_T4 or\r
1230                 reg_main_state = ST_A26_T3 or\r
1231                 reg_main_state = ST_A27_T5\r
1232             ) then\r
1233                 --execute cycle.\r
1234                 reg_d_out   <= (others => 'Z');\r
1235                 reg_r_nw    <= '1';\r
1236 \r
1237                 --address bus out.\r
1238                 if (reg_main_state = ST_A22_T2) then\r
1239                     --zp\r
1240                     reg_addr    <= "00000000" & reg_idl_l;\r
1241 \r
1242                 elsif (reg_main_state = ST_A23_T3) then\r
1243                     --abs\r
1244                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1245 \r
1246                 elsif (reg_main_state = ST_A24_T5) then\r
1247                     --ind, x\r
1248                     reg_addr    <= reg_tmp_h & reg_tmp_l;\r
1249 \r
1250                 elsif (reg_main_state = ST_A25_T4) then\r
1251                     --abs xy\r
1252                     if (reg_inst(1 downto 0) = "01") then\r
1253                         if (reg_inst(4 downto 2) = "110") then\r
1254                             --abs y\r
1255                             reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
1256                         elsif (reg_inst(4 downto 2) = "111") then\r
1257                             --abs x\r
1258                             reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1259                         end if; \r
1260                     elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then\r
1261                         --abs y\r
1262                         --ldx\r
1263                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
1264                     elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then\r
1265                         --abs x\r
1266                         --ldy\r
1267                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1268                     end if; \r
1269 \r
1270                 elsif (reg_main_state = ST_A26_T3) then\r
1271                     --zp xy\r
1272                     if (reg_inst(1 downto 0) = "01") then\r
1273                         if (reg_inst(4 downto 2) = "101") then\r
1274                             --zp x\r
1275                             reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1276                         end if; \r
1277                     elsif (reg_inst = conv_std_logic_vector(16#b6#, 8)) then\r
1278                         --zp y\r
1279                         --ldx\r
1280                         reg_addr    <= "00000000" & (reg_idl_l + reg_y);\r
1281                     elsif (reg_inst = conv_std_logic_vector(16#b4#, 8)) then\r
1282                         --zp y\r
1283                         --ldy\r
1284                         reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1285                     end if; \r
1286 \r
1287                 elsif (reg_main_state = ST_A27_T5) then\r
1288                     --ind y\r
1289                     reg_addr    <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
1290                 end if;\r
1291 \r
1292            --a3 instructions.\r
1293            --sta, stx, sty\r
1294             elsif (reg_main_state = ST_A31_T2 or\r
1295                 reg_main_state = ST_A32_T3 or\r
1296                 reg_main_state = ST_A33_T5 or\r
1297                 reg_main_state = ST_A34_T4 or\r
1298                 reg_main_state = ST_A35_T3 or\r
1299                 reg_main_state = ST_A36_T5\r
1300             ) then\r
1301                 --store cycle.\r
1302                 --data out\r
1303                 if (reg_inst(1 downto 0) = "01" and reg_inst(7 downto 5) = "100") then\r
1304                     --sta\r
1305                     reg_d_out   <= reg_acc;\r
1306                 elsif (reg_inst(1 downto 0) = "10" and reg_inst(7 downto 5) = "100") then\r
1307                     --stx\r
1308                     reg_d_out   <= reg_x;\r
1309                 elsif (reg_inst(1 downto 0) = "00" and reg_inst(7 downto 5) = "100") then\r
1310                     --sty\r
1311                     reg_d_out   <= reg_y;\r
1312                 end if;\r
1313 \r
1314                 --rw ctrl\r
1315                 if (reg_sub_state = ST_SUB32 or\r
1316                     reg_sub_state = ST_SUB33 or\r
1317                     reg_sub_state = ST_SUB40 or\r
1318                     reg_sub_state = ST_SUB41\r
1319                     ) then\r
1320                     reg_r_nw    <= '0';\r
1321                 else\r
1322                     reg_r_nw    <= 'Z';\r
1323                 end if;\r
1324 \r
1325                 --address bus out.\r
1326                 if (reg_main_state = ST_A31_T2) then\r
1327                     --zp\r
1328                     reg_addr    <= "00000000" & reg_idl_l;\r
1329 \r
1330                 elsif (reg_main_state = ST_A32_T3) then\r
1331                     --abs\r
1332                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1333 \r
1334                 elsif (reg_main_state = ST_A33_T5) then\r
1335                     --ind, x\r
1336                     reg_addr    <= reg_tmp_h & reg_tmp_l;\r
1337 \r
1338                 elsif (reg_main_state = ST_A34_T4) then\r
1339                     --abs xy\r
1340                     if (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
1341                         --sta, x\r
1342                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1343                     elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then\r
1344                         --sta, y\r
1345                         reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
1346                     end if;\r
1347 \r
1348                 elsif (reg_main_state = ST_A35_T3) then\r
1349                     --zp xy\r
1350                     --sta and sty has index x access,\r
1351                     --stx has index y access.\r
1352                     if (reg_inst = conv_std_logic_vector(16#95#, 8) or --sta\r
1353                         reg_inst = conv_std_logic_vector(16#94#, 8) --sty\r
1354                     ) then\r
1355                         reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1356                     elsif (reg_inst = conv_std_logic_vector(16#96#, 8)) then\r
1357                         --stx\r
1358                         reg_addr    <= "00000000" & (reg_idl_l + reg_y);\r
1359                     end if;\r
1360 \r
1361                 elsif (reg_main_state = ST_A36_T5) then\r
1362                     --ind y\r
1363                     reg_addr    <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
1364                 end if;\r
1365 \r
1366            --a4 instructions.\r
1367            --asl    lsr\r
1368            --dec    rol\r
1369            --inc    ror\r
1370             elsif (reg_main_state = ST_A41_T2 or\r
1371                 reg_main_state = ST_A42_T3 or\r
1372                 reg_main_state = ST_A43_T3 or\r
1373                 reg_main_state = ST_A44_T4\r
1374             ) then\r
1375                 --data fetch cycle.\r
1376                 reg_d_out   <= (others => 'Z');\r
1377                 reg_r_nw    <= '1';\r
1378 \r
1379                 --address bus out.\r
1380                 if (reg_main_state = ST_A41_T2) then\r
1381                     --zp\r
1382                     reg_addr    <= "00000000" & reg_idl_l;\r
1383 \r
1384                 elsif (reg_main_state = ST_A42_T3) then\r
1385                     --abs\r
1386                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1387 \r
1388                 elsif (reg_main_state = ST_A43_T3) then\r
1389                     --zp x\r
1390                     reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1391 \r
1392                 elsif (reg_main_state = ST_A44_T4) then\r
1393                     --abs x\r
1394                     reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1395                 end if;\r
1396 \r
1397             elsif (reg_main_state = ST_A41_T3 or\r
1398                 reg_main_state = ST_A41_T4 or\r
1399                 reg_main_state = ST_A42_T4 or\r
1400                 reg_main_state = ST_A42_T5 or\r
1401                 reg_main_state = ST_A43_T4 or\r
1402                 reg_main_state = ST_A43_T5 or\r
1403                 reg_main_state = ST_A44_T5 or\r
1404                 reg_main_state = ST_A44_T6\r
1405             ) then\r
1406                 --data store cycle.\r
1407                 --data out\r
1408                 reg_d_out   <= reg_tmp_data;\r
1409 \r
1410                 --rw ctrl\r
1411                 if (reg_sub_state = ST_SUB32 or\r
1412                     reg_sub_state = ST_SUB33 or\r
1413                     reg_sub_state = ST_SUB40 or\r
1414                     reg_sub_state = ST_SUB41\r
1415                     ) then\r
1416                     reg_r_nw    <= '0';\r
1417                 else\r
1418                     reg_r_nw    <= 'Z';\r
1419                 end if;\r
1420 \r
1421                 --address bus out.\r
1422                 if (reg_main_state = ST_A41_T3 or\r
1423                     reg_main_state = ST_A41_T4\r
1424                     ) then\r
1425                     --zp\r
1426                     reg_addr    <= "00000000" & reg_idl_l;\r
1427 \r
1428                 elsif (reg_main_state = ST_A42_T4 or\r
1429                     reg_main_state = ST_A42_T5\r
1430                     ) then\r
1431                     --abs\r
1432                     reg_addr    <= reg_idl_h & reg_idl_l;\r
1433 \r
1434                 elsif (reg_main_state = ST_A43_T4 or\r
1435                     reg_main_state = ST_A43_T5\r
1436                     ) then\r
1437                     --zp x\r
1438                     reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
1439 \r
1440                 elsif (reg_main_state = ST_A44_T5 or\r
1441                     reg_main_state = ST_A44_T6\r
1442                     ) then\r
1443                     --abs x\r
1444                     reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
1445                 end if;\r
1446 \r
1447             --jsr.\r
1448             elsif (reg_main_state = ST_A53_T2) then\r
1449                 --sp out (discarded.)\r
1450                 reg_addr    <= "00000001" & reg_sp;\r
1451                 reg_d_out   <= (others => 'Z');\r
1452                 reg_r_nw    <= '1';\r
1453             elsif (reg_main_state = ST_A53_T3) then\r
1454                 --push pch\r
1455                 reg_addr    <= "00000001" & reg_sp;\r
1456                 reg_d_out   <= reg_pc_h;\r
1457                 if (reg_sub_state = ST_SUB32 or\r
1458                     reg_sub_state = ST_SUB33 or\r
1459                     reg_sub_state = ST_SUB40 or\r
1460                     reg_sub_state = ST_SUB41\r
1461                     ) then\r
1462                     reg_r_nw    <= '0';\r
1463                 else\r
1464                     reg_r_nw    <= 'Z';\r
1465                 end if;\r
1466             elsif (reg_main_state = ST_A53_T4) then\r
1467                 --push pcl\r
1468                 reg_addr    <= "00000001" & reg_sp;\r
1469                 reg_d_out   <= reg_pc_l;\r
1470                 if (reg_sub_state = ST_SUB32 or\r
1471                     reg_sub_state = ST_SUB33 or\r
1472                     reg_sub_state = ST_SUB40 or\r
1473                     reg_sub_state = ST_SUB41\r
1474                     ) then\r
1475                     reg_r_nw    <= '0';\r
1476                 else\r
1477                     reg_r_nw    <= 'Z';\r
1478                 end if;\r
1479             elsif (reg_main_state = ST_A53_T5) then\r
1480                 if (reg_sub_state = ST_SUB00) then\r
1481                     --fetch next.\r
1482                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1483                     reg_d_out   <= (others => 'Z');\r
1484                     reg_r_nw    <= '1';\r
1485                 elsif (reg_sub_state = ST_SUB70) then\r
1486                     --go to sub-routine addr.\r
1487                     reg_pc_l    <= reg_idl_l;\r
1488                     reg_pc_h    <= reg_idl_h;\r
1489                 end if;\r
1490 \r
1491            --jmp.\r
1492             elsif (reg_main_state = ST_A561_T2) then\r
1493                 if (reg_sub_state = ST_SUB00) then\r
1494                     --fetch next.\r
1495                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1496                     reg_d_out   <= (others => 'Z');\r
1497                     reg_r_nw    <= '1';\r
1498                 elsif (reg_sub_state = ST_SUB70) then\r
1499                     reg_pc_l    <= reg_idl_l;\r
1500                     reg_pc_h    <= reg_idl_h;\r
1501                 end if;\r
1502 \r
1503            --rts.\r
1504             elsif (reg_main_state = ST_A57_T2) then\r
1505                 --sp out (discarded.)\r
1506                 reg_addr    <= "00000001" & reg_sp;\r
1507                 reg_d_out   <= (others => 'Z');\r
1508                 reg_r_nw    <= '1';\r
1509             elsif (reg_main_state = ST_A57_T3) then\r
1510                 --pull pcl\r
1511                 if (reg_sub_state = ST_SUB00) then\r
1512                     reg_addr    <= "00000001" & reg_sp;\r
1513                     reg_d_out   <= (others => 'Z');\r
1514                     reg_r_nw    <= '1';\r
1515                 elsif (reg_sub_state = ST_SUB70) then\r
1516                     reg_pc_l    <= reg_d_in;\r
1517                 end if;\r
1518             elsif (reg_main_state = ST_A57_T4) then\r
1519                 --pull pch\r
1520                 if (reg_sub_state = ST_SUB00) then\r
1521                     reg_addr    <= "00000001" & reg_sp;\r
1522                     reg_d_out   <= (others => 'Z');\r
1523                     reg_r_nw    <= '1';\r
1524                 elsif (reg_sub_state = ST_SUB70) then\r
1525                     reg_pc_h    <= reg_d_in;\r
1526                 end if;\r
1527             elsif (reg_main_state = ST_A57_T5) then\r
1528                 --pc out (discarded.)\r
1529                 if (reg_sub_state = ST_SUB00) then\r
1530                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1531                     reg_d_out   <= (others => 'Z');\r
1532                     reg_r_nw    <= '1';\r
1533                 elsif (reg_sub_state = ST_SUB70) then\r
1534                     reg_pc_l    <= reg_pc_l + 1;\r
1535                 end if;\r
1536 \r
1537            --conditional branch.\r
1538             elsif (reg_main_state = ST_A58_T2) then\r
1539                 if (reg_sub_state = ST_SUB10) then\r
1540                     calc_adl    := ("0" & reg_pc_l) + ("0" & reg_idl_l);\r
1541                     reg_tmp_pg_crossed <= calc_adl(8);\r
1542 \r
1543                     reg_pc_l    <= calc_adl(7 downto 0);\r
1544                     reg_addr    <= reg_pc_h & calc_adl(7 downto 0);\r
1545                     reg_d_out   <= (others => 'Z');\r
1546                     reg_r_nw    <= '1';\r
1547                 end if;\r
1548 \r
1549             --page crossed.\r
1550             elsif (reg_main_state = ST_A58_T3) then\r
1551                 if (reg_sub_state = ST_SUB10) then\r
1552                     reg_pc_l    <= reg_pc_h + "1";\r
1553                     reg_addr    <= (reg_pc_h + "1") & reg_pc_l;\r
1554                     reg_d_out   <= (others => 'Z');\r
1555                     reg_r_nw    <= '1';\r
1556                 end if;\r
1557             end if;--if (reg_main_state = ST_RS_T0) then\r
1558         end if;--if (pi_rst_n = '0') then\r
1559     end process;\r
1560 \r
1561     --internal data latch...\r
1562     --fetch first and second operand.\r
1563     idl_p : process (pi_rst_n, pi_base_clk)\r
1564     begin\r
1565         if (pi_rst_n = '0') then\r
1566             reg_idl_l <= (others => '0');\r
1567             reg_idl_h <= (others => '0');\r
1568             reg_tmp_l <= (others => '0');\r
1569             reg_tmp_h <= (others => '0');\r
1570         elsif (rising_edge(pi_base_clk)) then\r
1571             if (reg_main_state = ST_A21_T1 or\r
1572                 reg_main_state = ST_A22_T1 or\r
1573                 reg_main_state = ST_A23_T1 or\r
1574                 reg_main_state = ST_A24_T1 or\r
1575                 reg_main_state = ST_A25_T1 or\r
1576                 reg_main_state = ST_A26_T1 or\r
1577                 reg_main_state = ST_A27_T1 or\r
1578                 reg_main_state = ST_A31_T1 or\r
1579                 reg_main_state = ST_A32_T1 or\r
1580                 reg_main_state = ST_A33_T1 or\r
1581                 reg_main_state = ST_A34_T1 or\r
1582                 reg_main_state = ST_A35_T1 or\r
1583                 reg_main_state = ST_A36_T1 or\r
1584                 reg_main_state = ST_A41_T1 or\r
1585                 reg_main_state = ST_A42_T1 or\r
1586                 reg_main_state = ST_A43_T1 or\r
1587                 reg_main_state = ST_A44_T1 or\r
1588                 reg_main_state = ST_A53_T1 or\r
1589                 reg_main_state = ST_A561_T1 or\r
1590                 reg_main_state = ST_A562_T1 or\r
1591                 reg_main_state = ST_A58_T1) then\r
1592                 if (reg_sub_state = ST_SUB30) then\r
1593                     --get low data from rom.\r
1594                     reg_idl_l <= reg_d_in;\r
1595                 end if;\r
1596             elsif (reg_main_state = ST_A23_T2 or\r
1597                 reg_main_state = ST_A25_T2 or\r
1598                 reg_main_state = ST_A32_T2 or\r
1599                 reg_main_state = ST_A34_T2 or\r
1600                 reg_main_state = ST_A42_T2 or\r
1601                 reg_main_state = ST_A44_T2 or\r
1602                 reg_main_state = ST_A53_T5 or\r
1603                 reg_main_state = ST_A561_T2 or\r
1604                 reg_main_state = ST_A562_T2) then\r
1605                 if (reg_sub_state = ST_SUB30) then\r
1606                     --get high data from rom.\r
1607                     reg_idl_h <= reg_d_in;\r
1608                 end if;\r
1609             elsif (reg_main_state = ST_A24_T3 or\r
1610                 reg_main_state = ST_A27_T2 or\r
1611                 reg_main_state = ST_A33_T3 or\r
1612                 reg_main_state = ST_A36_T2\r
1613                 ) then\r
1614                 --a24 indr, x\r
1615                 --a27 indr, y\r
1616                 --a33 indr, x\r
1617                 --a36 indr, y\r
1618                 if (reg_sub_state = ST_SUB30) then\r
1619                     reg_tmp_l <= reg_d_in;\r
1620                 end if;\r
1621             elsif (reg_main_state = ST_A24_T4 or\r
1622                 reg_main_state = ST_A27_T3 or\r
1623                 reg_main_state = ST_A33_T4 or\r
1624                 reg_main_state = ST_A36_T3\r
1625                 ) then\r
1626                 --a24 indr, x\r
1627                 --a27 indr, y\r
1628                 --a33 indr, x\r
1629                 --a36 indr, y\r
1630                 if (reg_sub_state = ST_SUB30) then\r
1631                     reg_tmp_h <= reg_d_in;\r
1632                 end if;\r
1633             end if;--if (reg_main_state = ST_RS_T0)\r
1634         end if;--if (pi_rst_n = '0') then\r
1635     end process;\r
1636 \r
1637     --stack pointer...\r
1638     sp_p : process (pi_rst_n, pi_base_clk)\r
1639     begin\r
1640         if (pi_rst_n = '0') then\r
1641             reg_sp <= (others => '0');\r
1642         elsif (rising_edge(pi_base_clk)) then\r
1643             if (reg_main_state = ST_A1_T1) then\r
1644                 --txs inst.\r
1645                 if (reg_inst = conv_std_logic_vector(16#9a#, 8)) then\r
1646                     reg_sp <= reg_idl_l;\r
1647                 end if;\r
1648             elsif (reg_main_state = ST_A51_T2 or\r
1649                 reg_main_state = ST_A53_T3 or\r
1650                 reg_main_state = ST_A53_T4) then\r
1651                 --push, jsr.\r
1652                 if (reg_sub_state = ST_SUB70) then\r
1653                     reg_sp <= reg_sp - 1;\r
1654                 end if;\r
1655             elsif (reg_main_state = ST_A52_T2 or\r
1656                 reg_main_state = ST_A57_T2 or\r
1657                 reg_main_state = ST_A57_T3 or\r
1658                 reg_main_state = ST_A57_T4) then\r
1659                 --pull, rts.\r
1660                 if (reg_sub_state = ST_SUB70) then\r
1661                     reg_sp <= reg_sp + 1;\r
1662                 end if;\r
1663             end if;--if (reg_main_state = ST_RS_T0)\r
1664         end if;--if (pi_rst_n = '0') then\r
1665     end process;\r
1666 \r
1667     --calcuration process...\r
1668     --update acc, x, y, status registers.\r
1669     calc_p : process (pi_rst_n, pi_base_clk)\r
1670 \r
1671     variable calc_res : std_logic_vector (8 downto 0);\r
1672 procedure update_status (\r
1673     d       : in std_logic_vector(7 downto 0);\r
1674     set_n   : in integer range 0 to 1;\r
1675     set_z   : in integer range 0 to 1;\r
1676     set_c   : in integer range 0 to 1\r
1677 ) is\r
1678 begin\r
1679     if (set_n = 1) then\r
1680         if (d(7) = '1') then\r
1681             reg_status(FL_N) <= '1';\r
1682         else\r
1683             reg_status(FL_N) <= '0';\r
1684         end if;\r
1685     end if;\r
1686     if (set_z = 1) then\r
1687         if (d = "00000000") then\r
1688             reg_status(FL_Z) <= '1';\r
1689         else\r
1690             reg_status(FL_Z) <= '0';\r
1691         end if;\r
1692     end if;\r
1693     if (set_c = 1) then\r
1694         reg_status(FL_C) <= reg_tmp_carry;\r
1695     end if;\r
1696 end;\r
1697 \r
1698 procedure set_condition_result (\r
1699     flg   : in integer range 0 to 7;\r
1700     chk_val : in std_logic\r
1701 ) is\r
1702 begin\r
1703     if (reg_status(flg) = chk_val) then\r
1704         reg_tmp_condition <= '1';\r
1705     else\r
1706         reg_tmp_condition <= '0';\r
1707     end if;\r
1708 end;\r
1709 \r
1710     begin\r
1711         --Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc.\r
1712         if (pi_rst_n = '0') then\r
1713             reg_acc <= (others => '0');\r
1714             reg_x <= (others => '0');\r
1715             reg_y <= (others => '0');\r
1716             reg_status <= (others => '0');\r
1717             reg_tmp_carry <= '0';\r
1718             reg_tmp_ovf <= '0';\r
1719             reg_tmp_condition <= '0';\r
1720         elsif (rising_edge(pi_base_clk)) then\r
1721             --not used status pin initialize (to avoid latches).\r
1722             reg_status(5 downto 3) <= "000";\r
1723 \r
1724             --a1 instructions...\r
1725             --asl   dex     nop     tax     tya\r
1726             --clc   dey     rol     tay\r
1727             --cld   inx     sec     tsx\r
1728             --cli   iny     sed     txa\r
1729             --clv   lsr     sei     txs\r
1730             if (reg_main_state = ST_CM_T0) then\r
1731                 --init flag regs..\r
1732                 reg_tmp_carry <= '0';\r
1733                 reg_tmp_ovf <= '0';\r
1734                 reg_tmp_condition <= '0';\r
1735             elsif (reg_main_state = ST_A1_T1) then\r
1736                 --update reg\r
1737                 if (reg_sub_state = ST_SUB30) then\r
1738                     --case cc=10\r
1739                     if (reg_inst(1 downto 0) = "10") then\r
1740                         if (reg_inst(7 downto 5) = "000") then\r
1741                             --asl\r
1742                             reg_acc <= reg_acc(6 downto 0) & "0";\r
1743                             reg_tmp_carry <= reg_acc(7);\r
1744                         elsif (reg_inst(7 downto 5) = "001") then\r
1745                             --rol\r
1746                             reg_acc <= reg_acc(6 downto 0) & reg_status(FL_C);\r
1747                             reg_tmp_carry <= reg_acc(7);\r
1748                         elsif (reg_inst(7 downto 5) = "010") then\r
1749                             --lsr\r
1750                             reg_acc <= "0" & reg_acc(7 downto 1);\r
1751                             reg_tmp_carry <= reg_acc(0);\r
1752                         elsif (reg_inst(7 downto 5) = "011") then\r
1753                             --ror\r
1754                             reg_acc <= reg_status(FL_C) & reg_acc(7 downto 1);\r
1755                             reg_tmp_carry <= reg_acc(0);\r
1756                         elsif (reg_inst(7 downto 5) = "110") then\r
1757                             --dec\r
1758                             reg_acc <= reg_acc - 1;\r
1759                         elsif (reg_inst(7 downto 5) = "111") then\r
1760                             --inc\r
1761                             reg_acc <= reg_acc + 1;\r
1762                         end if;\r
1763                     elsif (reg_inst = conv_std_logic_vector(16#88#, 8)) then\r
1764                         --dey\r
1765                         reg_y <= reg_y - 1;\r
1766                     elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then\r
1767                         --tay\r
1768                         reg_y <= reg_acc;\r
1769                     elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then\r
1770                         --iny\r
1771                         reg_y <= reg_y + 1;\r
1772                     elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then\r
1773                         --inx\r
1774                         reg_x <= reg_x + 1;\r
1775                     elsif (reg_inst = conv_std_logic_vector(16#18#, 8)) then\r
1776                         --clc\r
1777                         reg_status(FL_C) <= '0';\r
1778                     elsif (reg_inst = conv_std_logic_vector(16#38#, 8)) then\r
1779                         --sec\r
1780                         reg_status(FL_C) <= '1';\r
1781                     elsif (reg_inst = conv_std_logic_vector(16#58#, 8)) then\r
1782                         --cli\r
1783                         reg_status(FL_I) <= '0';\r
1784                     elsif (reg_inst = conv_std_logic_vector(16#78#, 8)) then\r
1785                         --sei\r
1786                         reg_status(FL_I) <= '1';\r
1787                     elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then\r
1788                         --tya\r
1789                         reg_acc <= reg_y;\r
1790                     elsif (reg_inst = conv_std_logic_vector(16#b8#, 8)) then\r
1791                         --clv\r
1792                         reg_status(FL_V) <= '0';\r
1793                     elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then\r
1794                         --txa\r
1795                         reg_acc <= reg_y;\r
1796                     elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then\r
1797                         --tax\r
1798                         reg_x <= reg_acc;\r
1799                     elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then\r
1800                         --tsx\r
1801                         reg_x <= reg_sp;\r
1802                     elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then\r
1803                         --dex\r
1804                         reg_x <= reg_x - 1;\r
1805                     elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then\r
1806                         --nop\r
1807                         --do nothing...\r
1808                     end if;\r
1809 \r
1810                 --update status reg\r
1811                 elsif (reg_sub_state = ST_SUB31) then\r
1812                     --case cc=10\r
1813                     if (reg_inst(1 downto 0) = "10") then\r
1814                         if (reg_inst(7 downto 5) = "000") then\r
1815                             --asl\r
1816                             update_status(reg_acc, 1, 1, 1);\r
1817                         elsif (reg_inst(7 downto 5) = "001") then\r
1818                             --rol\r
1819                             update_status(reg_acc, 1, 1, 1);\r
1820                         elsif (reg_inst(7 downto 5) = "010") then\r
1821                             --lsr\r
1822                             update_status(reg_acc, 0, 1, 1);\r
1823                         elsif (reg_inst(7 downto 5) = "011") then\r
1824                             --ror\r
1825                             update_status(reg_acc, 1, 1, 1);\r
1826                         elsif (reg_inst(7 downto 5) = "110") then\r
1827                             --dec\r
1828                             update_status(reg_acc, 1, 1, 0);\r
1829                         elsif (reg_inst(7 downto 5) = "111") then\r
1830                             --inc\r
1831                             update_status(reg_acc, 1, 1, 0);\r
1832                         end if;\r
1833                     elsif (reg_inst = conv_std_logic_vector(16#88#, 8)) then\r
1834                         --dey\r
1835                         update_status(reg_y, 1, 1, 0);\r
1836                     elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then\r
1837                         --tay\r
1838                         update_status(reg_y, 1, 1, 0);\r
1839                     elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then\r
1840                         --iny\r
1841                         update_status(reg_y, 1, 1, 0);\r
1842                     elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then\r
1843                         --inx\r
1844                         update_status(reg_x, 1, 1, 0);\r
1845                     elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then\r
1846                         --tya\r
1847                         update_status(reg_acc, 1, 1, 0);\r
1848                     elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then\r
1849                         --txa\r
1850                         update_status(reg_acc, 1, 1, 0);\r
1851                     elsif (reg_inst = conv_std_logic_vector(16#9a#, 8)) then\r
1852                         --txs\r
1853                         update_status(reg_sp, 1, 1, 0);\r
1854                     elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then\r
1855                         --tax\r
1856                         update_status(reg_x, 1, 1, 0);\r
1857                     elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then\r
1858                         --tsx\r
1859                         update_status(reg_x, 1, 1, 0);\r
1860                     elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then\r
1861                         --dex\r
1862                         update_status(reg_x, 1, 1, 0);\r
1863                     elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then\r
1864                         --nop\r
1865                         --do nothing...\r
1866                     end if;\r
1867                 end if;--if (reg_sub_state = ST_SUB30) then\r
1868 \r
1869             --a2 instructions...\r
1870             --adc   cmp     eor     ldy\r
1871             --and   cpx     lda     ora\r
1872             --bit   cpy     ldx     sbc\r
1873             elsif (reg_main_state = ST_A21_T1 or\r
1874                 reg_main_state = ST_A22_T2 or\r
1875                 reg_main_state = ST_A23_T3 or\r
1876                 reg_main_state = ST_A24_T5 or\r
1877                 reg_main_state = ST_A25_T4 or\r
1878                 reg_main_state = ST_A25_T3 or\r
1879                 reg_main_state = ST_A26_T3 or\r
1880                 reg_main_state = ST_A27_T5) then\r
1881                 \r
1882                 --update reg\r
1883                 if (reg_sub_state = ST_SUB30) then\r
1884                     --case cc=01\r
1885                     if (reg_inst(1 downto 0) = "01") then\r
1886                         if (reg_inst(7 downto 5) = "000") then\r
1887                             --ora\r
1888                             reg_acc <= (reg_acc or reg_d_in);\r
1889                         elsif (reg_inst(7 downto 5) = "001") then\r
1890                             --and\r
1891                             reg_acc <= (reg_acc and reg_d_in);\r
1892                         elsif (reg_inst(7 downto 5) = "010") then\r
1893                             --eor\r
1894                             reg_acc <= (reg_acc xor reg_d_in);\r
1895                         elsif (reg_inst(7 downto 5) = "011") then\r
1896                             --adc\r
1897                             calc_res := ("0" & reg_acc) + ("0" & reg_d_in) + reg_status(FL_C);\r
1898                             reg_tmp_carry <= calc_res(8);\r
1899                             if ((reg_acc(7) = reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then\r
1900                                 reg_tmp_ovf <= '1';\r
1901                             else\r
1902                                 reg_tmp_ovf <= '0';\r
1903                             end if;\r
1904                             reg_acc <= calc_res(7 downto 0);\r
1905                         elsif (reg_inst(7 downto 5) = "101") then\r
1906                             --lda\r
1907                             reg_acc <= reg_d_in;\r
1908                         elsif (reg_inst(7 downto 5) = "110") then\r
1909                             --cmp\r
1910                             --do nothing.\r
1911                         elsif (reg_inst(7 downto 5) = "111") then\r
1912                             --sbc\r
1913                             ---A - M - ~C -> A\r
1914                             calc_res := ("0" & reg_acc) - ("0" & reg_d_in) - not reg_status(FL_C);\r
1915 \r
1916                             --c Set if unsigned borrow not required; cleared if unsigned borrow.\r
1917                             reg_tmp_carry <= not calc_res(7);\r
1918                             --v Set if signed borrow required; cleared if no signed borrow.\r
1919                             if ((reg_acc(7) /= reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then\r
1920                                 reg_tmp_ovf <= '1';\r
1921                             else\r
1922                                 reg_tmp_ovf <= '0';\r
1923                             end if;\r
1924                             reg_acc <= calc_res(7 downto 0);\r
1925                         end if;\r
1926                     --case cc=10\r
1927                     elsif (reg_inst(1 downto 0) = "10") then\r
1928                         if (reg_inst(7 downto 5) = "101") then\r
1929                             --ldx\r
1930                             reg_x <= reg_d_in;\r
1931                         end if;\r
1932                     --case cc=00\r
1933                     elsif (reg_inst(1 downto 0) = "00") then\r
1934                         if (reg_inst(7 downto 5) = "001") then\r
1935                             --bit\r
1936                             --do nothing.\r
1937                         elsif (reg_inst(7 downto 5) = "101") then\r
1938                             --ldy\r
1939                             reg_y <= reg_d_in;\r
1940                         elsif (reg_inst(7 downto 5) = "110") then\r
1941                             --cpy\r
1942                             --do nothing.\r
1943                         elsif (reg_inst(7 downto 5) = "111") then\r
1944                             --cpx\r
1945                             --do nothing.\r
1946                         end if;\r
1947                     end if;\r
1948 \r
1949                 --update status reg\r
1950                 elsif (reg_sub_state = ST_SUB31) then\r
1951                     --case cc=01\r
1952                     if (reg_inst(1 downto 0) = "01") then\r
1953                         if (reg_inst(7 downto 5) = "000") then\r
1954                             --ora\r
1955                             update_status(reg_x, 1, 1, 0);\r
1956                         elsif (reg_inst(7 downto 5) = "001") then\r
1957                             --and\r
1958                             update_status(reg_x, 1, 1, 0);\r
1959                         elsif (reg_inst(7 downto 5) = "010") then\r
1960                             --eor\r
1961                             update_status(reg_x, 1, 1, 0);\r
1962                         elsif (reg_inst(7 downto 5) = "011") then\r
1963                             --adc\r
1964                             update_status(reg_x, 1, 1, 1);\r
1965                             reg_status(FL_V) <= reg_tmp_ovf;\r
1966                         elsif (reg_inst(7 downto 5) = "101") then\r
1967                             --lda\r
1968                             update_status(reg_x, 1, 1, 0);\r
1969                         elsif (reg_inst(7 downto 5) = "110") then\r
1970                             --cmp\r
1971                             calc_res := (("0" & reg_acc) - ("0" & reg_d_in));\r
1972                             if (reg_acc >= reg_d_in) then\r
1973                                 reg_status(FL_C) <= '1';\r
1974                             else\r
1975                                 reg_status(FL_C) <= '0';\r
1976                             end if;\r
1977                             if (calc_res(7) = '1') then\r
1978                                 reg_status(FL_N) <= '1';\r
1979                             else\r
1980                                 reg_status(FL_N) <= '0';\r
1981                             end if;\r
1982                             if (calc_res = "000000000") then\r
1983                                 reg_status(FL_Z) <= '1';\r
1984                             else\r
1985                                 reg_status(FL_Z) <= '0';\r
1986                             end if;\r
1987                         elsif (reg_inst(7 downto 5) = "111") then\r
1988                             --sbc\r
1989                             update_status(reg_x, 1, 1, 1);\r
1990                             reg_status(FL_V) <= reg_tmp_ovf;\r
1991                         end if;\r
1992                     --case cc=10\r
1993                     elsif (reg_inst(1 downto 0) = "10") then\r
1994                         if (reg_inst(7 downto 5) = "101") then\r
1995                             --ldx\r
1996                             update_status(reg_x, 1, 1, 0);\r
1997                         end if;\r
1998                     --case cc=00\r
1999                     elsif (reg_inst(1 downto 0) = "00") then\r
2000                         if (reg_inst(7 downto 5) = "001") then\r
2001                             --bit\r
2002                             calc_res(7 downto 0) := (reg_acc and reg_d_in);\r
2003                             reg_status(FL_N) <= reg_d_in(7);\r
2004                             reg_status(FL_V) <= reg_d_in(6);\r
2005                             if (calc_res(7 downto 0) = "00000000") then\r
2006                                 reg_status(FL_Z) <= '1';\r
2007                             else\r
2008                                 reg_status(FL_Z) <= '0';\r
2009                             end if;\r
2010                         elsif (reg_inst(7 downto 5) = "101") then\r
2011                             --ldy\r
2012                             update_status(reg_x, 1, 1, 0);\r
2013                         elsif (reg_inst(7 downto 5) = "110") then\r
2014                             --cpy\r
2015                             calc_res := (("0" & reg_y) - ("0" & reg_d_in));\r
2016                             if (reg_y >= reg_d_in) then\r
2017                                 reg_status(FL_C) <= '1';\r
2018                             else\r
2019                                 reg_status(FL_C) <= '0';\r
2020                             end if;\r
2021                             if (calc_res(7) = '1') then\r
2022                                 reg_status(FL_N) <= '1';\r
2023                             else\r
2024                                 reg_status(FL_N) <= '0';\r
2025                             end if;\r
2026                             if (calc_res = "000000000") then\r
2027                                 reg_status(FL_Z) <= '1';\r
2028                             else\r
2029                                 reg_status(FL_Z) <= '0';\r
2030                             end if;\r
2031                         elsif (reg_inst(7 downto 5) = "111") then\r
2032                             --cpx\r
2033                             calc_res := (("0" & reg_x) - ("0" & reg_d_in));\r
2034                             if (reg_x >= reg_d_in) then\r
2035                                 reg_status(FL_C) <= '1';\r
2036                             else\r
2037                                 reg_status(FL_C) <= '0';\r
2038                             end if;\r
2039                             if (calc_res(7) = '1') then\r
2040                                 reg_status(FL_N) <= '1';\r
2041                             else\r
2042                                 reg_status(FL_N) <= '0';\r
2043                             end if;\r
2044                             if (calc_res = "000000000") then\r
2045                                 reg_status(FL_Z) <= '1';\r
2046                             else\r
2047                                 reg_status(FL_Z) <= '0';\r
2048                             end if;\r
2049                         end if;\r
2050                     end if;\r
2051                 end if;--if (reg_sub_state = ST_SUB30) then\r
2052 \r
2053            --a4 instructions.\r
2054            --asl    lsr\r
2055            --dec    rol\r
2056            --inc    ror\r
2057             elsif (reg_main_state = ST_A41_T2 or\r
2058                 reg_main_state = ST_A42_T3 or\r
2059                 reg_main_state = ST_A43_T3 or\r
2060                 reg_main_state = ST_A44_T4\r
2061                 ) then\r
2062                 --data fetch cycle.\r
2063                 reg_tmp_data <= reg_d_in;\r
2064 \r
2065             elsif (reg_main_state = ST_A41_T4 or\r
2066                 reg_main_state = ST_A42_T5 or\r
2067                 reg_main_state = ST_A43_T5 or\r
2068                 reg_main_state = ST_A44_T6\r
2069                 ) then\r
2070                 --data modify cycle.\r
2071 \r
2072                 --update reg\r
2073                 if (reg_sub_state = ST_SUB10) then\r
2074                     --case cc=10\r
2075                     if (reg_inst(1 downto 0) = "10") then\r
2076                         if (reg_inst(7 downto 5) = "000") then\r
2077                             --asl\r
2078                             reg_tmp_data <= reg_tmp_data(6 downto 0) & "0";\r
2079                             reg_tmp_carry <= reg_tmp_data(7);\r
2080                         elsif (reg_inst(7 downto 5) = "001") then\r
2081                             --rol\r
2082                             reg_tmp_data <= reg_tmp_data(6 downto 0) & reg_status(FL_C);\r
2083                             reg_tmp_carry <= reg_tmp_data(7);\r
2084                         elsif (reg_inst(7 downto 5) = "010") then\r
2085                             --lsr\r
2086                             reg_tmp_data <= "0" & reg_tmp_data(7 downto 1);\r
2087                             reg_tmp_carry <= reg_tmp_data(0);\r
2088                         elsif (reg_inst(7 downto 5) = "011") then\r
2089                             --ror\r
2090                             reg_tmp_data <= reg_status(FL_C) & reg_tmp_data(7 downto 1);\r
2091                             reg_tmp_carry <= reg_tmp_data(0);\r
2092                         elsif (reg_inst(7 downto 5) = "110") then\r
2093                             --dec\r
2094                             reg_tmp_data <= reg_tmp_data - 1;\r
2095                         elsif (reg_inst(7 downto 5) = "111") then\r
2096                             --inc\r
2097                             reg_tmp_data <= reg_tmp_data + 1;\r
2098                         end if;\r
2099                     end if;\r
2100 \r
2101                 --update status reg\r
2102                 elsif (reg_sub_state = ST_SUB20) then\r
2103                     --case cc=10\r
2104                     if (reg_inst(1 downto 0) = "10") then\r
2105                         if (reg_inst(7 downto 5) = "000") then\r
2106                             --asl\r
2107                             update_status(reg_tmp_data, 1, 1, 1);\r
2108                         elsif (reg_inst(7 downto 5) = "001") then\r
2109                             --rol\r
2110                             update_status(reg_tmp_data, 1, 1, 1);\r
2111                         elsif (reg_inst(7 downto 5) = "010") then\r
2112                             --lsr\r
2113                             update_status(reg_tmp_data, 0, 1, 1);\r
2114                         elsif (reg_inst(7 downto 5) = "011") then\r
2115                             --ror\r
2116                             update_status(reg_tmp_data, 1, 1, 1);\r
2117                         elsif (reg_inst(7 downto 5) = "110") then\r
2118                             --dec\r
2119                             update_status(reg_tmp_data, 1, 1, 0);\r
2120                         elsif (reg_inst(7 downto 5) = "111") then\r
2121                             --inc\r
2122                             update_status(reg_tmp_data, 1, 1, 0);\r
2123                         end if;\r
2124                     end if;\r
2125                 end if;\r
2126 \r
2127             --a5 instructions...\r
2128             --plp, pla\r
2129             elsif (reg_main_state = ST_A52_T3) then\r
2130                 --update reg\r
2131                 if (reg_sub_state = ST_SUB30) then\r
2132                     if (reg_inst = conv_std_logic_vector(16#28#, 8)) then\r
2133                         --plp\r
2134                         reg_status <= reg_d_in;\r
2135                     elsif (reg_inst = conv_std_logic_vector(16#68#, 8)) then\r
2136                         --pla\r
2137                         reg_acc <= reg_d_in;\r
2138                     end if;\r
2139 \r
2140                 --update status reg\r
2141                 elsif (reg_sub_state = ST_SUB31) then\r
2142                     if (reg_inst = conv_std_logic_vector(16#68#, 8)) then\r
2143                         --pla\r
2144                         update_status(reg_acc, 1, 1, 0);\r
2145                     end if;\r
2146                 end if;--if (reg_sub_state = ST_SUB30) then\r
2147 \r
2148             --a58 branch inst.\r
2149             --bcc   bne\r
2150             --bcs   bpl\r
2151             --beq   bvc\r
2152             --bmi   bvs\r
2153             elsif (reg_main_state = ST_A58_T1) then\r
2154                 if (reg_sub_state = ST_SUB30) then\r
2155                     if (reg_inst = conv_std_logic_vector(16#90#, 8)) then\r
2156                         --bcc\r
2157                         set_condition_result(FL_C, '0');\r
2158 \r
2159                     elsif (reg_inst = conv_std_logic_vector(16#b0#, 8)) then\r
2160                         --bcs\r
2161                         set_condition_result(FL_C, '1');\r
2162 \r
2163                     elsif (reg_inst = conv_std_logic_vector(16#f0#, 8)) then\r
2164                         --beq\r
2165                         set_condition_result(FL_Z, '1');\r
2166 \r
2167                     elsif (reg_inst = conv_std_logic_vector(16#30#, 8)) then\r
2168                         --bmi\r
2169                         set_condition_result(FL_N, '1');\r
2170 \r
2171                     elsif (reg_inst = conv_std_logic_vector(16#d0#, 8)) then\r
2172                         --bne\r
2173                         set_condition_result(FL_Z, '0');\r
2174 \r
2175                     elsif (reg_inst = conv_std_logic_vector(16#10#, 8)) then\r
2176                         --bpl\r
2177                         set_condition_result(FL_N, '0');\r
2178 \r
2179                     elsif (reg_inst = conv_std_logic_vector(16#50#, 8)) then\r
2180                         --bvc\r
2181                         set_condition_result(FL_V, '0');\r
2182 \r
2183                     elsif (reg_inst = conv_std_logic_vector(16#70#, 8)) then\r
2184                         --bvs\r
2185                         set_condition_result(FL_V, '1');\r
2186                     end if;\r
2187                 end if;\r
2188             end if;--if (reg_main_state = ST_A21_T1 or...\r
2189         end if;--if (pi_rst_n = '0') then\r
2190     end process;\r
2191 \r
2192 end rtl;\r
2193 \r