2 use ieee.std_logic_1164.all;
\r
3 use ieee.std_logic_unsigned.all;
\r
4 use ieee.std_logic_arith.conv_std_logic_vector;
\r
8 pi_rst_n : in std_logic;
\r
9 pi_base_clk : in std_logic;
\r
10 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
11 pi_rdy : in std_logic;
\r
12 pi_irq_n : in std_logic;
\r
13 pi_nmi_n : in std_logic;
\r
14 po_r_nw : out std_logic;
\r
15 po_addr : out std_logic_vector ( 15 downto 0);
\r
16 pio_d_io : inout std_logic_vector ( 7 downto 0)
\r
20 architecture rtl of mos6502 is
\r
23 type cpu_main_state is (
\r
24 --common state. idle and inst fetch.
\r
28 --single byte inst execute.
\r
31 --mem data operation
\r
35 ST_A22_T1, ST_A22_T2,
\r
37 ST_A23_T1, ST_A23_T2, ST_A23_T3,
\r
39 ST_A24_T1, ST_A24_T2, ST_A24_T3, ST_A24_T4, ST_A24_T5,
\r
41 ST_A25_T1, ST_A25_T2, ST_A25_T3, ST_A25_T4,
\r
43 ST_A26_T1, ST_A26_T2, ST_A26_T3,
\r
45 ST_A27_T1, ST_A27_T2, ST_A27_T3, ST_A27_T4, ST_A27_T5,
\r
49 ST_A31_T1, ST_A31_T2,
\r
51 ST_A32_T1, ST_A32_T2, ST_A32_T3,
\r
53 ST_A33_T1, ST_A33_T2, ST_A33_T3, ST_A33_T4, ST_A33_T5,
\r
55 ST_A34_T1, ST_A34_T2, ST_A34_T3, ST_A34_T4,
\r
57 ST_A35_T1, ST_A35_T2, ST_A35_T3,
\r
59 ST_A36_T1, ST_A36_T2, ST_A36_T3, ST_A36_T4, ST_A36_T5,
\r
61 --memory to memory op.
\r
63 ST_A41_T1, ST_A41_T2, ST_A41_T3, ST_A41_T4,
\r
65 ST_A42_T1, ST_A42_T2, ST_A42_T3, ST_A42_T4, ST_A42_T5,
\r
67 ST_A43_T1, ST_A43_T2, ST_A43_T3, ST_A43_T4, ST_A43_T5,
\r
69 ST_A44_T1, ST_A44_T2, ST_A44_T3, ST_A44_T4, ST_A44_T5, ST_A44_T6,
\r
73 ST_A51_T1, ST_A51_T2,
\r
75 ST_A52_T1, ST_A52_T2, ST_A52_T3,
\r
77 ST_A53_T1, ST_A53_T2, ST_A53_T3,ST_A53_T4, ST_A53_T5,
\r
79 ST_A55_T1, ST_A55_T2, ST_A55_T3, ST_A55_T4, ST_A55_T5,
\r
81 ST_A561_T1, ST_A561_T2,
\r
83 ST_A562_T1, ST_A562_T2, ST_A562_T3, ST_A562_T4,
\r
85 ST_A57_T1, ST_A57_T2, ST_A57_T3, ST_A57_T4, ST_A57_T5,
\r
87 ST_A58_T1, ST_A58_T2, ST_A58_T3,
\r
90 ST_RS_T0, ST_RS_T1, ST_RS_T2, ST_RS_T3, ST_RS_T4, ST_RS_T5, ST_RS_T6, ST_RS_T7,
\r
97 --1 cpu clock is split into 8 state.
\r
98 --1 cpu clock = 32 x base clock.
\r
99 type cpu_sub_state is (
\r
100 ST_SUB00, ST_SUB01, ST_SUB02, ST_SUB03,
\r
101 ST_SUB10, ST_SUB11, ST_SUB12, ST_SUB13,
\r
102 ST_SUB20, ST_SUB21, ST_SUB22, ST_SUB23,
\r
103 ST_SUB30, ST_SUB31, ST_SUB32, ST_SUB33,
\r
104 ST_SUB40, ST_SUB41, ST_SUB42, ST_SUB43,
\r
105 ST_SUB50, ST_SUB51, ST_SUB52, ST_SUB53,
\r
106 ST_SUB60, ST_SUB61, ST_SUB62, ST_SUB63,
\r
107 ST_SUB70, ST_SUB71, ST_SUB72, ST_SUB73
\r
110 type cpu_state_array is array (0 to 255) of cpu_main_state;
\r
111 constant inst_decode_rom : cpu_state_array := (
\r
112 --00 01 02 03 04 05 06 07
\r
113 ST_INV, ST_A24_T1, ST_INV, ST_INV, ST_INV, ST_A22_T1, ST_A41_T1, ST_INV,
\r
114 --08 09 0a 0b 0c 0d 0e 0f
\r
115 ST_A51_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_INV, ST_A23_T1, ST_A42_T1, ST_INV,
\r
116 --10 11 12 13 14 15 16 17
\r
117 ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_INV, ST_A26_T1, ST_A43_T1, ST_INV,
\r
118 --18 19 1a 1b 1c 1d 1e 1f
\r
119 ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,
\r
120 --20 21 22 23 24 25 26 27
\r
121 ST_A53_T1, ST_A24_T1, ST_INV, ST_INV, ST_A22_T1, ST_A22_T1, ST_A41_T1, ST_INV,
\r
122 --28 29 2a 2b 2c 2d 2e 2f
\r
123 ST_A52_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A23_T1, ST_A23_T1, ST_A42_T1, ST_INV,
\r
124 --30 31 32 33 34 35 36 37
\r
125 ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_A26_T1, ST_A43_T1, ST_INV,
\r
126 --38 39 3a 3b 3c 3d 3e 3f
\r
127 ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,
\r
128 --40 41 42 43 44 45 46 47
\r
129 ST_A55_T1, ST_A24_T1, ST_INV, ST_INV, ST_INV, ST_A22_T1, ST_A41_T1, ST_INV,
\r
130 --48 49 4a 4b 4c 4d 4e 4f
\r
131 ST_A51_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A561_T1, ST_A23_T1, ST_A42_T1, ST_INV,
\r
132 --50 51 52 53 54 55 56 57
\r
133 ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_INV, ST_A43_T1, ST_INV,
\r
134 --58 59 5a 5b 5c 5d 5e 5f
\r
135 ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,
\r
136 --60 61 62 63 64 65 66 67
\r
137 ST_A57_T1, ST_A24_T1, ST_INV, ST_INV, ST_INV, ST_A22_T1, ST_A41_T1, ST_INV,
\r
138 --68 69 6a 6b 6c 6d 6e 6f
\r
139 ST_A52_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A562_T1, ST_A23_T1, ST_A42_T1, ST_INV,
\r
140 --70 71 72 73 74 75 76 77
\r
141 ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_INV, ST_A43_T1, ST_INV,
\r
142 --78 79 7a 7b 7c 7d 7e 7f
\r
143 ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,
\r
144 --80 81 82 83 84 85 86 87
\r
145 ST_INV, ST_A33_T1, ST_INV, ST_INV, ST_A31_T1, ST_A31_T1, ST_A31_T1, ST_INV,
\r
146 --88 89 8a 8b 8c 8d 8e 8f
\r
147 ST_A1_T1, ST_INV, ST_A1_T1, ST_INV, ST_A32_T1, ST_A32_T1, ST_A32_T1, ST_INV,
\r
148 --90 91 92 93 94 95 96 97
\r
149 ST_A58_T1, ST_A36_T1, ST_INV, ST_INV, ST_A35_T1, ST_A35_T1, ST_A35_T1, ST_INV,
\r
150 --98 99 9a 9b 9c 9d 9e 9f
\r
151 ST_A1_T1, ST_A34_T1, ST_A1_T1, ST_INV, ST_INV, ST_A34_T1, ST_INV, ST_INV,
\r
152 --a0 a1 a2 a3 a4 a5 a6 a7
\r
153 ST_A21_T1, ST_A24_T1, ST_A21_T1, ST_INV, ST_A22_T1, ST_A22_T1, ST_A22_T1, ST_INV,
\r
154 --a8 a9 aa ab ac ad ae af
\r
155 ST_A1_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A23_T1, ST_A23_T1, ST_A23_T1, ST_INV,
\r
156 --b0 b1 b2 b3 b4 b5 b6 b7
\r
157 ST_A58_T1, ST_A27_T1, ST_INV, ST_A26_T1, ST_A26_T1, ST_A26_T1, ST_INV, ST_INV,
\r
158 --b8 b9 ba bb bc bd be bf
\r
159 ST_A1_T1, ST_A25_T1, ST_A1_T1, ST_INV, ST_A25_T1, ST_A25_T1, ST_A25_T1, ST_INV,
\r
160 --c0 c1 c2 c3 c4 c5 c6 c7
\r
161 ST_A21_T1, ST_A24_T1, ST_INV, ST_INV, ST_INV, ST_A22_T1, ST_A41_T1, ST_INV,
\r
162 --c8 c9 ca cb cc cd ce cf
\r
163 ST_A1_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A23_T1, ST_A23_T1, ST_A42_T1, ST_INV,
\r
164 --d0 d1 d2 d3 d4 d5 d6 d7
\r
165 ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_A26_T1, ST_INV, ST_A43_T1, ST_INV,
\r
166 --d8 d9 da db dc dd de df
\r
167 ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV,
\r
168 --e0 e1 e2 e3 e4 e5 e6 e7
\r
169 ST_A21_T1, ST_A24_T1, ST_INV, ST_INV, ST_A22_T1, ST_A22_T1, ST_A41_T1, ST_INV,
\r
170 --e8 e9 ea eb ec ed ee ef
\r
171 ST_A1_T1, ST_A21_T1, ST_A1_T1, ST_INV, ST_A23_T1, ST_A23_T1, ST_A42_T1, ST_INV,
\r
172 --f0 f1 f2 f3 f4 f5 f6 f7
\r
173 ST_A58_T1, ST_A27_T1, ST_INV, ST_INV, ST_INV, ST_A26_T1, ST_A43_T1, ST_INV,
\r
174 --f8 f9 fa fb fc fd fe ff
\r
175 ST_A1_T1, ST_A25_T1, ST_INV, ST_INV, ST_INV, ST_A25_T1, ST_A44_T1, ST_INV
\r
178 -- Flags (bit 7 to bit 0):
\r
181 -- - .... ignored -- always 1 for NES 6502
\r
183 -- D .... Decimal (use BCD for arithmetics) -- not supported. always 0.
\r
184 -- I .... Interrupt (IRQ disable)
\r
187 constant FL_N : integer := 7;
\r
188 constant FL_V : integer := 6;
\r
189 constant FL_I : integer := 2;
\r
190 constant FL_Z : integer := 1;
\r
191 constant FL_C : integer := 0;
\r
193 signal reg_main_state : cpu_main_state;
\r
194 signal reg_main_next_state : cpu_main_state;
\r
195 signal reg_sub_state : cpu_sub_state;
\r
196 signal reg_sub_next_state : cpu_sub_state;
\r
198 --6502 register definition...
\r
199 signal reg_inst : std_logic_vector (7 downto 0);
\r
200 signal reg_acc : std_logic_vector (7 downto 0);
\r
201 signal reg_x : std_logic_vector (7 downto 0);
\r
202 signal reg_y : std_logic_vector (7 downto 0);
\r
203 signal reg_idl_l : std_logic_vector (7 downto 0);
\r
204 signal reg_idl_h : std_logic_vector (7 downto 0);
\r
205 signal reg_sp : std_logic_vector (7 downto 0);
\r
206 signal reg_status : std_logic_vector (7 downto 0);
\r
207 signal reg_pc_l : std_logic_vector (7 downto 0);
\r
208 signal reg_pc_h : std_logic_vector (7 downto 0);
\r
211 signal reg_tmp_carry : std_logic;
\r
212 signal reg_tmp_ovf : std_logic;
\r
213 signal reg_tmp_condition : std_logic;
\r
214 signal reg_tmp_pg_crossed : std_logic;
\r
217 signal reg_tmp_l : std_logic_vector (7 downto 0);
\r
218 signal reg_tmp_h : std_logic_vector (7 downto 0);
\r
221 signal reg_tmp_data : std_logic_vector (7 downto 0);
\r
224 signal reg_r_nw : std_logic;
\r
225 signal reg_addr : std_logic_vector (15 downto 0);
\r
226 signal reg_d_in : std_logic_vector (7 downto 0);
\r
227 signal reg_d_out : std_logic_vector (7 downto 0);
\r
231 --state transition process...
\r
232 set_stat_p : process (pi_rst_n, pi_base_clk)
\r
234 if (pi_rst_n = '0') then
\r
235 reg_main_state <= ST_IDLE;
\r
236 reg_sub_state <= ST_SUB00;
\r
237 elsif (rising_edge(pi_base_clk)) then
\r
238 reg_main_state <= reg_main_next_state;
\r
239 reg_sub_state <= reg_sub_next_state;
\r
240 end if;--if (pi_rst_n = '0') then
\r
243 --fixed length sub status change (0 - 31 because cpu clock is 1/32 of base clock).
\r
244 tx_next_sub_stat_p : process (reg_sub_state, pi_cpu_en)
\r
246 case reg_sub_state is
\r
248 if (pi_cpu_en(0) = '1') then
\r
249 reg_sub_next_state <= ST_SUB01;
\r
251 reg_sub_next_state <= reg_sub_state;
\r
254 reg_sub_next_state <= ST_SUB02;
\r
256 reg_sub_next_state <= ST_SUB03;
\r
258 reg_sub_next_state <= ST_SUB10;
\r
260 reg_sub_next_state <= ST_SUB11;
\r
262 reg_sub_next_state <= ST_SUB12;
\r
264 reg_sub_next_state <= ST_SUB13;
\r
266 reg_sub_next_state <= ST_SUB20;
\r
268 reg_sub_next_state <= ST_SUB21;
\r
270 reg_sub_next_state <= ST_SUB22;
\r
272 reg_sub_next_state <= ST_SUB23;
\r
274 reg_sub_next_state <= ST_SUB30;
\r
276 reg_sub_next_state <= ST_SUB31;
\r
278 reg_sub_next_state <= ST_SUB32;
\r
280 reg_sub_next_state <= ST_SUB33;
\r
282 reg_sub_next_state <= ST_SUB40;
\r
284 reg_sub_next_state <= ST_SUB41;
\r
286 reg_sub_next_state <= ST_SUB42;
\r
288 reg_sub_next_state <= ST_SUB43;
\r
290 reg_sub_next_state <= ST_SUB50;
\r
292 reg_sub_next_state <= ST_SUB51;
\r
294 reg_sub_next_state <= ST_SUB52;
\r
296 reg_sub_next_state <= ST_SUB53;
\r
298 reg_sub_next_state <= ST_SUB60;
\r
300 reg_sub_next_state <= ST_SUB61;
\r
302 reg_sub_next_state <= ST_SUB62;
\r
304 reg_sub_next_state <= ST_SUB63;
\r
306 reg_sub_next_state <= ST_SUB70;
\r
308 reg_sub_next_state <= ST_SUB71;
\r
310 reg_sub_next_state <= ST_SUB72;
\r
312 reg_sub_next_state <= ST_SUB73;
\r
314 reg_sub_next_state <= ST_SUB00;
\r
318 --state change to next.
\r
319 tx_next_main_stat_p : process (pi_rst_n, reg_main_state, reg_sub_state,
\r
320 reg_inst, reg_tmp_condition, reg_tmp_pg_crossed)
\r
323 case reg_main_state is
\r
326 if (pi_rst_n = '0') then
\r
327 reg_main_next_state <= reg_main_state;
\r
329 reg_main_next_state <= ST_RS_T0;
\r
333 if (reg_sub_state = ST_SUB73) then
\r
334 reg_main_next_state <= ST_RS_T1;
\r
336 reg_main_next_state <= reg_main_state;
\r
339 if (reg_sub_state = ST_SUB73) then
\r
340 reg_main_next_state <= ST_RS_T2;
\r
342 reg_main_next_state <= reg_main_state;
\r
345 if (reg_sub_state = ST_SUB73) then
\r
346 reg_main_next_state <= ST_RS_T3;
\r
348 reg_main_next_state <= reg_main_state;
\r
351 if (reg_sub_state = ST_SUB73) then
\r
352 reg_main_next_state <= ST_RS_T4;
\r
354 reg_main_next_state <= reg_main_state;
\r
357 if (reg_sub_state = ST_SUB73) then
\r
358 reg_main_next_state <= ST_RS_T5;
\r
360 reg_main_next_state <= reg_main_state;
\r
363 if (reg_sub_state = ST_SUB73) then
\r
364 reg_main_next_state <= ST_RS_T6;
\r
366 reg_main_next_state <= reg_main_state;
\r
369 if (reg_sub_state = ST_SUB73) then
\r
370 reg_main_next_state <= ST_RS_T7;
\r
372 reg_main_next_state <= reg_main_state;
\r
375 if (reg_sub_state = ST_SUB73) then
\r
376 reg_main_next_state <= ST_CM_T0;
\r
378 reg_main_next_state <= reg_main_state;
\r
381 --instruction fetch
\r
383 if (reg_sub_state = ST_SUB73) then
\r
384 ---instruction decode next state.
\r
385 reg_main_next_state <= inst_decode_rom(conv_integer(reg_inst));
\r
387 reg_main_next_state <= reg_main_state;
\r
390 --A1 inst.(single byte)
\r
392 if (reg_sub_state = ST_SUB73) then
\r
393 reg_main_next_state <= ST_CM_T0;
\r
395 reg_main_next_state <= reg_main_state;
\r
400 if (reg_sub_state = ST_SUB73) then
\r
401 reg_main_next_state <= ST_CM_T0;
\r
403 reg_main_next_state <= reg_main_state;
\r
406 if (reg_sub_state = ST_SUB73) then
\r
407 reg_main_next_state <= ST_A22_T2;
\r
409 reg_main_next_state <= reg_main_state;
\r
412 if (reg_sub_state = ST_SUB73) then
\r
413 reg_main_next_state <= ST_CM_T0;
\r
415 reg_main_next_state <= reg_main_state;
\r
418 if (reg_sub_state = ST_SUB73) then
\r
419 reg_main_next_state <= ST_A23_T2;
\r
421 reg_main_next_state <= reg_main_state;
\r
424 if (reg_sub_state = ST_SUB73) then
\r
425 reg_main_next_state <= ST_A23_T3;
\r
427 reg_main_next_state <= reg_main_state;
\r
430 if (reg_sub_state = ST_SUB73) then
\r
431 reg_main_next_state <= ST_CM_T0;
\r
433 reg_main_next_state <= reg_main_state;
\r
436 if (reg_sub_state = ST_SUB73) then
\r
437 reg_main_next_state <= ST_A24_T2;
\r
439 reg_main_next_state <= reg_main_state;
\r
442 if (reg_sub_state = ST_SUB73) then
\r
443 reg_main_next_state <= ST_A24_T3;
\r
445 reg_main_next_state <= reg_main_state;
\r
448 if (reg_sub_state = ST_SUB73) then
\r
449 reg_main_next_state <= ST_A24_T4;
\r
451 reg_main_next_state <= reg_main_state;
\r
454 if (reg_sub_state = ST_SUB73) then
\r
455 reg_main_next_state <= ST_A24_T5;
\r
457 reg_main_next_state <= reg_main_state;
\r
460 if (reg_sub_state = ST_SUB73) then
\r
461 reg_main_next_state <= ST_CM_T0;
\r
463 reg_main_next_state <= reg_main_state;
\r
466 if (reg_sub_state = ST_SUB73) then
\r
467 reg_main_next_state <= ST_A25_T2;
\r
469 reg_main_next_state <= reg_main_state;
\r
472 if (reg_sub_state = ST_SUB73) then
\r
473 reg_main_next_state <= ST_A25_T3;
\r
475 reg_main_next_state <= reg_main_state;
\r
478 if (reg_sub_state = ST_SUB73) then
\r
479 --abs xy move to next only when page crossed.
\r
480 if (reg_tmp_pg_crossed = '1') then
\r
481 reg_main_next_state <= ST_A25_T4;
\r
483 reg_main_next_state <= ST_CM_T0;
\r
486 reg_main_next_state <= reg_main_state;
\r
489 if (reg_sub_state = ST_SUB73) then
\r
490 reg_main_next_state <= ST_CM_T0;
\r
492 reg_main_next_state <= reg_main_state;
\r
495 if (reg_sub_state = ST_SUB73) then
\r
496 reg_main_next_state <= ST_A26_T2;
\r
498 reg_main_next_state <= reg_main_state;
\r
501 if (reg_sub_state = ST_SUB73) then
\r
502 reg_main_next_state <= ST_A26_T3;
\r
504 reg_main_next_state <= reg_main_state;
\r
507 if (reg_sub_state = ST_SUB73) then
\r
508 reg_main_next_state <= ST_CM_T0;
\r
510 reg_main_next_state <= reg_main_state;
\r
513 if (reg_sub_state = ST_SUB73) then
\r
514 reg_main_next_state <= ST_A27_T2;
\r
516 reg_main_next_state <= reg_main_state;
\r
519 if (reg_sub_state = ST_SUB73) then
\r
520 reg_main_next_state <= ST_A27_T3;
\r
522 reg_main_next_state <= reg_main_state;
\r
525 if (reg_sub_state = ST_SUB73) then
\r
526 reg_main_next_state <= ST_A27_T4;
\r
528 reg_main_next_state <= reg_main_state;
\r
531 if (reg_sub_state = ST_SUB73) then
\r
532 --indir, y move to next only when page crossed.
\r
533 if (reg_tmp_pg_crossed = '1') then
\r
534 reg_main_next_state <= ST_A27_T5;
\r
536 reg_main_next_state <= ST_CM_T0;
\r
539 reg_main_next_state <= reg_main_state;
\r
542 if (reg_sub_state = ST_SUB73) then
\r
543 reg_main_next_state <= ST_CM_T0;
\r
545 reg_main_next_state <= reg_main_state;
\r
550 if (reg_sub_state = ST_SUB73) then
\r
551 reg_main_next_state <= ST_A31_T2;
\r
553 reg_main_next_state <= reg_main_state;
\r
556 if (reg_sub_state = ST_SUB73) then
\r
557 reg_main_next_state <= ST_CM_T0;
\r
559 reg_main_next_state <= reg_main_state;
\r
562 if (reg_sub_state = ST_SUB73) then
\r
563 reg_main_next_state <= ST_A32_T2;
\r
565 reg_main_next_state <= reg_main_state;
\r
568 if (reg_sub_state = ST_SUB73) then
\r
569 reg_main_next_state <= ST_A32_T3;
\r
571 reg_main_next_state <= reg_main_state;
\r
574 if (reg_sub_state = ST_SUB73) then
\r
575 reg_main_next_state <= ST_CM_T0;
\r
577 reg_main_next_state <= reg_main_state;
\r
580 if (reg_sub_state = ST_SUB73) then
\r
581 reg_main_next_state <= ST_A33_T2;
\r
583 reg_main_next_state <= reg_main_state;
\r
586 if (reg_sub_state = ST_SUB73) then
\r
587 reg_main_next_state <= ST_A33_T3;
\r
589 reg_main_next_state <= reg_main_state;
\r
592 if (reg_sub_state = ST_SUB73) then
\r
593 reg_main_next_state <= ST_A33_T4;
\r
595 reg_main_next_state <= reg_main_state;
\r
598 if (reg_sub_state = ST_SUB73) then
\r
599 reg_main_next_state <= ST_A33_T5;
\r
601 reg_main_next_state <= reg_main_state;
\r
604 if (reg_sub_state = ST_SUB73) then
\r
605 reg_main_next_state <= ST_CM_T0;
\r
607 reg_main_next_state <= reg_main_state;
\r
610 if (reg_sub_state = ST_SUB73) then
\r
611 reg_main_next_state <= ST_A34_T2;
\r
613 reg_main_next_state <= reg_main_state;
\r
616 if (reg_sub_state = ST_SUB73) then
\r
617 reg_main_next_state <= ST_A34_T3;
\r
619 reg_main_next_state <= reg_main_state;
\r
622 if (reg_sub_state = ST_SUB73) then
\r
623 reg_main_next_state <= ST_A34_T4;
\r
625 reg_main_next_state <= reg_main_state;
\r
628 if (reg_sub_state = ST_SUB73) then
\r
629 reg_main_next_state <= ST_CM_T0;
\r
631 reg_main_next_state <= reg_main_state;
\r
634 if (reg_sub_state = ST_SUB73) then
\r
635 reg_main_next_state <= ST_A35_T2;
\r
637 reg_main_next_state <= reg_main_state;
\r
640 if (reg_sub_state = ST_SUB73) then
\r
641 reg_main_next_state <= ST_A35_T3;
\r
643 reg_main_next_state <= reg_main_state;
\r
646 if (reg_sub_state = ST_SUB73) then
\r
647 reg_main_next_state <= ST_CM_T0;
\r
649 reg_main_next_state <= reg_main_state;
\r
652 if (reg_sub_state = ST_SUB73) then
\r
653 reg_main_next_state <= ST_A36_T2;
\r
655 reg_main_next_state <= reg_main_state;
\r
658 if (reg_sub_state = ST_SUB73) then
\r
659 reg_main_next_state <= ST_A36_T3;
\r
661 reg_main_next_state <= reg_main_state;
\r
664 if (reg_sub_state = ST_SUB73) then
\r
665 reg_main_next_state <= ST_A36_T4;
\r
667 reg_main_next_state <= reg_main_state;
\r
670 if (reg_sub_state = ST_SUB73) then
\r
671 reg_main_next_state <= ST_A36_T5;
\r
673 reg_main_next_state <= reg_main_state;
\r
676 if (reg_sub_state = ST_SUB73) then
\r
677 reg_main_next_state <= ST_CM_T0;
\r
679 reg_main_next_state <= reg_main_state;
\r
685 if (reg_sub_state = ST_SUB73) then
\r
686 reg_main_next_state <= ST_A41_T2;
\r
688 reg_main_next_state <= reg_main_state;
\r
691 if (reg_sub_state = ST_SUB73) then
\r
692 reg_main_next_state <= ST_A41_T3;
\r
694 reg_main_next_state <= reg_main_state;
\r
697 if (reg_sub_state = ST_SUB73) then
\r
698 reg_main_next_state <= ST_A41_T4;
\r
700 reg_main_next_state <= reg_main_state;
\r
703 if (reg_sub_state = ST_SUB73) then
\r
704 reg_main_next_state <= ST_CM_T0;
\r
706 reg_main_next_state <= reg_main_state;
\r
709 if (reg_sub_state = ST_SUB73) then
\r
710 reg_main_next_state <= ST_A42_T2;
\r
712 reg_main_next_state <= reg_main_state;
\r
715 if (reg_sub_state = ST_SUB73) then
\r
716 reg_main_next_state <= ST_A42_T3;
\r
718 reg_main_next_state <= reg_main_state;
\r
721 if (reg_sub_state = ST_SUB73) then
\r
722 reg_main_next_state <= ST_A42_T4;
\r
724 reg_main_next_state <= reg_main_state;
\r
727 if (reg_sub_state = ST_SUB73) then
\r
728 reg_main_next_state <= ST_A42_T5;
\r
730 reg_main_next_state <= reg_main_state;
\r
733 if (reg_sub_state = ST_SUB73) then
\r
734 reg_main_next_state <= ST_CM_T0;
\r
736 reg_main_next_state <= reg_main_state;
\r
739 if (reg_sub_state = ST_SUB73) then
\r
740 reg_main_next_state <= ST_A43_T2;
\r
742 reg_main_next_state <= reg_main_state;
\r
745 if (reg_sub_state = ST_SUB73) then
\r
746 reg_main_next_state <= ST_CM_T0;
\r
748 reg_main_next_state <= reg_main_state;
\r
751 if (reg_sub_state = ST_SUB73) then
\r
752 reg_main_next_state <= ST_A43_T4;
\r
754 reg_main_next_state <= reg_main_state;
\r
757 if (reg_sub_state = ST_SUB73) then
\r
758 reg_main_next_state <= ST_A43_T5;
\r
760 reg_main_next_state <= reg_main_state;
\r
763 if (reg_sub_state = ST_SUB73) then
\r
764 reg_main_next_state <= ST_CM_T0;
\r
766 reg_main_next_state <= reg_main_state;
\r
769 if (reg_sub_state = ST_SUB73) then
\r
770 reg_main_next_state <= ST_A44_T2;
\r
772 reg_main_next_state <= reg_main_state;
\r
775 if (reg_sub_state = ST_SUB73) then
\r
776 reg_main_next_state <= ST_A44_T3;
\r
778 reg_main_next_state <= reg_main_state;
\r
781 if (reg_sub_state = ST_SUB73) then
\r
782 reg_main_next_state <= ST_A44_T4;
\r
784 reg_main_next_state <= reg_main_state;
\r
787 if (reg_sub_state = ST_SUB73) then
\r
788 reg_main_next_state <= ST_A44_T5;
\r
790 reg_main_next_state <= reg_main_state;
\r
793 if (reg_sub_state = ST_SUB73) then
\r
794 reg_main_next_state <= ST_A44_T6;
\r
796 reg_main_next_state <= reg_main_state;
\r
799 if (reg_sub_state = ST_SUB73) then
\r
800 reg_main_next_state <= ST_CM_T0;
\r
802 reg_main_next_state <= reg_main_state;
\r
808 if (reg_sub_state = ST_SUB73) then
\r
809 reg_main_next_state <= ST_A51_T2;
\r
811 reg_main_next_state <= reg_main_state;
\r
814 if (reg_sub_state = ST_SUB73) then
\r
815 reg_main_next_state <= ST_CM_T0;
\r
817 reg_main_next_state <= reg_main_state;
\r
820 if (reg_sub_state = ST_SUB73) then
\r
821 reg_main_next_state <= ST_A52_T2;
\r
823 reg_main_next_state <= reg_main_state;
\r
826 if (reg_sub_state = ST_SUB73) then
\r
827 reg_main_next_state <= ST_A52_T3;
\r
829 reg_main_next_state <= reg_main_state;
\r
832 if (reg_sub_state = ST_SUB73) then
\r
833 reg_main_next_state <= ST_CM_T0;
\r
835 reg_main_next_state <= reg_main_state;
\r
838 if (reg_sub_state = ST_SUB73) then
\r
839 reg_main_next_state <= ST_A53_T2;
\r
841 reg_main_next_state <= reg_main_state;
\r
844 if (reg_sub_state = ST_SUB73) then
\r
845 reg_main_next_state <= ST_A53_T3;
\r
847 reg_main_next_state <= reg_main_state;
\r
850 if (reg_sub_state = ST_SUB73) then
\r
851 reg_main_next_state <= ST_A53_T4;
\r
853 reg_main_next_state <= reg_main_state;
\r
856 if (reg_sub_state = ST_SUB73) then
\r
857 reg_main_next_state <= ST_A53_T5;
\r
859 reg_main_next_state <= reg_main_state;
\r
862 if (reg_sub_state = ST_SUB73) then
\r
863 reg_main_next_state <= ST_CM_T0;
\r
865 reg_main_next_state <= reg_main_state;
\r
868 if (reg_sub_state = ST_SUB73) then
\r
869 reg_main_next_state <= ST_A55_T2;
\r
871 reg_main_next_state <= reg_main_state;
\r
874 if (reg_sub_state = ST_SUB73) then
\r
875 reg_main_next_state <= ST_A55_T3;
\r
877 reg_main_next_state <= reg_main_state;
\r
880 if (reg_sub_state = ST_SUB73) then
\r
881 reg_main_next_state <= ST_A55_T4;
\r
883 reg_main_next_state <= reg_main_state;
\r
886 if (reg_sub_state = ST_SUB73) then
\r
887 reg_main_next_state <= ST_A55_T5;
\r
889 reg_main_next_state <= reg_main_state;
\r
892 if (reg_sub_state = ST_SUB73) then
\r
893 reg_main_next_state <= ST_CM_T0;
\r
895 reg_main_next_state <= reg_main_state;
\r
898 if (reg_sub_state = ST_SUB73) then
\r
899 reg_main_next_state <= ST_A561_T2;
\r
901 reg_main_next_state <= reg_main_state;
\r
904 if (reg_sub_state = ST_SUB73) then
\r
905 reg_main_next_state <= ST_CM_T0;
\r
907 reg_main_next_state <= reg_main_state;
\r
910 if (reg_sub_state = ST_SUB73) then
\r
911 reg_main_next_state <= ST_A562_T2;
\r
913 reg_main_next_state <= reg_main_state;
\r
916 if (reg_sub_state = ST_SUB73) then
\r
917 reg_main_next_state <= ST_A562_T3;
\r
919 reg_main_next_state <= reg_main_state;
\r
922 if (reg_sub_state = ST_SUB73) then
\r
923 reg_main_next_state <= ST_A562_T4;
\r
925 reg_main_next_state <= reg_main_state;
\r
928 if (reg_sub_state = ST_SUB73) then
\r
929 reg_main_next_state <= ST_CM_T0;
\r
931 reg_main_next_state <= reg_main_state;
\r
934 if (reg_sub_state = ST_SUB73) then
\r
935 reg_main_next_state <= ST_A57_T2;
\r
937 reg_main_next_state <= reg_main_state;
\r
940 if (reg_sub_state = ST_SUB73) then
\r
941 reg_main_next_state <= ST_A57_T3;
\r
943 reg_main_next_state <= reg_main_state;
\r
946 if (reg_sub_state = ST_SUB73) then
\r
947 reg_main_next_state <= ST_A57_T4;
\r
949 reg_main_next_state <= reg_main_state;
\r
952 if (reg_sub_state = ST_SUB73) then
\r
953 reg_main_next_state <= ST_A57_T5;
\r
955 reg_main_next_state <= reg_main_state;
\r
958 if (reg_sub_state = ST_SUB73) then
\r
959 reg_main_next_state <= ST_CM_T0;
\r
961 reg_main_next_state <= reg_main_state;
\r
964 if (reg_sub_state = ST_SUB73) then
\r
965 if (reg_tmp_condition = '1') then
\r
966 --condition met. move to branch state.
\r
967 reg_main_next_state <= ST_A58_T2;
\r
969 --condition not met. goto next inst fetch.
\r
970 reg_main_next_state <= ST_CM_T0;
\r
973 reg_main_next_state <= reg_main_state;
\r
976 if (reg_sub_state = ST_SUB73) then
\r
977 if (reg_tmp_pg_crossed = '1') then
\r
978 --page crossed. move to next.
\r
979 reg_main_next_state <= ST_A58_T2;
\r
981 --page not crossed. move to next inst fetch.
\r
982 reg_main_next_state <= ST_CM_T0;
\r
985 reg_main_next_state <= reg_main_state;
\r
988 if (reg_sub_state = ST_SUB73) then
\r
989 reg_main_next_state <= ST_CM_T0;
\r
991 reg_main_next_state <= reg_main_state;
\r
995 ---failed to decode next...
\r
996 reg_main_next_state <= reg_main_state;
\r
997 -- ---not ready yet...
\r
999 -- reg_main_next_state <= reg_main_state;
\r
1004 po_r_nw <= reg_r_nw;
\r
1005 po_addr <= reg_addr;
\r
1006 pio_d_io <= reg_d_out;
\r
1008 --addressing general process...
\r
1009 --pc, io bus, r/w, instruction regs...
\r
1010 ad_general_p : process (pi_rst_n, pi_base_clk)
\r
1012 --address calcuratin w/ carry.
\r
1013 variable calc_adl : std_logic_vector(8 downto 0);
\r
1015 procedure pc_inc is
\r
1017 if (reg_pc_l = "11111111") then
\r
1019 reg_pc_l <= "00000000";
\r
1020 reg_pc_h <= reg_pc_h + 1;
\r
1022 reg_pc_l <= reg_pc_l + 1;
\r
1027 if (pi_rst_n = '0') then
\r
1028 reg_pc_l <= (others => '0');
\r
1029 reg_pc_h <= (others => '0');
\r
1030 reg_inst <= (others => '0');
\r
1031 reg_addr <= (others => 'Z');
\r
1032 reg_d_out <= (others => 'Z');
\r
1033 reg_d_in <= (others => '0');
\r
1035 reg_tmp_pg_crossed <= '0';
\r
1036 calc_adl := (others => '0');
\r
1037 elsif (rising_edge(pi_base_clk)) then
\r
1039 --general input data register.
\r
1040 reg_d_in <= pio_d_io;
\r
1042 --i/o data bus state change.
\r
1043 if (reg_main_state = ST_RS_T0) then
\r
1044 reg_pc_l <= (others => '0');
\r
1045 reg_pc_h <= (others => '0');
\r
1046 reg_inst <= (others => '0');
\r
1047 reg_addr <= (others => '0');
\r
1048 reg_d_out <= (others => 'Z');
\r
1050 elsif (reg_main_state = ST_RS_T3) then
\r
1052 reg_addr <= "11111111" & reg_sp;
\r
1053 reg_d_out <= (others => 'Z');
\r
1055 elsif (reg_main_state = ST_RS_T4) then
\r
1057 reg_addr <= "11111111" & (reg_sp - 1);
\r
1058 reg_d_out <= (others => 'Z');
\r
1060 elsif (reg_main_state = ST_RS_T5) then
\r
1062 reg_addr <= "11111111" & (reg_sp - 2);
\r
1063 reg_d_out <= (others => 'Z');
\r
1065 elsif (reg_main_state = ST_RS_T6) then
\r
1066 --reset vector low...
\r
1067 reg_addr <= "1111111111111100";
\r
1068 reg_d_out <= (others => 'Z');
\r
1070 reg_pc_l <= reg_d_in;
\r
1071 elsif (reg_main_state = ST_RS_T7) then
\r
1072 --reset vector high...
\r
1073 reg_addr <= "1111111111111101";
\r
1074 reg_d_out <= (others => 'Z');
\r
1076 reg_pc_h <= reg_d_in;
\r
1077 elsif (reg_main_state = ST_CM_T0) then
\r
1078 --init pg crossing flag.
\r
1079 reg_tmp_pg_crossed <= '0';
\r
1080 calc_adl := (others => '0');
\r
1082 if (reg_sub_state = ST_SUB00) then
\r
1084 reg_addr <= reg_pc_h & reg_pc_l;
\r
1085 reg_d_out <= (others => 'Z');
\r
1087 elsif (reg_sub_state = ST_SUB30) then
\r
1088 --update instruction register.
\r
1089 reg_inst <= reg_d_in;
\r
1090 elsif (reg_sub_state = ST_SUB70) then
\r
1094 --fetch and move next case.
\r
1095 elsif (reg_main_state = ST_A21_T1 or
\r
1096 reg_main_state = ST_A22_T1 or
\r
1097 reg_main_state = ST_A23_T1 or
\r
1098 reg_main_state = ST_A23_T2 or
\r
1099 reg_main_state = ST_A24_T1 or
\r
1100 reg_main_state = ST_A25_T1 or
\r
1101 reg_main_state = ST_A25_T2 or
\r
1102 reg_main_state = ST_A26_T1 or
\r
1103 reg_main_state = ST_A27_T1 or
\r
1104 reg_main_state = ST_A31_T1 or
\r
1105 reg_main_state = ST_A32_T1 or
\r
1106 reg_main_state = ST_A32_T2 or
\r
1107 reg_main_state = ST_A33_T1 or
\r
1108 reg_main_state = ST_A34_T1 or
\r
1109 reg_main_state = ST_A34_T2 or
\r
1110 reg_main_state = ST_A35_T1 or
\r
1111 reg_main_state = ST_A36_T1 or
\r
1112 reg_main_state = ST_A41_T1 or
\r
1113 reg_main_state = ST_A42_T1 or
\r
1114 reg_main_state = ST_A42_T2 or
\r
1115 reg_main_state = ST_A43_T1 or
\r
1116 reg_main_state = ST_A44_T1 or
\r
1117 reg_main_state = ST_A44_T2 or
\r
1118 reg_main_state = ST_A53_T1 or
\r
1119 reg_main_state = ST_A561_T1 or
\r
1120 reg_main_state = ST_A562_T1 or
\r
1121 reg_main_state = ST_A57_T1 or
\r
1122 reg_main_state = ST_A58_T1) then
\r
1123 if (reg_sub_state = ST_SUB00) then
\r
1125 reg_addr <= reg_pc_h & reg_pc_l;
\r
1126 reg_d_out <= (others => 'Z');
\r
1128 elsif (reg_sub_state = ST_SUB70) then
\r
1133 --intermediate cycles..
\r
1134 elsif (reg_main_state = ST_A24_T2 or
\r
1135 reg_main_state = ST_A26_T2 or
\r
1136 reg_main_state = ST_A33_T2 or
\r
1137 reg_main_state = ST_A35_T2 or
\r
1138 reg_main_state = ST_A27_T2 or
\r
1139 reg_main_state = ST_A36_T2 or
\r
1140 reg_main_state = ST_A43_T2
\r
1144 -->>discarded cycle.
\r
1147 reg_addr <= "00000000" & reg_idl_l;
\r
1148 reg_d_out <= (others => 'Z');
\r
1150 elsif (reg_main_state = ST_A24_T3 or
\r
1151 reg_main_state = ST_A33_T3
\r
1155 reg_addr <= "00000000" & (reg_idl_l + reg_x);
\r
1156 reg_d_out <= (others => 'Z');
\r
1158 elsif (reg_main_state = ST_A24_T4 or
\r
1159 reg_main_state = ST_A33_T4) then
\r
1161 --bal + x + 1 cycle.
\r
1162 reg_addr <= "00000000" & (reg_idl_l + reg_x + 1);
\r
1163 reg_d_out <= (others => 'Z');
\r
1165 elsif (reg_main_state = ST_A25_T3 or
\r
1166 reg_main_state = ST_A34_T3 or
\r
1167 reg_main_state = ST_A44_T3
\r
1170 --(discarded cycle for store inst..)
\r
1171 if (reg_inst(1 downto 0) = "01") then
\r
1172 if (reg_inst(4 downto 2) = "110") then
\r
1174 reg_addr <= reg_idl_h & (reg_idl_l + reg_y);
\r
1175 elsif (reg_inst(4 downto 2) = "111") then
\r
1177 reg_addr <= reg_idl_h & (reg_idl_l + reg_x);
\r
1179 elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then
\r
1182 reg_addr <= reg_idl_h & (reg_idl_l + reg_y);
\r
1183 elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then
\r
1186 reg_addr <= reg_idl_h & (reg_idl_l + reg_x);
\r
1187 elsif (reg_inst = conv_std_logic_vector(16#9d#, 8)) then
\r
1189 reg_addr <= reg_idl_h & (reg_idl_l + reg_x);
\r
1190 calc_adl := ("0" & reg_idl_l) + ("0" & reg_x);
\r
1191 elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then
\r
1193 reg_addr <= reg_idl_h & (reg_idl_l + reg_y);
\r
1194 calc_adl := ("0" & reg_idl_l) + ("0" & reg_y);
\r
1195 elsif (reg_inst(1 downto 0) = "10") then
\r
1197 if (reg_inst(4 downto 2) = "111") then
\r
1199 reg_addr <= reg_idl_h & (reg_idl_l + reg_x);
\r
1200 calc_adl := ("0" & reg_idl_l) + ("0" & reg_y);
\r
1203 reg_d_out <= (others => 'Z');
\r
1206 reg_tmp_pg_crossed <= calc_adl(8);
\r
1207 elsif (reg_main_state = ST_A27_T3 or
\r
1208 reg_main_state = ST_A36_T3) then
\r
1211 reg_addr <= "00000000" & (reg_idl_l + 1);
\r
1212 reg_d_out <= (others => 'Z');
\r
1214 elsif (reg_main_state = ST_A27_T4 or
\r
1215 reg_main_state = ST_A36_T4) then
\r
1218 reg_addr <= reg_tmp_h & (reg_tmp_l + reg_y);
\r
1219 reg_d_out <= (others => 'Z');
\r
1221 calc_adl := ("0" & reg_tmp_l) + ("0" & reg_y);
\r
1222 reg_tmp_pg_crossed <= calc_adl(8);
\r
1223 elsif (reg_main_state = ST_A51_T1 or
\r
1224 reg_main_state = ST_A52_T1) then
\r
1226 --discard pc cycle.
\r
1227 reg_addr <= reg_pc_h & (reg_pc_l + 1);
\r
1228 reg_d_out <= (others => 'Z');
\r
1230 elsif (reg_main_state = ST_A52_T2 or
\r
1231 reg_main_state = ST_A53_T2
\r
1234 --discard sp cycle.
\r
1235 reg_addr <= "00000001" & reg_sp;
\r
1236 reg_d_out <= (others => 'Z');
\r
1241 --a2 instructions.
\r
1242 elsif (reg_main_state = ST_A22_T2 or
\r
1243 reg_main_state = ST_A23_T3 or
\r
1244 reg_main_state = ST_A24_T5 or
\r
1245 reg_main_state = ST_A25_T4 or
\r
1246 reg_main_state = ST_A26_T3 or
\r
1247 reg_main_state = ST_A27_T5
\r
1250 reg_d_out <= (others => 'Z');
\r
1253 --address bus out.
\r
1254 if (reg_main_state = ST_A22_T2) then
\r
1256 reg_addr <= "00000000" & reg_idl_l;
\r
1258 elsif (reg_main_state = ST_A23_T3) then
\r
1260 reg_addr <= reg_idl_h & reg_idl_l;
\r
1262 elsif (reg_main_state = ST_A24_T5) then
\r
1264 reg_addr <= reg_tmp_h & reg_tmp_l;
\r
1266 elsif (reg_main_state = ST_A25_T4) then
\r
1268 if (reg_inst(1 downto 0) = "01") then
\r
1269 if (reg_inst(4 downto 2) = "110") then
\r
1271 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);
\r
1272 elsif (reg_inst(4 downto 2) = "111") then
\r
1274 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);
\r
1276 elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then
\r
1279 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);
\r
1280 elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then
\r
1283 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);
\r
1286 elsif (reg_main_state = ST_A26_T3) then
\r
1288 if (reg_inst(1 downto 0) = "01") then
\r
1289 if (reg_inst(4 downto 2) = "101") then
\r
1291 reg_addr <= "00000000" & (reg_idl_l + reg_x);
\r
1293 elsif (reg_inst = conv_std_logic_vector(16#b6#, 8)) then
\r
1296 reg_addr <= "00000000" & (reg_idl_l + reg_y);
\r
1297 elsif (reg_inst = conv_std_logic_vector(16#b4#, 8)) then
\r
1300 reg_addr <= "00000000" & (reg_idl_l + reg_x);
\r
1303 elsif (reg_main_state = ST_A27_T5) then
\r
1305 reg_addr <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);
\r
1308 --a3 instructions.
\r
1310 elsif (reg_main_state = ST_A31_T2 or
\r
1311 reg_main_state = ST_A32_T3 or
\r
1312 reg_main_state = ST_A33_T5 or
\r
1313 reg_main_state = ST_A34_T4 or
\r
1314 reg_main_state = ST_A35_T3 or
\r
1315 reg_main_state = ST_A36_T5
\r
1319 if (reg_inst(1 downto 0) = "01" and reg_inst(7 downto 5) = "100") then
\r
1321 reg_d_out <= reg_acc;
\r
1322 elsif (reg_inst(1 downto 0) = "10" and reg_inst(7 downto 5) = "100") then
\r
1324 reg_d_out <= reg_x;
\r
1325 elsif (reg_inst(1 downto 0) = "00" and reg_inst(7 downto 5) = "100") then
\r
1327 reg_d_out <= reg_y;
\r
1331 if (reg_sub_state = ST_SUB32 or
\r
1332 reg_sub_state = ST_SUB33 or
\r
1333 reg_sub_state = ST_SUB40 or
\r
1334 reg_sub_state = ST_SUB41
\r
1341 --address bus out.
\r
1342 if (reg_main_state = ST_A31_T2) then
\r
1344 reg_addr <= "00000000" & reg_idl_l;
\r
1346 elsif (reg_main_state = ST_A32_T3) then
\r
1348 reg_addr <= reg_idl_h & reg_idl_l;
\r
1350 elsif (reg_main_state = ST_A33_T5) then
\r
1352 reg_addr <= reg_tmp_h & reg_tmp_l;
\r
1354 elsif (reg_main_state = ST_A34_T4) then
\r
1356 if (reg_inst = conv_std_logic_vector(16#9d#, 8)) then
\r
1358 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);
\r
1359 elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then
\r
1361 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);
\r
1364 elsif (reg_main_state = ST_A35_T3) then
\r
1366 --sta and sty has index x access,
\r
1367 --stx has index y access.
\r
1368 if (reg_inst = conv_std_logic_vector(16#95#, 8) or --sta
\r
1369 reg_inst = conv_std_logic_vector(16#94#, 8) --sty
\r
1371 reg_addr <= "00000000" & (reg_idl_l + reg_x);
\r
1372 elsif (reg_inst = conv_std_logic_vector(16#96#, 8)) then
\r
1374 reg_addr <= "00000000" & (reg_idl_l + reg_y);
\r
1377 elsif (reg_main_state = ST_A36_T5) then
\r
1379 reg_addr <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);
\r
1382 --a4 instructions.
\r
1386 elsif (reg_main_state = ST_A41_T2 or
\r
1387 reg_main_state = ST_A42_T3 or
\r
1388 reg_main_state = ST_A43_T3 or
\r
1389 reg_main_state = ST_A44_T4
\r
1391 --data fetch cycle.
\r
1392 reg_d_out <= (others => 'Z');
\r
1395 --address bus out.
\r
1396 if (reg_main_state = ST_A41_T2) then
\r
1398 reg_addr <= "00000000" & reg_idl_l;
\r
1400 elsif (reg_main_state = ST_A42_T3) then
\r
1402 reg_addr <= reg_idl_h & reg_idl_l;
\r
1404 elsif (reg_main_state = ST_A43_T3) then
\r
1406 reg_addr <= "00000000" & (reg_idl_l + reg_x);
\r
1408 elsif (reg_main_state = ST_A44_T4) then
\r
1410 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);
\r
1413 elsif (reg_main_state = ST_A41_T3 or
\r
1414 reg_main_state = ST_A41_T4 or
\r
1415 reg_main_state = ST_A42_T4 or
\r
1416 reg_main_state = ST_A42_T5 or
\r
1417 reg_main_state = ST_A43_T4 or
\r
1418 reg_main_state = ST_A43_T5 or
\r
1419 reg_main_state = ST_A44_T5 or
\r
1420 reg_main_state = ST_A44_T6
\r
1422 --data store cycle.
\r
1424 reg_d_out <= reg_tmp_data;
\r
1427 if (reg_sub_state = ST_SUB32 or
\r
1428 reg_sub_state = ST_SUB33 or
\r
1429 reg_sub_state = ST_SUB40 or
\r
1430 reg_sub_state = ST_SUB41
\r
1437 --address bus out.
\r
1438 if (reg_main_state = ST_A41_T3 or
\r
1439 reg_main_state = ST_A41_T4
\r
1442 reg_addr <= "00000000" & reg_idl_l;
\r
1444 elsif (reg_main_state = ST_A42_T4 or
\r
1445 reg_main_state = ST_A42_T5
\r
1448 reg_addr <= reg_idl_h & reg_idl_l;
\r
1450 elsif (reg_main_state = ST_A43_T4 or
\r
1451 reg_main_state = ST_A43_T5
\r
1454 reg_addr <= "00000000" & (reg_idl_l + reg_x);
\r
1456 elsif (reg_main_state = ST_A44_T5 or
\r
1457 reg_main_state = ST_A44_T6
\r
1460 reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);
\r
1463 --a5 instruction...
\r
1465 elsif (reg_main_state = ST_A51_T2) then
\r
1466 reg_addr <= "00000001" & reg_sp;
\r
1467 if (reg_sub_state = ST_SUB32 or
\r
1468 reg_sub_state = ST_SUB33 or
\r
1469 reg_sub_state = ST_SUB40 or
\r
1470 reg_sub_state = ST_SUB41
\r
1476 if (reg_inst = conv_std_logic_vector(16#48#, 8)) then
\r
1478 reg_d_out <= reg_acc;
\r
1479 elsif (reg_inst = conv_std_logic_vector(16#08#, 8)) then
\r
1481 reg_d_out <= reg_status;
\r
1485 elsif (reg_main_state = ST_A52_T3) then
\r
1486 reg_addr <= "00000001" & reg_sp;
\r
1488 reg_d_out <= (others => 'Z');
\r
1491 elsif (reg_main_state = ST_A53_T3) then
\r
1493 reg_addr <= "00000001" & reg_sp;
\r
1494 reg_d_out <= reg_pc_h;
\r
1495 if (reg_sub_state = ST_SUB32 or
\r
1496 reg_sub_state = ST_SUB33 or
\r
1497 reg_sub_state = ST_SUB40 or
\r
1498 reg_sub_state = ST_SUB41
\r
1504 elsif (reg_main_state = ST_A53_T4) then
\r
1506 reg_addr <= "00000001" & reg_sp;
\r
1507 reg_d_out <= reg_pc_l;
\r
1508 if (reg_sub_state = ST_SUB32 or
\r
1509 reg_sub_state = ST_SUB33 or
\r
1510 reg_sub_state = ST_SUB40 or
\r
1511 reg_sub_state = ST_SUB41
\r
1517 elsif (reg_main_state = ST_A53_T5) then
\r
1518 if (reg_sub_state = ST_SUB00) then
\r
1520 reg_addr <= reg_pc_h & reg_pc_l;
\r
1521 reg_d_out <= (others => 'Z');
\r
1523 elsif (reg_sub_state = ST_SUB70) then
\r
1524 --go to sub-routine addr.
\r
1525 reg_pc_l <= reg_idl_l;
\r
1526 reg_pc_h <= reg_idl_h;
\r
1530 elsif (reg_main_state = ST_A561_T2) then
\r
1531 if (reg_sub_state = ST_SUB00) then
\r
1533 reg_addr <= reg_pc_h & reg_pc_l;
\r
1534 reg_d_out <= (others => 'Z');
\r
1536 elsif (reg_sub_state = ST_SUB70) then
\r
1537 reg_pc_l <= reg_idl_l;
\r
1538 reg_pc_h <= reg_idl_h;
\r
1542 elsif (reg_main_state = ST_A57_T2) then
\r
1543 --sp out (discarded.)
\r
1544 reg_addr <= "00000001" & reg_sp;
\r
1545 reg_d_out <= (others => 'Z');
\r
1547 elsif (reg_main_state = ST_A57_T3) then
\r
1549 if (reg_sub_state = ST_SUB00) then
\r
1550 reg_addr <= "00000001" & reg_sp;
\r
1551 reg_d_out <= (others => 'Z');
\r
1553 elsif (reg_sub_state = ST_SUB70) then
\r
1554 reg_pc_l <= reg_d_in;
\r
1556 elsif (reg_main_state = ST_A57_T4) then
\r
1558 if (reg_sub_state = ST_SUB00) then
\r
1559 reg_addr <= "00000001" & reg_sp;
\r
1560 reg_d_out <= (others => 'Z');
\r
1562 elsif (reg_sub_state = ST_SUB70) then
\r
1563 reg_pc_h <= reg_d_in;
\r
1565 elsif (reg_main_state = ST_A57_T5) then
\r
1566 --pc out (discarded.)
\r
1567 if (reg_sub_state = ST_SUB00) then
\r
1568 reg_addr <= reg_pc_h & reg_pc_l;
\r
1569 reg_d_out <= (others => 'Z');
\r
1571 elsif (reg_sub_state = ST_SUB70) then
\r
1572 reg_pc_l <= reg_pc_l + 1;
\r
1575 --conditional branch.
\r
1576 elsif (reg_main_state = ST_A58_T2) then
\r
1577 if (reg_sub_state = ST_SUB10) then
\r
1578 calc_adl := ("0" & reg_pc_l) + ("0" & reg_idl_l);
\r
1579 reg_tmp_pg_crossed <= calc_adl(8);
\r
1581 reg_pc_l <= calc_adl(7 downto 0);
\r
1582 reg_addr <= reg_pc_h & calc_adl(7 downto 0);
\r
1583 reg_d_out <= (others => 'Z');
\r
1588 elsif (reg_main_state = ST_A58_T3) then
\r
1589 if (reg_sub_state = ST_SUB10) then
\r
1590 reg_pc_l <= reg_pc_h + "1";
\r
1591 reg_addr <= (reg_pc_h + "1") & reg_pc_l;
\r
1592 reg_d_out <= (others => 'Z');
\r
1595 end if;--if (reg_main_state = ST_RS_T0) then
\r
1596 end if;--if (pi_rst_n = '0') then
\r
1599 --internal data latch...
\r
1600 --fetch first and second operand.
\r
1601 idl_p : process (pi_rst_n, pi_base_clk)
\r
1603 if (pi_rst_n = '0') then
\r
1604 reg_idl_l <= (others => '0');
\r
1605 reg_idl_h <= (others => '0');
\r
1606 reg_tmp_l <= (others => '0');
\r
1607 reg_tmp_h <= (others => '0');
\r
1608 elsif (rising_edge(pi_base_clk)) then
\r
1609 if (reg_main_state = ST_A21_T1 or
\r
1610 reg_main_state = ST_A22_T1 or
\r
1611 reg_main_state = ST_A23_T1 or
\r
1612 reg_main_state = ST_A24_T1 or
\r
1613 reg_main_state = ST_A25_T1 or
\r
1614 reg_main_state = ST_A26_T1 or
\r
1615 reg_main_state = ST_A27_T1 or
\r
1616 reg_main_state = ST_A31_T1 or
\r
1617 reg_main_state = ST_A32_T1 or
\r
1618 reg_main_state = ST_A33_T1 or
\r
1619 reg_main_state = ST_A34_T1 or
\r
1620 reg_main_state = ST_A35_T1 or
\r
1621 reg_main_state = ST_A36_T1 or
\r
1622 reg_main_state = ST_A41_T1 or
\r
1623 reg_main_state = ST_A42_T1 or
\r
1624 reg_main_state = ST_A43_T1 or
\r
1625 reg_main_state = ST_A44_T1 or
\r
1626 reg_main_state = ST_A53_T1 or
\r
1627 reg_main_state = ST_A561_T1 or
\r
1628 reg_main_state = ST_A562_T1 or
\r
1629 reg_main_state = ST_A58_T1) then
\r
1630 if (reg_sub_state = ST_SUB30) then
\r
1631 --get low data from rom.
\r
1632 reg_idl_l <= reg_d_in;
\r
1634 elsif (reg_main_state = ST_A23_T2 or
\r
1635 reg_main_state = ST_A25_T2 or
\r
1636 reg_main_state = ST_A32_T2 or
\r
1637 reg_main_state = ST_A34_T2 or
\r
1638 reg_main_state = ST_A42_T2 or
\r
1639 reg_main_state = ST_A44_T2 or
\r
1640 reg_main_state = ST_A53_T5 or
\r
1641 reg_main_state = ST_A561_T2 or
\r
1642 reg_main_state = ST_A562_T2) then
\r
1643 if (reg_sub_state = ST_SUB30) then
\r
1644 --get high data from rom.
\r
1645 reg_idl_h <= reg_d_in;
\r
1647 elsif (reg_main_state = ST_A24_T3 or
\r
1648 reg_main_state = ST_A27_T2 or
\r
1649 reg_main_state = ST_A33_T3 or
\r
1650 reg_main_state = ST_A36_T2
\r
1656 if (reg_sub_state = ST_SUB30) then
\r
1657 reg_tmp_l <= reg_d_in;
\r
1659 elsif (reg_main_state = ST_A24_T4 or
\r
1660 reg_main_state = ST_A27_T3 or
\r
1661 reg_main_state = ST_A33_T4 or
\r
1662 reg_main_state = ST_A36_T3
\r
1668 if (reg_sub_state = ST_SUB30) then
\r
1669 reg_tmp_h <= reg_d_in;
\r
1671 end if;--if (reg_main_state = ST_RS_T0)
\r
1672 end if;--if (pi_rst_n = '0') then
\r
1675 --stack pointer...
\r
1676 sp_p : process (pi_rst_n, pi_base_clk)
\r
1678 if (pi_rst_n = '0') then
\r
1679 reg_sp <= (others => '0');
\r
1680 elsif (rising_edge(pi_base_clk)) then
\r
1681 if (reg_main_state = ST_A1_T1) then
\r
1683 if (reg_inst = conv_std_logic_vector(16#9a#, 8)) then
\r
1684 reg_sp <= reg_idl_l;
\r
1686 elsif (reg_main_state = ST_A51_T2 or
\r
1687 reg_main_state = ST_A53_T3 or
\r
1688 reg_main_state = ST_A53_T4) then
\r
1690 if (reg_sub_state = ST_SUB70) then
\r
1691 reg_sp <= reg_sp - 1;
\r
1693 elsif (reg_main_state = ST_A52_T2 or
\r
1694 reg_main_state = ST_A57_T2 or
\r
1695 reg_main_state = ST_A57_T3 or
\r
1696 reg_main_state = ST_A57_T4) then
\r
1698 if (reg_sub_state = ST_SUB70) then
\r
1699 reg_sp <= reg_sp + 1;
\r
1701 end if;--if (reg_main_state = ST_RS_T0)
\r
1702 end if;--if (pi_rst_n = '0') then
\r
1705 --calcuration process...
\r
1706 --update acc, x, y, status registers.
\r
1707 calc_p : process (pi_rst_n, pi_base_clk)
\r
1709 variable calc_res : std_logic_vector (8 downto 0);
\r
1710 procedure update_status (
\r
1711 d : in std_logic_vector(7 downto 0);
\r
1712 set_n : in integer range 0 to 1;
\r
1713 set_z : in integer range 0 to 1;
\r
1714 set_c : in integer range 0 to 1
\r
1717 if (set_n = 1) then
\r
1718 if (d(7) = '1') then
\r
1719 reg_status(FL_N) <= '1';
\r
1721 reg_status(FL_N) <= '0';
\r
1724 if (set_z = 1) then
\r
1725 if (d = "00000000") then
\r
1726 reg_status(FL_Z) <= '1';
\r
1728 reg_status(FL_Z) <= '0';
\r
1731 if (set_c = 1) then
\r
1732 reg_status(FL_C) <= reg_tmp_carry;
\r
1736 procedure set_condition_result (
\r
1737 flg : in integer range 0 to 7;
\r
1738 chk_val : in std_logic
\r
1741 if (reg_status(flg) = chk_val) then
\r
1742 reg_tmp_condition <= '1';
\r
1744 reg_tmp_condition <= '0';
\r
1749 --Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc.
\r
1750 if (pi_rst_n = '0') then
\r
1751 reg_acc <= (others => '0');
\r
1752 reg_x <= (others => '0');
\r
1753 reg_y <= (others => '0');
\r
1754 reg_status <= (others => '0');
\r
1755 reg_tmp_carry <= '0';
\r
1756 reg_tmp_ovf <= '0';
\r
1757 reg_tmp_condition <= '0';
\r
1758 elsif (rising_edge(pi_base_clk)) then
\r
1759 --not used status pin initialize (to avoid latches).
\r
1760 reg_status(5 downto 3) <= "000";
\r
1762 --a1 instructions...
\r
1763 --asl dex nop tax tya
\r
1768 if (reg_main_state = ST_CM_T0) then
\r
1769 --init flag regs..
\r
1770 reg_tmp_carry <= '0';
\r
1771 reg_tmp_ovf <= '0';
\r
1772 reg_tmp_condition <= '0';
\r
1773 elsif (reg_main_state = ST_A1_T1) then
\r
1775 if (reg_sub_state = ST_SUB30) then
\r
1777 if (reg_inst(1 downto 0) = "10") then
\r
1778 if (reg_inst(7 downto 5) = "000") then
\r
1780 reg_acc <= reg_acc(6 downto 0) & "0";
\r
1781 reg_tmp_carry <= reg_acc(7);
\r
1782 elsif (reg_inst(7 downto 5) = "001") then
\r
1784 reg_acc <= reg_acc(6 downto 0) & reg_status(FL_C);
\r
1785 reg_tmp_carry <= reg_acc(7);
\r
1786 elsif (reg_inst(7 downto 5) = "010") then
\r
1788 reg_acc <= "0" & reg_acc(7 downto 1);
\r
1789 reg_tmp_carry <= reg_acc(0);
\r
1790 elsif (reg_inst(7 downto 5) = "011") then
\r
1792 reg_acc <= reg_status(FL_C) & reg_acc(7 downto 1);
\r
1793 reg_tmp_carry <= reg_acc(0);
\r
1794 elsif (reg_inst(7 downto 5) = "110") then
\r
1796 reg_acc <= reg_acc - 1;
\r
1797 elsif (reg_inst(7 downto 5) = "111") then
\r
1799 reg_acc <= reg_acc + 1;
\r
1801 elsif (reg_inst = conv_std_logic_vector(16#88#, 8)) then
\r
1803 reg_y <= reg_y - 1;
\r
1804 elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then
\r
1807 elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then
\r
1809 reg_y <= reg_y + 1;
\r
1810 elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then
\r
1812 reg_x <= reg_x + 1;
\r
1813 elsif (reg_inst = conv_std_logic_vector(16#18#, 8)) then
\r
1815 reg_status(FL_C) <= '0';
\r
1816 elsif (reg_inst = conv_std_logic_vector(16#38#, 8)) then
\r
1818 reg_status(FL_C) <= '1';
\r
1819 elsif (reg_inst = conv_std_logic_vector(16#58#, 8)) then
\r
1821 reg_status(FL_I) <= '0';
\r
1822 elsif (reg_inst = conv_std_logic_vector(16#78#, 8)) then
\r
1824 reg_status(FL_I) <= '1';
\r
1825 elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then
\r
1828 elsif (reg_inst = conv_std_logic_vector(16#b8#, 8)) then
\r
1830 reg_status(FL_V) <= '0';
\r
1831 elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then
\r
1834 elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then
\r
1837 elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then
\r
1840 elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then
\r
1842 reg_x <= reg_x - 1;
\r
1843 elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then
\r
1848 --update status reg
\r
1849 elsif (reg_sub_state = ST_SUB31) then
\r
1851 if (reg_inst(1 downto 0) = "10") then
\r
1852 if (reg_inst(7 downto 5) = "000") then
\r
1854 update_status(reg_acc, 1, 1, 1);
\r
1855 elsif (reg_inst(7 downto 5) = "001") then
\r
1857 update_status(reg_acc, 1, 1, 1);
\r
1858 elsif (reg_inst(7 downto 5) = "010") then
\r
1860 update_status(reg_acc, 0, 1, 1);
\r
1861 elsif (reg_inst(7 downto 5) = "011") then
\r
1863 update_status(reg_acc, 1, 1, 1);
\r
1864 elsif (reg_inst(7 downto 5) = "110") then
\r
1866 update_status(reg_acc, 1, 1, 0);
\r
1867 elsif (reg_inst(7 downto 5) = "111") then
\r
1869 update_status(reg_acc, 1, 1, 0);
\r
1871 elsif (reg_inst = conv_std_logic_vector(16#88#, 8)) then
\r
1873 update_status(reg_y, 1, 1, 0);
\r
1874 elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then
\r
1876 update_status(reg_y, 1, 1, 0);
\r
1877 elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then
\r
1879 update_status(reg_y, 1, 1, 0);
\r
1880 elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then
\r
1882 update_status(reg_x, 1, 1, 0);
\r
1883 elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then
\r
1885 update_status(reg_acc, 1, 1, 0);
\r
1886 elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then
\r
1888 update_status(reg_acc, 1, 1, 0);
\r
1889 elsif (reg_inst = conv_std_logic_vector(16#9a#, 8)) then
\r
1891 update_status(reg_sp, 1, 1, 0);
\r
1892 elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then
\r
1894 update_status(reg_x, 1, 1, 0);
\r
1895 elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then
\r
1897 update_status(reg_x, 1, 1, 0);
\r
1898 elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then
\r
1900 update_status(reg_x, 1, 1, 0);
\r
1901 elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then
\r
1905 end if;--if (reg_sub_state = ST_SUB30) then
\r
1907 --a2 instructions...
\r
1911 elsif (reg_main_state = ST_A21_T1 or
\r
1912 reg_main_state = ST_A22_T2 or
\r
1913 reg_main_state = ST_A23_T3 or
\r
1914 reg_main_state = ST_A24_T5 or
\r
1915 reg_main_state = ST_A25_T4 or
\r
1916 reg_main_state = ST_A25_T3 or
\r
1917 reg_main_state = ST_A26_T3 or
\r
1918 reg_main_state = ST_A27_T5) then
\r
1921 if (reg_sub_state = ST_SUB30) then
\r
1923 if (reg_inst(1 downto 0) = "01") then
\r
1924 if (reg_inst(7 downto 5) = "000") then
\r
1926 reg_acc <= (reg_acc or reg_d_in);
\r
1927 elsif (reg_inst(7 downto 5) = "001") then
\r
1929 reg_acc <= (reg_acc and reg_d_in);
\r
1930 elsif (reg_inst(7 downto 5) = "010") then
\r
1932 reg_acc <= (reg_acc xor reg_d_in);
\r
1933 elsif (reg_inst(7 downto 5) = "011") then
\r
1935 calc_res := ("0" & reg_acc) + ("0" & reg_d_in) + reg_status(FL_C);
\r
1936 reg_tmp_carry <= calc_res(8);
\r
1937 if ((reg_acc(7) = reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then
\r
1938 reg_tmp_ovf <= '1';
\r
1940 reg_tmp_ovf <= '0';
\r
1942 reg_acc <= calc_res(7 downto 0);
\r
1943 elsif (reg_inst(7 downto 5) = "101") then
\r
1945 reg_acc <= reg_d_in;
\r
1946 elsif (reg_inst(7 downto 5) = "110") then
\r
1949 elsif (reg_inst(7 downto 5) = "111") then
\r
1951 ---A - M - ~C -> A
\r
1952 calc_res := ("0" & reg_acc) - ("0" & reg_d_in) - not reg_status(FL_C);
\r
1954 --c Set if unsigned borrow not required; cleared if unsigned borrow.
\r
1955 reg_tmp_carry <= not calc_res(7);
\r
1956 --v Set if signed borrow required; cleared if no signed borrow.
\r
1957 if ((reg_acc(7) /= reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then
\r
1958 reg_tmp_ovf <= '1';
\r
1960 reg_tmp_ovf <= '0';
\r
1962 reg_acc <= calc_res(7 downto 0);
\r
1965 elsif (reg_inst(1 downto 0) = "10") then
\r
1966 if (reg_inst(7 downto 5) = "101") then
\r
1968 reg_x <= reg_d_in;
\r
1971 elsif (reg_inst(1 downto 0) = "00") then
\r
1972 if (reg_inst(7 downto 5) = "001") then
\r
1975 elsif (reg_inst(7 downto 5) = "101") then
\r
1977 reg_y <= reg_d_in;
\r
1978 elsif (reg_inst(7 downto 5) = "110") then
\r
1981 elsif (reg_inst(7 downto 5) = "111") then
\r
1987 --update status reg
\r
1988 elsif (reg_sub_state = ST_SUB31) then
\r
1990 if (reg_inst(1 downto 0) = "01") then
\r
1991 if (reg_inst(7 downto 5) = "000") then
\r
1993 update_status(reg_x, 1, 1, 0);
\r
1994 elsif (reg_inst(7 downto 5) = "001") then
\r
1996 update_status(reg_x, 1, 1, 0);
\r
1997 elsif (reg_inst(7 downto 5) = "010") then
\r
1999 update_status(reg_x, 1, 1, 0);
\r
2000 elsif (reg_inst(7 downto 5) = "011") then
\r
2002 update_status(reg_x, 1, 1, 1);
\r
2003 reg_status(FL_V) <= reg_tmp_ovf;
\r
2004 elsif (reg_inst(7 downto 5) = "101") then
\r
2006 update_status(reg_x, 1, 1, 0);
\r
2007 elsif (reg_inst(7 downto 5) = "110") then
\r
2009 calc_res := (("0" & reg_acc) - ("0" & reg_d_in));
\r
2010 if (reg_acc >= reg_d_in) then
\r
2011 reg_status(FL_C) <= '1';
\r
2013 reg_status(FL_C) <= '0';
\r
2015 if (calc_res(7) = '1') then
\r
2016 reg_status(FL_N) <= '1';
\r
2018 reg_status(FL_N) <= '0';
\r
2020 if (calc_res = "000000000") then
\r
2021 reg_status(FL_Z) <= '1';
\r
2023 reg_status(FL_Z) <= '0';
\r
2025 elsif (reg_inst(7 downto 5) = "111") then
\r
2027 update_status(reg_x, 1, 1, 1);
\r
2028 reg_status(FL_V) <= reg_tmp_ovf;
\r
2031 elsif (reg_inst(1 downto 0) = "10") then
\r
2032 if (reg_inst(7 downto 5) = "101") then
\r
2034 update_status(reg_x, 1, 1, 0);
\r
2037 elsif (reg_inst(1 downto 0) = "00") then
\r
2038 if (reg_inst(7 downto 5) = "001") then
\r
2040 calc_res(7 downto 0) := (reg_acc and reg_d_in);
\r
2041 reg_status(FL_N) <= reg_d_in(7);
\r
2042 reg_status(FL_V) <= reg_d_in(6);
\r
2043 if (calc_res(7 downto 0) = "00000000") then
\r
2044 reg_status(FL_Z) <= '1';
\r
2046 reg_status(FL_Z) <= '0';
\r
2048 elsif (reg_inst(7 downto 5) = "101") then
\r
2050 update_status(reg_x, 1, 1, 0);
\r
2051 elsif (reg_inst(7 downto 5) = "110") then
\r
2053 calc_res := (("0" & reg_y) - ("0" & reg_d_in));
\r
2054 if (reg_y >= reg_d_in) then
\r
2055 reg_status(FL_C) <= '1';
\r
2057 reg_status(FL_C) <= '0';
\r
2059 if (calc_res(7) = '1') then
\r
2060 reg_status(FL_N) <= '1';
\r
2062 reg_status(FL_N) <= '0';
\r
2064 if (calc_res = "000000000") then
\r
2065 reg_status(FL_Z) <= '1';
\r
2067 reg_status(FL_Z) <= '0';
\r
2069 elsif (reg_inst(7 downto 5) = "111") then
\r
2071 calc_res := (("0" & reg_x) - ("0" & reg_d_in));
\r
2072 if (reg_x >= reg_d_in) then
\r
2073 reg_status(FL_C) <= '1';
\r
2075 reg_status(FL_C) <= '0';
\r
2077 if (calc_res(7) = '1') then
\r
2078 reg_status(FL_N) <= '1';
\r
2080 reg_status(FL_N) <= '0';
\r
2082 if (calc_res = "000000000") then
\r
2083 reg_status(FL_Z) <= '1';
\r
2085 reg_status(FL_Z) <= '0';
\r
2089 end if;--if (reg_sub_state = ST_SUB30) then
\r
2091 --a4 instructions.
\r
2095 elsif (reg_main_state = ST_A41_T2 or
\r
2096 reg_main_state = ST_A42_T3 or
\r
2097 reg_main_state = ST_A43_T3 or
\r
2098 reg_main_state = ST_A44_T4
\r
2100 --data fetch cycle.
\r
2101 reg_tmp_data <= reg_d_in;
\r
2103 elsif (reg_main_state = ST_A41_T4 or
\r
2104 reg_main_state = ST_A42_T5 or
\r
2105 reg_main_state = ST_A43_T5 or
\r
2106 reg_main_state = ST_A44_T6
\r
2108 --data modify cycle.
\r
2111 if (reg_sub_state = ST_SUB10) then
\r
2113 if (reg_inst(1 downto 0) = "10") then
\r
2114 if (reg_inst(7 downto 5) = "000") then
\r
2116 reg_tmp_data <= reg_tmp_data(6 downto 0) & "0";
\r
2117 reg_tmp_carry <= reg_tmp_data(7);
\r
2118 elsif (reg_inst(7 downto 5) = "001") then
\r
2120 reg_tmp_data <= reg_tmp_data(6 downto 0) & reg_status(FL_C);
\r
2121 reg_tmp_carry <= reg_tmp_data(7);
\r
2122 elsif (reg_inst(7 downto 5) = "010") then
\r
2124 reg_tmp_data <= "0" & reg_tmp_data(7 downto 1);
\r
2125 reg_tmp_carry <= reg_tmp_data(0);
\r
2126 elsif (reg_inst(7 downto 5) = "011") then
\r
2128 reg_tmp_data <= reg_status(FL_C) & reg_tmp_data(7 downto 1);
\r
2129 reg_tmp_carry <= reg_tmp_data(0);
\r
2130 elsif (reg_inst(7 downto 5) = "110") then
\r
2132 reg_tmp_data <= reg_tmp_data - 1;
\r
2133 elsif (reg_inst(7 downto 5) = "111") then
\r
2135 reg_tmp_data <= reg_tmp_data + 1;
\r
2139 --update status reg
\r
2140 elsif (reg_sub_state = ST_SUB20) then
\r
2142 if (reg_inst(1 downto 0) = "10") then
\r
2143 if (reg_inst(7 downto 5) = "000") then
\r
2145 update_status(reg_tmp_data, 1, 1, 1);
\r
2146 elsif (reg_inst(7 downto 5) = "001") then
\r
2148 update_status(reg_tmp_data, 1, 1, 1);
\r
2149 elsif (reg_inst(7 downto 5) = "010") then
\r
2151 update_status(reg_tmp_data, 0, 1, 1);
\r
2152 elsif (reg_inst(7 downto 5) = "011") then
\r
2154 update_status(reg_tmp_data, 1, 1, 1);
\r
2155 elsif (reg_inst(7 downto 5) = "110") then
\r
2157 update_status(reg_tmp_data, 1, 1, 0);
\r
2158 elsif (reg_inst(7 downto 5) = "111") then
\r
2160 update_status(reg_tmp_data, 1, 1, 0);
\r
2165 --a5 instructions...
\r
2167 elsif (reg_main_state = ST_A52_T3) then
\r
2169 if (reg_sub_state = ST_SUB30) then
\r
2170 if (reg_inst = conv_std_logic_vector(16#28#, 8)) then
\r
2172 reg_status <= reg_d_in;
\r
2173 elsif (reg_inst = conv_std_logic_vector(16#68#, 8)) then
\r
2175 reg_acc <= reg_d_in;
\r
2178 --update status reg
\r
2179 elsif (reg_sub_state = ST_SUB31) then
\r
2180 if (reg_inst = conv_std_logic_vector(16#68#, 8)) then
\r
2182 update_status(reg_acc, 1, 1, 0);
\r
2184 end if;--if (reg_sub_state = ST_SUB30) then
\r
2186 --a58 branch inst.
\r
2191 elsif (reg_main_state = ST_A58_T1) then
\r
2192 if (reg_sub_state = ST_SUB30) then
\r
2193 if (reg_inst = conv_std_logic_vector(16#90#, 8)) then
\r
2195 set_condition_result(FL_C, '0');
\r
2197 elsif (reg_inst = conv_std_logic_vector(16#b0#, 8)) then
\r
2199 set_condition_result(FL_C, '1');
\r
2201 elsif (reg_inst = conv_std_logic_vector(16#f0#, 8)) then
\r
2203 set_condition_result(FL_Z, '1');
\r
2205 elsif (reg_inst = conv_std_logic_vector(16#30#, 8)) then
\r
2207 set_condition_result(FL_N, '1');
\r
2209 elsif (reg_inst = conv_std_logic_vector(16#d0#, 8)) then
\r
2211 set_condition_result(FL_Z, '0');
\r
2213 elsif (reg_inst = conv_std_logic_vector(16#10#, 8)) then
\r
2215 set_condition_result(FL_N, '0');
\r
2217 elsif (reg_inst = conv_std_logic_vector(16#50#, 8)) then
\r
2219 set_condition_result(FL_V, '0');
\r
2221 elsif (reg_inst = conv_std_logic_vector(16#70#, 8)) then
\r
2223 set_condition_result(FL_V, '1');
\r
2226 end if;--if (reg_main_state = ST_A21_T1 or...
\r
2227 end if;--if (pi_rst_n = '0') then
\r