de0_cv_nes/mos6502.vhd

   1 library ieee;\r
   2 use ieee.std_logic_1164.all;\r
   3 use ieee.std_logic_unsigned.all;\r
   4 \r
   5 entity mos6502 is \r
   6     port (  \r
   7             pi_rst_n       : in std_logic;\r
   8             pi_base_clk         : in std_logic;\r
   9             pi_cpu_en       : in std_logic_vector (7 downto 0);\r
  10             pi_rdy         : in std_logic;\r
  11             pi_irq_n       : in std_logic;\r
  12             pi_nmi_n       : in std_logic;\r
  13             po_r_nw        : out std_logic;\r
  14             po_addr        : out std_logic_vector ( 15 downto 0);\r
  15             pio_d_io       : inout std_logic_vector ( 7 downto 0)\r
  16     );\r
  17 end mos6502;\r
  18 \r
  19 architecture rtl of mos6502 is\r
  20 \r
  21 ---cpu main state:\r
  22 type cpu_main_state is (\r
  23     --common state. idle and inst fetch.\r
  24     ST_IDLE,\r
  25     ST_CM_T0,\r
  26 \r
  27     --single byte inst execute.\r
  28     ST_A1_T1,\r
  29 \r
  30     --mem data operation\r
  31     ST_A21_T1,\r
  32     ST_A22_T1, ST_A22_T2,\r
  33     ST_A23_T1, ST_A23_T2, ST_A23_T3,\r
  34     ST_A24_T1, ST_A24_T2, ST_A24_T3, ST_A24_T4, ST_A24_T5,\r
  35     ST_A25_T1, ST_A25_T2, ST_A25_T3, ST_A25_T4,\r
  36     ST_A26_T1, ST_A26_T2, ST_A26_T3,\r
  37     ST_A27_T1, ST_A27_T2, ST_A27_T3, ST_A27_T4, ST_A27_T5,\r
  38 \r
  39     --store op.\r
  40     ST_A31_T1, ST_A31_T2,\r
  41     ST_A32_T1, ST_A32_T2, ST_A32_T3,\r
  42     ST_A33_T1, ST_A33_T2, ST_A33_T3, ST_A33_T4, ST_A33_T5,\r
  43     ST_A34_T1, ST_A34_T2, ST_A34_T3, ST_A34_T4,\r
  44     ST_A35_T1, ST_A35_T2, ST_A35_T3,\r
  45     ST_A36_T1, ST_A36_T2, ST_A36_T3, ST_A36_T4, ST_A36_T5,\r
  46 \r
  47     --memory to memory op.\r
  48     ST_A41_T1, ST_A41_T2, ST_A41_T3, ST_A41_T4,\r
  49     ST_A42_T1, ST_A42_T2, ST_A42_T3, ST_A42_T4, ST_A42_T5,\r
  50     ST_A43_T1, ST_A43_T2, ST_A43_T3, ST_A43_T4, ST_A43_T5,\r
  51     ST_A44_T1, ST_A44_T2, ST_A44_T3, ST_A44_T4, ST_A44_T5, ST_A44_T6, \r
  52 \r
  53     --misc operation.\r
  54     ST_A51_T1, ST_A51_T2,\r
  55     ST_A52_T1, ST_A52_T2, ST_A52_T3,\r
  56     ST_A53_T1, ST_A53_T2, ST_A53_T3,ST_A53_T4, ST_A53_T5,\r
  57     ST_A55_T1, ST_A55_T2, ST_A55_T3, ST_A55_T4, ST_A55_T5,\r
  58     ST_A561_T1, ST_A561_T2,\r
  59     ST_A562_T1, ST_A562_T2, ST_A562_T3, ST_A562_T4,\r
  60     ST_A57_T1, ST_A57_T2, ST_A57_T3, ST_A57_T4, ST_A57_T5,\r
  61     ST_A58_T1, ST_A58_T2, ST_A58_T3,\r
  62 \r
  63     --reset vector.\r
  64     ST_RS_T0, ST_RS_T1, ST_RS_T2, ST_RS_T3, ST_RS_T4, ST_RS_T5, ST_RS_T6, ST_RS_T7\r
  65     );\r
  66 \r
  67 --cpu sub state.\r
  68 --1 cpu clock is split into 8 state.\r
  69 --1 cpu clock = 32 x base clock.\r
  70 type cpu_sub_state is (\r
  71     ST_SUB00, ST_SUB01, ST_SUB02, ST_SUB03,\r
  72     ST_SUB10, ST_SUB11, ST_SUB12, ST_SUB13,\r
  73     ST_SUB20, ST_SUB21, ST_SUB22, ST_SUB23,\r
  74     ST_SUB30, ST_SUB31, ST_SUB32, ST_SUB33,\r
  75     ST_SUB40, ST_SUB41, ST_SUB42, ST_SUB43,\r
  76     ST_SUB50, ST_SUB51, ST_SUB52, ST_SUB53,\r
  77     ST_SUB60, ST_SUB61, ST_SUB62, ST_SUB63,\r
  78     ST_SUB70, ST_SUB71, ST_SUB72, ST_SUB73\r
  79     );\r
  80 \r
  81 signal reg_main_state           : cpu_main_state;\r
  82 signal reg_main_next_state      : cpu_main_state;\r
  83 signal reg_sub_state            : cpu_sub_state;\r
  84 signal reg_sub_next_state       : cpu_sub_state;\r
  85 \r
  86 --6502 register definition...\r
  87 signal reg_inst     : std_logic_vector (7 downto 0);\r
  88 signal reg_acc      : std_logic_vector (7 downto 0);\r
  89 signal reg_x        : std_logic_vector (7 downto 0);\r
  90 signal reg_y        : std_logic_vector (7 downto 0);\r
  91 signal reg_idl_l    : std_logic_vector (7 downto 0);\r
  92 signal reg_idl_h    : std_logic_vector (7 downto 0);\r
  93 signal reg_sp       : std_logic_vector (7 downto 0);\r
  94 signal reg_status   : std_logic_vector (7 downto 0);\r
  95 signal reg_pc_l     : std_logic_vector (7 downto 0);\r
  96 signal reg_pc_h     : std_logic_vector (7 downto 0);\r
  97 \r
  98 --bus i/o reg.\r
  99 signal reg_r_nw     : std_logic;\r
 100 signal reg_addr     : std_logic_vector (15 downto 0);\r
 101 signal reg_d_in     : std_logic_vector (7 downto 0);\r
 102 signal reg_d_out    : std_logic_vector (7 downto 0);\r
 103 \r
 104 \r
 105 begin\r
 106     --state transition process...\r
 107     set_stat_p : process (pi_rst_n, pi_base_clk)\r
 108     begin\r
 109         if (pi_rst_n = '0') then\r
 110             reg_main_state <= ST_IDLE;\r
 111             reg_sub_state <= ST_SUB00;\r
 112         elsif (rising_edge(pi_base_clk)) then\r
 113             reg_main_state <= reg_main_next_state;\r
 114             reg_sub_state <= reg_sub_next_state;\r
 115         end if;--if (pi_rst_n = '0') then\r
 116     end process;\r
 117 \r
 118     --state change to next.\r
 119     tx_next_sub_stat_p : process (reg_sub_state, pi_cpu_en)\r
 120     begin\r
 121         case reg_sub_state is\r
 122             when ST_SUB00 =>\r
 123                 if (pi_cpu_en(0) = '1') then\r
 124                     reg_sub_next_state <= ST_SUB01;\r
 125                 else\r
 126                     reg_sub_next_state <= reg_sub_state;\r
 127                 end if;\r
 128             when ST_SUB01 =>\r
 129                 reg_sub_next_state <= ST_SUB02;\r
 130             when ST_SUB02 =>\r
 131                 reg_sub_next_state <= ST_SUB03;\r
 132             when ST_SUB03 =>\r
 133                 reg_sub_next_state <= ST_SUB10;\r
 134             when ST_SUB10 =>\r
 135                 reg_sub_next_state <= ST_SUB11;\r
 136             when ST_SUB11 =>\r
 137                 reg_sub_next_state <= ST_SUB12;\r
 138             when ST_SUB12 =>\r
 139                 reg_sub_next_state <= ST_SUB13;\r
 140             when ST_SUB13 =>\r
 141                 reg_sub_next_state <= ST_SUB20;\r
 142             when ST_SUB20 =>\r
 143                 reg_sub_next_state <= ST_SUB21;\r
 144             when ST_SUB21 =>\r
 145                 reg_sub_next_state <= ST_SUB22;\r
 146             when ST_SUB22 =>\r
 147                 reg_sub_next_state <= ST_SUB23;\r
 148             when ST_SUB23 =>\r
 149                 reg_sub_next_state <= ST_SUB30;\r
 150             when ST_SUB30 =>\r
 151                 reg_sub_next_state <= ST_SUB31;\r
 152             when ST_SUB31 =>\r
 153                 reg_sub_next_state <= ST_SUB32;\r
 154             when ST_SUB32 =>\r
 155                 reg_sub_next_state <= ST_SUB33;\r
 156             when ST_SUB33 =>\r
 157                 reg_sub_next_state <= ST_SUB40;\r
 158             when ST_SUB40 =>\r
 159                 reg_sub_next_state <= ST_SUB41;\r
 160             when ST_SUB41 =>\r
 161                 reg_sub_next_state <= ST_SUB42;\r
 162             when ST_SUB42 =>\r
 163                 reg_sub_next_state <= ST_SUB43;\r
 164             when ST_SUB43 =>\r
 165                 reg_sub_next_state <= ST_SUB50;\r
 166             when ST_SUB50 =>\r
 167                 reg_sub_next_state <= ST_SUB51;\r
 168             when ST_SUB51 =>\r
 169                 reg_sub_next_state <= ST_SUB52;\r
 170             when ST_SUB52 =>\r
 171                 reg_sub_next_state <= ST_SUB53;\r
 172             when ST_SUB53 =>\r
 173                 reg_sub_next_state <= ST_SUB60;\r
 174             when ST_SUB60 =>\r
 175                 reg_sub_next_state <= ST_SUB61;\r
 176             when ST_SUB61 =>\r
 177                 reg_sub_next_state <= ST_SUB62;\r
 178             when ST_SUB62 =>\r
 179                 reg_sub_next_state <= ST_SUB63;\r
 180             when ST_SUB63 =>\r
 181                 reg_sub_next_state <= ST_SUB70;\r
 182             when ST_SUB70 =>\r
 183                 reg_sub_next_state <= ST_SUB71;\r
 184             when ST_SUB71 =>\r
 185                 reg_sub_next_state <= ST_SUB72;\r
 186             when ST_SUB72 =>\r
 187                 reg_sub_next_state <= ST_SUB73;\r
 188             when ST_SUB73 =>\r
 189                 reg_sub_next_state <= ST_SUB00;\r
 190         end case;\r
 191     end process;\r
 192 \r
 193     --state change to next.\r
 194     tx_next_main_stat_p : process (reg_main_state, reg_sub_state, pi_rst_n)\r
 195 \r
 196 ---fake docode function...\r
 197 variable test_index : integer range 0 to 26 := 0;\r
 198 variable next_inst_state : cpu_main_state;\r
 199 \r
 200 procedure get_next_inst_state is\r
 201 begin\r
 202     if (test_index <= 25) then\r
 203         test_index := test_index + 1;\r
 204     else\r
 205         test_index := 1;\r
 206     end if;\r
 207     \r
 208     if (test_index = 1) then\r
 209         next_inst_state := ST_A1_T1;\r
 210     elsif (test_index = 2) then\r
 211         next_inst_state := ST_A22_T1;\r
 212     elsif (test_index = 3) then\r
 213         next_inst_state := ST_A23_T1;\r
 214     elsif (test_index = 4) then\r
 215         next_inst_state := ST_A24_T1;\r
 216     elsif (test_index = 5) then\r
 217         next_inst_state := ST_A25_T1;\r
 218     elsif (test_index = 6) then\r
 219         next_inst_state := ST_A26_T1;\r
 220     elsif (test_index = 7) then\r
 221         next_inst_state := ST_A27_T1;\r
 222     elsif (test_index = 8) then\r
 223         next_inst_state := ST_A31_T1;\r
 224     elsif (test_index = 9) then\r
 225         next_inst_state := ST_A32_T1;\r
 226     elsif (test_index = 10) then\r
 227         next_inst_state := ST_A33_T1;\r
 228     elsif (test_index = 11) then\r
 229         next_inst_state := ST_A34_T1;\r
 230     elsif (test_index = 12) then\r
 231         next_inst_state := ST_A35_T1;\r
 232     elsif (test_index = 13) then\r
 233         next_inst_state := ST_A36_T1;\r
 234     elsif (test_index = 14) then\r
 235         next_inst_state := ST_A41_T1;\r
 236     elsif (test_index = 15) then\r
 237         next_inst_state := ST_A42_T1;\r
 238     elsif (test_index = 16) then\r
 239         next_inst_state := ST_A43_T1;\r
 240     elsif (test_index = 17) then\r
 241         next_inst_state := ST_A44_T1;\r
 242     elsif (test_index = 18) then\r
 243         next_inst_state := ST_A51_T1;\r
 244     elsif (test_index = 19) then\r
 245         next_inst_state := ST_A52_T1;\r
 246     elsif (test_index = 20) then\r
 247         next_inst_state := ST_A53_T1;\r
 248     elsif (test_index = 21) then\r
 249         next_inst_state := ST_A55_T1;\r
 250     elsif (test_index = 22) then\r
 251         next_inst_state := ST_A561_T1;\r
 252     elsif (test_index = 23) then\r
 253         next_inst_state := ST_A562_T1;\r
 254     elsif (test_index = 24) then\r
 255         next_inst_state := ST_A57_T1;\r
 256     elsif (test_index = 25) then\r
 257         next_inst_state := ST_A58_T1;\r
 258     else\r
 259         next_inst_state := ST_IDLE;\r
 260     end if;\r
 261 end;\r
 262 \r
 263     begin\r
 264         case reg_main_state is\r
 265             -----idle...\r
 266             when ST_IDLE =>\r
 267                 if (pi_rst_n = '0') then\r
 268                     reg_main_next_state <= reg_main_state;\r
 269                 else\r
 270                     reg_main_next_state <= ST_RS_T0;\r
 271                 end if;\r
 272             -----reset...\r
 273             when ST_RS_T0 =>\r
 274                 if (reg_sub_state = ST_SUB73) then\r
 275                     reg_main_next_state <= ST_RS_T1;\r
 276                 else\r
 277                     reg_main_next_state <= reg_main_state;\r
 278                 end if;\r
 279             when ST_RS_T1 =>\r
 280                 if (reg_sub_state = ST_SUB73) then\r
 281                     reg_main_next_state <= ST_RS_T2;\r
 282                 else\r
 283                     reg_main_next_state <= reg_main_state;\r
 284                 end if;\r
 285             when ST_RS_T2 =>\r
 286                 if (reg_sub_state = ST_SUB73) then\r
 287                     reg_main_next_state <= ST_RS_T3;\r
 288                 else\r
 289                     reg_main_next_state <= reg_main_state;\r
 290                 end if;\r
 291             when ST_RS_T3 =>\r
 292                 if (reg_sub_state = ST_SUB73) then\r
 293                     reg_main_next_state <= ST_RS_T4;\r
 294                 else\r
 295                     reg_main_next_state <= reg_main_state;\r
 296                 end if;\r
 297             when ST_RS_T4 =>\r
 298                 if (reg_sub_state = ST_SUB73) then\r
 299                     reg_main_next_state <= ST_RS_T5;\r
 300                 else\r
 301                     reg_main_next_state <= reg_main_state;\r
 302                 end if;\r
 303             when ST_RS_T5 =>\r
 304                 if (reg_sub_state = ST_SUB73) then\r
 305                     reg_main_next_state <= ST_RS_T6;\r
 306                 else\r
 307                     reg_main_next_state <= reg_main_state;\r
 308                 end if;\r
 309             when ST_RS_T6 =>\r
 310                 if (reg_sub_state = ST_SUB73) then\r
 311                     reg_main_next_state <= ST_RS_T7;\r
 312                 else\r
 313                     reg_main_next_state <= reg_main_state;\r
 314                 end if;\r
 315             when ST_RS_T7 =>\r
 316                 if (reg_sub_state = ST_SUB73) then\r
 317                     reg_main_next_state <= ST_CM_T0;\r
 318                 else\r
 319                     reg_main_next_state <= reg_main_state;\r
 320                 end if;\r
 321 \r
 322             --instruction fetch\r
 323             when ST_CM_T0 =>\r
 324                 if (reg_sub_state = ST_SUB73) then\r
 325                     get_next_inst_state;\r
 326                     reg_main_next_state <= next_inst_state;\r
 327                 else\r
 328                     reg_main_next_state <= reg_main_state;\r
 329                 end if;\r
 330 \r
 331             --A1 inst.(single byte)\r
 332             when ST_A1_T1 =>\r
 333                 if (reg_sub_state = ST_SUB73) then\r
 334                     reg_main_next_state <= ST_CM_T0;\r
 335                 else\r
 336                     reg_main_next_state <= reg_main_state;\r
 337                 end if;\r
 338 \r
 339             --A2 inst.\r
 340             when ST_A21_T1 =>\r
 341                 if (reg_sub_state = ST_SUB73) then\r
 342                     reg_main_next_state <= ST_CM_T0;\r
 343                 else\r
 344                     reg_main_next_state <= reg_main_state;\r
 345                 end if;\r
 346             when ST_A22_T1 =>\r
 347                 if (reg_sub_state = ST_SUB73) then\r
 348                     reg_main_next_state <= ST_A22_T2;\r
 349                 else\r
 350                     reg_main_next_state <= reg_main_state;\r
 351                 end if;\r
 352             when ST_A22_T2 =>\r
 353                 if (reg_sub_state = ST_SUB73) then\r
 354                     reg_main_next_state <= ST_CM_T0;\r
 355                 else\r
 356                     reg_main_next_state <= reg_main_state;\r
 357                 end if;\r
 358             when ST_A23_T1 =>\r
 359                 if (reg_sub_state = ST_SUB73) then\r
 360                     reg_main_next_state <= ST_A23_T2;\r
 361                 else\r
 362                     reg_main_next_state <= reg_main_state;\r
 363                 end if;\r
 364             when ST_A23_T2 =>\r
 365                 if (reg_sub_state = ST_SUB73) then\r
 366                     reg_main_next_state <= ST_A23_T3;\r
 367                 else\r
 368                     reg_main_next_state <= reg_main_state;\r
 369                 end if;\r
 370             when ST_A23_T3 =>\r
 371                 if (reg_sub_state = ST_SUB73) then\r
 372                     reg_main_next_state <= ST_CM_T0;\r
 373                 else\r
 374                     reg_main_next_state <= reg_main_state;\r
 375                 end if;\r
 376             when ST_A24_T1 =>\r
 377                 if (reg_sub_state = ST_SUB73) then\r
 378                     reg_main_next_state <= ST_A24_T2;\r
 379                 else\r
 380                     reg_main_next_state <= reg_main_state;\r
 381                 end if;\r
 382             when ST_A24_T2 =>\r
 383                 if (reg_sub_state = ST_SUB73) then\r
 384                     reg_main_next_state <= ST_A24_T3;\r
 385                 else\r
 386                     reg_main_next_state <= reg_main_state;\r
 387                 end if;\r
 388             when ST_A24_T3 =>\r
 389                 if (reg_sub_state = ST_SUB73) then\r
 390                     reg_main_next_state <= ST_A24_T4;\r
 391                 else\r
 392                     reg_main_next_state <= reg_main_state;\r
 393                 end if;\r
 394             when ST_A24_T4 =>\r
 395                 if (reg_sub_state = ST_SUB73) then\r
 396                     reg_main_next_state <= ST_A24_T5;\r
 397                 else\r
 398                     reg_main_next_state <= reg_main_state;\r
 399                 end if;\r
 400             when ST_A24_T5 =>\r
 401                 if (reg_sub_state = ST_SUB73) then\r
 402                     reg_main_next_state <= ST_CM_T0;\r
 403                 else\r
 404                     reg_main_next_state <= reg_main_state;\r
 405                 end if;\r
 406             when ST_A25_T1 =>\r
 407                 if (reg_sub_state = ST_SUB73) then\r
 408                     reg_main_next_state <= ST_A25_T2;\r
 409                 else\r
 410                     reg_main_next_state <= reg_main_state;\r
 411                 end if;\r
 412             when ST_A25_T2 =>\r
 413                 if (reg_sub_state = ST_SUB73) then\r
 414                     reg_main_next_state <= ST_A25_T3;\r
 415                 else\r
 416                     reg_main_next_state <= reg_main_state;\r
 417                 end if;\r
 418             when ST_A25_T3 =>\r
 419                 if (reg_sub_state = ST_SUB73) then\r
 420                     reg_main_next_state <= ST_A25_T4;\r
 421                 else\r
 422                     reg_main_next_state <= reg_main_state;\r
 423                 end if;\r
 424             when ST_A25_T4 =>\r
 425                 if (reg_sub_state = ST_SUB73) then\r
 426                     reg_main_next_state <= ST_CM_T0;\r
 427                 else\r
 428                     reg_main_next_state <= reg_main_state;\r
 429                 end if;\r
 430             when ST_A26_T1 =>\r
 431                 if (reg_sub_state = ST_SUB73) then\r
 432                     reg_main_next_state <= ST_A26_T2;\r
 433                 else\r
 434                     reg_main_next_state <= reg_main_state;\r
 435                 end if;\r
 436             when ST_A26_T2 =>\r
 437                 if (reg_sub_state = ST_SUB73) then\r
 438                     reg_main_next_state <= ST_A26_T3;\r
 439                 else\r
 440                     reg_main_next_state <= reg_main_state;\r
 441                 end if;\r
 442             when ST_A26_T3 =>\r
 443                 if (reg_sub_state = ST_SUB73) then\r
 444                     reg_main_next_state <= ST_CM_T0;\r
 445                 else\r
 446                     reg_main_next_state <= reg_main_state;\r
 447                 end if;\r
 448             when ST_A27_T1 =>\r
 449                 if (reg_sub_state = ST_SUB73) then\r
 450                     reg_main_next_state <= ST_A27_T2;\r
 451                 else\r
 452                     reg_main_next_state <= reg_main_state;\r
 453                 end if;\r
 454             when ST_A27_T2 =>\r
 455                 if (reg_sub_state = ST_SUB73) then\r
 456                     reg_main_next_state <= ST_A27_T3;\r
 457                 else\r
 458                     reg_main_next_state <= reg_main_state;\r
 459                 end if;\r
 460             when ST_A27_T3 =>\r
 461                 if (reg_sub_state = ST_SUB73) then\r
 462                     reg_main_next_state <= ST_A27_T4;\r
 463                 else\r
 464                     reg_main_next_state <= reg_main_state;\r
 465                 end if;\r
 466             when ST_A27_T4 =>\r
 467                 if (reg_sub_state = ST_SUB73) then\r
 468                     reg_main_next_state <= ST_A27_T5;\r
 469                 else\r
 470                     reg_main_next_state <= reg_main_state;\r
 471                 end if;\r
 472             when ST_A27_T5 =>\r
 473                 if (reg_sub_state = ST_SUB73) then\r
 474                     reg_main_next_state <= ST_CM_T0;\r
 475                 else\r
 476                     reg_main_next_state <= reg_main_state;\r
 477                 end if;\r
 478 \r
 479             --A3 inst.\r
 480             when ST_A31_T1 =>\r
 481                 if (reg_sub_state = ST_SUB73) then\r
 482                     reg_main_next_state <= ST_A31_T2;\r
 483                 else\r
 484                     reg_main_next_state <= reg_main_state;\r
 485                 end if;\r
 486             when ST_A31_T2 =>\r
 487                 if (reg_sub_state = ST_SUB73) then\r
 488                     reg_main_next_state <= ST_CM_T0;\r
 489                 else\r
 490                     reg_main_next_state <= reg_main_state;\r
 491                 end if;\r
 492             when ST_A32_T1 =>\r
 493                 if (reg_sub_state = ST_SUB73) then\r
 494                     reg_main_next_state <= ST_A32_T2;\r
 495                 else\r
 496                     reg_main_next_state <= reg_main_state;\r
 497                 end if;\r
 498             when ST_A32_T2 =>\r
 499                 if (reg_sub_state = ST_SUB73) then\r
 500                     reg_main_next_state <= ST_A32_T3;\r
 501                 else\r
 502                     reg_main_next_state <= reg_main_state;\r
 503                 end if;\r
 504             when ST_A32_T3 =>\r
 505                 if (reg_sub_state = ST_SUB73) then\r
 506                     reg_main_next_state <= ST_CM_T0;\r
 507                 else\r
 508                     reg_main_next_state <= reg_main_state;\r
 509                 end if;\r
 510             when ST_A33_T1 =>\r
 511                 if (reg_sub_state = ST_SUB73) then\r
 512                     reg_main_next_state <= ST_A33_T2;\r
 513                 else\r
 514                     reg_main_next_state <= reg_main_state;\r
 515                 end if;\r
 516             when ST_A33_T2 =>\r
 517                 if (reg_sub_state = ST_SUB73) then\r
 518                     reg_main_next_state <= ST_A33_T3;\r
 519                 else\r
 520                     reg_main_next_state <= reg_main_state;\r
 521                 end if;\r
 522             when ST_A33_T3 =>\r
 523                 if (reg_sub_state = ST_SUB73) then\r
 524                     reg_main_next_state <= ST_A33_T4;\r
 525                 else\r
 526                     reg_main_next_state <= reg_main_state;\r
 527                 end if;\r
 528             when ST_A33_T4 =>\r
 529                 if (reg_sub_state = ST_SUB73) then\r
 530                     reg_main_next_state <= ST_A33_T5;\r
 531                 else\r
 532                     reg_main_next_state <= reg_main_state;\r
 533                 end if;\r
 534             when ST_A33_T5 =>\r
 535                 if (reg_sub_state = ST_SUB73) then\r
 536                     reg_main_next_state <= ST_CM_T0;\r
 537                 else\r
 538                     reg_main_next_state <= reg_main_state;\r
 539                 end if;\r
 540             when ST_A34_T1 =>\r
 541                 if (reg_sub_state = ST_SUB73) then\r
 542                     reg_main_next_state <= ST_A34_T2;\r
 543                 else\r
 544                     reg_main_next_state <= reg_main_state;\r
 545                 end if;\r
 546             when ST_A34_T2 =>\r
 547                 if (reg_sub_state = ST_SUB73) then\r
 548                     reg_main_next_state <= ST_A34_T3;\r
 549                 else\r
 550                     reg_main_next_state <= reg_main_state;\r
 551                 end if;\r
 552             when ST_A34_T3 =>\r
 553                 if (reg_sub_state = ST_SUB73) then\r
 554                     reg_main_next_state <= ST_A34_T4;\r
 555                 else\r
 556                     reg_main_next_state <= reg_main_state;\r
 557                 end if;\r
 558             when ST_A34_T4 =>\r
 559                 if (reg_sub_state = ST_SUB73) then\r
 560                     reg_main_next_state <= ST_CM_T0;\r
 561                 else\r
 562                     reg_main_next_state <= reg_main_state;\r
 563                 end if;\r
 564             when ST_A35_T1 =>\r
 565                 if (reg_sub_state = ST_SUB73) then\r
 566                     reg_main_next_state <= ST_A35_T2;\r
 567                 else\r
 568                     reg_main_next_state <= reg_main_state;\r
 569                 end if;\r
 570             when ST_A35_T2 =>\r
 571                 if (reg_sub_state = ST_SUB73) then\r
 572                     reg_main_next_state <= ST_A35_T3;\r
 573                 else\r
 574                     reg_main_next_state <= reg_main_state;\r
 575                 end if;\r
 576             when ST_A35_T3 =>\r
 577                 if (reg_sub_state = ST_SUB73) then\r
 578                     reg_main_next_state <= ST_CM_T0;\r
 579                 else\r
 580                     reg_main_next_state <= reg_main_state;\r
 581                 end if;\r
 582             when ST_A36_T1 =>\r
 583                 if (reg_sub_state = ST_SUB73) then\r
 584                     reg_main_next_state <= ST_A36_T2;\r
 585                 else\r
 586                     reg_main_next_state <= reg_main_state;\r
 587                 end if;\r
 588             when ST_A36_T2 =>\r
 589                 if (reg_sub_state = ST_SUB73) then\r
 590                     reg_main_next_state <= ST_A36_T3;\r
 591                 else\r
 592                     reg_main_next_state <= reg_main_state;\r
 593                 end if;\r
 594             when ST_A36_T3 =>\r
 595                 if (reg_sub_state = ST_SUB73) then\r
 596                     reg_main_next_state <= ST_A36_T4;\r
 597                 else\r
 598                     reg_main_next_state <= reg_main_state;\r
 599                 end if;\r
 600             when ST_A36_T4 =>\r
 601                 if (reg_sub_state = ST_SUB73) then\r
 602                     reg_main_next_state <= ST_A36_T5;\r
 603                 else\r
 604                     reg_main_next_state <= reg_main_state;\r
 605                 end if;\r
 606             when ST_A36_T5 =>\r
 607                 if (reg_sub_state = ST_SUB73) then\r
 608                     reg_main_next_state <= ST_CM_T0;\r
 609                 else\r
 610                     reg_main_next_state <= reg_main_state;\r
 611                 end if;\r
 612 \r
 613 \r
 614             --A4 inst.\r
 615             when ST_A41_T1 =>\r
 616                 if (reg_sub_state = ST_SUB73) then\r
 617                     reg_main_next_state <= ST_A41_T2;\r
 618                 else\r
 619                     reg_main_next_state <= reg_main_state;\r
 620                 end if;\r
 621             when ST_A41_T2 =>\r
 622                 if (reg_sub_state = ST_SUB73) then\r
 623                     reg_main_next_state <= ST_A41_T3;\r
 624                 else\r
 625                     reg_main_next_state <= reg_main_state;\r
 626                 end if;\r
 627             when ST_A41_T3 =>\r
 628                 if (reg_sub_state = ST_SUB73) then\r
 629                     reg_main_next_state <= ST_A41_T4;\r
 630                 else\r
 631                     reg_main_next_state <= reg_main_state;\r
 632                 end if;\r
 633             when ST_A41_T4 =>\r
 634                 if (reg_sub_state = ST_SUB73) then\r
 635                     reg_main_next_state <= ST_CM_T0;\r
 636                 else\r
 637                     reg_main_next_state <= reg_main_state;\r
 638                 end if;\r
 639             when ST_A42_T1 =>\r
 640                 if (reg_sub_state = ST_SUB73) then\r
 641                     reg_main_next_state <= ST_A42_T2;\r
 642                 else\r
 643                     reg_main_next_state <= reg_main_state;\r
 644                 end if;\r
 645             when ST_A42_T2 =>\r
 646                 if (reg_sub_state = ST_SUB73) then\r
 647                     reg_main_next_state <= ST_A42_T3;\r
 648                 else\r
 649                     reg_main_next_state <= reg_main_state;\r
 650                 end if;\r
 651             when ST_A42_T3 =>\r
 652                 if (reg_sub_state = ST_SUB73) then\r
 653                     reg_main_next_state <= ST_A42_T4;\r
 654                 else\r
 655                     reg_main_next_state <= reg_main_state;\r
 656                 end if;\r
 657             when ST_A42_T4 =>\r
 658                 if (reg_sub_state = ST_SUB73) then\r
 659                     reg_main_next_state <= ST_A42_T5;\r
 660                 else\r
 661                     reg_main_next_state <= reg_main_state;\r
 662                 end if;\r
 663             when ST_A42_T5 =>\r
 664                 if (reg_sub_state = ST_SUB73) then\r
 665                     reg_main_next_state <= ST_CM_T0;\r
 666                 else\r
 667                     reg_main_next_state <= reg_main_state;\r
 668                 end if;\r
 669             when ST_A43_T1 =>\r
 670                 if (reg_sub_state = ST_SUB73) then\r
 671                     reg_main_next_state <= ST_A43_T2;\r
 672                 else\r
 673                     reg_main_next_state <= reg_main_state;\r
 674                 end if;\r
 675             when ST_A43_T2 =>\r
 676                 if (reg_sub_state = ST_SUB73) then\r
 677                     reg_main_next_state <= ST_CM_T0;\r
 678                 else\r
 679                     reg_main_next_state <= reg_main_state;\r
 680                 end if;\r
 681             when ST_A43_T3 =>\r
 682                 if (reg_sub_state = ST_SUB73) then\r
 683                     reg_main_next_state <= ST_A43_T4;\r
 684                 else\r
 685                     reg_main_next_state <= reg_main_state;\r
 686                 end if;\r
 687             when ST_A43_T4 =>\r
 688                 if (reg_sub_state = ST_SUB73) then\r
 689                     reg_main_next_state <= ST_A43_T5;\r
 690                 else\r
 691                     reg_main_next_state <= reg_main_state;\r
 692                 end if;\r
 693             when ST_A43_T5 =>\r
 694                 if (reg_sub_state = ST_SUB73) then\r
 695                     reg_main_next_state <= ST_CM_T0;\r
 696                 else\r
 697                     reg_main_next_state <= reg_main_state;\r
 698                 end if;\r
 699             when ST_A44_T1 =>\r
 700                 if (reg_sub_state = ST_SUB73) then\r
 701                     reg_main_next_state <= ST_A44_T2;\r
 702                 else\r
 703                     reg_main_next_state <= reg_main_state;\r
 704                 end if;\r
 705             when ST_A44_T2 =>\r
 706                 if (reg_sub_state = ST_SUB73) then\r
 707                     reg_main_next_state <= ST_A44_T3;\r
 708                 else\r
 709                     reg_main_next_state <= reg_main_state;\r
 710                 end if;\r
 711             when ST_A44_T3 =>\r
 712                 if (reg_sub_state = ST_SUB73) then\r
 713                     reg_main_next_state <= ST_A44_T4;\r
 714                 else\r
 715                     reg_main_next_state <= reg_main_state;\r
 716                 end if;\r
 717             when ST_A44_T4 =>\r
 718                 if (reg_sub_state = ST_SUB73) then\r
 719                     reg_main_next_state <= ST_A44_T5;\r
 720                 else\r
 721                     reg_main_next_state <= reg_main_state;\r
 722                 end if;\r
 723             when ST_A44_T5 =>\r
 724                 if (reg_sub_state = ST_SUB73) then\r
 725                     reg_main_next_state <= ST_A44_T6;\r
 726                 else\r
 727                     reg_main_next_state <= reg_main_state;\r
 728                 end if;\r
 729             when ST_A44_T6 =>\r
 730                 if (reg_sub_state = ST_SUB73) then\r
 731                     reg_main_next_state <= ST_CM_T0;\r
 732                 else\r
 733                     reg_main_next_state <= reg_main_state;\r
 734                 end if;\r
 735 \r
 736 \r
 737             --A5 inst.\r
 738             when ST_A51_T1 =>\r
 739                 if (reg_sub_state = ST_SUB73) then\r
 740                     reg_main_next_state <= ST_A51_T2;\r
 741                 else\r
 742                     reg_main_next_state <= reg_main_state;\r
 743                 end if;\r
 744             when ST_A51_T2 =>\r
 745                 if (reg_sub_state = ST_SUB73) then\r
 746                     reg_main_next_state <= ST_CM_T0;\r
 747                 else\r
 748                     reg_main_next_state <= reg_main_state;\r
 749                 end if;\r
 750             when ST_A52_T1 =>\r
 751                 if (reg_sub_state = ST_SUB73) then\r
 752                     reg_main_next_state <= ST_A52_T2;\r
 753                 else\r
 754                     reg_main_next_state <= reg_main_state;\r
 755                 end if;\r
 756             when ST_A52_T2 =>\r
 757                 if (reg_sub_state = ST_SUB73) then\r
 758                     reg_main_next_state <= ST_A52_T3;\r
 759                 else\r
 760                     reg_main_next_state <= reg_main_state;\r
 761                 end if;\r
 762             when ST_A52_T3 =>\r
 763                 if (reg_sub_state = ST_SUB73) then\r
 764                     reg_main_next_state <= ST_CM_T0;\r
 765                 else\r
 766                     reg_main_next_state <= reg_main_state;\r
 767                 end if;\r
 768             when ST_A53_T1 =>\r
 769                 if (reg_sub_state = ST_SUB73) then\r
 770                     reg_main_next_state <= ST_A53_T2;\r
 771                 else\r
 772                     reg_main_next_state <= reg_main_state;\r
 773                 end if;\r
 774             when ST_A53_T2 =>\r
 775                 if (reg_sub_state = ST_SUB73) then\r
 776                     reg_main_next_state <= ST_A53_T3;\r
 777                 else\r
 778                     reg_main_next_state <= reg_main_state;\r
 779                 end if;\r
 780             when ST_A53_T3 =>\r
 781                 if (reg_sub_state = ST_SUB73) then\r
 782                     reg_main_next_state <= ST_A53_T4;\r
 783                 else\r
 784                     reg_main_next_state <= reg_main_state;\r
 785                 end if;\r
 786             when ST_A53_T4 =>\r
 787                 if (reg_sub_state = ST_SUB73) then\r
 788                     reg_main_next_state <= ST_A53_T5;\r
 789                 else\r
 790                     reg_main_next_state <= reg_main_state;\r
 791                 end if;\r
 792             when ST_A53_T5 =>\r
 793                 if (reg_sub_state = ST_SUB73) then\r
 794                     reg_main_next_state <= ST_CM_T0;\r
 795                 else\r
 796                     reg_main_next_state <= reg_main_state;\r
 797                 end if;\r
 798             when ST_A55_T1 =>\r
 799                 if (reg_sub_state = ST_SUB73) then\r
 800                     reg_main_next_state <= ST_A55_T2;\r
 801                 else\r
 802                     reg_main_next_state <= reg_main_state;\r
 803                 end if;\r
 804             when ST_A55_T2 =>\r
 805                 if (reg_sub_state = ST_SUB73) then\r
 806                     reg_main_next_state <= ST_A55_T3;\r
 807                 else\r
 808                     reg_main_next_state <= reg_main_state;\r
 809                 end if;\r
 810             when ST_A55_T3 =>\r
 811                 if (reg_sub_state = ST_SUB73) then\r
 812                     reg_main_next_state <= ST_A55_T4;\r
 813                 else\r
 814                     reg_main_next_state <= reg_main_state;\r
 815                 end if;\r
 816             when ST_A55_T4 =>\r
 817                 if (reg_sub_state = ST_SUB73) then\r
 818                     reg_main_next_state <= ST_A55_T5;\r
 819                 else\r
 820                     reg_main_next_state <= reg_main_state;\r
 821                 end if;\r
 822             when ST_A55_T5 =>\r
 823                 if (reg_sub_state = ST_SUB73) then\r
 824                     reg_main_next_state <= ST_CM_T0;\r
 825                 else\r
 826                     reg_main_next_state <= reg_main_state;\r
 827                 end if;\r
 828             when ST_A561_T1 =>\r
 829                 if (reg_sub_state = ST_SUB73) then\r
 830                     reg_main_next_state <= ST_A561_T2;\r
 831                 else\r
 832                     reg_main_next_state <= reg_main_state;\r
 833                 end if;\r
 834             when ST_A561_T2 =>\r
 835                 if (reg_sub_state = ST_SUB73) then\r
 836                     reg_main_next_state <= ST_CM_T0;\r
 837                 else\r
 838                     reg_main_next_state <= reg_main_state;\r
 839                 end if;\r
 840             when ST_A562_T1 =>\r
 841                 if (reg_sub_state = ST_SUB73) then\r
 842                     reg_main_next_state <= ST_A562_T2;\r
 843                 else\r
 844                     reg_main_next_state <= reg_main_state;\r
 845                 end if;\r
 846             when ST_A562_T2 =>\r
 847                 if (reg_sub_state = ST_SUB73) then\r
 848                     reg_main_next_state <= ST_A562_T3;\r
 849                 else\r
 850                     reg_main_next_state <= reg_main_state;\r
 851                 end if;\r
 852             when ST_A562_T3 =>\r
 853                 if (reg_sub_state = ST_SUB73) then\r
 854                     reg_main_next_state <= ST_A562_T4;\r
 855                 else\r
 856                     reg_main_next_state <= reg_main_state;\r
 857                 end if;\r
 858             when ST_A562_T4 =>\r
 859                 if (reg_sub_state = ST_SUB73) then\r
 860                     reg_main_next_state <= ST_CM_T0;\r
 861                 else\r
 862                     reg_main_next_state <= reg_main_state;\r
 863                 end if;\r
 864             when ST_A57_T1 =>\r
 865                 if (reg_sub_state = ST_SUB73) then\r
 866                     reg_main_next_state <= ST_A57_T2;\r
 867                 else\r
 868                     reg_main_next_state <= reg_main_state;\r
 869                 end if;\r
 870             when ST_A57_T2 =>\r
 871                 if (reg_sub_state = ST_SUB73) then\r
 872                     reg_main_next_state <= ST_A57_T3;\r
 873                 else\r
 874                     reg_main_next_state <= reg_main_state;\r
 875                 end if;\r
 876             when ST_A57_T3 =>\r
 877                 if (reg_sub_state = ST_SUB73) then\r
 878                     reg_main_next_state <= ST_A57_T4;\r
 879                 else\r
 880                     reg_main_next_state <= reg_main_state;\r
 881                 end if;\r
 882             when ST_A57_T4 =>\r
 883                 if (reg_sub_state = ST_SUB73) then\r
 884                     reg_main_next_state <= ST_A57_T5;\r
 885                 else\r
 886                     reg_main_next_state <= reg_main_state;\r
 887                 end if;\r
 888             when ST_A57_T5 =>\r
 889                 if (reg_sub_state = ST_SUB73) then\r
 890                     reg_main_next_state <= ST_CM_T0;\r
 891                 else\r
 892                     reg_main_next_state <= reg_main_state;\r
 893                 end if;\r
 894             when ST_A58_T1 =>\r
 895                 if (reg_sub_state = ST_SUB73) then\r
 896                     reg_main_next_state <= ST_A58_T2;\r
 897                 else\r
 898                     reg_main_next_state <= reg_main_state;\r
 899                 end if;\r
 900             when ST_A58_T2 =>\r
 901                 if (reg_sub_state = ST_SUB73) then\r
 902                     reg_main_next_state <= ST_A58_T3;\r
 903                 else\r
 904                     reg_main_next_state <= reg_main_state;\r
 905                 end if;\r
 906             when ST_A58_T3 =>\r
 907                 if (reg_sub_state = ST_SUB73) then\r
 908                     reg_main_next_state <= ST_CM_T0;\r
 909                 else\r
 910                     reg_main_next_state <= reg_main_state;\r
 911                 end if;\r
 912 \r
 913 --            ---not ready yet...\r
 914 --            when others =>\r
 915 --                reg_main_next_state <= reg_main_state;\r
 916         end case;\r
 917     end process;\r
 918 \r
 919     --addressing general process...\r
 920     --pc, io bus, r/w, instruction regs...\r
 921     ad_general_p : process (pi_rst_n, pi_base_clk)\r
 922     begin\r
 923         if (pi_rst_n = '0') then\r
 924             reg_pc_l    <= (others => '0');\r
 925             reg_pc_h    <= (others => '0');\r
 926             reg_addr    <= (others => 'Z');\r
 927             reg_d_out   <= (others => 'Z');\r
 928             reg_r_nw    <= 'Z';\r
 929         elsif (rising_edge(pi_base_clk)) then\r
 930             if (reg_main_state = ST_RS_T0) then\r
 931                 reg_pc_l    <= (others => '0');\r
 932                 reg_pc_h    <= (others => '0');\r
 933                 reg_inst    <= (others => '0');\r
 934                 reg_addr    <= (others => '0');\r
 935                 reg_d_out   <= (others => 'Z');\r
 936                 reg_r_nw    <= '1';\r
 937             elsif (reg_main_state = ST_RS_T6) then\r
 938                 --reset vector low...\r
 939                 reg_addr    <= "1111111111111100";\r
 940                 reg_d_out   <= (others => 'Z');\r
 941                 reg_r_nw    <= '1';\r
 942                 reg_pc_l    <= reg_d_in;\r
 943             elsif (reg_main_state = ST_RS_T7) then\r
 944                 --reset vector high...\r
 945                 reg_addr    <= "1111111111111101";\r
 946                 reg_d_out   <= (others => 'Z');\r
 947                 reg_r_nw    <= '1';\r
 948                 reg_pc_h    <= reg_d_in;\r
 949             elsif (reg_main_state = ST_CM_T0) then\r
 950                 if (reg_sub_state = ST_SUB00) then\r
 951                     reg_addr    <= reg_pc_h & reg_pc_l;\r
 952                     reg_d_out   <= (others => 'Z');\r
 953                     reg_r_nw    <= '1';\r
 954                 elsif (reg_sub_state = ST_SUB60) then\r
 955                     reg_inst    <= reg_d_in;\r
 956                 elsif (reg_sub_state = ST_SUB70) then\r
 957                     reg_pc_l    <= reg_pc_l + 1;\r
 958                 end if;\r
 959             end if;\r
 960         end if;--if (pi_rst_n = '0') then\r
 961     end process;\r
 962 \r
 963     po_r_nw     <= reg_r_nw;\r
 964     po_addr     <= reg_addr;\r
 965     pio_d_io    <= reg_d_out;\r
 966     reg_d_in    <= pio_d_io;\r
 967 \r
 968 end rtl;\r
 969 \r