de0_cv_nes/mos6502.vhd

   1 library ieee;\r
   2 use ieee.std_logic_1164.all;\r
   3 use ieee.std_logic_unsigned.all;\r
   4 \r
   5 entity mos6502 is \r
   6     port (  \r
   7             pi_rst_n       : in std_logic;\r
   8             pi_base_clk         : in std_logic;\r
   9             pi_cpu_en       : in std_logic_vector (7 downto 0);\r
  10             pi_rdy         : in std_logic;\r
  11             pi_irq_n       : in std_logic;\r
  12             pi_nmi_n       : in std_logic;\r
  13             po_r_nw        : out std_logic;\r
  14             po_addr        : out std_logic_vector ( 15 downto 0);\r
  15             pio_d_io       : inout std_logic_vector ( 7 downto 0)\r
  16     );\r
  17 end mos6502;\r
  18 \r
  19 architecture rtl of mos6502 is\r
  20 \r
  21 ---cpu main state:\r
  22 type cpu_main_state is (\r
  23     --common state. idle and inst fetch.\r
  24     ST_IDLE,\r
  25     ST_CM_T0,\r
  26 \r
  27     --single byte inst execute.\r
  28     ST_A1_T1,\r
  29 \r
  30     --mem data operation\r
  31     --imm\r
  32     ST_A21_T1,\r
  33     --zp\r
  34     ST_A22_T1, ST_A22_T2,\r
  35     --abs\r
  36     ST_A23_T1, ST_A23_T2, ST_A23_T3,\r
  37     --indir, x\r
  38     ST_A24_T1, ST_A24_T2, ST_A24_T3, ST_A24_T4, ST_A24_T5,\r
  39     --abs xy\r
  40     ST_A25_T1, ST_A25_T2, ST_A25_T3, ST_A25_T4,\r
  41     --zp xy\r
  42     ST_A26_T1, ST_A26_T2, ST_A26_T3,\r
  43     --indir, y\r
  44     ST_A27_T1, ST_A27_T2, ST_A27_T3, ST_A27_T4, ST_A27_T5,\r
  45 \r
  46     --store op.\r
  47     --zp\r
  48     ST_A31_T1, ST_A31_T2,\r
  49     --abs\r
  50     ST_A32_T1, ST_A32_T2, ST_A32_T3,\r
  51     --indir, x\r
  52     ST_A33_T1, ST_A33_T2, ST_A33_T3, ST_A33_T4, ST_A33_T5,\r
  53     --abs xy\r
  54     ST_A34_T1, ST_A34_T2, ST_A34_T3, ST_A34_T4,\r
  55     --zp xy\r
  56     ST_A35_T1, ST_A35_T2, ST_A35_T3,\r
  57     --indir, y\r
  58     ST_A36_T1, ST_A36_T2, ST_A36_T3, ST_A36_T4, ST_A36_T5,\r
  59 \r
  60     --memory to memory op.\r
  61     --zp\r
  62     ST_A41_T1, ST_A41_T2, ST_A41_T3, ST_A41_T4,\r
  63     --abs\r
  64     ST_A42_T1, ST_A42_T2, ST_A42_T3, ST_A42_T4, ST_A42_T5,\r
  65     --zp x\r
  66     ST_A43_T1, ST_A43_T2, ST_A43_T3, ST_A43_T4, ST_A43_T5,\r
  67     --abs x\r
  68     ST_A44_T1, ST_A44_T2, ST_A44_T3, ST_A44_T4, ST_A44_T5, ST_A44_T6, \r
  69 \r
  70     --misc operation.\r
  71     --push\r
  72     ST_A51_T1, ST_A51_T2,\r
  73     --pull\r
  74     ST_A52_T1, ST_A52_T2, ST_A52_T3,\r
  75     --jmp\r
  76     ST_A53_T1, ST_A53_T2, ST_A53_T3,ST_A53_T4, ST_A53_T5,\r
  77     --rti\r
  78     ST_A55_T1, ST_A55_T2, ST_A55_T3, ST_A55_T4, ST_A55_T5,\r
  79     --jmp abs\r
  80     ST_A561_T1, ST_A561_T2,\r
  81     --jmp indir\r
  82     ST_A562_T1, ST_A562_T2, ST_A562_T3, ST_A562_T4,\r
  83     --rts\r
  84     ST_A57_T1, ST_A57_T2, ST_A57_T3, ST_A57_T4, ST_A57_T5,\r
  85     --branch\r
  86     ST_A58_T1, ST_A58_T2, ST_A58_T3,\r
  87 \r
  88     --reset vector.\r
  89     ST_RS_T0, ST_RS_T1, ST_RS_T2, ST_RS_T3, ST_RS_T4, ST_RS_T5, ST_RS_T6, ST_RS_T7,\r
  90 \r
  91     --invalid state\r
  92     ST_INV\r
  93     );\r
  94 \r
  95 --cpu sub state.\r
  96 --1 cpu clock is split into 8 state.\r
  97 --1 cpu clock = 32 x base clock.\r
  98 type cpu_sub_state is (\r
  99     ST_SUB00, ST_SUB01, ST_SUB02, ST_SUB03,\r
 100     ST_SUB10, ST_SUB11, ST_SUB12, ST_SUB13,\r
 101     ST_SUB20, ST_SUB21, ST_SUB22, ST_SUB23,\r
 102     ST_SUB30, ST_SUB31, ST_SUB32, ST_SUB33,\r
 103     ST_SUB40, ST_SUB41, ST_SUB42, ST_SUB43,\r
 104     ST_SUB50, ST_SUB51, ST_SUB52, ST_SUB53,\r
 105     ST_SUB60, ST_SUB61, ST_SUB62, ST_SUB63,\r
 106     ST_SUB70, ST_SUB71, ST_SUB72, ST_SUB73\r
 107     );\r
 108 \r
 109 --Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc. \r
 110 --The aaa and cc bits determine the opcode, and the bbb bits determine the addressing mode.\r
 111 type cpu_state_array    is array (0 to 255) of cpu_main_state;\r
 112 constant inst_decode_rom : cpu_state_array := (\r
 113     --00 - 07\r
 114     ST_INV,     ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_INV,     ST_INV,\r
 115     --08 - 0f\r
 116     ST_INV,     ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_INV,     ST_A23_T1,  ST_INV,     ST_INV,\r
 117     --10 - 17\r
 118     ST_INV,     ST_A27_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_INV,\r
 119     --18 - 1f\r
 120     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_INV,     ST_INV,\r
 121     --20 - 27\r
 122     ST_INV,     ST_A24_T1,  ST_INV,     ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_INV,     ST_INV,\r
 123     --28 - 2f\r
 124     ST_INV,     ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_INV,     ST_INV,\r
 125     --30 - 37\r
 126     ST_INV,     ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_INV,     ST_INV,\r
 127     --38 - 3f\r
 128     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_INV,     ST_INV,\r
 129     --40 - 47\r
 130     ST_INV,     ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_INV,     ST_INV,\r
 131     --48 - 4f\r
 132     ST_INV,     ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_INV,     ST_A23_T1,  ST_INV,     ST_INV,\r
 133     --50 - 57\r
 134     ST_INV,     ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_INV,     ST_INV,\r
 135     --58 - 5f\r
 136     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_INV,     ST_INV,\r
 137     --60 - 67\r
 138     ST_INV,     ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_INV,     ST_INV,\r
 139     --68 - 6f\r
 140     ST_INV,     ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_INV,     ST_A23_T1,  ST_INV,     ST_INV,\r
 141     --70 - 77\r
 142     ST_INV,     ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_INV,     ST_INV,\r
 143     --78 - 7f\r
 144     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_INV,     ST_INV,\r
 145     --80 - 87\r
 146     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,\r
 147     --88 - 8f\r
 148     ST_A1_T1,   ST_INV,     ST_A1_T1,   ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,\r
 149     --90 - 97\r
 150     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,\r
 151     --98 - 9f\r
 152     ST_A1_T1,   ST_INV,     ST_A1_T1,   ST_INV,     ST_INV,     ST_INV,     ST_INV,     ST_INV,\r
 153     --a0 - a7\r
 154     ST_A21_T1,  ST_A24_T1,  ST_A21_T1,  ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_A22_T1,  ST_INV,\r
 155     --a8 - af\r
 156     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A23_T1,  ST_INV,\r
 157     --b0 - b7\r
 158     ST_INV,     ST_A27_T1,  ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A26_T1,  ST_INV,     ST_INV,\r
 159     --b8 - bf\r
 160     ST_A1_T1,   ST_A25_T1,  ST_A1_T1,   ST_INV,     ST_A25_T1,  ST_A25_T1,  ST_A25_T1,  ST_INV,\r
 161     --c0 - c7\r
 162     ST_A21_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A22_T1,  ST_INV,     ST_INV,\r
 163     --c8 - cf\r
 164     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_INV,     ST_INV,\r
 165     --d0 - d7\r
 166     ST_INV,     ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_INV,     ST_INV,\r
 167     --d8 - df\r
 168     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_INV,     ST_INV,\r
 169     --e0 - e7\r
 170     ST_A21_T1,  ST_A24_T1,  ST_INV,     ST_INV,     ST_A22_T1,  ST_A22_T1,  ST_INV,     ST_INV,\r
 171     --e8 - ef\r
 172     ST_A1_T1,   ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_INV,     ST_INV,\r
 173     --f0 - f7\r
 174     ST_INV,     ST_A27_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_INV,\r
 175     --f8 - ff\r
 176     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_INV,     ST_INV\r
 177 );\r
 178 \r
 179 signal reg_main_state           : cpu_main_state;\r
 180 signal reg_main_next_state      : cpu_main_state;\r
 181 signal reg_sub_state            : cpu_sub_state;\r
 182 signal reg_sub_next_state       : cpu_sub_state;\r
 183 \r
 184 --6502 register definition...\r
 185 signal reg_inst     : std_logic_vector (7 downto 0);\r
 186 signal reg_acc      : std_logic_vector (7 downto 0);\r
 187 signal reg_x        : std_logic_vector (7 downto 0);\r
 188 signal reg_y        : std_logic_vector (7 downto 0);\r
 189 signal reg_idl_l    : std_logic_vector (7 downto 0);\r
 190 signal reg_idl_h    : std_logic_vector (7 downto 0);\r
 191 signal reg_sp       : std_logic_vector (7 downto 0);\r
 192 signal reg_status   : std_logic_vector (7 downto 0);\r
 193 signal reg_pc_l     : std_logic_vector (7 downto 0);\r
 194 signal reg_pc_h     : std_logic_vector (7 downto 0);\r
 195 \r
 196 --bus i/o reg.\r
 197 signal reg_r_nw     : std_logic;\r
 198 signal reg_addr     : std_logic_vector (15 downto 0);\r
 199 signal reg_d_in     : std_logic_vector (7 downto 0);\r
 200 signal reg_d_out    : std_logic_vector (7 downto 0);\r
 201 \r
 202 \r
 203 begin\r
 204     --state transition process...\r
 205     set_stat_p : process (pi_rst_n, pi_base_clk)\r
 206     begin\r
 207         if (pi_rst_n = '0') then\r
 208             reg_main_state <= ST_IDLE;\r
 209             reg_sub_state <= ST_SUB00;\r
 210         elsif (rising_edge(pi_base_clk)) then\r
 211             reg_main_state <= reg_main_next_state;\r
 212             reg_sub_state <= reg_sub_next_state;\r
 213         end if;--if (pi_rst_n = '0') then\r
 214     end process;\r
 215 \r
 216     --state change to next.\r
 217     tx_next_sub_stat_p : process (reg_sub_state, pi_cpu_en)\r
 218     begin\r
 219         case reg_sub_state is\r
 220             when ST_SUB00 =>\r
 221                 if (pi_cpu_en(0) = '1') then\r
 222                     reg_sub_next_state <= ST_SUB01;\r
 223                 else\r
 224                     reg_sub_next_state <= reg_sub_state;\r
 225                 end if;\r
 226             when ST_SUB01 =>\r
 227                 reg_sub_next_state <= ST_SUB02;\r
 228             when ST_SUB02 =>\r
 229                 reg_sub_next_state <= ST_SUB03;\r
 230             when ST_SUB03 =>\r
 231                 reg_sub_next_state <= ST_SUB10;\r
 232             when ST_SUB10 =>\r
 233                 reg_sub_next_state <= ST_SUB11;\r
 234             when ST_SUB11 =>\r
 235                 reg_sub_next_state <= ST_SUB12;\r
 236             when ST_SUB12 =>\r
 237                 reg_sub_next_state <= ST_SUB13;\r
 238             when ST_SUB13 =>\r
 239                 reg_sub_next_state <= ST_SUB20;\r
 240             when ST_SUB20 =>\r
 241                 reg_sub_next_state <= ST_SUB21;\r
 242             when ST_SUB21 =>\r
 243                 reg_sub_next_state <= ST_SUB22;\r
 244             when ST_SUB22 =>\r
 245                 reg_sub_next_state <= ST_SUB23;\r
 246             when ST_SUB23 =>\r
 247                 reg_sub_next_state <= ST_SUB30;\r
 248             when ST_SUB30 =>\r
 249                 reg_sub_next_state <= ST_SUB31;\r
 250             when ST_SUB31 =>\r
 251                 reg_sub_next_state <= ST_SUB32;\r
 252             when ST_SUB32 =>\r
 253                 reg_sub_next_state <= ST_SUB33;\r
 254             when ST_SUB33 =>\r
 255                 reg_sub_next_state <= ST_SUB40;\r
 256             when ST_SUB40 =>\r
 257                 reg_sub_next_state <= ST_SUB41;\r
 258             when ST_SUB41 =>\r
 259                 reg_sub_next_state <= ST_SUB42;\r
 260             when ST_SUB42 =>\r
 261                 reg_sub_next_state <= ST_SUB43;\r
 262             when ST_SUB43 =>\r
 263                 reg_sub_next_state <= ST_SUB50;\r
 264             when ST_SUB50 =>\r
 265                 reg_sub_next_state <= ST_SUB51;\r
 266             when ST_SUB51 =>\r
 267                 reg_sub_next_state <= ST_SUB52;\r
 268             when ST_SUB52 =>\r
 269                 reg_sub_next_state <= ST_SUB53;\r
 270             when ST_SUB53 =>\r
 271                 reg_sub_next_state <= ST_SUB60;\r
 272             when ST_SUB60 =>\r
 273                 reg_sub_next_state <= ST_SUB61;\r
 274             when ST_SUB61 =>\r
 275                 reg_sub_next_state <= ST_SUB62;\r
 276             when ST_SUB62 =>\r
 277                 reg_sub_next_state <= ST_SUB63;\r
 278             when ST_SUB63 =>\r
 279                 reg_sub_next_state <= ST_SUB70;\r
 280             when ST_SUB70 =>\r
 281                 reg_sub_next_state <= ST_SUB71;\r
 282             when ST_SUB71 =>\r
 283                 reg_sub_next_state <= ST_SUB72;\r
 284             when ST_SUB72 =>\r
 285                 reg_sub_next_state <= ST_SUB73;\r
 286             when ST_SUB73 =>\r
 287                 reg_sub_next_state <= ST_SUB00;\r
 288         end case;\r
 289     end process;\r
 290 \r
 291     --state change to next.\r
 292     tx_next_main_stat_p : process (reg_main_state, reg_sub_state, pi_rst_n)\r
 293 \r
 294     begin\r
 295         case reg_main_state is\r
 296             -----idle...\r
 297             when ST_IDLE =>\r
 298                 if (pi_rst_n = '0') then\r
 299                     reg_main_next_state <= reg_main_state;\r
 300                 else\r
 301                     reg_main_next_state <= ST_RS_T0;\r
 302                 end if;\r
 303             -----reset...\r
 304             when ST_RS_T0 =>\r
 305                 if (reg_sub_state = ST_SUB73) then\r
 306                     reg_main_next_state <= ST_RS_T1;\r
 307                 else\r
 308                     reg_main_next_state <= reg_main_state;\r
 309                 end if;\r
 310             when ST_RS_T1 =>\r
 311                 if (reg_sub_state = ST_SUB73) then\r
 312                     reg_main_next_state <= ST_RS_T2;\r
 313                 else\r
 314                     reg_main_next_state <= reg_main_state;\r
 315                 end if;\r
 316             when ST_RS_T2 =>\r
 317                 if (reg_sub_state = ST_SUB73) then\r
 318                     reg_main_next_state <= ST_RS_T3;\r
 319                 else\r
 320                     reg_main_next_state <= reg_main_state;\r
 321                 end if;\r
 322             when ST_RS_T3 =>\r
 323                 if (reg_sub_state = ST_SUB73) then\r
 324                     reg_main_next_state <= ST_RS_T4;\r
 325                 else\r
 326                     reg_main_next_state <= reg_main_state;\r
 327                 end if;\r
 328             when ST_RS_T4 =>\r
 329                 if (reg_sub_state = ST_SUB73) then\r
 330                     reg_main_next_state <= ST_RS_T5;\r
 331                 else\r
 332                     reg_main_next_state <= reg_main_state;\r
 333                 end if;\r
 334             when ST_RS_T5 =>\r
 335                 if (reg_sub_state = ST_SUB73) then\r
 336                     reg_main_next_state <= ST_RS_T6;\r
 337                 else\r
 338                     reg_main_next_state <= reg_main_state;\r
 339                 end if;\r
 340             when ST_RS_T6 =>\r
 341                 if (reg_sub_state = ST_SUB73) then\r
 342                     reg_main_next_state <= ST_RS_T7;\r
 343                 else\r
 344                     reg_main_next_state <= reg_main_state;\r
 345                 end if;\r
 346             when ST_RS_T7 =>\r
 347                 if (reg_sub_state = ST_SUB73) then\r
 348                     reg_main_next_state <= ST_CM_T0;\r
 349                 else\r
 350                     reg_main_next_state <= reg_main_state;\r
 351                 end if;\r
 352 \r
 353             --instruction fetch\r
 354             when ST_CM_T0 =>\r
 355                 if (reg_sub_state = ST_SUB73) then\r
 356                     ---instruction decode next state.\r
 357                     reg_main_next_state <= inst_decode_rom(conv_integer(reg_inst));\r
 358                 else\r
 359                     reg_main_next_state <= reg_main_state;\r
 360                 end if;\r
 361 \r
 362             --A1 inst.(single byte)\r
 363             when ST_A1_T1 =>\r
 364                 if (reg_sub_state = ST_SUB73) then\r
 365                     reg_main_next_state <= ST_CM_T0;\r
 366                 else\r
 367                     reg_main_next_state <= reg_main_state;\r
 368                 end if;\r
 369 \r
 370             --A2 inst.\r
 371             when ST_A21_T1 =>\r
 372                 if (reg_sub_state = ST_SUB73) then\r
 373                     reg_main_next_state <= ST_CM_T0;\r
 374                 else\r
 375                     reg_main_next_state <= reg_main_state;\r
 376                 end if;\r
 377             when ST_A22_T1 =>\r
 378                 if (reg_sub_state = ST_SUB73) then\r
 379                     reg_main_next_state <= ST_A22_T2;\r
 380                 else\r
 381                     reg_main_next_state <= reg_main_state;\r
 382                 end if;\r
 383             when ST_A22_T2 =>\r
 384                 if (reg_sub_state = ST_SUB73) then\r
 385                     reg_main_next_state <= ST_CM_T0;\r
 386                 else\r
 387                     reg_main_next_state <= reg_main_state;\r
 388                 end if;\r
 389             when ST_A23_T1 =>\r
 390                 if (reg_sub_state = ST_SUB73) then\r
 391                     reg_main_next_state <= ST_A23_T2;\r
 392                 else\r
 393                     reg_main_next_state <= reg_main_state;\r
 394                 end if;\r
 395             when ST_A23_T2 =>\r
 396                 if (reg_sub_state = ST_SUB73) then\r
 397                     reg_main_next_state <= ST_A23_T3;\r
 398                 else\r
 399                     reg_main_next_state <= reg_main_state;\r
 400                 end if;\r
 401             when ST_A23_T3 =>\r
 402                 if (reg_sub_state = ST_SUB73) then\r
 403                     reg_main_next_state <= ST_CM_T0;\r
 404                 else\r
 405                     reg_main_next_state <= reg_main_state;\r
 406                 end if;\r
 407             when ST_A24_T1 =>\r
 408                 if (reg_sub_state = ST_SUB73) then\r
 409                     reg_main_next_state <= ST_A24_T2;\r
 410                 else\r
 411                     reg_main_next_state <= reg_main_state;\r
 412                 end if;\r
 413             when ST_A24_T2 =>\r
 414                 if (reg_sub_state = ST_SUB73) then\r
 415                     reg_main_next_state <= ST_A24_T3;\r
 416                 else\r
 417                     reg_main_next_state <= reg_main_state;\r
 418                 end if;\r
 419             when ST_A24_T3 =>\r
 420                 if (reg_sub_state = ST_SUB73) then\r
 421                     reg_main_next_state <= ST_A24_T4;\r
 422                 else\r
 423                     reg_main_next_state <= reg_main_state;\r
 424                 end if;\r
 425             when ST_A24_T4 =>\r
 426                 if (reg_sub_state = ST_SUB73) then\r
 427                     reg_main_next_state <= ST_A24_T5;\r
 428                 else\r
 429                     reg_main_next_state <= reg_main_state;\r
 430                 end if;\r
 431             when ST_A24_T5 =>\r
 432                 if (reg_sub_state = ST_SUB73) then\r
 433                     reg_main_next_state <= ST_CM_T0;\r
 434                 else\r
 435                     reg_main_next_state <= reg_main_state;\r
 436                 end if;\r
 437             when ST_A25_T1 =>\r
 438                 if (reg_sub_state = ST_SUB73) then\r
 439                     reg_main_next_state <= ST_A25_T2;\r
 440                 else\r
 441                     reg_main_next_state <= reg_main_state;\r
 442                 end if;\r
 443             when ST_A25_T2 =>\r
 444                 if (reg_sub_state = ST_SUB73) then\r
 445                     reg_main_next_state <= ST_A25_T3;\r
 446                 else\r
 447                     reg_main_next_state <= reg_main_state;\r
 448                 end if;\r
 449             when ST_A25_T3 =>\r
 450                 if (reg_sub_state = ST_SUB73) then\r
 451                     reg_main_next_state <= ST_A25_T4;\r
 452                 else\r
 453                     reg_main_next_state <= reg_main_state;\r
 454                 end if;\r
 455             when ST_A25_T4 =>\r
 456                 if (reg_sub_state = ST_SUB73) then\r
 457                     reg_main_next_state <= ST_CM_T0;\r
 458                 else\r
 459                     reg_main_next_state <= reg_main_state;\r
 460                 end if;\r
 461             when ST_A26_T1 =>\r
 462                 if (reg_sub_state = ST_SUB73) then\r
 463                     reg_main_next_state <= ST_A26_T2;\r
 464                 else\r
 465                     reg_main_next_state <= reg_main_state;\r
 466                 end if;\r
 467             when ST_A26_T2 =>\r
 468                 if (reg_sub_state = ST_SUB73) then\r
 469                     reg_main_next_state <= ST_A26_T3;\r
 470                 else\r
 471                     reg_main_next_state <= reg_main_state;\r
 472                 end if;\r
 473             when ST_A26_T3 =>\r
 474                 if (reg_sub_state = ST_SUB73) then\r
 475                     reg_main_next_state <= ST_CM_T0;\r
 476                 else\r
 477                     reg_main_next_state <= reg_main_state;\r
 478                 end if;\r
 479             when ST_A27_T1 =>\r
 480                 if (reg_sub_state = ST_SUB73) then\r
 481                     reg_main_next_state <= ST_A27_T2;\r
 482                 else\r
 483                     reg_main_next_state <= reg_main_state;\r
 484                 end if;\r
 485             when ST_A27_T2 =>\r
 486                 if (reg_sub_state = ST_SUB73) then\r
 487                     reg_main_next_state <= ST_A27_T3;\r
 488                 else\r
 489                     reg_main_next_state <= reg_main_state;\r
 490                 end if;\r
 491             when ST_A27_T3 =>\r
 492                 if (reg_sub_state = ST_SUB73) then\r
 493                     reg_main_next_state <= ST_A27_T4;\r
 494                 else\r
 495                     reg_main_next_state <= reg_main_state;\r
 496                 end if;\r
 497             when ST_A27_T4 =>\r
 498                 if (reg_sub_state = ST_SUB73) then\r
 499                     reg_main_next_state <= ST_A27_T5;\r
 500                 else\r
 501                     reg_main_next_state <= reg_main_state;\r
 502                 end if;\r
 503             when ST_A27_T5 =>\r
 504                 if (reg_sub_state = ST_SUB73) then\r
 505                     reg_main_next_state <= ST_CM_T0;\r
 506                 else\r
 507                     reg_main_next_state <= reg_main_state;\r
 508                 end if;\r
 509 \r
 510             --A3 inst.\r
 511             when ST_A31_T1 =>\r
 512                 if (reg_sub_state = ST_SUB73) then\r
 513                     reg_main_next_state <= ST_A31_T2;\r
 514                 else\r
 515                     reg_main_next_state <= reg_main_state;\r
 516                 end if;\r
 517             when ST_A31_T2 =>\r
 518                 if (reg_sub_state = ST_SUB73) then\r
 519                     reg_main_next_state <= ST_CM_T0;\r
 520                 else\r
 521                     reg_main_next_state <= reg_main_state;\r
 522                 end if;\r
 523             when ST_A32_T1 =>\r
 524                 if (reg_sub_state = ST_SUB73) then\r
 525                     reg_main_next_state <= ST_A32_T2;\r
 526                 else\r
 527                     reg_main_next_state <= reg_main_state;\r
 528                 end if;\r
 529             when ST_A32_T2 =>\r
 530                 if (reg_sub_state = ST_SUB73) then\r
 531                     reg_main_next_state <= ST_A32_T3;\r
 532                 else\r
 533                     reg_main_next_state <= reg_main_state;\r
 534                 end if;\r
 535             when ST_A32_T3 =>\r
 536                 if (reg_sub_state = ST_SUB73) then\r
 537                     reg_main_next_state <= ST_CM_T0;\r
 538                 else\r
 539                     reg_main_next_state <= reg_main_state;\r
 540                 end if;\r
 541             when ST_A33_T1 =>\r
 542                 if (reg_sub_state = ST_SUB73) then\r
 543                     reg_main_next_state <= ST_A33_T2;\r
 544                 else\r
 545                     reg_main_next_state <= reg_main_state;\r
 546                 end if;\r
 547             when ST_A33_T2 =>\r
 548                 if (reg_sub_state = ST_SUB73) then\r
 549                     reg_main_next_state <= ST_A33_T3;\r
 550                 else\r
 551                     reg_main_next_state <= reg_main_state;\r
 552                 end if;\r
 553             when ST_A33_T3 =>\r
 554                 if (reg_sub_state = ST_SUB73) then\r
 555                     reg_main_next_state <= ST_A33_T4;\r
 556                 else\r
 557                     reg_main_next_state <= reg_main_state;\r
 558                 end if;\r
 559             when ST_A33_T4 =>\r
 560                 if (reg_sub_state = ST_SUB73) then\r
 561                     reg_main_next_state <= ST_A33_T5;\r
 562                 else\r
 563                     reg_main_next_state <= reg_main_state;\r
 564                 end if;\r
 565             when ST_A33_T5 =>\r
 566                 if (reg_sub_state = ST_SUB73) then\r
 567                     reg_main_next_state <= ST_CM_T0;\r
 568                 else\r
 569                     reg_main_next_state <= reg_main_state;\r
 570                 end if;\r
 571             when ST_A34_T1 =>\r
 572                 if (reg_sub_state = ST_SUB73) then\r
 573                     reg_main_next_state <= ST_A34_T2;\r
 574                 else\r
 575                     reg_main_next_state <= reg_main_state;\r
 576                 end if;\r
 577             when ST_A34_T2 =>\r
 578                 if (reg_sub_state = ST_SUB73) then\r
 579                     reg_main_next_state <= ST_A34_T3;\r
 580                 else\r
 581                     reg_main_next_state <= reg_main_state;\r
 582                 end if;\r
 583             when ST_A34_T3 =>\r
 584                 if (reg_sub_state = ST_SUB73) then\r
 585                     reg_main_next_state <= ST_A34_T4;\r
 586                 else\r
 587                     reg_main_next_state <= reg_main_state;\r
 588                 end if;\r
 589             when ST_A34_T4 =>\r
 590                 if (reg_sub_state = ST_SUB73) then\r
 591                     reg_main_next_state <= ST_CM_T0;\r
 592                 else\r
 593                     reg_main_next_state <= reg_main_state;\r
 594                 end if;\r
 595             when ST_A35_T1 =>\r
 596                 if (reg_sub_state = ST_SUB73) then\r
 597                     reg_main_next_state <= ST_A35_T2;\r
 598                 else\r
 599                     reg_main_next_state <= reg_main_state;\r
 600                 end if;\r
 601             when ST_A35_T2 =>\r
 602                 if (reg_sub_state = ST_SUB73) then\r
 603                     reg_main_next_state <= ST_A35_T3;\r
 604                 else\r
 605                     reg_main_next_state <= reg_main_state;\r
 606                 end if;\r
 607             when ST_A35_T3 =>\r
 608                 if (reg_sub_state = ST_SUB73) then\r
 609                     reg_main_next_state <= ST_CM_T0;\r
 610                 else\r
 611                     reg_main_next_state <= reg_main_state;\r
 612                 end if;\r
 613             when ST_A36_T1 =>\r
 614                 if (reg_sub_state = ST_SUB73) then\r
 615                     reg_main_next_state <= ST_A36_T2;\r
 616                 else\r
 617                     reg_main_next_state <= reg_main_state;\r
 618                 end if;\r
 619             when ST_A36_T2 =>\r
 620                 if (reg_sub_state = ST_SUB73) then\r
 621                     reg_main_next_state <= ST_A36_T3;\r
 622                 else\r
 623                     reg_main_next_state <= reg_main_state;\r
 624                 end if;\r
 625             when ST_A36_T3 =>\r
 626                 if (reg_sub_state = ST_SUB73) then\r
 627                     reg_main_next_state <= ST_A36_T4;\r
 628                 else\r
 629                     reg_main_next_state <= reg_main_state;\r
 630                 end if;\r
 631             when ST_A36_T4 =>\r
 632                 if (reg_sub_state = ST_SUB73) then\r
 633                     reg_main_next_state <= ST_A36_T5;\r
 634                 else\r
 635                     reg_main_next_state <= reg_main_state;\r
 636                 end if;\r
 637             when ST_A36_T5 =>\r
 638                 if (reg_sub_state = ST_SUB73) then\r
 639                     reg_main_next_state <= ST_CM_T0;\r
 640                 else\r
 641                     reg_main_next_state <= reg_main_state;\r
 642                 end if;\r
 643 \r
 644 \r
 645             --A4 inst.\r
 646             when ST_A41_T1 =>\r
 647                 if (reg_sub_state = ST_SUB73) then\r
 648                     reg_main_next_state <= ST_A41_T2;\r
 649                 else\r
 650                     reg_main_next_state <= reg_main_state;\r
 651                 end if;\r
 652             when ST_A41_T2 =>\r
 653                 if (reg_sub_state = ST_SUB73) then\r
 654                     reg_main_next_state <= ST_A41_T3;\r
 655                 else\r
 656                     reg_main_next_state <= reg_main_state;\r
 657                 end if;\r
 658             when ST_A41_T3 =>\r
 659                 if (reg_sub_state = ST_SUB73) then\r
 660                     reg_main_next_state <= ST_A41_T4;\r
 661                 else\r
 662                     reg_main_next_state <= reg_main_state;\r
 663                 end if;\r
 664             when ST_A41_T4 =>\r
 665                 if (reg_sub_state = ST_SUB73) then\r
 666                     reg_main_next_state <= ST_CM_T0;\r
 667                 else\r
 668                     reg_main_next_state <= reg_main_state;\r
 669                 end if;\r
 670             when ST_A42_T1 =>\r
 671                 if (reg_sub_state = ST_SUB73) then\r
 672                     reg_main_next_state <= ST_A42_T2;\r
 673                 else\r
 674                     reg_main_next_state <= reg_main_state;\r
 675                 end if;\r
 676             when ST_A42_T2 =>\r
 677                 if (reg_sub_state = ST_SUB73) then\r
 678                     reg_main_next_state <= ST_A42_T3;\r
 679                 else\r
 680                     reg_main_next_state <= reg_main_state;\r
 681                 end if;\r
 682             when ST_A42_T3 =>\r
 683                 if (reg_sub_state = ST_SUB73) then\r
 684                     reg_main_next_state <= ST_A42_T4;\r
 685                 else\r
 686                     reg_main_next_state <= reg_main_state;\r
 687                 end if;\r
 688             when ST_A42_T4 =>\r
 689                 if (reg_sub_state = ST_SUB73) then\r
 690                     reg_main_next_state <= ST_A42_T5;\r
 691                 else\r
 692                     reg_main_next_state <= reg_main_state;\r
 693                 end if;\r
 694             when ST_A42_T5 =>\r
 695                 if (reg_sub_state = ST_SUB73) then\r
 696                     reg_main_next_state <= ST_CM_T0;\r
 697                 else\r
 698                     reg_main_next_state <= reg_main_state;\r
 699                 end if;\r
 700             when ST_A43_T1 =>\r
 701                 if (reg_sub_state = ST_SUB73) then\r
 702                     reg_main_next_state <= ST_A43_T2;\r
 703                 else\r
 704                     reg_main_next_state <= reg_main_state;\r
 705                 end if;\r
 706             when ST_A43_T2 =>\r
 707                 if (reg_sub_state = ST_SUB73) then\r
 708                     reg_main_next_state <= ST_CM_T0;\r
 709                 else\r
 710                     reg_main_next_state <= reg_main_state;\r
 711                 end if;\r
 712             when ST_A43_T3 =>\r
 713                 if (reg_sub_state = ST_SUB73) then\r
 714                     reg_main_next_state <= ST_A43_T4;\r
 715                 else\r
 716                     reg_main_next_state <= reg_main_state;\r
 717                 end if;\r
 718             when ST_A43_T4 =>\r
 719                 if (reg_sub_state = ST_SUB73) then\r
 720                     reg_main_next_state <= ST_A43_T5;\r
 721                 else\r
 722                     reg_main_next_state <= reg_main_state;\r
 723                 end if;\r
 724             when ST_A43_T5 =>\r
 725                 if (reg_sub_state = ST_SUB73) then\r
 726                     reg_main_next_state <= ST_CM_T0;\r
 727                 else\r
 728                     reg_main_next_state <= reg_main_state;\r
 729                 end if;\r
 730             when ST_A44_T1 =>\r
 731                 if (reg_sub_state = ST_SUB73) then\r
 732                     reg_main_next_state <= ST_A44_T2;\r
 733                 else\r
 734                     reg_main_next_state <= reg_main_state;\r
 735                 end if;\r
 736             when ST_A44_T2 =>\r
 737                 if (reg_sub_state = ST_SUB73) then\r
 738                     reg_main_next_state <= ST_A44_T3;\r
 739                 else\r
 740                     reg_main_next_state <= reg_main_state;\r
 741                 end if;\r
 742             when ST_A44_T3 =>\r
 743                 if (reg_sub_state = ST_SUB73) then\r
 744                     reg_main_next_state <= ST_A44_T4;\r
 745                 else\r
 746                     reg_main_next_state <= reg_main_state;\r
 747                 end if;\r
 748             when ST_A44_T4 =>\r
 749                 if (reg_sub_state = ST_SUB73) then\r
 750                     reg_main_next_state <= ST_A44_T5;\r
 751                 else\r
 752                     reg_main_next_state <= reg_main_state;\r
 753                 end if;\r
 754             when ST_A44_T5 =>\r
 755                 if (reg_sub_state = ST_SUB73) then\r
 756                     reg_main_next_state <= ST_A44_T6;\r
 757                 else\r
 758                     reg_main_next_state <= reg_main_state;\r
 759                 end if;\r
 760             when ST_A44_T6 =>\r
 761                 if (reg_sub_state = ST_SUB73) then\r
 762                     reg_main_next_state <= ST_CM_T0;\r
 763                 else\r
 764                     reg_main_next_state <= reg_main_state;\r
 765                 end if;\r
 766 \r
 767 \r
 768             --A5 inst.\r
 769             when ST_A51_T1 =>\r
 770                 if (reg_sub_state = ST_SUB73) then\r
 771                     reg_main_next_state <= ST_A51_T2;\r
 772                 else\r
 773                     reg_main_next_state <= reg_main_state;\r
 774                 end if;\r
 775             when ST_A51_T2 =>\r
 776                 if (reg_sub_state = ST_SUB73) then\r
 777                     reg_main_next_state <= ST_CM_T0;\r
 778                 else\r
 779                     reg_main_next_state <= reg_main_state;\r
 780                 end if;\r
 781             when ST_A52_T1 =>\r
 782                 if (reg_sub_state = ST_SUB73) then\r
 783                     reg_main_next_state <= ST_A52_T2;\r
 784                 else\r
 785                     reg_main_next_state <= reg_main_state;\r
 786                 end if;\r
 787             when ST_A52_T2 =>\r
 788                 if (reg_sub_state = ST_SUB73) then\r
 789                     reg_main_next_state <= ST_A52_T3;\r
 790                 else\r
 791                     reg_main_next_state <= reg_main_state;\r
 792                 end if;\r
 793             when ST_A52_T3 =>\r
 794                 if (reg_sub_state = ST_SUB73) then\r
 795                     reg_main_next_state <= ST_CM_T0;\r
 796                 else\r
 797                     reg_main_next_state <= reg_main_state;\r
 798                 end if;\r
 799             when ST_A53_T1 =>\r
 800                 if (reg_sub_state = ST_SUB73) then\r
 801                     reg_main_next_state <= ST_A53_T2;\r
 802                 else\r
 803                     reg_main_next_state <= reg_main_state;\r
 804                 end if;\r
 805             when ST_A53_T2 =>\r
 806                 if (reg_sub_state = ST_SUB73) then\r
 807                     reg_main_next_state <= ST_A53_T3;\r
 808                 else\r
 809                     reg_main_next_state <= reg_main_state;\r
 810                 end if;\r
 811             when ST_A53_T3 =>\r
 812                 if (reg_sub_state = ST_SUB73) then\r
 813                     reg_main_next_state <= ST_A53_T4;\r
 814                 else\r
 815                     reg_main_next_state <= reg_main_state;\r
 816                 end if;\r
 817             when ST_A53_T4 =>\r
 818                 if (reg_sub_state = ST_SUB73) then\r
 819                     reg_main_next_state <= ST_A53_T5;\r
 820                 else\r
 821                     reg_main_next_state <= reg_main_state;\r
 822                 end if;\r
 823             when ST_A53_T5 =>\r
 824                 if (reg_sub_state = ST_SUB73) then\r
 825                     reg_main_next_state <= ST_CM_T0;\r
 826                 else\r
 827                     reg_main_next_state <= reg_main_state;\r
 828                 end if;\r
 829             when ST_A55_T1 =>\r
 830                 if (reg_sub_state = ST_SUB73) then\r
 831                     reg_main_next_state <= ST_A55_T2;\r
 832                 else\r
 833                     reg_main_next_state <= reg_main_state;\r
 834                 end if;\r
 835             when ST_A55_T2 =>\r
 836                 if (reg_sub_state = ST_SUB73) then\r
 837                     reg_main_next_state <= ST_A55_T3;\r
 838                 else\r
 839                     reg_main_next_state <= reg_main_state;\r
 840                 end if;\r
 841             when ST_A55_T3 =>\r
 842                 if (reg_sub_state = ST_SUB73) then\r
 843                     reg_main_next_state <= ST_A55_T4;\r
 844                 else\r
 845                     reg_main_next_state <= reg_main_state;\r
 846                 end if;\r
 847             when ST_A55_T4 =>\r
 848                 if (reg_sub_state = ST_SUB73) then\r
 849                     reg_main_next_state <= ST_A55_T5;\r
 850                 else\r
 851                     reg_main_next_state <= reg_main_state;\r
 852                 end if;\r
 853             when ST_A55_T5 =>\r
 854                 if (reg_sub_state = ST_SUB73) then\r
 855                     reg_main_next_state <= ST_CM_T0;\r
 856                 else\r
 857                     reg_main_next_state <= reg_main_state;\r
 858                 end if;\r
 859             when ST_A561_T1 =>\r
 860                 if (reg_sub_state = ST_SUB73) then\r
 861                     reg_main_next_state <= ST_A561_T2;\r
 862                 else\r
 863                     reg_main_next_state <= reg_main_state;\r
 864                 end if;\r
 865             when ST_A561_T2 =>\r
 866                 if (reg_sub_state = ST_SUB73) then\r
 867                     reg_main_next_state <= ST_CM_T0;\r
 868                 else\r
 869                     reg_main_next_state <= reg_main_state;\r
 870                 end if;\r
 871             when ST_A562_T1 =>\r
 872                 if (reg_sub_state = ST_SUB73) then\r
 873                     reg_main_next_state <= ST_A562_T2;\r
 874                 else\r
 875                     reg_main_next_state <= reg_main_state;\r
 876                 end if;\r
 877             when ST_A562_T2 =>\r
 878                 if (reg_sub_state = ST_SUB73) then\r
 879                     reg_main_next_state <= ST_A562_T3;\r
 880                 else\r
 881                     reg_main_next_state <= reg_main_state;\r
 882                 end if;\r
 883             when ST_A562_T3 =>\r
 884                 if (reg_sub_state = ST_SUB73) then\r
 885                     reg_main_next_state <= ST_A562_T4;\r
 886                 else\r
 887                     reg_main_next_state <= reg_main_state;\r
 888                 end if;\r
 889             when ST_A562_T4 =>\r
 890                 if (reg_sub_state = ST_SUB73) then\r
 891                     reg_main_next_state <= ST_CM_T0;\r
 892                 else\r
 893                     reg_main_next_state <= reg_main_state;\r
 894                 end if;\r
 895             when ST_A57_T1 =>\r
 896                 if (reg_sub_state = ST_SUB73) then\r
 897                     reg_main_next_state <= ST_A57_T2;\r
 898                 else\r
 899                     reg_main_next_state <= reg_main_state;\r
 900                 end if;\r
 901             when ST_A57_T2 =>\r
 902                 if (reg_sub_state = ST_SUB73) then\r
 903                     reg_main_next_state <= ST_A57_T3;\r
 904                 else\r
 905                     reg_main_next_state <= reg_main_state;\r
 906                 end if;\r
 907             when ST_A57_T3 =>\r
 908                 if (reg_sub_state = ST_SUB73) then\r
 909                     reg_main_next_state <= ST_A57_T4;\r
 910                 else\r
 911                     reg_main_next_state <= reg_main_state;\r
 912                 end if;\r
 913             when ST_A57_T4 =>\r
 914                 if (reg_sub_state = ST_SUB73) then\r
 915                     reg_main_next_state <= ST_A57_T5;\r
 916                 else\r
 917                     reg_main_next_state <= reg_main_state;\r
 918                 end if;\r
 919             when ST_A57_T5 =>\r
 920                 if (reg_sub_state = ST_SUB73) then\r
 921                     reg_main_next_state <= ST_CM_T0;\r
 922                 else\r
 923                     reg_main_next_state <= reg_main_state;\r
 924                 end if;\r
 925             when ST_A58_T1 =>\r
 926                 if (reg_sub_state = ST_SUB73) then\r
 927                     reg_main_next_state <= ST_A58_T2;\r
 928                 else\r
 929                     reg_main_next_state <= reg_main_state;\r
 930                 end if;\r
 931             when ST_A58_T2 =>\r
 932                 if (reg_sub_state = ST_SUB73) then\r
 933                     reg_main_next_state <= ST_A58_T3;\r
 934                 else\r
 935                     reg_main_next_state <= reg_main_state;\r
 936                 end if;\r
 937             when ST_A58_T3 =>\r
 938                 if (reg_sub_state = ST_SUB73) then\r
 939                     reg_main_next_state <= ST_CM_T0;\r
 940                 else\r
 941                     reg_main_next_state <= reg_main_state;\r
 942                 end if;\r
 943 \r
 944             when ST_INV =>\r
 945                 ---failed to decode next...\r
 946                     reg_main_next_state <= reg_main_state;\r
 947 --            ---not ready yet...\r
 948 --            when others =>\r
 949 --                reg_main_next_state <= reg_main_state;\r
 950         end case;\r
 951     end process;\r
 952 \r
 953     --addressing general process...\r
 954     --pc, io bus, r/w, instruction regs...\r
 955     ad_general_p : process (pi_rst_n, pi_base_clk)\r
 956 \r
 957 procedure pc_inc is\r
 958 begin\r
 959     if (reg_pc_l = "11111111") then\r
 960         --pch page next.\r
 961         reg_pc_l    <= "00000000";\r
 962         reg_pc_h    <= reg_pc_h + 1;\r
 963     else\r
 964         reg_pc_l    <= reg_pc_l + 1;\r
 965     end if;\r
 966 end;\r
 967 \r
 968     begin\r
 969         if (pi_rst_n = '0') then\r
 970             reg_pc_l    <= (others => '0');\r
 971             reg_pc_h    <= (others => '0');\r
 972             reg_inst    <= (others => '0');\r
 973             reg_addr    <= (others => 'Z');\r
 974             reg_d_out   <= (others => 'Z');\r
 975             reg_r_nw    <= 'Z';\r
 976         elsif (rising_edge(pi_base_clk)) then\r
 977             if (reg_main_state = ST_RS_T0) then\r
 978                 reg_pc_l    <= (others => '0');\r
 979                 reg_pc_h    <= (others => '0');\r
 980                 reg_inst    <= (others => '0');\r
 981                 reg_addr    <= (others => '0');\r
 982                 reg_d_out   <= (others => 'Z');\r
 983                 reg_r_nw    <= '1';\r
 984             elsif (reg_main_state = ST_RS_T3) then\r
 985                 --dummy sp out 1.\r
 986                 reg_addr    <= "11111111" & reg_sp;\r
 987                 reg_d_out   <= (others => 'Z');\r
 988                 reg_r_nw    <= '0';\r
 989             elsif (reg_main_state = ST_RS_T4) then\r
 990                 --dummy sp out 2.\r
 991                 reg_addr    <= "11111111" & (reg_sp - 1);\r
 992                 reg_d_out   <= (others => 'Z');\r
 993                 reg_r_nw    <= '0';\r
 994             elsif (reg_main_state = ST_RS_T5) then\r
 995                 --dummy sp out 3.\r
 996                 reg_addr    <= "11111111" & (reg_sp - 2);\r
 997                 reg_d_out   <= (others => 'Z');\r
 998                 reg_r_nw    <= '0';\r
 999             elsif (reg_main_state = ST_RS_T6) then\r
1000                 --reset vector low...\r
1001                 reg_addr    <= "1111111111111100";\r
1002                 reg_d_out   <= (others => 'Z');\r
1003                 reg_r_nw    <= '1';\r
1004                 reg_pc_l    <= reg_d_in;\r
1005             elsif (reg_main_state = ST_RS_T7) then\r
1006                 --reset vector high...\r
1007                 reg_addr    <= "1111111111111101";\r
1008                 reg_d_out   <= (others => 'Z');\r
1009                 reg_r_nw    <= '1';\r
1010                 reg_pc_h    <= reg_d_in;\r
1011             elsif (reg_main_state = ST_CM_T0) then\r
1012                 if (reg_sub_state = ST_SUB00) then\r
1013                     reg_addr    <= reg_pc_h & reg_pc_l;\r
1014                     reg_d_out   <= (others => 'Z');\r
1015                     reg_r_nw    <= '1';\r
1016                 elsif (reg_sub_state = ST_SUB30) then\r
1017                     reg_inst    <= reg_d_in;\r
1018                 elsif (reg_sub_state = ST_SUB70) then\r
1019                     pc_inc;\r
1020                 end if;\r
1021             end if;\r
1022         end if;--if (pi_rst_n = '0') then\r
1023     end process;\r
1024 \r
1025     po_r_nw     <= reg_r_nw;\r
1026     po_addr     <= reg_addr;\r
1027     pio_d_io    <= reg_d_out;\r
1028     reg_d_in    <= pio_d_io;\r
1029 \r
1030 end rtl;\r
1031 \r