2 use ieee.std_logic_1164.all;
4 -- this address decoder inserts dummy setup time on write.
5 entity address_decoder is
6 generic (abus_size : integer := 16; dbus_size : integer := 8);
7 port ( phi2 : in std_logic; --dropping edge syncronized clock.
8 R_nW : in std_logic; -- active high on read / active low on write.
9 addr : in std_logic_vector (abus_size - 1 downto 0);
10 d_io : inout std_logic_vector (dbus_size - 1 downto 0);
11 ppu_ce_n : out std_logic;
12 apu_ce_n : out std_logic
18 -- * 0x0000 - 0x07FF RAM
19 -- * 0x0800 - 0x1FFF mirror RAM
20 -- * 0x2000 - 0x2007 I/O PPU
21 -- * 0x4000 - 0x401F I/O APU
22 -- * 0x6000 - 0x7FFF battery backup ram
23 -- * 0x8000 - 0xFFFF PRG-ROM
26 architecture rtl of address_decoder is
28 generic (abus_size : integer := 16; dbus_size : integer := 8);
29 port ( ce_n, oe_n, we_n : in std_logic; --select pin active low.
30 addr : in std_logic_vector (abus_size - 1 downto 0);
31 d_io : inout std_logic_vector (dbus_size - 1 downto 0)
35 generic (abus_size : integer := 15; dbus_size : integer := 8);
36 port ( ce_n : in std_logic; --active low.
37 addr : in std_logic_vector (abus_size - 1 downto 0);
38 data : out std_logic_vector (dbus_size - 1 downto 0)
42 constant dsize : integer := 8;
43 constant ram_2k : integer := 11; --2k = 11 bit width.
44 constant rom_32k : integer := 15; --32k = 15 bit width.
46 constant CPU_DST : time := 100 ns; --write data setup time.
48 signal rom_ce_n : std_logic;
49 signal rom_out : std_logic_vector (dsize - 1 downto 0);
51 signal ram_ce_n : std_logic;
52 signal ram_oe_n : std_logic;
53 signal ram_io : std_logic_vector (dsize - 1 downto 0);
57 rom_ce_n <= '0' when (addr(15) = '1' and R_nW = '1') else
59 romport : prg_rom generic map (rom_32k, dsize)
60 port map (rom_ce_n, addr(rom_32k - 1 downto 0), rom_out);
63 when (r_nw = '0' and ((addr(15) or addr(14) or addr(13)) = '0')) else
66 ramport : ram generic map (ram_2k, dsize)
67 port map (ram_ce_n, ram_oe_n, R_nW,
68 addr(ram_2k - 1 downto 0), ram_io);
70 --must explicitly drive to for inout port.
72 when (((addr(15) or addr(14) or addr(13)) = '0') and r_nw = '1') else
74 when ((addr(15) = '1') and r_nw = '1') else
79 when (addr(15) = '0' and addr(14) = '0' and addr(13) = '1') else
83 when (addr(15) = '0' and addr(14) = '1' and addr(13) = '0') else
87 main_p : process (phi2, addr, d_io, R_nW)
89 -- ram range : 0 - 0x2000.
90 -- 0x2000 is 0010_0000_0000_0000
91 if ((addr(15) or addr(14) or addr(13)) = '0') then
92 --if (addr < "0010000000000000") then
95 --write timing slided by half clock.
97 elsif (R_nW = '1') then
112 -----------------------------------------------------
113 -----------------------------------------------------
114 ---------- VRAM / CHR ROM Address Decoder -----------
115 -----------------------------------------------------
116 -----------------------------------------------------
119 use ieee.std_logic_1164.all;
121 entity v_address_decoder is
122 generic (abus_size : integer := 14; dbus_size : integer := 8);
123 port ( clk : in std_logic;
127 vram_ad : inout std_logic_vector (7 downto 0);
128 vram_a : in std_logic_vector (13 downto 8)
130 end v_address_decoder;
132 -- Address Size Description
133 -- $0000-$0FFF $1000 Pattern Table 0 [lower CHR bank]
134 -- $1000-$1FFF $1000 Pattern Table 1 [upper CHR bank]
135 -- $2000-$23FF $0400 Name Table #0
136 -- $2400-$27FF $0400 Name Table #1
137 -- $2800-$2BFF $0400 Name Table #2
138 -- $2C00-$2FFF $0400 Name Table #3
139 -- $3000-$3EFF $0F00 Mirrors of $2000-$2FFF
140 -- $3F00-$3F1F $0020 Palette RAM indexes [not RGB values]
141 -- $3F20-$3FFF $0080 Mirrors of $3F00-$3F1F
143 architecture rtl of v_address_decoder is
145 generic (abus_size : integer := 16; dbus_size : integer := 8);
146 port ( ce_n, oe_n, we_n : in std_logic; --select pin active low.
147 addr : in std_logic_vector (abus_size - 1 downto 0);
148 d_io : inout std_logic_vector (dbus_size - 1 downto 0)
153 generic (abus_size : integer := 13; dbus_size : integer := 8);
154 port ( ce_n : in std_logic; --active low.
155 addr : in std_logic_vector (abus_size - 1 downto 0);
156 data : out std_logic_vector (dbus_size - 1 downto 0);
157 nt_v_mirror : out std_logic
165 port ( c : in std_logic;
167 d : in std_logic_vector(dsize - 1 downto 0);
168 q : out std_logic_vector(dsize - 1 downto 0)
172 constant dsize : integer := 8;
173 constant vram_1k : integer := 10; --2k = 11 bit width.
174 constant chr_rom_8k : integer := 13; --32k = 15 bit width.
176 signal v_addr : std_logic_vector (13 downto 0);
177 --signal nt_v_mirror2 : std_logic;
178 signal nt_v_mirror : std_logic;
180 signal pt_ce_n : std_logic;
181 signal nt0_ce_n : std_logic;
182 signal nt1_ce_n : std_logic;
186 --transparent d-latch
187 latch_inst : ls373 generic map (dsize)
188 port map(ale, '0', vram_ad, v_addr(7 downto 0));
189 v_addr (13 downto 8) <= vram_a;
192 pt_ce_n <= '0' when (v_addr(13) = '0' and rd_n = '0') else
194 --nt_v_mirror <= '0';
195 pattern_tbl : chr_rom generic map (chr_rom_8k, dsize)
196 port map (pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);
198 --name table/attr table
199 name_tbl0 : ram generic map (vram_1k, dsize)
200 port map (nt0_ce_n, rd_n, wr_n,
201 v_addr(vram_1k - 1 downto 0), vram_ad);
203 name_tbl1 : ram generic map (vram_1k, dsize)
204 port map (nt1_ce_n, rd_n, wr_n,
205 v_addr(vram_1k - 1 downto 0), vram_ad);
207 --palette table data is stored in the inside ppu
210 main_p : process (clk, v_addr, vram_ad, wr_n)
212 if (v_addr(13) = '1') then
214 if ((v_addr(12) and v_addr(11) and v_addr(10)
215 and v_addr(9) and v_addr(8)) = '0') then
216 if (nt_v_mirror = '1') then
217 --bit 10 is the name table selector.
218 if (v_addr(10) = '0') then
219 --name table 0 enable.
224 elsif (rd_n = '0') then
231 --name table 1 enable.
236 elsif (rd_n = '0') then
245 --bit 11 is the name table selector.
246 if (v_addr(11) = '0') then
247 --name table 0 enable.
252 elsif (rd_n = '0') then
259 --name table 1 enable.
264 elsif (rd_n = '0') then
271 end if; --if (nt_v_mirror = '1') then
279 end if; --if (v_addr(13) = '1') then