de1_nes/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5 use work.motonesfpga_common.all;
   6
   7 entity decoder is
   8     generic (dsize : integer := 8);
   9     port (
  10 --    signal dbg_ea_carry     : out std_logic;
  11
  12
  13             set_clk         : in std_logic;
  14             trig_clk        : in std_logic;
  15             res_n           : in std_logic;
  16             irq_n           : in std_logic;
  17             nmi_n           : in std_logic;
  18             rdy             : in std_logic;
  19             instruction     : in std_logic_vector (dsize - 1 downto 0);
  20             exec_cycle      : in std_logic_vector (5 downto 0);
  21             next_cycle      : out std_logic_vector (5 downto 0);
  22             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  23             inst_we_n       : out std_logic;
  24             ad_oe_n         : out std_logic;
  25             dbuf_int_oe_n   : out std_logic;
  26             dl_al_we_n      : out std_logic;
  27             dl_ah_we_n      : out std_logic;
  28             dl_al_oe_n      : out std_logic;
  29             dl_ah_oe_n      : out std_logic;
  30             dl_dh_oe_n      : out std_logic;
  31             pcl_inc_n       : out std_logic;
  32             pch_inc_n       : out std_logic;
  33             pcl_cmd         : out std_logic_vector(3 downto 0);
  34             pch_cmd         : out std_logic_vector(3 downto 0);
  35             sp_cmd          : out std_logic_vector(3 downto 0);
  36             sp_oe_n         : out std_logic;
  37             sp_push_n       : out std_logic;
  38             sp_pop_n        : out std_logic;
  39             acc_cmd         : out std_logic_vector(3 downto 0);
  40             x_cmd           : out std_logic_vector(3 downto 0);
  41             y_cmd           : out std_logic_vector(3 downto 0);
  42             abs_xy_n        : out std_logic;
  43             ea_carry        : in  std_logic;
  44             pg_next_n       : out std_logic;
  45             zp_n            : out std_logic;
  46             zp_xy_n         : out std_logic;
  47             rel_calc_n      : out std_logic;
  48             indir_n         : out std_logic;
  49             indir_x_n       : out std_logic;
  50             indir_y_n       : out std_logic;
  51             arith_en_n      : out std_logic;
  52             stat_dec_oe_n   : out std_logic;
  53             stat_bus_oe_n   : out std_logic;
  54             stat_set_flg_n  : out std_logic;
  55             stat_flg        : out std_logic;
  56             stat_bus_all_n  : out std_logic;
  57             stat_bus_nz_n   : out std_logic;
  58             stat_alu_we_n   : out std_logic;
  59             r_vec_oe_n      : out std_logic;
  60             n_vec_oe_n      : out std_logic;
  61             i_vec_oe_n      : out std_logic;
  62             r_nw            : out std_logic
  63             ;---for parameter check purpose!!!
  64             check_bit     : out std_logic_vector(1 to 5)
  65         );
  66 end decoder;
  67
  68 architecture rtl of decoder is
  69
  70 component d_flip_flop_bit
  71     port (
  72             clk     : in std_logic;
  73             res_n   : in std_logic;
  74             set_n   : in std_logic;
  75             we_n    : in std_logic;
  76             d       : in std_logic;
  77             q       : out std_logic
  78         );
  79 end component;
  80
  81 --cycle bit format
  82 -- bit 5    : pcl increment carry flag
  83 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  84 -- bit 2-0  : cycle
  85
  86 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
  87 constant T0 : std_logic_vector (5 downto 0) := "000000";
  88 constant T1 : std_logic_vector (5 downto 0) := "000001";
  89 constant T2 : std_logic_vector (5 downto 0) := "000010";
  90 constant T3 : std_logic_vector (5 downto 0) := "000011";
  91 constant T4 : std_logic_vector (5 downto 0) := "000100";
  92 constant T5 : std_logic_vector (5 downto 0) := "000101";
  93 constant T6 : std_logic_vector (5 downto 0) := "000110";
  94
  95 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
  96 constant R0 : std_logic_vector (5 downto 0) := "001000";
  97 constant R1 : std_logic_vector (5 downto 0) := "001001";
  98 constant R2 : std_logic_vector (5 downto 0) := "001010";
  99 constant R3 : std_logic_vector (5 downto 0) := "001011";
 100 constant R4 : std_logic_vector (5 downto 0) := "001100";
 101 constant R5 : std_logic_vector (5 downto 0) := "001101";
 102
 103 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
 104 constant N1 : std_logic_vector (5 downto 0) := "010001";
 105 constant N2 : std_logic_vector (5 downto 0) := "010010";
 106 constant N3 : std_logic_vector (5 downto 0) := "010011";
 107 constant N4 : std_logic_vector (5 downto 0) := "010100";
 108 constant N5 : std_logic_vector (5 downto 0) := "010101";
 109
 110 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
 111 constant I1 : std_logic_vector (5 downto 0) := "011001";
 112 constant I2 : std_logic_vector (5 downto 0) := "011010";
 113 constant I3 : std_logic_vector (5 downto 0) := "011011";
 114 constant I4 : std_logic_vector (5 downto 0) := "011100";
 115 constant I5 : std_logic_vector (5 downto 0) := "011101";
 116
 117 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 118
 119 -- SR Flags (bit 7 to bit 0):
 120 --  7   N   ....    Negative
 121 --  6   V   ....    Overflow
 122 --  5   -   ....    ignored
 123 --  4   B   ....    Break
 124 --  3   D   ....    Decimal (use BCD for arithmetics)
 125 --  2   I   ....    Interrupt (IRQ disable)
 126 --  1   Z   ....    Zero
 127 --  0   C   ....    Carry
 128 constant st_N : integer := 7;
 129 constant st_V : integer := 6;
 130 constant st_B : integer := 4;
 131 constant st_D : integer := 3;
 132 constant st_I : integer := 2;
 133 constant st_Z : integer := 1;
 134 constant st_C : integer := 0;
 135
 136 ---for pch_inc_n.
 137 signal pch_inc_input : std_logic;
 138
 139 ---for nmi handling
 140 signal nmi_handled_n : std_logic;
 141
 142 -- page boundary handling
 143 signal wk_next_cycle      : std_logic_vector (5 downto 0);
 144 signal wk_acc_cmd         : std_logic_vector(3 downto 0);
 145 signal wk_x_cmd           : std_logic_vector(3 downto 0);
 146 signal wk_y_cmd           : std_logic_vector(3 downto 0);
 147 signal wk_stat_alu_we_n   : std_logic;
 148 signal ea_carry_reg       : std_logic;
 149
 150 begin
 151
 152     ---pc page next is connected to top bit of exec_cycle
 153     pch_inc_input <= not exec_cycle(5);
 154     pch_inc_reg : d_flip_flop_bit
 155             port map(set_clk, '1', '1', '0', pch_inc_input, pch_inc_n);
 156
 157     ea_carry_inst: d_flip_flop_bit
 158             port map(trig_clk, '1', '1', '0', ea_carry, ea_carry_reg);
 159
 160     --acc,x,y next cycle is changed when it goes page across.
 161     --The conditional branch instructions all have the form xxy10000
 162     next_cycle <= wk_next_cycle;
 163     acc_cmd <= wk_acc_cmd(3) & '1' & wk_acc_cmd(1) & '1'
 164                     when ea_carry = '1' and
 165                          wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
 166                wk_acc_cmd;
 167
 168     x_cmd <= wk_x_cmd(3) & '1' & wk_x_cmd(1 downto 0)
 169                 when ea_carry = '1' and
 170                          wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
 171              wk_x_cmd;
 172     y_cmd <= wk_y_cmd(3) & '1' & wk_y_cmd(1 downto 0)
 173                 when ea_carry = '1' and
 174                          wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
 175              wk_y_cmd;
 176     stat_alu_we_n <= '1' when ea_carry = '1' and
 177                          wk_next_cycle = T0 and instruction(4 downto 0) = "10000" else
 178                      wk_stat_alu_we_n;
 179
 180     main_p : process (set_clk, res_n, nmi_n)
 181
 182 -------------------------------------------------------------
 183 -------------------------------------------------------------
 184 ----------------------- comon routines ----------------------
 185 -------------------------------------------------------------
 186 -------------------------------------------------------------
 187
 188 ----------gate_cmd format
 189 ------3 : front port oe_n
 190 ------2 : front port we_n
 191 ------1 : back port oe_n
 192 ------0 : back port we_n
 193 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 194     val : in std_logic) is
 195 begin
 196     cmd(3) <= val;
 197 end;
 198 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 199     val : in std_logic) is
 200 begin
 201     cmd(2) <= val;
 202 end;
 203 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 204     val : in std_logic) is
 205 begin
 206     cmd(1) <= val;
 207 end;
 208 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 209     val : in std_logic) is
 210 begin
 211     cmd(0) <= val;
 212 end;
 213
 214 procedure fetch_next is
 215 begin
 216     pcl_inc_n <= '0';
 217     back_oe(pcl_cmd, '0');
 218     back_oe(pch_cmd, '0');
 219     back_we(pcl_cmd, '0');
 220     back_we(pch_cmd, '1');
 221 end procedure;
 222
 223 procedure fetch_stop is
 224 begin
 225     pcl_inc_n <= '1';
 226     back_oe(pcl_cmd, '1');
 227     back_oe(pch_cmd, '1');
 228     back_we(pcl_cmd, '1');
 229 end procedure;
 230
 231 procedure read_status is
 232 begin
 233     status_reg <= (others => 'Z');
 234     stat_dec_oe_n <= '0';
 235 end  procedure;
 236
 237 procedure disable_pins is
 238 begin
 239 --following pins are not set in this function.
 240 --            inst_we_n       : out std_logic;
 241 --            ad_oe_n         : out std_logic;
 242 --            dl_al_oe_n      : out std_logic;
 243 --            pcl_inc_n       : out std_logic;
 244 --            pcl_cmd         : out std_logic_vector(3 downto 0);
 245 --            pch_cmd         : out std_logic_vector(3 downto 0);
 246 --            r_nw            : out std_logic
 247
 248     --disable the last opration pins.
 249     dbuf_int_oe_n <= '1';
 250     dl_al_we_n <= '1';
 251     dl_ah_we_n <= '1';
 252     dl_ah_oe_n <= '1';
 253     dl_dh_oe_n <= '1';
 254     sp_cmd <= "1111";
 255     sp_oe_n <= '1';
 256     sp_push_n <= '1';
 257     sp_pop_n <= '1';
 258     wk_acc_cmd <= "1111";
 259     wk_x_cmd <= "1111";
 260     wk_y_cmd <= "1111";
 261
 262     abs_xy_n <= '1';
 263     pg_next_n <= '1';
 264     zp_n <= '1';
 265     zp_xy_n <= '1';
 266     rel_calc_n <= '1';
 267     indir_n <= '1';
 268     indir_x_n <= '1';
 269     indir_y_n <= '1';
 270     arith_en_n <= '1';
 271
 272     read_status;
 273     stat_bus_oe_n <= '1';
 274     stat_set_flg_n <= '1';
 275     stat_flg <= '1';
 276     stat_bus_all_n <= '1';
 277     stat_bus_nz_n <= '1';
 278     wk_stat_alu_we_n <= '1';
 279
 280     r_vec_oe_n <= '1';
 281     n_vec_oe_n <= '1';
 282     i_vec_oe_n <= '1';
 283
 284 end  procedure;
 285
 286 procedure fetch_inst (inc_pcl : in std_logic) is
 287 begin
 288     if instruction = conv_std_logic_vector(16#4c#, dsize) then
 289         --if prior cycle is jump instruction,
 290         --fetch opcode from where the latch is pointing to.
 291
 292         --latch > al.
 293         dl_al_oe_n <= '0';
 294         pcl_cmd <= "1110";
 295     else
 296         --fetch opcode and pcl increment.
 297         pcl_cmd <= "1100";
 298         dl_al_oe_n <= '1';
 299     end if;
 300
 301     ad_oe_n <= '0';
 302     pch_cmd <= "1101";
 303     inst_we_n <= '0';
 304     pcl_inc_n <= inc_pcl;
 305     r_nw <= '1';
 306
 307     d_print(string'("fetch 1"));
 308 end  procedure;
 309
 310 ---T0 cycle routine
 311 ---(along with the page boundary condition, the last
 312 ---cycle is bypassed and slided to T0.)
 313 procedure t0_cycle is
 314 begin
 315     disable_pins;
 316     if (nmi_n = '0' and nmi_handled_n = '1') then
 317         --start nmi handling...
 318         fetch_inst('1');
 319         wk_next_cycle <= N1;
 320     else
 321         fetch_inst('0');
 322         wk_next_cycle <= T1;
 323     end if;
 324 end  procedure;
 325
 326 ---common routine for single byte instruction.
 327 procedure single_inst is
 328 begin
 329     fetch_stop;
 330     wk_next_cycle <= T0;
 331 end  procedure;
 332
 333 procedure fetch_imm is
 334 begin
 335     d_print("immediate");
 336     fetch_next;
 337     --send data from data bus buffer.
 338     --receiver is instruction dependent.
 339     dbuf_int_oe_n <= '0';
 340     wk_next_cycle <= T0;
 341 end  procedure;
 342
 343 procedure set_nz_from_bus is
 344 begin
 345     --status register n/z bit update.
 346     stat_bus_nz_n <= '0';
 347 end  procedure;
 348
 349 procedure set_zc_from_alu is
 350 begin
 351     --status register n/z bit update.
 352     wk_stat_alu_we_n <= '0';
 353     stat_dec_oe_n <= '1';
 354     status_reg <= "00000011";
 355 end  procedure;
 356
 357 procedure set_nz_from_alu is
 358 begin
 359     --status register n/z/c bit update.
 360     wk_stat_alu_we_n <= '0';
 361     stat_dec_oe_n <= '1';
 362     status_reg <= "10000010";
 363 end  procedure;
 364
 365 procedure set_nzc_from_alu is
 366 begin
 367     --status register n/z/c bit update.
 368     wk_stat_alu_we_n <= '0';
 369     stat_dec_oe_n <= '1';
 370     status_reg <= "10000011";
 371 end  procedure;
 372
 373 procedure set_nvz_from_alu is
 374 begin
 375     --status register n/z/v bit update.
 376     wk_stat_alu_we_n <= '0';
 377     stat_dec_oe_n <= '1';
 378     status_reg <= "11000010";
 379 end  procedure;
 380
 381 procedure set_nvzc_from_alu is
 382 begin
 383     wk_stat_alu_we_n <= '0';
 384     stat_dec_oe_n <= '1';
 385     status_reg <= "11000011";
 386 end  procedure;
 387
 388 --flag on/off instruction
 389 procedure set_flag (int_flg : in integer; val : in std_logic) is
 390 begin
 391     stat_dec_oe_n <= '1';
 392     stat_set_flg_n <= '0';
 393     --specify which to set.
 394     status_reg(7 downto int_flg + 1)
 395         <= (others =>'0');
 396     status_reg(int_flg - 1 downto 0)
 397         <= (others =>'0');
 398     status_reg(int_flg) <= '1';
 399     stat_flg <= val;
 400 end  procedure;
 401
 402 --for sec/clc
 403 procedure set_flag0 (val : in std_logic) is
 404 begin
 405     stat_dec_oe_n <= '1';
 406     stat_set_flg_n <= '0';
 407     status_reg <= "00000001";
 408     stat_flg <= val;
 409 end  procedure;
 410
 411 procedure fetch_low is
 412 begin
 413     d_print("fetch low 2");
 414     --fetch next opcode (abs low).
 415     fetch_next;
 416     --latch abs low data.
 417     dbuf_int_oe_n <= '0';
 418     dl_al_we_n <= '0';
 419     wk_next_cycle <= T2;
 420 end  procedure;
 421
 422 procedure abs_fetch_high is
 423 begin
 424     d_print("abs (xy) 3");
 425     dl_al_we_n <= '1';
 426
 427     --latch abs hi data.
 428     fetch_next;
 429     dbuf_int_oe_n <= '0';
 430     dl_ah_we_n <= '0';
 431     wk_next_cycle <= T3;
 432 end  procedure;
 433
 434 procedure abs_latch_out is
 435 begin
 436     --d_print("abs 4");
 437     dl_ah_we_n <= '1';
 438     fetch_stop;
 439
 440     --latch > al/ah.
 441     dl_al_oe_n <= '0';
 442     dl_ah_oe_n <= '0';
 443 end  procedure;
 444
 445 procedure ea_x_out is
 446 begin
 447     -----calucurate and output effective addr
 448     back_oe(wk_x_cmd, '0');
 449     abs_xy_n <= '0';
 450 end  procedure;
 451
 452 procedure ea_y_out is
 453 begin
 454     back_oe(wk_y_cmd, '0');
 455     abs_xy_n <= '0';
 456 end  procedure;
 457
 458 --A.2. internal execution on memory data
 459
 460 procedure a2_zp is
 461 begin
 462     if exec_cycle = T1 then
 463         fetch_low;
 464     elsif exec_cycle = T2 then
 465         fetch_stop;
 466         dbuf_int_oe_n <= '0';
 467         dl_al_we_n <= '1';
 468
 469         --calc zp.
 470         dl_al_oe_n <= '0';
 471         zp_n <= '0';
 472         wk_next_cycle <= T0;
 473     end if;
 474 end  procedure;
 475
 476 procedure a2_abs is
 477 begin
 478     if exec_cycle = T1 then
 479         fetch_low;
 480     elsif exec_cycle = T2 then
 481         abs_fetch_high;
 482     elsif exec_cycle = T3 then
 483         abs_latch_out;
 484         dbuf_int_oe_n <= '0';
 485         wk_next_cycle <= T0;
 486     end if;
 487 end  procedure;
 488
 489 procedure a2_page_next is
 490 begin
 491     --close open gate if page boundary crossed.
 492     back_we(wk_acc_cmd, '1');
 493     front_we(wk_acc_cmd, '1');
 494     front_we(wk_x_cmd, '1');
 495     front_we(wk_y_cmd, '1');
 496     wk_stat_alu_we_n <= '1';
 497 end  procedure;
 498
 499 procedure a2_abs_xy (is_x : in boolean) is
 500 begin
 501     if exec_cycle = T1 then
 502         fetch_low;
 503     elsif exec_cycle = T2 then
 504         abs_fetch_high;
 505     elsif exec_cycle = T3 then
 506         --ea calc & lda
 507         pg_next_n <= '1';
 508         abs_latch_out;
 509         if (is_x = true) then
 510             ea_x_out;
 511         else
 512             ea_y_out;
 513         end if;
 514         dbuf_int_oe_n <= '0';
 515
 516         wk_next_cycle <= T0;
 517         d_print("absx step 1");
 518     elsif (exec_cycle = T0 and ea_carry_reg = '1') then
 519         --case page boundary crossed.
 520         --redo inst.
 521         d_print("absx 5 (page boudary crossed.)");
 522         --next page.
 523         pg_next_n <= '0';
 524         wk_next_cycle <= T0;
 525     end if;
 526 end  procedure;
 527
 528 procedure a2_zp_xy (is_x : in boolean) is
 529 begin
 530     if exec_cycle = T1 then
 531         fetch_low;
 532     elsif exec_cycle = T2 then
 533         fetch_stop;
 534         --output BAL only
 535         dbuf_int_oe_n <= '0';
 536         dl_al_we_n <= '1';
 537
 538         --calc zp.
 539         dl_al_oe_n <= '0';
 540         zp_n <= '0';
 541         wk_next_cycle <= T3;
 542     elsif exec_cycle = T3 then
 543         --t3 zp, xy
 544         zp_xy_n <= '0';
 545         if (is_x = true) then
 546             back_oe(wk_x_cmd, '0');
 547         else
 548             back_oe(wk_y_cmd, '0');
 549         end if;
 550         wk_next_cycle <= T0;
 551     end if;
 552 end  procedure;
 553
 554 procedure a2_indir_y is
 555 begin
 556     if exec_cycle = T1 then
 557         fetch_low;
 558         --get IAL
 559         dl_al_we_n <= '0';
 560
 561     elsif exec_cycle = T2 then
 562         fetch_stop;
 563         dl_al_we_n <= '1';
 564
 565         ---address is 00:IAL
 566         --output BAL @IAL
 567         indir_y_n <= '0';
 568         dl_al_oe_n <= '0';
 569         dbuf_int_oe_n <= '0';
 570         wk_next_cycle <= T3;
 571
 572     elsif exec_cycle = T3 then
 573         indir_y_n <= '0';
 574         dl_al_oe_n <= '0';
 575         --output BAH @IAL+1
 576         dbuf_int_oe_n <= '0';
 577         wk_next_cycle <= T4;
 578
 579     elsif exec_cycle = T4 then
 580         dl_al_oe_n <= '1';
 581         dbuf_int_oe_n <= '1';
 582
 583         --add index y.
 584         pg_next_n <= '1';
 585         back_oe(wk_y_cmd, '0');
 586         indir_y_n <= '0';
 587         dbuf_int_oe_n <= '0';
 588
 589         if (ea_carry = '1') then
 590             wk_next_cycle <= T5;
 591         else
 592             wk_next_cycle <= T0;
 593         end if;
 594     elsif (exec_cycle = T5) then
 595         --case page boundary crossed.
 596         --redo inst.
 597         d_print("(indir), y (page boudary crossed.)");
 598         --next page.
 599         pg_next_n <= '0';
 600         wk_next_cycle <= T0;
 601     end if;
 602 end  procedure;
 603
 604 procedure a2_indir_x is
 605 begin
 606     if exec_cycle = T1 then
 607         fetch_low;
 608         --get IAL
 609         dl_al_we_n <= '0';
 610
 611     elsif exec_cycle = T2 then
 612         fetch_stop;
 613         dl_al_we_n <= '1';
 614
 615         ---address is 00:IAL
 616         --output BAL @IAL, but cycle #2 is discarded
 617         indir_x_n <= '0';
 618         dl_al_oe_n <= '0';
 619         wk_next_cycle <= T3;
 620
 621     elsif exec_cycle = T3 then
 622         indir_x_n <= '0';
 623         dl_al_oe_n <= '1';
 624
 625         --output BAH @IAL+x
 626         dbuf_int_oe_n <= '0';
 627         back_oe(wk_x_cmd, '0');
 628         wk_next_cycle <= T4;
 629
 630     elsif exec_cycle = T4 then
 631         indir_x_n <= '0';
 632
 633         --output BAH @IAL+x+1
 634         dbuf_int_oe_n <= '0';
 635         back_oe(wk_x_cmd, '0');
 636
 637         wk_next_cycle <= T5;
 638     elsif (exec_cycle = T5) then
 639         indir_x_n <= '0';
 640         wk_next_cycle <= T0;
 641     end if;
 642 end  procedure;
 643
 644 --A.3. store operation.
 645
 646 procedure a3_zp is
 647 begin
 648     if exec_cycle = T1 then
 649         fetch_low;
 650     elsif exec_cycle = T2 then
 651         fetch_stop;
 652         dbuf_int_oe_n <= '1';
 653         dl_al_we_n <= '1';
 654
 655         --calc zp.
 656         dl_al_oe_n <= '0';
 657         zp_n <= '0';
 658         r_nw <= '0';
 659         wk_next_cycle <= T0;
 660     end if;
 661 end  procedure;
 662
 663 procedure a3_zp_xy (is_x : in boolean) is
 664 begin
 665     if exec_cycle = T1 then
 666         fetch_low;
 667     elsif exec_cycle = T2 then
 668         fetch_stop;
 669         dbuf_int_oe_n <= '1';
 670         dl_al_we_n <= '1';
 671
 672         --calc zp.
 673         dl_al_oe_n <= '0';
 674         zp_n <= '0';
 675         wk_next_cycle <= T3;
 676     elsif exec_cycle = T3 then
 677         --calc zp + index.
 678         dl_al_oe_n <= '0';
 679         zp_n <= '0';
 680         zp_xy_n <= '0';
 681         if (is_x = true) then
 682             back_oe(wk_x_cmd, '0');
 683         else
 684             back_oe(wk_y_cmd, '0');
 685         end if;
 686
 687         --write data
 688         r_nw <= '0';
 689         wk_next_cycle <= T0;
 690     end if;
 691 end  procedure;
 692
 693 procedure a3_abs is
 694 begin
 695     if exec_cycle = T1 then
 696         fetch_low;
 697     elsif exec_cycle = T2 then
 698         abs_fetch_high;
 699     elsif exec_cycle = T3 then
 700         abs_latch_out;
 701         dbuf_int_oe_n <= '1';
 702         r_nw <= '0';
 703         wk_next_cycle <= T0;
 704     end if;
 705 end  procedure;
 706
 707 procedure a3_abs_xy (is_x : in boolean) is
 708 begin
 709     if exec_cycle = T1 then
 710         fetch_low;
 711     elsif exec_cycle = T2 then
 712         abs_fetch_high;
 713     elsif exec_cycle = T3 then
 714         --ea calc & lda
 715         pg_next_n <= '1';
 716         abs_latch_out;
 717         dbuf_int_oe_n <= '1';
 718         if (is_x = true) then
 719             ea_x_out;
 720         else
 721             ea_y_out;
 722         end if;
 723         wk_next_cycle <= T4;
 724     elsif exec_cycle = T4 then
 725         if (ea_carry_reg = '1') then
 726             pg_next_n <= '0';
 727         else
 728             pg_next_n <= '1';
 729         end if;
 730         abs_latch_out;
 731         if (is_x = true) then
 732             ea_x_out;
 733         else
 734             ea_y_out;
 735         end if;
 736         r_nw <= '0';
 737         wk_next_cycle <= T0;
 738     end if;
 739 end  procedure;
 740
 741
 742 procedure a3_indir_y is
 743 begin
 744     if exec_cycle = T1 then
 745         fetch_low;
 746         --get IAL
 747         dl_al_we_n <= '0';
 748
 749     elsif exec_cycle = T2 then
 750         fetch_stop;
 751         dl_al_we_n <= '1';
 752
 753         ---address is 00:IAL
 754         --output BAL @IAL
 755         indir_y_n <= '0';
 756         dl_al_oe_n <= '0';
 757         dbuf_int_oe_n <= '0';
 758         wk_next_cycle <= T3;
 759
 760     elsif exec_cycle = T3 then
 761         indir_y_n <= '0';
 762         dl_al_oe_n <= '0';
 763         --output BAH @IAL+1
 764         dbuf_int_oe_n <= '0';
 765         wk_next_cycle <= T4;
 766
 767     elsif exec_cycle = T4 then
 768         dl_al_oe_n <= '1';
 769         dbuf_int_oe_n <= '1';
 770
 771         --add index y.
 772         pg_next_n <= '1';
 773         back_oe(wk_y_cmd, '0');
 774         indir_y_n <= '0';
 775         wk_next_cycle <= T5;
 776
 777     elsif exec_cycle = T5 then
 778         --page handling.
 779         back_oe(wk_y_cmd, '1');
 780         indir_y_n <= '0';
 781
 782         --ea_carry reg is suspicious. timing is not garanteed...
 783         if (ea_carry_reg = '1') then
 784             pg_next_n <= '0';
 785         else
 786             pg_next_n <= '1';
 787         end if;
 788         r_nw <= '0';
 789         wk_next_cycle <= T0;
 790     end if;
 791 end  procedure;
 792
 793 procedure a3_indir_x is
 794 begin
 795     if exec_cycle = T1 then
 796         fetch_low;
 797         --get IAL
 798         dl_al_we_n <= '0';
 799
 800     elsif exec_cycle = T2 then
 801         fetch_stop;
 802         dl_al_we_n <= '1';
 803
 804         ---address is 00:IAL
 805         --output BAL @IAL, but cycle #2 is discarded
 806         indir_x_n <= '0';
 807         dl_al_oe_n <= '0';
 808         wk_next_cycle <= T3;
 809
 810     elsif exec_cycle = T3 then
 811         indir_x_n <= '0';
 812         dl_al_oe_n <= '1';
 813
 814         --output BAH @IAL+x
 815         dbuf_int_oe_n <= '0';
 816         back_oe(wk_x_cmd, '0');
 817         wk_next_cycle <= T4;
 818
 819     elsif exec_cycle = T4 then
 820         indir_x_n <= '0';
 821
 822         --output BAH @IAL+x+1
 823         dbuf_int_oe_n <= '0';
 824         back_oe(wk_x_cmd, '0');
 825
 826         wk_next_cycle <= T5;
 827     elsif (exec_cycle = T5) then
 828         indir_x_n <= '0';
 829         dbuf_int_oe_n <= '1';
 830         r_nw <= '0';
 831         wk_next_cycle <= T0;
 832     end if;
 833 end  procedure;
 834
 835 ---A.4. read-modify-write operation
 836
 837 procedure a4_zp is
 838 begin
 839     if exec_cycle = T1 then
 840         fetch_low;
 841     elsif exec_cycle = T2 then
 842         fetch_stop;
 843         dl_al_we_n <= '1';
 844
 845         --t2 cycle read and,
 846         dl_al_oe_n <= '0';
 847         zp_n <= '0';
 848         --keep data in the alu reg.
 849         arith_en_n <= '0';
 850         dbuf_int_oe_n <= '0';
 851         wk_next_cycle <= T3;
 852     elsif exec_cycle = T3 then
 853         --t3 fix alu internal register.
 854         dl_al_oe_n <= '0';
 855         zp_n <= '0';
 856         arith_en_n <= '0';
 857         dbuf_int_oe_n <= '1';
 858         wk_next_cycle <= T4;
 859     elsif exec_cycle = T4 then
 860         --t5 cycle writes modified value.
 861         dl_al_oe_n <= '0';
 862         zp_n <= '0';
 863         r_nw <= '0';
 864         arith_en_n <= '0';
 865         wk_next_cycle <= T0;
 866     end if;
 867 end  procedure;
 868
 869 procedure a4_zp_x is
 870 begin
 871     if exec_cycle = T1 then
 872         fetch_low;
 873     elsif exec_cycle = T2 then
 874         fetch_stop;
 875         dbuf_int_oe_n <= '1';
 876         dl_al_we_n <= '1';
 877
 878         --t2 cycle read bal only.
 879         dl_al_oe_n <= '0';
 880         zp_n <= '0';
 881         wk_next_cycle <= T3;
 882     elsif exec_cycle = T3 then
 883         --t3 cycle read bal + x
 884         dl_al_oe_n <= '0';
 885         zp_n <= '0';
 886         zp_xy_n <= '0';
 887         back_oe(wk_x_cmd, '0');
 888
 889         --keep data in the alu reg.
 890         arith_en_n <= '0';
 891         dbuf_int_oe_n <= '0';
 892
 893         wk_next_cycle <= T4;
 894     elsif exec_cycle = T4 then
 895         dl_al_oe_n <= '0';
 896         zp_n <= '0';
 897         zp_xy_n <= '0';
 898         back_oe(wk_x_cmd, '0');
 899
 900         --fix alu internal register.
 901         arith_en_n <= '0';
 902         dbuf_int_oe_n <= '1';
 903         wk_next_cycle <= T5;
 904     elsif exec_cycle = T5 then
 905         dbuf_int_oe_n <= '1';
 906
 907         --t5 cycle writes modified value.
 908         dl_al_oe_n <= '0';
 909         zp_n <= '0';
 910         zp_xy_n <= '0';
 911         back_oe(wk_x_cmd, '0');
 912         r_nw <= '0';
 913         arith_en_n <= '0';
 914         wk_next_cycle <= T0;
 915     end if;
 916 end  procedure;
 917
 918
 919 procedure a4_abs is
 920 begin
 921     if exec_cycle = T1 then
 922         fetch_low;
 923     elsif exec_cycle = T2 then
 924         abs_fetch_high;
 925     elsif exec_cycle = T3 then
 926         abs_latch_out;
 927
 928         --keep data in the alu reg.
 929         arith_en_n <= '0';
 930         dbuf_int_oe_n <= '0';
 931         wk_next_cycle <= T4;
 932     elsif exec_cycle = T4 then
 933         abs_latch_out;
 934
 935         --fix alu internal register.
 936         arith_en_n <= '0';
 937         dbuf_int_oe_n <= '1';
 938         wk_next_cycle <= T5;
 939     elsif exec_cycle = T5 then
 940         dbuf_int_oe_n <= '1';
 941
 942         --t5 cycle writes modified value.
 943         r_nw <= '0';
 944         arith_en_n <= '0';
 945         wk_next_cycle <= T0;
 946     end if;
 947 end  procedure;
 948
 949 procedure a4_abs_x is
 950 begin
 951     if exec_cycle = T1 then
 952         fetch_low;
 953     elsif exec_cycle = T2 then
 954         abs_fetch_high;
 955     elsif exec_cycle = T3 then
 956         --T3 cycle discarded.
 957         pg_next_n <= '1';
 958         abs_latch_out;
 959         ea_x_out;
 960         dbuf_int_oe_n <= '0';
 961         wk_next_cycle <= T4;
 962
 963     elsif exec_cycle = T4 then
 964         abs_latch_out;
 965         ea_x_out;
 966         if (ea_carry_reg = '1') then
 967             pg_next_n <= '0';
 968         else
 969             pg_next_n <= '1';
 970         end if;
 971
 972         --keep data in the alu reg.
 973         arith_en_n <= '0';
 974         dbuf_int_oe_n <= '0';
 975         wk_next_cycle <= T5;
 976
 977     elsif exec_cycle = T5 then
 978         --fix alu internal register.
 979         arith_en_n <= '0';
 980         dbuf_int_oe_n <= '1';
 981         wk_next_cycle <= T6;
 982
 983     elsif exec_cycle = T6 then
 984         --t5 cycle writes modified value.
 985         r_nw <= '0';
 986         arith_en_n <= '0';
 987         wk_next_cycle <= T0;
 988
 989     end if;
 990 end  procedure;
 991
 992
 993 -- A.5.1 push stack
 994 procedure a51_push is
 995 begin
 996     if exec_cycle = T1 then
 997         fetch_stop;
 998         wk_next_cycle <= T2;
 999     elsif exec_cycle = T2 then
1000         back_oe(sp_cmd, '0');
1001         back_we(sp_cmd, '0');
1002         sp_push_n <= '0';
1003         sp_oe_n <= '0';
1004         r_nw <= '0';
1005         wk_next_cycle <= T0;
1006     end if;
1007 end procedure;
1008
1009 -- A.5.2 pull stack
1010 procedure a52_pull is
1011 begin
1012     if exec_cycle = T1 then
1013         fetch_stop;
1014         wk_next_cycle <= T2;
1015
1016     elsif exec_cycle = T2 then
1017         --stack decrement first.
1018         back_oe(sp_cmd, '0');
1019         back_we(sp_cmd, '0');
1020         sp_pop_n <= '0';
1021         sp_oe_n <= '0';
1022         wk_next_cycle <= T3;
1023
1024     elsif exec_cycle = T3 then
1025         sp_pop_n <= '1';
1026         back_we(sp_cmd, '1');
1027
1028         ---pop data from stack.
1029         back_oe(sp_cmd, '0');
1030         sp_oe_n <= '0';
1031         dbuf_int_oe_n <= '0';
1032         wk_next_cycle <= T0;
1033     end if;
1034 end procedure;
1035
1036
1037 -- A.5.8 branch operations
1038
1039 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
1040 begin
1041     if exec_cycle = T1 then
1042         fetch_next;
1043         if status_reg(int_flg) = br_cond then
1044             d_print("get rel");
1045
1046             --latch rel value.
1047             dbuf_int_oe_n <= '0';
1048             dl_ah_we_n <= '0';
1049             wk_next_cycle <= T2;
1050         else
1051             d_print("no branch");
1052             wk_next_cycle <= T0;
1053         end if;
1054     elsif exec_cycle = T2 then
1055         d_print("rel ea");
1056         fetch_stop;
1057         dbuf_int_oe_n <= '1';
1058         dl_ah_we_n <= '1';
1059
1060         --calc relative addr.
1061         rel_calc_n <= '0';
1062         pg_next_n <= '1';
1063         dl_dh_oe_n <= '0';
1064         back_oe(pcl_cmd, '0');
1065         back_oe(pch_cmd, '0');
1066         back_we(pcl_cmd, '0');
1067
1068         wk_next_cycle <= T0;
1069     elsif (exec_cycle = T0 and ea_carry = '1') then
1070         d_print("page crossed.");
1071         --page crossed. adh calc.
1072         back_we(pcl_cmd, '1');
1073         back_oe(pcl_cmd, '0');
1074         back_oe(pch_cmd, '0');
1075         back_we(pch_cmd, '0');
1076         dl_dh_oe_n <= '0';
1077
1078         rel_calc_n <= '0';
1079         pg_next_n <= '0';
1080         wk_next_cycle <= T0;
1081     end if;
1082 end  procedure;
1083
1084 -------------------------------------------------------------
1085 -------------------------------------------------------------
1086 ---------------- main state machine start.... ---------------
1087 -------------------------------------------------------------
1088 -------------------------------------------------------------
1089     begin
1090
1091         if (res_n = '0') then
1092             --prevent status revister from broken.
1093             stat_dec_oe_n <= '0';
1094             stat_bus_oe_n <= '1';
1095             stat_set_flg_n <= '1';
1096             stat_flg <= '1';
1097             stat_bus_all_n <= '1';
1098             stat_bus_nz_n <= '1';
1099             wk_stat_alu_we_n <= '1';
1100
1101             --pc l/h is reset vector.
1102             pcl_cmd <= "1110";
1103             pch_cmd <= "1110";
1104             wk_next_cycle <= R0;
1105
1106         elsif (rising_edge(set_clk)) then
1107             d_print(string'("-"));
1108
1109             if (nmi_n = '1') then
1110                 --nmi handle flag reset.
1111                 nmi_handled_n <= '1';
1112             end if;
1113
1114             if rdy = '0' then
1115                 --case dma is runnting.
1116                 disable_pins;
1117                 inst_we_n <= '1';
1118                 ad_oe_n <= '1';
1119                 dl_al_oe_n <= '1';
1120                 pcl_inc_n <= '1';
1121                 pcl_cmd <= "1111";
1122                 pch_cmd <= "1111";
1123                 r_nw <= 'Z';
1124             elsif (exec_cycle = T0 and ea_carry = '0') then
1125                 --cycle #1
1126                 t0_cycle;
1127
1128             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
1129                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or
1130                 (exec_cycle = T0 and ea_carry = '1') then
1131                 --execute inst.
1132
1133                 ---asyncronous page change might happen.
1134                 back_we(pch_cmd, '1');
1135
1136                 if exec_cycle = T1 then
1137                     d_print("decode and execute inst: "
1138                             & conv_hex8(conv_integer(instruction)));
1139                     --disable pin for jmp instruction
1140                     dl_al_oe_n <= '1';
1141                     back_we(pcl_cmd, '1');
1142                     front_we(pch_cmd, '1');
1143
1144                     --grab instruction register data.
1145                     inst_we_n <= '1';
1146                 end if;
1147
1148                 --imelementation is wriiten in the order of hardware manual
1149                 --appendix A.
1150
1151                 ----------------------------------------
1152                 --A.1. Single byte instruction.
1153                 ----------------------------------------
1154                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
1155                     --asl acc mode.
1156                     d_print("asl");
1157                     arith_en_n <= '0';
1158                     back_oe(wk_acc_cmd, '0');
1159                     front_we(wk_acc_cmd, '0');
1160                     set_nzc_from_alu;
1161                     single_inst;
1162
1163                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
1164                     d_print("clc");
1165                     set_flag0 ('0');
1166                     single_inst;
1167
1168                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
1169                     d_print("cld");
1170                     set_flag (st_D, '0');
1171                     single_inst;
1172
1173                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
1174                     d_print("cli");
1175                     set_flag (st_I, '0');
1176                     single_inst;
1177
1178                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
1179                     d_print("clv");
1180                     set_flag (st_V, '0');
1181                     single_inst;
1182
1183                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
1184                     d_print("dex");
1185                     arith_en_n <= '0';
1186                     back_oe(wk_x_cmd, '0');
1187                     front_we(wk_x_cmd, '0');
1188                     --set nz bit.
1189                     set_nz_from_bus;
1190                     single_inst;
1191
1192                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
1193                     d_print("dey");
1194                     arith_en_n <= '0';
1195                     back_oe(wk_y_cmd, '0');
1196                     front_we(wk_y_cmd, '0');
1197                     --set nz bit.
1198                     set_nz_from_bus;
1199                     single_inst;
1200
1201                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
1202                     d_print("inx");
1203                     arith_en_n <= '0';
1204                     back_oe(wk_x_cmd, '0');
1205                     front_we(wk_x_cmd, '0');
1206                     --set nz bit.
1207                     set_nz_from_bus;
1208                     single_inst;
1209
1210                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
1211                     d_print("iny");
1212                     arith_en_n <= '0';
1213                     back_oe(wk_y_cmd, '0');
1214                     front_we(wk_y_cmd, '0');
1215                     set_nz_from_bus;
1216                     single_inst;
1217
1218                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
1219                     --lsr acc mode
1220                     d_print("lsr");
1221                     arith_en_n <= '0';
1222                     back_oe(wk_acc_cmd, '0');
1223                     front_we(wk_acc_cmd, '0');
1224                     set_zc_from_alu;
1225                     single_inst;
1226
1227                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
1228                     d_print("nop");
1229                     single_inst;
1230
1231                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
1232                     --rol acc
1233                     d_print("rol");
1234                     arith_en_n <= '0';
1235                     back_oe(wk_acc_cmd, '0');
1236                     front_we(wk_acc_cmd, '0');
1237                     set_nzc_from_alu;
1238                     single_inst;
1239
1240                 elsif instruction = conv_std_logic_vector(16#6a#, dsize) then
1241                     --ror acc
1242                     d_print("ror");
1243                     arith_en_n <= '0';
1244                     back_oe(wk_acc_cmd, '0');
1245                     front_we(wk_acc_cmd, '0');
1246                     set_nzc_from_alu;
1247                     single_inst;
1248
1249                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
1250                     d_print("sec");
1251                     set_flag0 ('1');
1252                     single_inst;
1253
1254                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
1255                     d_print("sed");
1256                     set_flag (st_D, '1');
1257                     single_inst;
1258
1259                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
1260                     d_print("sei");
1261                     set_flag (st_I, '1');
1262                     single_inst;
1263
1264                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
1265                     d_print("tax");
1266                     set_nz_from_bus;
1267                     single_inst;
1268                     front_oe(wk_acc_cmd, '0');
1269                     front_we(wk_x_cmd, '0');
1270
1271                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
1272                     d_print("tay");
1273                     set_nz_from_bus;
1274                     single_inst;
1275                     front_oe(wk_acc_cmd, '0');
1276                     front_we(wk_y_cmd, '0');
1277
1278                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
1279                     d_print("tsx");
1280                     set_nz_from_bus;
1281                     single_inst;
1282                     front_oe(sp_cmd, '0');
1283                     front_we(wk_x_cmd, '0');
1284
1285                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1286                     d_print("txa");
1287                     set_nz_from_bus;
1288                     single_inst;
1289                     front_oe(wk_x_cmd, '0');
1290                     front_we(wk_acc_cmd, '0');
1291
1292                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1293                     d_print("txs");
1294                     set_nz_from_bus;
1295                     single_inst;
1296                     front_oe(wk_x_cmd, '0');
1297                     front_we(sp_cmd, '0');
1298
1299                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1300                     d_print("tya");
1301                     set_nz_from_bus;
1302                     single_inst;
1303                     front_oe(wk_y_cmd, '0');
1304                     front_we(wk_acc_cmd, '0');
1305
1306
1307
1308                 ----------------------------------------
1309                 --A.2. internal execution on memory data
1310                 ----------------------------------------
1311                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1312                     --imm
1313                     d_print("adc");
1314                     fetch_imm;
1315                     arith_en_n <= '0';
1316                     back_oe(wk_acc_cmd, '0');
1317                     back_we(wk_acc_cmd, '0');
1318                     set_nvzc_from_alu;
1319
1320                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1321                     --zp
1322                     d_print("adc");
1323                     a2_zp;
1324                     if exec_cycle = T2 then
1325                         arith_en_n <= '0';
1326                         back_oe(wk_acc_cmd, '0');
1327                         back_we(wk_acc_cmd, '0');
1328                         set_nvzc_from_alu;
1329                     end if;
1330
1331                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1332                     --zp, x
1333                     d_print("adc");
1334                     a2_zp_xy(true);
1335                     if exec_cycle = T3 then
1336                         arith_en_n <= '0';
1337                         back_oe(wk_acc_cmd, '0');
1338                         back_we(wk_acc_cmd, '0');
1339                         set_nvzc_from_alu;
1340                     end if;
1341
1342                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1343                     --abs
1344                     d_print("adc");
1345                     a2_abs;
1346                     if exec_cycle = T3 then
1347                         arith_en_n <= '0';
1348                         back_oe(wk_acc_cmd, '0');
1349                         back_we(wk_acc_cmd, '0');
1350                         set_nvzc_from_alu;
1351                     end if;
1352
1353                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1354                     --abs, x
1355                     d_print("adc");
1356                     a2_abs_xy(true);
1357                     if exec_cycle = T3 or exec_cycle = T0 then
1358                         arith_en_n <= '0';
1359                         back_oe(wk_acc_cmd, '0');
1360                         back_we(wk_acc_cmd, '0');
1361                         set_nvzc_from_alu;
1362                     end if;
1363
1364                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1365                     --abs, y
1366                     d_print("adc");
1367                     a2_abs_xy(false);
1368                     if exec_cycle = T3 or exec_cycle = T0 then
1369                         arith_en_n <= '0';
1370                         back_oe(wk_acc_cmd, '0');
1371                         back_we(wk_acc_cmd, '0');
1372                         set_nvzc_from_alu;
1373                     end if;
1374
1375                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1376                     --(indir, x)
1377                     d_print("adc");
1378                     a2_indir_x;
1379                     if exec_cycle = T5 then
1380                         arith_en_n <= '0';
1381                         back_oe(wk_acc_cmd, '0');
1382                         back_we(wk_acc_cmd, '0');
1383                         set_nvzc_from_alu;
1384                     end if;
1385
1386                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1387                     --(indir), y
1388                     d_print("adc");
1389                     a2_indir_y;
1390                     if exec_cycle = T4 or exec_cycle = T0 then
1391                         arith_en_n <= '0';
1392                         back_oe(wk_acc_cmd, '0');
1393                         back_we(wk_acc_cmd, '0');
1394                         set_nvzc_from_alu;
1395                     end if;
1396
1397                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1398                     --imm
1399                     d_print("and");
1400                     fetch_imm;
1401                     arith_en_n <= '0';
1402                     back_oe(wk_acc_cmd, '0');
1403                     back_we(wk_acc_cmd, '0');
1404                     set_nz_from_alu;
1405
1406                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1407                     --zp
1408                     d_print("and");
1409                     a2_zp;
1410                     if exec_cycle = T2 then
1411                         arith_en_n <= '0';
1412                         back_oe(wk_acc_cmd, '0');
1413                         back_we(wk_acc_cmd, '0');
1414                         set_nz_from_alu;
1415                     end if;
1416
1417                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1418                     --zp, x
1419                     d_print("and");
1420                     a2_zp_xy(true);
1421                     if exec_cycle = T3 then
1422                         arith_en_n <= '0';
1423                         back_oe(wk_acc_cmd, '0');
1424                         back_we(wk_acc_cmd, '0');
1425                         set_nz_from_alu;
1426                     end if;
1427
1428                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1429                     --abs
1430                     d_print("and");
1431                     a2_abs;
1432                     if exec_cycle = T3 then
1433                         arith_en_n <= '0';
1434                         back_oe(wk_acc_cmd, '0');
1435                         back_we(wk_acc_cmd, '0');
1436                         set_nz_from_alu;
1437                     end if;
1438
1439                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1440                     --abs, x
1441                     d_print("and");
1442                     a2_abs_xy(true);
1443                     if exec_cycle = T3 or exec_cycle = T0 then
1444                         arith_en_n <= '0';
1445                         back_oe(wk_acc_cmd, '0');
1446                         back_we(wk_acc_cmd, '0');
1447                         set_nz_from_alu;
1448                     end if;
1449
1450                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1451                     --abs, y
1452                     d_print("and");
1453                     a2_abs_xy(false);
1454                     if exec_cycle = T3 or exec_cycle = T0 then
1455                         arith_en_n <= '0';
1456                         back_oe(wk_acc_cmd, '0');
1457                         back_we(wk_acc_cmd, '0');
1458                         set_nz_from_alu;
1459                     end if;
1460
1461                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1462                     --(indir, x)
1463                     d_print("and");
1464                     a2_indir_x;
1465                     if exec_cycle = T5 then
1466                         arith_en_n <= '0';
1467                         back_oe(wk_acc_cmd, '0');
1468                         back_we(wk_acc_cmd, '0');
1469                         set_nz_from_alu;
1470                     end if;
1471
1472                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1473                     --(indir), y
1474                     d_print("and");
1475                     a2_indir_y;
1476                     if exec_cycle = T4 or exec_cycle = T0 then
1477                         arith_en_n <= '0';
1478                         back_oe(wk_acc_cmd, '0');
1479                         back_we(wk_acc_cmd, '0');
1480                         set_nz_from_alu;
1481                     end if;
1482
1483                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1484                     --zp
1485                     d_print("bit");
1486                     a2_zp;
1487                     if exec_cycle = T2 then
1488                         arith_en_n <= '0';
1489                         back_oe(wk_acc_cmd, '0');
1490                         set_nvz_from_alu;
1491                     end if;
1492
1493                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1494                     --abs
1495                     d_print("bit");
1496                     a2_abs;
1497                     if exec_cycle = T3 then
1498                         arith_en_n <= '0';
1499                         back_oe(wk_acc_cmd, '0');
1500                         set_nvz_from_alu;
1501                     end if;
1502
1503                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1504                     --imm
1505                     d_print("cmp");
1506                     fetch_imm;
1507                     arith_en_n <= '0';
1508                     back_oe(wk_acc_cmd, '0');
1509                     set_nzc_from_alu;
1510
1511                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1512                     --zp
1513                     d_print("cmp");
1514                     a2_zp;
1515                     if exec_cycle = T2 then
1516                         arith_en_n <= '0';
1517                         back_oe(wk_acc_cmd, '0');
1518                         set_nzc_from_alu;
1519                     end if;
1520
1521                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1522                     --zp, x
1523                     d_print("cmp");
1524                     a2_zp_xy(true);
1525                     if exec_cycle = T3 then
1526                         arith_en_n <= '0';
1527                         back_oe(wk_acc_cmd, '0');
1528                         set_nzc_from_alu;
1529                     end if;
1530
1531                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1532                     --abs
1533                     d_print("cmp");
1534                     a2_abs;
1535                     if exec_cycle = T3 then
1536                         arith_en_n <= '0';
1537                         back_oe(wk_acc_cmd, '0');
1538                         set_nzc_from_alu;
1539                     end if;
1540
1541                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1542                     --abs, x
1543                     d_print("cmp");
1544                     a2_abs_xy(true);
1545                     if exec_cycle = T3 or exec_cycle = T0 then
1546                         arith_en_n <= '0';
1547                         back_oe(wk_acc_cmd, '0');
1548                         set_nzc_from_alu;
1549                     end if;
1550
1551                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1552                     --abs, y
1553                     d_print("cmp");
1554                     a2_abs_xy(false);
1555                     if exec_cycle = T3 or exec_cycle = T0 then
1556                         arith_en_n <= '0';
1557                         back_oe(wk_acc_cmd, '0');
1558                         set_nzc_from_alu;
1559                     end if;
1560
1561                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1562                     --(indir, x)
1563                     d_print("cmp");
1564                     a2_indir_x;
1565                     if exec_cycle = T5 then
1566                         arith_en_n <= '0';
1567                         back_oe(wk_acc_cmd, '0');
1568                         set_nzc_from_alu;
1569                     end if;
1570
1571                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1572                     --(indir), y
1573                     d_print("cmp");
1574                     a2_indir_y;
1575                     if exec_cycle = T4 or exec_cycle = T0 then
1576                         arith_en_n <= '0';
1577                         back_oe(wk_acc_cmd, '0');
1578                         set_nzc_from_alu;
1579                     end if;
1580
1581                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1582                     --imm
1583                     d_print("cpx");
1584                     fetch_imm;
1585                     arith_en_n <= '0';
1586                     back_oe(wk_x_cmd, '0');
1587                     set_nzc_from_alu;
1588
1589                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1590                     --zp
1591                     d_print("cpx");
1592                     a2_zp;
1593                     if exec_cycle = T2 then
1594                         arith_en_n <= '0';
1595                         back_oe(wk_x_cmd, '0');
1596                         set_nzc_from_alu;
1597                     end if;
1598
1599                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1600                     --abs
1601                     d_print("cpx");
1602                     a2_abs;
1603                     if exec_cycle = T3 then
1604                         arith_en_n <= '0';
1605                         back_oe(wk_x_cmd, '0');
1606                         set_nzc_from_alu;
1607                     end if;
1608
1609                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1610                     --imm
1611                     d_print("cpy");
1612                     fetch_imm;
1613                     arith_en_n <= '0';
1614                     back_oe(wk_y_cmd, '0');
1615                     set_nzc_from_alu;
1616
1617                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1618                     --zp
1619                     d_print("cpy");
1620                     a2_zp;
1621                     if exec_cycle = T2 then
1622                         arith_en_n <= '0';
1623                         back_oe(wk_y_cmd, '0');
1624                         set_nzc_from_alu;
1625                     end if;
1626
1627                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1628                     --abs
1629                     d_print("cpy");
1630                     a2_abs;
1631                     if exec_cycle = T3 then
1632                         arith_en_n <= '0';
1633                         back_oe(wk_y_cmd, '0');
1634                         set_nzc_from_alu;
1635                     end if;
1636
1637                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1638                     --imm
1639                     d_print("eor");
1640                     fetch_imm;
1641                     arith_en_n <= '0';
1642                     back_oe(wk_acc_cmd, '0');
1643                     back_we(wk_acc_cmd, '0');
1644                     set_nz_from_alu;
1645
1646                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1647                     --zp
1648                     d_print("eor");
1649                     a2_zp;
1650                     if exec_cycle = T2 then
1651                         arith_en_n <= '0';
1652                         back_oe(wk_acc_cmd, '0');
1653                         back_we(wk_acc_cmd, '0');
1654                         set_nz_from_alu;
1655                     end if;
1656
1657                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1658                     --zp, x
1659                     d_print("eor");
1660                     a2_zp_xy(true);
1661                     if exec_cycle = T3 then
1662                         arith_en_n <= '0';
1663                         back_oe(wk_acc_cmd, '0');
1664                         back_we(wk_acc_cmd, '0');
1665                         set_nz_from_alu;
1666                     end if;
1667
1668                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1669                     --abs
1670                     d_print("eor");
1671                     a2_abs;
1672                     if exec_cycle = T3 then
1673                         arith_en_n <= '0';
1674                         back_oe(wk_acc_cmd, '0');
1675                         back_we(wk_acc_cmd, '0');
1676                         set_nz_from_alu;
1677                     end if;
1678
1679                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1680                     --abs, x
1681                     d_print("eor");
1682                     a2_abs_xy(true);
1683                     if exec_cycle = T3 or exec_cycle = T0 then
1684                         arith_en_n <= '0';
1685                         back_oe(wk_acc_cmd, '0');
1686                         back_we(wk_acc_cmd, '0');
1687                         set_nz_from_alu;
1688                     end if;
1689
1690                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1691                     --abs, y
1692                     d_print("eor");
1693                     a2_abs_xy(false);
1694                     if exec_cycle = T3 or exec_cycle = T0 then
1695                         arith_en_n <= '0';
1696                         back_oe(wk_acc_cmd, '0');
1697                         back_we(wk_acc_cmd, '0');
1698                         set_nz_from_alu;
1699                     end if;
1700
1701                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1702                     --(indir, x)
1703                     d_print("eor");
1704                     a2_indir_x;
1705                     if exec_cycle = T5 then
1706                         arith_en_n <= '0';
1707                         back_oe(wk_acc_cmd, '0');
1708                         back_we(wk_acc_cmd, '0');
1709                         set_nz_from_alu;
1710                     end if;
1711
1712                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1713                     --(indir), y
1714                     d_print("eor");
1715                     a2_indir_y;
1716                     if exec_cycle = T4 or exec_cycle = T0 then
1717                         arith_en_n <= '0';
1718                         back_oe(wk_acc_cmd, '0');
1719                         back_we(wk_acc_cmd, '0');
1720                         set_nz_from_alu;
1721                     end if;
1722
1723                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1724                     --imm
1725                     d_print("lda");
1726                     fetch_imm;
1727                     front_we(wk_acc_cmd, '0');
1728                     set_nz_from_bus;
1729
1730                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1731                     --zp
1732                     d_print("lda");
1733                     a2_zp;
1734                     if exec_cycle = T2 then
1735                         front_we(wk_acc_cmd, '0');
1736                         set_nz_from_bus;
1737                     end if;
1738
1739                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1740                     --zp, x
1741                     d_print("lda");
1742                     a2_zp_xy(true);
1743                     if exec_cycle = T3 then
1744                         front_we(wk_acc_cmd, '0');
1745                         set_nz_from_bus;
1746                     end if;
1747
1748                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1749                     --abs
1750                     d_print("lda");
1751                     a2_abs;
1752                     if exec_cycle = T3 then
1753                         set_nz_from_bus;
1754                         front_we(wk_acc_cmd, '0');
1755                     end if;
1756
1757                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1758                     --abs, x
1759                     d_print("lda");
1760                     a2_abs_xy(true);
1761                     if exec_cycle = T3 or exec_cycle = T0 then
1762                         --lda.
1763                         front_we(wk_acc_cmd, '0');
1764                         set_nz_from_bus;
1765                     end if;
1766
1767                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1768                     --abs, y
1769                     d_print("lda");
1770                     a2_abs_xy(false);
1771                     if exec_cycle = T3 or exec_cycle = T0 then
1772                         --lda.
1773                         front_we(wk_acc_cmd, '0');
1774                         set_nz_from_bus;
1775                     end if;
1776
1777                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1778                     --(indir, x)
1779                     d_print("lda");
1780                     a2_indir_x;
1781                     if exec_cycle = T5 then
1782                         front_we(wk_acc_cmd, '0');
1783                         set_nz_from_bus;
1784                     end if;
1785
1786                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1787                     --(indir), y
1788                     d_print("lda");
1789                     a2_indir_y;
1790                     if exec_cycle = T4 or exec_cycle = T0 then
1791                         --lda.
1792                         front_we(wk_acc_cmd, '0');
1793                         set_nz_from_bus;
1794                     end if;
1795
1796                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1797                     --imm
1798                     d_print("ldx");
1799                     fetch_imm;
1800                     set_nz_from_bus;
1801                     front_we(wk_x_cmd, '0');
1802
1803                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1804                     --zp
1805                     d_print("ldx");
1806                     a2_zp;
1807                     if exec_cycle = T2 then
1808                         front_we(wk_x_cmd, '0');
1809                         set_nz_from_bus;
1810                     end if;
1811
1812                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1813                     --zp, y
1814                     d_print("ldx");
1815                     a2_zp_xy(false);
1816                     if exec_cycle = T3 then
1817                         front_we(wk_x_cmd, '0');
1818                         set_nz_from_bus;
1819                     end if;
1820
1821                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1822                     --abs
1823                     d_print("ldx");
1824                     a2_abs;
1825                     if exec_cycle = T3 then
1826                         set_nz_from_bus;
1827                         front_we(wk_x_cmd, '0');
1828                     end if;
1829
1830                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1831                     --abs, y
1832                     d_print("ldx");
1833                     a2_abs_xy(false);
1834                     if exec_cycle = T3 or exec_cycle = T0 then
1835                         front_we(wk_x_cmd, '0');
1836                         set_nz_from_bus;
1837                     end if;
1838
1839                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1840                     --imm
1841                     d_print("ldy");
1842                     fetch_imm;
1843                     set_nz_from_bus;
1844                     front_we(wk_y_cmd, '0');
1845
1846                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1847                     --zp
1848                     d_print("ldy");
1849                     a2_zp;
1850                     if exec_cycle = T2 then
1851                         front_we(wk_y_cmd, '0');
1852                         set_nz_from_bus;
1853                     end if;
1854
1855                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1856                     --zp, x
1857                     d_print("ldy");
1858                     a2_zp_xy(true);
1859                     if exec_cycle = T3 then
1860                         front_we(wk_y_cmd, '0');
1861                         set_nz_from_bus;
1862                     end if;
1863
1864                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1865                     --abs
1866                     d_print("ldy");
1867                     a2_abs;
1868                     if exec_cycle = T3 then
1869                         set_nz_from_bus;
1870                         front_we(wk_y_cmd, '0');
1871                     end if;
1872
1873                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1874                     --abs, x
1875                     d_print("ldy");
1876                     a2_abs_xy(true);
1877                     if exec_cycle = T3 or exec_cycle = T0 then
1878                         set_nz_from_bus;
1879                         front_we(wk_y_cmd, '0');
1880                     end if;
1881
1882                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1883                     --imm
1884                     d_print("ora");
1885                     fetch_imm;
1886                     arith_en_n <= '0';
1887                     back_oe(wk_acc_cmd, '0');
1888                     back_we(wk_acc_cmd, '0');
1889                     set_nz_from_alu;
1890
1891                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1892                     --zp
1893                     d_print("ora");
1894                     a2_zp;
1895                     if exec_cycle = T2 then
1896                         arith_en_n <= '0';
1897                         back_oe(wk_acc_cmd, '0');
1898                         back_we(wk_acc_cmd, '0');
1899                         set_nz_from_alu;
1900                     end if;
1901
1902                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1903                     --zp, x
1904                     d_print("ora");
1905                     a2_zp_xy(true);
1906                     if exec_cycle = T3 then
1907                         arith_en_n <= '0';
1908                         back_oe(wk_acc_cmd, '0');
1909                         back_we(wk_acc_cmd, '0');
1910                         set_nz_from_alu;
1911                     end if;
1912
1913                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1914                     --abs
1915                     d_print("ora");
1916                     a2_abs;
1917                     if exec_cycle = T3 then
1918                         arith_en_n <= '0';
1919                         back_oe(wk_acc_cmd, '0');
1920                         back_we(wk_acc_cmd, '0');
1921                         set_nz_from_alu;
1922                     end if;
1923
1924                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1925                     --abs, x
1926                     d_print("ora");
1927                     a2_abs_xy(true);
1928                     if exec_cycle = T3 or exec_cycle = T0 then
1929                         arith_en_n <= '0';
1930                         back_oe(wk_acc_cmd, '0');
1931                         back_we(wk_acc_cmd, '0');
1932                         set_nz_from_alu;
1933                     end if;
1934
1935                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1936                     --abs, y
1937                     d_print("ora");
1938                     a2_abs_xy(false);
1939                     if exec_cycle = T3 or exec_cycle = T0 then
1940                         arith_en_n <= '0';
1941                         back_oe(wk_acc_cmd, '0');
1942                         back_we(wk_acc_cmd, '0');
1943                         set_nz_from_alu;
1944                     end if;
1945
1946                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
1947                     --(indir, x)
1948                     d_print("ora");
1949                     a2_indir_x;
1950                     if exec_cycle = T5 then
1951                         arith_en_n <= '0';
1952                         back_oe(wk_acc_cmd, '0');
1953                         back_we(wk_acc_cmd, '0');
1954                         set_nz_from_alu;
1955                     end if;
1956
1957                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
1958                     --(indir), y
1959                     d_print("ora");
1960                     a2_indir_y;
1961                     if exec_cycle = T4 or exec_cycle = T0 then
1962                         arith_en_n <= '0';
1963                         back_oe(wk_acc_cmd, '0');
1964                         back_we(wk_acc_cmd, '0');
1965                         set_nz_from_alu;
1966                     end if;
1967
1968                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
1969                     --imm
1970                     d_print("sbc");
1971                     fetch_imm;
1972                     arith_en_n <= '0';
1973                     back_oe(wk_acc_cmd, '0');
1974                     back_we(wk_acc_cmd, '0');
1975                     set_nvzc_from_alu;
1976
1977                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
1978                     --zp
1979                     d_print("sbc");
1980                     a2_zp;
1981                     if exec_cycle = T2 then
1982                         arith_en_n <= '0';
1983                         back_oe(wk_acc_cmd, '0');
1984                         back_we(wk_acc_cmd, '0');
1985                         set_nvzc_from_alu;
1986                     end if;
1987
1988                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
1989                     --zp, x
1990                     d_print("sbc");
1991                     a2_zp_xy(true);
1992                     if exec_cycle = T3 then
1993                         arith_en_n <= '0';
1994                         back_oe(wk_acc_cmd, '0');
1995                         back_we(wk_acc_cmd, '0');
1996                         set_nvzc_from_alu;
1997                     end if;
1998
1999                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
2000                     --abs
2001                     d_print("sbc");
2002                     a2_abs;
2003                     if exec_cycle = T3 then
2004                         arith_en_n <= '0';
2005                         back_oe(wk_acc_cmd, '0');
2006                         back_we(wk_acc_cmd, '0');
2007                         set_nvzc_from_alu;
2008                     end if;
2009
2010                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
2011                     --abs, x
2012                     d_print("sbc");
2013                     a2_abs_xy(true);
2014                     if exec_cycle = T3 or exec_cycle = T0 then
2015                         arith_en_n <= '0';
2016                         back_oe(wk_acc_cmd, '0');
2017                         back_we(wk_acc_cmd, '0');
2018                         set_nvzc_from_alu;
2019                     end if;
2020
2021                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
2022                     --abs, y
2023                     d_print("sbc");
2024                     a2_abs_xy(false);
2025                     if exec_cycle = T3 or exec_cycle = T0 then
2026                         arith_en_n <= '0';
2027                         back_oe(wk_acc_cmd, '0');
2028                         back_we(wk_acc_cmd, '0');
2029                         set_nvzc_from_alu;
2030                     end if;
2031
2032                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
2033                     --(indir, x)
2034                     d_print("sbc");
2035                     a2_indir_x;
2036                     if exec_cycle = T5 then
2037                         arith_en_n <= '0';
2038                         back_oe(wk_acc_cmd, '0');
2039                         back_we(wk_acc_cmd, '0');
2040                         set_nvzc_from_alu;
2041                     end if;
2042
2043                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
2044                     --(indir), y
2045                     d_print("sbc");
2046                     a2_indir_y;
2047                     if exec_cycle = T4 or exec_cycle = T0 then
2048                         arith_en_n <= '0';
2049                         back_oe(wk_acc_cmd, '0');
2050                         back_we(wk_acc_cmd, '0');
2051                         set_nvzc_from_alu;
2052                     end if;
2053
2054
2055
2056                 ----------------------------------------
2057                 ---A.3. store operation.
2058                 ----------------------------------------
2059                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
2060                     --zp
2061                     d_print("sta");
2062                     a3_zp;
2063                     if exec_cycle = T2 then
2064                         front_oe(wk_acc_cmd, '0');
2065                     end if;
2066
2067                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
2068                     --zp, x
2069                     d_print("sta");
2070                     a3_zp_xy(true);
2071                     if exec_cycle = T2 then
2072                         front_oe(wk_acc_cmd, '0');
2073                     end if;
2074
2075                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
2076                     --abs
2077                     d_print("sta");
2078                     a3_abs;
2079                     if exec_cycle = T3 then
2080                         front_oe(wk_acc_cmd, '0');
2081                     end if;
2082
2083                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
2084                     --abs, x
2085                     d_print("sta");
2086                     a3_abs_xy (true);
2087                     if exec_cycle = T4 then
2088                         front_oe(wk_acc_cmd, '0');
2089                     end if;
2090
2091                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
2092                     --abs, y
2093                     d_print("sta");
2094                     a3_abs_xy (false);
2095                     if exec_cycle = T4 then
2096                         front_oe(wk_acc_cmd, '0');
2097                     end if;
2098
2099                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
2100                     --(indir, x)
2101                     d_print("sta");
2102                     a3_indir_x;
2103                     if exec_cycle = T5 then
2104                         front_oe(wk_acc_cmd, '0');
2105                     end if;
2106
2107                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
2108                     --(indir), y
2109                     d_print("sta");
2110                     a3_indir_y;
2111                     if exec_cycle = T5 then
2112                         front_oe(wk_acc_cmd, '0');
2113                     end if;
2114
2115                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
2116                     --zp
2117                     d_print("stx");
2118                     a3_zp;
2119                     if exec_cycle = T2 then
2120                         front_oe(wk_x_cmd, '0');
2121                     end if;
2122
2123                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
2124                     --zp, y
2125                     d_print("stx");
2126                     a3_zp_xy(false);
2127                     if exec_cycle = T2 then
2128                         front_oe(wk_x_cmd, '0');
2129                     end if;
2130
2131                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
2132                     --abs
2133                     d_print("stx");
2134                     a3_abs;
2135                     if exec_cycle = T3 then
2136                         front_oe(wk_x_cmd, '0');
2137                     end if;
2138
2139                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
2140                     --zp
2141                     d_print("sty");
2142                     a3_zp;
2143                     if exec_cycle = T2 then
2144                         front_oe(wk_y_cmd, '0');
2145                     end if;
2146
2147                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
2148                     --zp, x
2149                     d_print("sty");
2150                     a3_zp_xy(true);
2151                     if exec_cycle = T2 then
2152                         front_oe(wk_y_cmd, '0');
2153                     end if;
2154
2155                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
2156                     --abs
2157                     d_print("sty");
2158                     a3_abs;
2159                     if exec_cycle = T3 then
2160                         front_oe(wk_y_cmd, '0');
2161                     end if;
2162
2163
2164                 ----------------------------------------
2165                 ---A.4. read-modify-write operation
2166                 ----------------------------------------
2167                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
2168                     --zp
2169                     d_print("asl");
2170                     a4_zp;
2171                     if exec_cycle = T4 then
2172                         set_nzc_from_alu;
2173                     end if;
2174
2175                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
2176                     --zp, x
2177                     d_print("asl");
2178                     a4_zp_x;
2179                     if exec_cycle = T5 then
2180                         set_nzc_from_alu;
2181                     end if;
2182
2183                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
2184                     --abs
2185                     d_print("asl");
2186                     a4_abs;
2187                     if exec_cycle = T5 then
2188                         set_nzc_from_alu;
2189                     end if;
2190
2191                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
2192                     --abs, x
2193                     d_print("asl");
2194                     a4_abs_x;
2195                     if exec_cycle = T6 then
2196                         set_nzc_from_alu;
2197                     end if;
2198
2199                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
2200                     --zp
2201                     d_print("dec");
2202                     a4_zp;
2203                     if exec_cycle = T4 then
2204                         set_nz_from_bus;
2205                     end if;
2206
2207                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
2208                     --zp, x
2209                     d_print("dec");
2210                     a4_zp_x;
2211                     if exec_cycle = T5 then
2212                         set_nz_from_bus;
2213                     end if;
2214
2215                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
2216                     --abs
2217                     d_print("dec");
2218                     a4_abs;
2219                     if exec_cycle = T5 then
2220                         set_nz_from_bus;
2221                     end if;
2222
2223                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
2224                     --abs, x
2225                     d_print("dec");
2226                     a4_abs_x;
2227                     if exec_cycle = T6 then
2228                         set_nz_from_bus;
2229                     end if;
2230
2231                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
2232                     --zp
2233                     d_print("inc");
2234                     a4_zp;
2235                     if exec_cycle = T4 then
2236                         set_nz_from_bus;
2237                     end if;
2238
2239                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
2240                     --zp, x
2241                     d_print("inc");
2242                     a4_zp_x;
2243                     if exec_cycle = T5 then
2244                         set_nz_from_bus;
2245                     end if;
2246
2247                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
2248                     --abs
2249                     d_print("inc");
2250                     a4_abs;
2251                     if exec_cycle = T5 then
2252                         set_nz_from_bus;
2253                     end if;
2254
2255                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
2256                     --abs, x
2257                     d_print("inc");
2258                     a4_abs_x;
2259                     if exec_cycle = T6 then
2260                         set_nz_from_bus;
2261                     end if;
2262
2263                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
2264                     --zp
2265                     d_print("lsr");
2266                     a4_zp;
2267                     if exec_cycle = T4 then
2268                         set_zc_from_alu;
2269                     end if;
2270
2271                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
2272                     --zp, x
2273                     d_print("lsr");
2274                     a4_zp_x;
2275                     if exec_cycle = T5 then
2276                         set_zc_from_alu;
2277                     end if;
2278
2279                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
2280                     --abs
2281                     d_print("lsr");
2282                     a4_abs;
2283                     if exec_cycle = T5 then
2284                         set_zc_from_alu;
2285                     end if;
2286
2287                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
2288                     --abs, x
2289                     d_print("lsr");
2290                     a4_abs_x;
2291                     if exec_cycle = T6 then
2292                         set_zc_from_alu;
2293                     end if;
2294
2295                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
2296                     --zp
2297                     d_print("rol");
2298                     a4_zp;
2299                     if exec_cycle = T4 then
2300                         set_nzc_from_alu;
2301                     end if;
2302
2303                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
2304                     --zp, x
2305                     d_print("rol");
2306                     a4_zp_x;
2307                     if exec_cycle = T5 then
2308                         set_nzc_from_alu;
2309                     end if;
2310
2311                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
2312                     --abs
2313                     d_print("rol");
2314                     a4_abs;
2315                     if exec_cycle = T5 then
2316                         set_nzc_from_alu;
2317                     end if;
2318
2319                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
2320                     --abs, x
2321                     d_print("rol");
2322                     a4_abs_x;
2323                     if exec_cycle = T6 then
2324                         set_nzc_from_alu;
2325                     end if;
2326
2327                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
2328                     --zp
2329                     d_print("ror");
2330                     a4_zp;
2331                     if exec_cycle = T4 then
2332                         set_nzc_from_alu;
2333                     end if;
2334
2335                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
2336                     --zp, x
2337                     d_print("ror");
2338                     a4_zp_x;
2339                     if exec_cycle = T5 then
2340                         set_nzc_from_alu;
2341                     end if;
2342
2343                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
2344                     --abs
2345                     d_print("ror");
2346                     a4_abs;
2347                     if exec_cycle = T5 then
2348                         set_nzc_from_alu;
2349                     end if;
2350
2351                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
2352                     --abs, x
2353                     d_print("ror");
2354                     a4_abs_x;
2355                     if exec_cycle = T6 then
2356                         set_nzc_from_alu;
2357                     end if;
2358
2359
2360                 ----------------------------------------
2361                 --A.5. miscellaneous oprations.
2362                 ----------------------------------------
2363
2364                 -- A.5.1 push/pull
2365                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
2366                     d_print("php");
2367                     a51_push;
2368                     if exec_cycle = T2 then
2369                         stat_bus_oe_n <= '0';
2370                     end if;
2371
2372                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
2373                     d_print("pha");
2374                     a51_push;
2375                     if exec_cycle = T2 then
2376                         front_oe(wk_acc_cmd, '0');
2377                     end if;
2378
2379                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
2380                     d_print("plp");
2381                     a52_pull;
2382                     if exec_cycle = T3 then
2383                         stat_dec_oe_n <= '1';
2384                         stat_bus_all_n <= '0';
2385                     end if;
2386
2387                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
2388                     d_print("pla");
2389                     a52_pull;
2390                     if exec_cycle = T3 then
2391                         front_we(wk_acc_cmd, '0');
2392                         set_nz_from_bus;
2393                     end if;
2394
2395
2396                 ----------------------------------------
2397                 -- A.5.3 jsr
2398                 ----------------------------------------
2399                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
2400                     if exec_cycle = T1 then
2401                         d_print("jsr abs 2");
2402                         --fetch opcode.
2403                         fetch_next;
2404                         dbuf_int_oe_n <= '0';
2405                         --latch adl
2406                         dl_al_we_n <= '0';
2407                         wk_next_cycle <= T2;
2408                     elsif exec_cycle = T2 then
2409                         d_print("jsr 3");
2410                         fetch_stop;
2411                         dbuf_int_oe_n <= '1';
2412                         dl_al_we_n <= '1';
2413
2414                        --push return addr high into stack.
2415                         sp_push_n <= '0';
2416                         sp_oe_n <= '0';
2417                         front_oe(pch_cmd, '0');
2418                         back_oe(sp_cmd, '0');
2419                         back_we(sp_cmd, '0');
2420                         r_nw <= '0';
2421                         wk_next_cycle <= T3;
2422                     elsif exec_cycle = T3 then
2423                         d_print("jsr 4");
2424                         front_oe(pch_cmd, '1');
2425
2426                        --push return addr low into stack.
2427                         sp_push_n <= '0';
2428                         sp_oe_n <= '0';
2429                         front_oe(pcl_cmd, '0');
2430                         back_oe(sp_cmd, '0');
2431                         back_we(sp_cmd, '0');
2432                         r_nw <= '0';
2433
2434                         wk_next_cycle <= T4;
2435                     elsif exec_cycle = T4 then
2436                         d_print("jsr 5");
2437                         sp_push_n <= '1';
2438                         sp_oe_n <= '1';
2439                         front_oe(pcl_cmd, '1');
2440                         back_oe(sp_cmd, '1');
2441                         back_we(sp_cmd, '1');
2442                         r_nw <= '1';
2443
2444                         --fetch last op.
2445                         back_oe(pch_cmd, '0');
2446                         back_oe(pcl_cmd, '0');
2447                         dbuf_int_oe_n <= '0';
2448                         dl_ah_we_n <= '0';
2449
2450                         wk_next_cycle <= T5;
2451                     elsif exec_cycle = T5 then
2452                         d_print("jsr 6");
2453
2454                         back_oe(pch_cmd, '1');
2455                         back_oe(pcl_cmd, '1');
2456                         dbuf_int_oe_n <= '1';
2457                         dl_ah_we_n <= '1';
2458
2459                         --load/output  pch
2460                         ad_oe_n <= '1';
2461                         dl_dh_oe_n <= '0';
2462                         front_we(pch_cmd, '0');
2463
2464                         --load pcl.
2465                         dl_al_oe_n <= '0';
2466                         back_we(pcl_cmd, '0');
2467
2468                         wk_next_cycle <= T0;
2469                     end if; --if exec_cycle = T1 then
2470
2471                 -- A.5.4 break
2472                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
2473
2474                 ----------------------------------------
2475                 -- A.5.5 return from interrupt
2476                 ----------------------------------------
2477                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
2478                     if exec_cycle = T1 then
2479                         d_print("rti 2");
2480                         fetch_stop;
2481
2482                         --pop stack (decrement only)
2483                         back_oe(sp_cmd, '0');
2484                         back_we(sp_cmd, '0');
2485                         sp_pop_n <= '0';
2486                         sp_oe_n <= '0';
2487
2488                         wk_next_cycle <= T2;
2489                     elsif exec_cycle = T2 then
2490                         d_print("rti 3");
2491
2492                         --pop p (status)
2493                         back_oe(sp_cmd, '0');
2494                         back_we(sp_cmd, '0');
2495                         sp_pop_n <= '0';
2496                         sp_oe_n <= '0';
2497
2498                         --load status reg
2499                         stat_dec_oe_n <= '1';
2500                         dbuf_int_oe_n <= '0';
2501                         stat_bus_all_n <= '0';
2502
2503                         wk_next_cycle <= T3;
2504                     elsif exec_cycle = T3 then
2505                         d_print("rti 4");
2506                         stat_bus_all_n <= '1';
2507
2508                         --pop pcl
2509                         back_oe(sp_cmd, '0');
2510                         back_we(sp_cmd, '0');
2511                         sp_pop_n <= '0';
2512                         sp_oe_n <= '0';
2513
2514                         --load lo addr.
2515                         dbuf_int_oe_n <= '0';
2516                         front_we(pcl_cmd, '0');
2517
2518                         wk_next_cycle <= T4;
2519                     elsif exec_cycle = T4 then
2520                         d_print("rti 5");
2521                         --stack decrement stop.
2522                         back_we(sp_cmd, '1');
2523                         sp_pop_n <= '1';
2524                         front_we(pcl_cmd, '1');
2525
2526                         --pop pch
2527                         back_oe(sp_cmd, '0');
2528                         sp_oe_n <= '0';
2529                         --load hi addr.
2530                         dbuf_int_oe_n <= '0';
2531                         front_we(pch_cmd, '0');
2532
2533                         wk_next_cycle <= T5;
2534                     elsif exec_cycle = T5 then
2535                         d_print("rti 6");
2536                         back_oe(sp_cmd, '1');
2537                         sp_oe_n <= '1';
2538                         --load hi addr.
2539                         dbuf_int_oe_n <= '1';
2540                         front_we(pch_cmd, '1');
2541
2542                         --increment pc.
2543                         wk_next_cycle <= T0;
2544                     end if; --if exec_cycle = T1 then
2545
2546                 ----------------------------------------
2547                 -- A.5.6 jmp
2548                 ----------------------------------------
2549                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
2550                     --abs
2551                     if exec_cycle = T1 then
2552                         d_print("jmp 2");
2553                         --fetch next opcode (abs low).
2554                         fetch_next;
2555
2556                         --latch abs low data.
2557                         dbuf_int_oe_n <= '0';
2558                         dl_al_we_n <= '0';
2559                         wk_next_cycle <= T2;
2560                     elsif exec_cycle = T2 then
2561                         d_print("jmp 3");
2562                         dl_al_we_n <= '1';
2563
2564                         --fetch abs hi
2565                         fetch_next;
2566
2567                         --latch  in dlh
2568                         dbuf_int_oe_n <= '0';
2569                         dl_ah_we_n <= '0';
2570                         ---load pch.
2571                         front_we(pch_cmd, '0');
2572
2573                         wk_next_cycle <= T0;
2574                     end if;
2575
2576                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
2577                     --jmp (indir)
2578                     if exec_cycle = T1 then
2579                         d_print("jmp 2");
2580                         --fetch next opcode (abs low).
2581                         fetch_next;
2582
2583                         --latch abs low data.
2584                         dbuf_int_oe_n <= '0';
2585                         dl_al_we_n <= '0';
2586                         wk_next_cycle <= T2;
2587                     elsif exec_cycle = T2 then
2588                         d_print("jmp 3");
2589                         dl_al_we_n <= '1';
2590
2591                         --fetch abs hi
2592                         fetch_next;
2593
2594                         --latch  in dlh
2595                         dbuf_int_oe_n <= '0';
2596                         dl_ah_we_n <= '0';
2597                         wk_next_cycle <= T3;
2598
2599                     elsif exec_cycle = T3 then
2600                         fetch_stop;
2601                         dl_ah_we_n <= '1';
2602
2603                         --IAH/IAL > ADL
2604                         dl_ah_oe_n <= '0';
2605                         dl_al_oe_n <= '0';
2606                         front_we(pcl_cmd, '0');
2607                         wk_next_cycle <= T4;
2608
2609                     elsif exec_cycle = T4 then
2610                         dl_ah_oe_n <= '0';
2611                         dl_al_oe_n <= '0';
2612                         front_we(pcl_cmd, '1');
2613
2614                         --IAH/IAL+1 > ADH
2615                         front_we(pch_cmd, '0');
2616                         indir_n <= '0';
2617
2618                         wk_next_cycle <= T0;
2619
2620                     end if;
2621
2622
2623                 ----------------------------------------
2624                 -- A.5.7 return from soubroutine
2625                 ----------------------------------------
2626                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
2627                     if exec_cycle = T1 then
2628                         d_print("rts 2");
2629                         fetch_stop;
2630
2631                         --pop stack (decrement only)
2632                         back_oe(sp_cmd, '0');
2633                         back_we(sp_cmd, '0');
2634                         sp_pop_n <= '0';
2635                         sp_oe_n <= '0';
2636
2637                         wk_next_cycle <= T2;
2638                     elsif exec_cycle = T2 then
2639                         d_print("rts 3");
2640
2641                         --pop pcl
2642                         back_oe(sp_cmd, '0');
2643                         back_we(sp_cmd, '0');
2644                         sp_pop_n <= '0';
2645                         sp_oe_n <= '0';
2646
2647                         --load lo addr.
2648                         dbuf_int_oe_n <= '0';
2649                         front_we(pcl_cmd, '0');
2650
2651                         wk_next_cycle <= T3;
2652                     elsif exec_cycle = T3 then
2653                         d_print("rts 4");
2654                         --stack decrement stop.
2655                         back_we(sp_cmd, '1');
2656                         sp_pop_n <= '1';
2657                         front_we(pcl_cmd, '1');
2658
2659                         --pop pch
2660                         back_oe(sp_cmd, '0');
2661                         sp_oe_n <= '0';
2662                         --load hi addr.
2663                         dbuf_int_oe_n <= '0';
2664                         front_we(pch_cmd, '0');
2665
2666                         wk_next_cycle <= T4;
2667                     elsif exec_cycle = T4 then
2668                         d_print("rts 5");
2669                         back_oe(sp_cmd, '1');
2670                         sp_oe_n <= '1';
2671                         --load hi addr.
2672                         dbuf_int_oe_n <= '1';
2673                         front_we(pch_cmd, '1');
2674                         --empty cycle.
2675                         --complying h/w manual...
2676                         wk_next_cycle <= T5;
2677                     elsif exec_cycle = T5 then
2678                         d_print("rts 6");
2679
2680                         --increment pc.
2681                         fetch_next;
2682                         wk_next_cycle <= T0;
2683                     end if; --if exec_cycle = T1 then
2684
2685                 ----------------------------------------
2686                 -- A.5.8 branch operations
2687                 ----------------------------------------
2688                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
2689                     d_print("bcc");
2690                     a58_branch (st_C, '0');
2691
2692                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
2693                     d_print("bcs");
2694                     a58_branch (st_C, '1');
2695
2696                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
2697                     d_print("beq");
2698                     a58_branch (st_Z, '1');
2699
2700                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
2701                     d_print("bmi");
2702                     a58_branch (st_N, '1');
2703
2704                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
2705                     d_print("bne");
2706                     a58_branch (st_Z, '0');
2707
2708                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
2709                     d_print("bpl");
2710                     a58_branch (st_N, '0');
2711
2712                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
2713                     d_print("bvc");
2714                     a58_branch (st_V, '0');
2715
2716                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
2717                     d_print("bvs");
2718                     a58_branch (st_V, '1');
2719
2720                 else
2721                     ---unknown instruction!!!!
2722                     assert false
2723                         report "======== unknow instruction "
2724                             & conv_hex8(conv_integer(instruction))
2725                         severity failure;
2726                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
2727
2728             elsif exec_cycle = R0 then
2729                 d_print(string'("reset"));
2730
2731                 --initialize port...
2732                 inst_we_n <= '1';
2733                 ad_oe_n <= '1';
2734                 dbuf_int_oe_n <= '1';
2735                 dl_al_we_n <= '1';
2736                 dl_ah_we_n <= '1';
2737                 dl_al_oe_n <= '1';
2738                 dl_ah_oe_n <= '1';
2739                 dl_dh_oe_n <= '1';
2740                 pcl_inc_n <= '1';
2741                 pcl_cmd <= "1111";
2742                 pch_cmd <= "1111";
2743                 sp_cmd <= "1111";
2744                 sp_oe_n <= '1';
2745                 sp_push_n <= '1';
2746                 sp_pop_n <= '1';
2747                 wk_acc_cmd <= "1111";
2748                 wk_x_cmd <= "1111";
2749                 wk_y_cmd <= "1111";
2750
2751                 abs_xy_n <= '1';
2752                 pg_next_n <= '1';
2753                 zp_n <= '1';
2754                 zp_xy_n <= '1';
2755                 rel_calc_n <= '1';
2756                 indir_n <= '1';
2757                 indir_x_n <= '1';
2758                 indir_y_n <= '1';
2759                 arith_en_n <= '1';
2760
2761                 stat_dec_oe_n <= '0';
2762                 stat_bus_oe_n <= '1';
2763                 stat_set_flg_n <= '1';
2764                 stat_flg <= '1';
2765                 stat_bus_all_n <= '1';
2766                 stat_bus_nz_n <= '1';
2767                 wk_stat_alu_we_n <= '1';
2768
2769                 r_vec_oe_n <= '1';
2770                 n_vec_oe_n <= '1';
2771                 i_vec_oe_n <= '1';
2772                 nmi_handled_n <= '1';
2773                 r_nw <= '1';
2774
2775                 wk_next_cycle <= R1;
2776             elsif exec_cycle = R1 or exec_cycle = N1 then
2777                 pcl_cmd <= "1111";
2778                 pcl_inc_n <= '1';
2779                 inst_we_n <= '1';
2780                 dl_al_oe_n <= '1';
2781
2782                 --push pch.
2783                 d_print("R1");
2784                 ad_oe_n <= '0';
2785                 sp_push_n <= '0';
2786                 sp_oe_n <= '0';
2787                 pch_cmd <= "0111";
2788                 --front_oe(pch_cmd, '0');
2789                 back_oe(sp_cmd, '0');
2790                 back_we(sp_cmd, '0');
2791                 r_nw <= '0';
2792
2793                 if exec_cycle = R1 then
2794                     wk_next_cycle <= R2;
2795                 elsif exec_cycle = N1 then
2796                     wk_next_cycle <= N2;
2797                 end if;
2798
2799             elsif exec_cycle = R2 or exec_cycle = N2 then
2800                 front_oe(pch_cmd, '1');
2801
2802                --push pcl.
2803                 sp_push_n <= '0';
2804                 sp_oe_n <= '0';
2805                 front_oe(pcl_cmd, '0');
2806                 back_oe(sp_cmd, '0');
2807                 back_we(sp_cmd, '0');
2808                 r_nw <= '0';
2809
2810                 if exec_cycle = R2 then
2811                     wk_next_cycle <= R3;
2812                 elsif exec_cycle = N2 then
2813                     wk_next_cycle <= N3;
2814                 end if;
2815
2816             elsif exec_cycle = R3 or exec_cycle = N3 then
2817                 front_oe(pcl_cmd, '1');
2818
2819                --push status.
2820                 sp_push_n <= '0';
2821                 sp_oe_n <= '0';
2822                 stat_bus_oe_n <= '0';
2823                 back_oe(sp_cmd, '0');
2824                 back_we(sp_cmd, '0');
2825                 r_nw <= '0';
2826
2827                 if exec_cycle = R3 then
2828                     wk_next_cycle <= R4;
2829                 elsif exec_cycle = N3 then
2830                     wk_next_cycle <= N4;
2831                 end if;
2832
2833             elsif exec_cycle = R4 or exec_cycle = N4 then
2834                 stat_bus_oe_n <= '1';
2835                 sp_push_n <= '1';
2836                 sp_oe_n <= '1';
2837                 front_oe(pcl_cmd, '1');
2838                 back_oe(sp_cmd, '1');
2839                 back_we(sp_cmd, '1');
2840
2841                 --fetch reset vector low
2842                 r_nw <= '1';
2843                 dbuf_int_oe_n <= '0';
2844                 front_we(pcl_cmd, '0');
2845                 dl_al_oe_n <= '1';
2846                 dl_ah_oe_n <= '1';
2847
2848                 if exec_cycle = R4 then
2849                     r_vec_oe_n <= '0';
2850                     n_vec_oe_n <= '1';
2851                     wk_next_cycle <= R5;
2852                 elsif exec_cycle = N4 then
2853                     r_vec_oe_n <= '1';
2854                     n_vec_oe_n <= '0';
2855                     wk_next_cycle <= N5;
2856                 end if;
2857
2858             elsif exec_cycle = R5 or exec_cycle = N5 then
2859                 front_we(pcl_cmd, '1');
2860
2861                 --fetch reset vector hi
2862                 r_nw <= '1';
2863                 dbuf_int_oe_n <= '0';
2864                 front_we(pch_cmd, '0');
2865                 indir_n <= '0';
2866
2867                 if exec_cycle = N5 then
2868                     nmi_handled_n <= '0';
2869                 end if;
2870                 --start execute cycle.
2871                 wk_next_cycle <= T0;
2872
2873             elsif exec_cycle(5) = '1' then
2874                 ---pc increment and next page.
2875                 d_print(string'("pch next page..."));
2876                 --pcl stop increment
2877                 pcl_inc_n <= '1';
2878                 back_we(pcl_cmd, '1');
2879
2880                 if ('0' & exec_cycle(4 downto 0) = T0 and
2881                     instruction = conv_std_logic_vector(16#4c#, dsize) ) then
2882                     --jmp instruction t0 cycle discards pch increment.
2883                     back_we(pch_cmd, '1');
2884                     front_we(pch_cmd, '1');
2885                 else
2886                     --pch increment
2887                     back_we(pch_cmd, '0');
2888                     back_oe(pch_cmd, '0');
2889                 end if;
2890
2891                 if ('0' & exec_cycle(4 downto 0) = T0) then
2892                     --do the t0 identical routine.
2893                     disable_pins;
2894                     inst_we_n <= '1';
2895                     r_nw <= '1';
2896
2897                 elsif ('0' & exec_cycle(4 downto 0) = T1) then
2898                     --if fetch cycle, preserve instrution register
2899                     inst_we_n <= '1';
2900
2901                 elsif ('0' & exec_cycle(4 downto 0) = T2) then
2902                     --disable previous we_n gate.
2903                     --t1 cycle is fetch low oprand.
2904                     dl_al_we_n <= '1';
2905                     dl_ah_we_n <= '1';
2906                 elsif ('0' & exec_cycle(4 downto 0) = T3) then
2907                     --t2 cycle is fetch high oprand.
2908                     dl_ah_we_n <= '1';
2909                 end if;
2910
2911             end if; --if rdy = '0' then
2912
2913         end if; -- if (res_n = '0') then
2914
2915     end process;
2916
2917 end rtl;
2918