de1_nes/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5 use work.motonesfpga_common.all;
   6
   7 entity decoder is
   8     generic (dsize : integer := 8);
   9     port (
  10             --input lines.
  11             set_clk         : in std_logic;
  12             trig_clk        : in std_logic;
  13             res_n           : in std_logic;
  14             irq_n           : in std_logic;
  15             nmi_n           : in std_logic;
  16             rdy             : in std_logic;
  17             instruction     : in std_logic_vector (dsize - 1 downto 0);
  18             exec_cycle      : in std_logic_vector (5 downto 0);
  19             next_cycle      : out std_logic_vector (5 downto 0);
  20             ea_carry        : in  std_logic;
  21             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  22
  23             --general control.
  24             inst_we_n       : out std_logic;
  25             ad_oe_n         : out std_logic;
  26             dbuf_int_oe_n   : out std_logic;
  27             r_nw            : out std_logic;
  28
  29             ----control line for dual port registers.
  30             idl_l_cmd       : out std_logic_vector(3 downto 0);
  31             idl_h_cmd       : out std_logic_vector(3 downto 0);
  32             pcl_cmd         : out std_logic_vector(3 downto 0);
  33             pch_cmd         : out std_logic_vector(3 downto 0);
  34             sp_cmd          : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             acc_cmd         : out std_logic_vector(3 downto 0);
  38
  39             --addr calc control
  40             pcl_inc_n       : out std_logic;
  41             sp_oe_n         : out std_logic;
  42             sp_push_n       : out std_logic;
  43             sp_pop_n        : out std_logic;
  44             abs_xy_n        : out std_logic;
  45             pg_next_n       : out std_logic;
  46             zp_n            : out std_logic;
  47             zp_xy_n         : out std_logic;
  48             rel_calc_n      : out std_logic;
  49             indir_n         : out std_logic;
  50             indir_x_n       : out std_logic;
  51             indir_y_n       : out std_logic;
  52
  53             ---status register
  54             stat_dec_oe_n   : out std_logic;
  55             stat_bus_oe_n   : out std_logic;
  56             stat_set_flg_n  : out std_logic;
  57             stat_flg        : out std_logic;
  58             stat_bus_all_n  : out std_logic;
  59             stat_bus_nz_n   : out std_logic;
  60             stat_alu_we_n   : out std_logic;
  61
  62             --ALU control
  63             arith_en_n      : out std_logic;
  64
  65             --reset vectors.
  66             r_vec_oe_n      : out std_logic;
  67             n_vec_oe_n      : out std_logic;
  68             i_vec_oe_n      : out std_logic
  69
  70             ;---for parameter check purpose!!!
  71             check_bit     : out std_logic_vector(1 to 5)
  72         );
  73 end decoder;
  74
  75 architecture rtl of decoder is
  76
  77 component d_flip_flop_bit
  78     port (
  79             clk     : in std_logic;
  80             res_n   : in std_logic;
  81             set_n   : in std_logic;
  82             we_n    : in std_logic;
  83             d       : in std_logic;
  84             q       : out std_logic
  85         );
  86 end component;
  87
  88 --cycle bit format
  89 -- bit 5    : pcl increment carry flag
  90 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  91 -- bit 2-0  : cycle
  92
  93 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
  94 constant T0 : std_logic_vector (5 downto 0) := "000000";
  95 constant T1 : std_logic_vector (5 downto 0) := "000001";
  96 constant T2 : std_logic_vector (5 downto 0) := "000010";
  97 constant T3 : std_logic_vector (5 downto 0) := "000011";
  98 constant T4 : std_logic_vector (5 downto 0) := "000100";
  99 constant T5 : std_logic_vector (5 downto 0) := "000101";
 100 constant T6 : std_logic_vector (5 downto 0) := "000110";
 101
 102 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
 103 constant R0 : std_logic_vector (5 downto 0) := "001000";
 104 constant R1 : std_logic_vector (5 downto 0) := "001001";
 105 constant R2 : std_logic_vector (5 downto 0) := "001010";
 106 constant R3 : std_logic_vector (5 downto 0) := "001011";
 107 constant R4 : std_logic_vector (5 downto 0) := "001100";
 108 constant R5 : std_logic_vector (5 downto 0) := "001101";
 109
 110 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > T0
 111 constant N1 : std_logic_vector (5 downto 0) := "010001";
 112 constant N2 : std_logic_vector (5 downto 0) := "010010";
 113 constant N3 : std_logic_vector (5 downto 0) := "010011";
 114 constant N4 : std_logic_vector (5 downto 0) := "010100";
 115 constant N5 : std_logic_vector (5 downto 0) := "010101";
 116
 117 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > T0
 118 constant I1 : std_logic_vector (5 downto 0) := "011001";
 119 constant I2 : std_logic_vector (5 downto 0) := "011010";
 120 constant I3 : std_logic_vector (5 downto 0) := "011011";
 121 constant I4 : std_logic_vector (5 downto 0) := "011100";
 122 constant I5 : std_logic_vector (5 downto 0) := "011101";
 123
 124 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 125
 126 -- SR Flags (bit 7 to bit 0):
 127 --  7   N   ....    Negative
 128 --  6   V   ....    Overflow
 129 --  5   -   ....    ignored
 130 --  4   B   ....    Break
 131 --  3   D   ....    Decimal (use BCD for arithmetics)
 132 --  2   I   ....    Interrupt (IRQ disable)
 133 --  1   Z   ....    Zero
 134 --  0   C   ....    Carry
 135 constant st_N : integer := 7;
 136 constant st_V : integer := 6;
 137 constant st_B : integer := 4;
 138 constant st_D : integer := 3;
 139 constant st_I : integer := 2;
 140 constant st_Z : integer := 1;
 141 constant st_C : integer := 0;
 142
 143 ---for nmi handling
 144 signal nmi_handled_n : std_logic;
 145
 146 signal ea_carry_reg       : std_logic;
 147
 148 begin
 149
 150     ea_carry_inst: d_flip_flop_bit
 151             port map(trig_clk, '1', '1', '0', ea_carry, ea_carry_reg);
 152
 153     main_p : process (set_clk, res_n, nmi_n)
 154
 155 -------------------------------------------------------------
 156 -------------------------------------------------------------
 157 ----------------------- comon routines ----------------------
 158 -------------------------------------------------------------
 159 -------------------------------------------------------------
 160
 161 ----------gate_cmd format
 162 ------3 : front port oe_n
 163 ------2 : front port we_n
 164 ------1 : back port oe_n
 165 ------0 : back port we_n
 166 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 167     val : in std_logic) is
 168 begin
 169     cmd(3) <= val;
 170 end;
 171 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 172     val : in std_logic) is
 173 begin
 174     cmd(2) <= val;
 175 end;
 176 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 177     val : in std_logic) is
 178 begin
 179     cmd(1) <= val;
 180 end;
 181 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 182     val : in std_logic) is
 183 begin
 184     cmd(0) <= val;
 185 end;
 186
 187 procedure fetch_next is
 188 begin
 189     pcl_inc_n <= '0';
 190     back_oe(pcl_cmd, '0');
 191     back_oe(pch_cmd, '0');
 192     back_we(pcl_cmd, '0');
 193     back_we(pch_cmd, '1');
 194 end procedure;
 195
 196 procedure fetch_stop is
 197 begin
 198     pcl_inc_n <= '1';
 199     back_oe(pcl_cmd, '1');
 200     back_oe(pch_cmd, '1');
 201     back_we(pcl_cmd, '1');
 202     ad_oe_n <= '1';
 203 end procedure;
 204
 205 procedure read_status is
 206 begin
 207     status_reg <= (others => 'Z');
 208     stat_dec_oe_n <= '0';
 209 end  procedure;
 210
 211 procedure disable_pins is
 212 begin
 213 --following pins are not set in this function.
 214 --            inst_we_n       : out std_logic;
 215 --            ad_oe_n         : out std_logic;
 216 --            dl_al_oe_n      : out std_logic;
 217 --            pcl_inc_n       : out std_logic;
 218 --            pcl_cmd         : out std_logic_vector(3 downto 0);
 219 --            pch_cmd         : out std_logic_vector(3 downto 0);
 220 --            r_nw            : out std_logic
 221
 222     --disable the last opration pins.
 223     dbuf_int_oe_n <= '1';
 224
 225     idl_l_cmd <= "1111";
 226     idl_h_cmd <= "1111";
 227     pcl_cmd   <= "1111";
 228     pch_cmd   <= "1111";
 229     sp_cmd <= "1111";
 230     acc_cmd <= "1111";
 231     x_cmd <= "1111";
 232     y_cmd <= "1111";
 233
 234     sp_oe_n <= '1';
 235     sp_push_n <= '1';
 236     sp_pop_n <= '1';
 237     abs_xy_n <= '1';
 238     pg_next_n <= '1';
 239     zp_n <= '1';
 240     zp_xy_n <= '1';
 241     rel_calc_n <= '1';
 242     indir_n <= '1';
 243     indir_x_n <= '1';
 244     indir_y_n <= '1';
 245     arith_en_n <= '1';
 246
 247     read_status;
 248     stat_bus_oe_n <= '1';
 249     stat_set_flg_n <= '1';
 250     stat_flg <= '1';
 251     stat_bus_all_n <= '1';
 252     stat_bus_nz_n <= '1';
 253     stat_alu_we_n <= '1';
 254
 255     r_vec_oe_n <= '1';
 256     n_vec_oe_n <= '1';
 257     i_vec_oe_n <= '1';
 258
 259 end  procedure;
 260
 261 procedure fetch_inst is
 262 begin
 263     if instruction = conv_std_logic_vector(16#4c#, dsize) then
 264         --if prior cycle is jump instruction,
 265         --fetch opcode from where the latch is pointing to.
 266
 267         --latch > al.
 268         idl_l_cmd <= "1110";
 269         pcl_cmd <= "1110";
 270     else
 271         --fetch opcode and pcl increment.
 272         pcl_cmd <= "1100";
 273         --dl_al_oe_n <= '1';
 274     end if;
 275
 276     ad_oe_n <= '0';
 277     pch_cmd <= "1101";
 278     inst_we_n <= '0';
 279     pcl_inc_n <= '0';
 280     r_nw <= '1';
 281
 282     d_print(string'("fetch 1"));
 283 end  procedure;
 284
 285 ---T0 cycle routine
 286 ---(along with the page boundary condition, the last
 287 ---cycle is bypassed and slided to T0.)
 288 procedure t0_cycle is
 289 begin
 290     disable_pins;
 291     if (nmi_n = '0' and nmi_handled_n = '1') then
 292         --start nmi handling...
 293         --fetch_inst('1');
 294         next_cycle <= N1;
 295     else
 296         fetch_inst;
 297         next_cycle <= T1;
 298     end if;
 299 end  procedure;
 300
 301 ---common routine for single byte instruction.
 302 procedure single_inst is
 303 begin
 304     fetch_stop;
 305     next_cycle <= T0;
 306 end  procedure;
 307
 308 procedure fetch_imm is
 309 begin
 310     d_print("immediate");
 311     fetch_next;
 312     --send data from data bus buffer.
 313     --receiver is instruction dependent.
 314     dbuf_int_oe_n <= '0';
 315     next_cycle <= T0;
 316 end  procedure;
 317
 318 procedure set_nz_from_bus is
 319 begin
 320     --status register n/z bit update.
 321     stat_bus_nz_n <= '0';
 322 end  procedure;
 323
 324 procedure set_zc_from_alu is
 325 begin
 326     --status register n/z bit update.
 327     stat_alu_we_n <= '0';
 328     stat_dec_oe_n <= '1';
 329     status_reg <= "00000011";
 330 end  procedure;
 331
 332 procedure set_nz_from_alu is
 333 begin
 334     --status register n/z/c bit update.
 335     stat_alu_we_n <= '0';
 336     stat_dec_oe_n <= '1';
 337     status_reg <= "10000010";
 338 end  procedure;
 339
 340 procedure set_nzc_from_alu is
 341 begin
 342     --status register n/z/c bit update.
 343     stat_alu_we_n <= '0';
 344     stat_dec_oe_n <= '1';
 345     status_reg <= "10000011";
 346 end  procedure;
 347
 348 procedure set_nvz_from_alu is
 349 begin
 350     --status register n/z/v bit update.
 351     stat_alu_we_n <= '0';
 352     stat_dec_oe_n <= '1';
 353     status_reg <= "11000010";
 354 end  procedure;
 355
 356 procedure set_nvzc_from_alu is
 357 begin
 358     stat_alu_we_n <= '0';
 359     stat_dec_oe_n <= '1';
 360     status_reg <= "11000011";
 361 end  procedure;
 362
 363 --flag on/off instruction
 364 procedure set_flag (int_flg : in integer; val : in std_logic) is
 365 begin
 366     stat_dec_oe_n <= '1';
 367     stat_set_flg_n <= '0';
 368     --specify which to set.
 369     status_reg(7 downto int_flg + 1)
 370         <= (others =>'0');
 371     status_reg(int_flg - 1 downto 0)
 372         <= (others =>'0');
 373     status_reg(int_flg) <= '1';
 374     stat_flg <= val;
 375 end  procedure;
 376
 377 --for sec/clc
 378 procedure set_flag0 (val : in std_logic) is
 379 begin
 380     stat_dec_oe_n <= '1';
 381     stat_set_flg_n <= '0';
 382     status_reg <= "00000001";
 383     stat_flg <= val;
 384 end  procedure;
 385
 386 procedure fetch_low is
 387 begin
 388     d_print("fetch low 2");
 389     --fetch next opcode (abs low).
 390     fetch_next;
 391     --latch abs low data.
 392     dbuf_int_oe_n <= '0';
 393     --dl_al_we_n <= '0';
 394     next_cycle <= T2;
 395 end  procedure;
 396
 397 procedure abs_fetch_high is
 398 begin
 399     d_print("abs (xy) 3");
 400     --dl_al_we_n <= '1';
 401
 402     --latch abs hi data.
 403     fetch_next;
 404     dbuf_int_oe_n <= '0';
 405     --dl_ah_we_n <= '0';
 406     next_cycle <= T3;
 407 end  procedure;
 408
 409 procedure abs_latch_out is
 410 begin
 411     --d_print("abs 4");
 412     --dl_ah_we_n <= '1';
 413     fetch_stop;
 414
 415     --latch > al/ah.
 416     --dl_al_oe_n <= '0';
 417     --dl_ah_oe_n <= '0';
 418 end  procedure;
 419
 420 procedure ea_x_out is
 421 begin
 422     -----calucurate and output effective addr
 423     back_oe(x_cmd, '0');
 424     abs_xy_n <= '0';
 425 end  procedure;
 426
 427 procedure ea_y_out is
 428 begin
 429     back_oe(y_cmd, '0');
 430     abs_xy_n <= '0';
 431 end  procedure;
 432
 433 --A.2. internal execution on memory data
 434
 435 procedure a2_zp is
 436 begin
 437     if exec_cycle = T1 then
 438         fetch_low;
 439     elsif exec_cycle = T2 then
 440         fetch_stop;
 441         dbuf_int_oe_n <= '0';
 442         --dl_al_we_n <= '1';
 443
 444         --calc zp.
 445         --dl_al_oe_n <= '0';
 446         zp_n <= '0';
 447         next_cycle <= T0;
 448     end if;
 449 end  procedure;
 450
 451 procedure a2_abs is
 452 begin
 453     if exec_cycle = T1 then
 454         fetch_low;
 455     elsif exec_cycle = T2 then
 456         abs_fetch_high;
 457     elsif exec_cycle = T3 then
 458         abs_latch_out;
 459         dbuf_int_oe_n <= '0';
 460         next_cycle <= T0;
 461     end if;
 462 end  procedure;
 463
 464 procedure a2_page_next is
 465 begin
 466     --close open gate if page boundary crossed.
 467     back_we(acc_cmd, '1');
 468     front_we(acc_cmd, '1');
 469     front_we(x_cmd, '1');
 470     front_we(y_cmd, '1');
 471     stat_alu_we_n <= '1';
 472 end  procedure;
 473
 474 procedure a2_abs_xy (is_x : in boolean) is
 475 begin
 476     if exec_cycle = T1 then
 477         fetch_low;
 478     elsif exec_cycle = T2 then
 479         abs_fetch_high;
 480     elsif exec_cycle = T3 then
 481         --ea calc & lda
 482         pg_next_n <= '1';
 483         abs_latch_out;
 484         if (is_x = true) then
 485             ea_x_out;
 486         else
 487             ea_y_out;
 488         end if;
 489         dbuf_int_oe_n <= '0';
 490
 491         next_cycle <= T0;
 492         d_print("absx step 1");
 493     elsif (exec_cycle = T0 and ea_carry_reg = '1') then
 494         --case page boundary crossed.
 495         --redo inst.
 496         d_print("absx 5 (page boudary crossed.)");
 497         --next page.
 498         pg_next_n <= '0';
 499         next_cycle <= T0;
 500     end if;
 501 end  procedure;
 502
 503 procedure a2_zp_xy (is_x : in boolean) is
 504 begin
 505     if exec_cycle = T1 then
 506         fetch_low;
 507     elsif exec_cycle = T2 then
 508         fetch_stop;
 509         --output BAL only
 510         dbuf_int_oe_n <= '0';
 511         --dl_al_we_n <= '1';
 512
 513         --calc zp.
 514         --dl_al_oe_n <= '0';
 515         zp_n <= '0';
 516         next_cycle <= T3;
 517     elsif exec_cycle = T3 then
 518         --t3 zp, xy
 519         zp_xy_n <= '0';
 520         if (is_x = true) then
 521             back_oe(x_cmd, '0');
 522         else
 523             back_oe(y_cmd, '0');
 524         end if;
 525         next_cycle <= T0;
 526     end if;
 527 end  procedure;
 528
 529 procedure a2_indir_y is
 530 begin
 531     if exec_cycle = T1 then
 532         fetch_low;
 533         --get IAL
 534         --dl_al_we_n <= '0';
 535
 536     elsif exec_cycle = T2 then
 537         fetch_stop;
 538         --dl_al_we_n <= '1';
 539
 540         ---address is 00:IAL
 541         --output BAL @IAL
 542         indir_y_n <= '0';
 543         --dl_al_oe_n <= '0';
 544         dbuf_int_oe_n <= '0';
 545         next_cycle <= T3;
 546
 547     elsif exec_cycle = T3 then
 548         indir_y_n <= '0';
 549         --dl_al_oe_n <= '0';
 550         --output BAH @IAL+1
 551         dbuf_int_oe_n <= '0';
 552         next_cycle <= T4;
 553
 554     elsif exec_cycle = T4 then
 555         --dl_al_oe_n <= '1';
 556         dbuf_int_oe_n <= '1';
 557
 558         --add index y.
 559         pg_next_n <= '1';
 560         back_oe(y_cmd, '0');
 561         indir_y_n <= '0';
 562         dbuf_int_oe_n <= '0';
 563
 564         if (ea_carry = '1') then
 565             next_cycle <= T5;
 566         else
 567             next_cycle <= T0;
 568         end if;
 569     elsif (exec_cycle = T5) then
 570         --case page boundary crossed.
 571         --redo inst.
 572         d_print("(indir), y (page boudary crossed.)");
 573         --next page.
 574         pg_next_n <= '0';
 575         next_cycle <= T0;
 576     end if;
 577 end  procedure;
 578
 579 procedure a2_indir_x is
 580 begin
 581     if exec_cycle = T1 then
 582         fetch_low;
 583         --get IAL
 584         --dl_al_we_n <= '0';
 585
 586     elsif exec_cycle = T2 then
 587         fetch_stop;
 588         --dl_al_we_n <= '1';
 589
 590         ---address is 00:IAL
 591         --output BAL @IAL, but cycle #2 is discarded
 592         indir_x_n <= '0';
 593         --dl_al_oe_n <= '0';
 594         next_cycle <= T3;
 595
 596     elsif exec_cycle = T3 then
 597         indir_x_n <= '0';
 598         --dl_al_oe_n <= '1';
 599
 600         --output BAH @IAL+x
 601         dbuf_int_oe_n <= '0';
 602         back_oe(x_cmd, '0');
 603         next_cycle <= T4;
 604
 605     elsif exec_cycle = T4 then
 606         indir_x_n <= '0';
 607
 608         --output BAH @IAL+x+1
 609         dbuf_int_oe_n <= '0';
 610         back_oe(x_cmd, '0');
 611
 612         next_cycle <= T5;
 613     elsif (exec_cycle = T5) then
 614         indir_x_n <= '0';
 615         next_cycle <= T0;
 616     end if;
 617 end  procedure;
 618
 619 --A.3. store operation.
 620
 621 procedure a3_zp is
 622 begin
 623     if exec_cycle = T1 then
 624         fetch_low;
 625     elsif exec_cycle = T2 then
 626         fetch_stop;
 627         dbuf_int_oe_n <= '1';
 628         --dl_al_we_n <= '1';
 629
 630         --calc zp.
 631         --dl_al_oe_n <= '0';
 632         zp_n <= '0';
 633         r_nw <= '0';
 634         next_cycle <= T0;
 635     end if;
 636 end  procedure;
 637
 638 procedure a3_zp_xy (is_x : in boolean) is
 639 begin
 640     if exec_cycle = T1 then
 641         fetch_low;
 642     elsif exec_cycle = T2 then
 643         fetch_stop;
 644         dbuf_int_oe_n <= '1';
 645         --dl_al_we_n <= '1';
 646
 647         --calc zp.
 648         --dl_al_oe_n <= '0';
 649         zp_n <= '0';
 650         next_cycle <= T3;
 651     elsif exec_cycle = T3 then
 652         --calc zp + index.
 653         --dl_al_oe_n <= '0';
 654         zp_n <= '0';
 655         zp_xy_n <= '0';
 656         if (is_x = true) then
 657             back_oe(x_cmd, '0');
 658         else
 659             back_oe(y_cmd, '0');
 660         end if;
 661
 662         --write data
 663         r_nw <= '0';
 664         next_cycle <= T0;
 665     end if;
 666 end  procedure;
 667
 668 procedure a3_abs is
 669 begin
 670     if exec_cycle = T1 then
 671         fetch_low;
 672     elsif exec_cycle = T2 then
 673         abs_fetch_high;
 674     elsif exec_cycle = T3 then
 675         abs_latch_out;
 676         dbuf_int_oe_n <= '1';
 677         r_nw <= '0';
 678         next_cycle <= T0;
 679     end if;
 680 end  procedure;
 681
 682 procedure a3_abs_xy (is_x : in boolean) is
 683 begin
 684     if exec_cycle = T1 then
 685         fetch_low;
 686     elsif exec_cycle = T2 then
 687         abs_fetch_high;
 688     elsif exec_cycle = T3 then
 689         --ea calc & lda
 690         pg_next_n <= '1';
 691         abs_latch_out;
 692         dbuf_int_oe_n <= '1';
 693         if (is_x = true) then
 694             ea_x_out;
 695         else
 696             ea_y_out;
 697         end if;
 698         next_cycle <= T4;
 699     elsif exec_cycle = T4 then
 700         if (ea_carry_reg = '1') then
 701             pg_next_n <= '0';
 702         else
 703             pg_next_n <= '1';
 704         end if;
 705         abs_latch_out;
 706         if (is_x = true) then
 707             ea_x_out;
 708         else
 709             ea_y_out;
 710         end if;
 711         r_nw <= '0';
 712         next_cycle <= T0;
 713     end if;
 714 end  procedure;
 715
 716
 717 procedure a3_indir_y is
 718 begin
 719     if exec_cycle = T1 then
 720         fetch_low;
 721         --get IAL
 722         --dl_al_we_n <= '0';
 723
 724     elsif exec_cycle = T2 then
 725         fetch_stop;
 726         --dl_al_we_n <= '1';
 727
 728         ---address is 00:IAL
 729         --output BAL @IAL
 730         indir_y_n <= '0';
 731         --dl_al_oe_n <= '0';
 732         dbuf_int_oe_n <= '0';
 733         next_cycle <= T3;
 734
 735     elsif exec_cycle = T3 then
 736         indir_y_n <= '0';
 737         --dl_al_oe_n <= '0';
 738         --output BAH @IAL+1
 739         dbuf_int_oe_n <= '0';
 740         next_cycle <= T4;
 741
 742     elsif exec_cycle = T4 then
 743         --dl_al_oe_n <= '1';
 744         dbuf_int_oe_n <= '1';
 745
 746         --add index y.
 747         pg_next_n <= '1';
 748         back_oe(y_cmd, '0');
 749         indir_y_n <= '0';
 750         next_cycle <= T5;
 751
 752     elsif exec_cycle = T5 then
 753         --page handling.
 754         back_oe(y_cmd, '1');
 755         indir_y_n <= '0';
 756
 757         --ea_carry reg is suspicious. timing is not garanteed...
 758         if (ea_carry_reg = '1') then
 759             pg_next_n <= '0';
 760         else
 761             pg_next_n <= '1';
 762         end if;
 763         r_nw <= '0';
 764         next_cycle <= T0;
 765     end if;
 766 end  procedure;
 767
 768 procedure a3_indir_x is
 769 begin
 770     if exec_cycle = T1 then
 771         fetch_low;
 772         --get IAL
 773         --dl_al_we_n <= '0';
 774
 775     elsif exec_cycle = T2 then
 776         fetch_stop;
 777         --dl_al_we_n <= '1';
 778
 779         ---address is 00:IAL
 780         --output BAL @IAL, but cycle #2 is discarded
 781         indir_x_n <= '0';
 782         --dl_al_oe_n <= '0';
 783         next_cycle <= T3;
 784
 785     elsif exec_cycle = T3 then
 786         indir_x_n <= '0';
 787         --dl_al_oe_n <= '1';
 788
 789         --output BAH @IAL+x
 790         dbuf_int_oe_n <= '0';
 791         back_oe(x_cmd, '0');
 792         next_cycle <= T4;
 793
 794     elsif exec_cycle = T4 then
 795         indir_x_n <= '0';
 796
 797         --output BAH @IAL+x+1
 798         dbuf_int_oe_n <= '0';
 799         back_oe(x_cmd, '0');
 800
 801         next_cycle <= T5;
 802     elsif (exec_cycle = T5) then
 803         indir_x_n <= '0';
 804         dbuf_int_oe_n <= '1';
 805         r_nw <= '0';
 806         next_cycle <= T0;
 807     end if;
 808 end  procedure;
 809
 810 ---A.4. read-modify-write operation
 811
 812 procedure a4_zp is
 813 begin
 814     if exec_cycle = T1 then
 815         fetch_low;
 816     elsif exec_cycle = T2 then
 817         fetch_stop;
 818         --dl_al_we_n <= '1';
 819
 820         --t2 cycle read and,
 821         --dl_al_oe_n <= '0';
 822         zp_n <= '0';
 823         --keep data in the alu reg.
 824         arith_en_n <= '0';
 825         dbuf_int_oe_n <= '0';
 826         next_cycle <= T3;
 827     elsif exec_cycle = T3 then
 828         --t3 fix alu internal register.
 829         --dl_al_oe_n <= '0';
 830         zp_n <= '0';
 831         arith_en_n <= '0';
 832         dbuf_int_oe_n <= '1';
 833         next_cycle <= T4;
 834     elsif exec_cycle = T4 then
 835         --t5 cycle writes modified value.
 836         --dl_al_oe_n <= '0';
 837         zp_n <= '0';
 838         r_nw <= '0';
 839         arith_en_n <= '0';
 840         next_cycle <= T0;
 841     end if;
 842 end  procedure;
 843
 844 procedure a4_zp_x is
 845 begin
 846     if exec_cycle = T1 then
 847         fetch_low;
 848     elsif exec_cycle = T2 then
 849         fetch_stop;
 850         dbuf_int_oe_n <= '1';
 851         --dl_al_we_n <= '1';
 852
 853         --t2 cycle read bal only.
 854         --dl_al_oe_n <= '0';
 855         zp_n <= '0';
 856         next_cycle <= T3;
 857     elsif exec_cycle = T3 then
 858         --t3 cycle read bal + x
 859         --dl_al_oe_n <= '0';
 860         zp_n <= '0';
 861         zp_xy_n <= '0';
 862         back_oe(x_cmd, '0');
 863
 864         --keep data in the alu reg.
 865         arith_en_n <= '0';
 866         dbuf_int_oe_n <= '0';
 867
 868         next_cycle <= T4;
 869     elsif exec_cycle = T4 then
 870         --dl_al_oe_n <= '0';
 871         zp_n <= '0';
 872         zp_xy_n <= '0';
 873         back_oe(x_cmd, '0');
 874
 875         --fix alu internal register.
 876         arith_en_n <= '0';
 877         dbuf_int_oe_n <= '1';
 878         next_cycle <= T5;
 879     elsif exec_cycle = T5 then
 880         dbuf_int_oe_n <= '1';
 881
 882         --t5 cycle writes modified value.
 883         --dl_al_oe_n <= '0';
 884         zp_n <= '0';
 885         zp_xy_n <= '0';
 886         back_oe(x_cmd, '0');
 887         r_nw <= '0';
 888         arith_en_n <= '0';
 889         next_cycle <= T0;
 890     end if;
 891 end  procedure;
 892
 893
 894 procedure a4_abs is
 895 begin
 896     if exec_cycle = T1 then
 897         fetch_low;
 898     elsif exec_cycle = T2 then
 899         abs_fetch_high;
 900     elsif exec_cycle = T3 then
 901         abs_latch_out;
 902
 903         --keep data in the alu reg.
 904         arith_en_n <= '0';
 905         dbuf_int_oe_n <= '0';
 906         next_cycle <= T4;
 907     elsif exec_cycle = T4 then
 908         abs_latch_out;
 909
 910         --fix alu internal register.
 911         arith_en_n <= '0';
 912         dbuf_int_oe_n <= '1';
 913         next_cycle <= T5;
 914     elsif exec_cycle = T5 then
 915         dbuf_int_oe_n <= '1';
 916
 917         --t5 cycle writes modified value.
 918         r_nw <= '0';
 919         arith_en_n <= '0';
 920         next_cycle <= T0;
 921     end if;
 922 end  procedure;
 923
 924 procedure a4_abs_x is
 925 begin
 926     if exec_cycle = T1 then
 927         fetch_low;
 928     elsif exec_cycle = T2 then
 929         abs_fetch_high;
 930     elsif exec_cycle = T3 then
 931         --T3 cycle discarded.
 932         pg_next_n <= '1';
 933         abs_latch_out;
 934         ea_x_out;
 935         dbuf_int_oe_n <= '0';
 936         next_cycle <= T4;
 937
 938     elsif exec_cycle = T4 then
 939         abs_latch_out;
 940         ea_x_out;
 941         if (ea_carry_reg = '1') then
 942             pg_next_n <= '0';
 943         else
 944             pg_next_n <= '1';
 945         end if;
 946
 947         --keep data in the alu reg.
 948         arith_en_n <= '0';
 949         dbuf_int_oe_n <= '0';
 950         next_cycle <= T5;
 951
 952     elsif exec_cycle = T5 then
 953         --fix alu internal register.
 954         arith_en_n <= '0';
 955         dbuf_int_oe_n <= '1';
 956         next_cycle <= T6;
 957
 958     elsif exec_cycle = T6 then
 959         --t5 cycle writes modified value.
 960         r_nw <= '0';
 961         arith_en_n <= '0';
 962         next_cycle <= T0;
 963
 964     end if;
 965 end  procedure;
 966
 967
 968 -- A.5.1 push stack
 969 procedure a51_push is
 970 begin
 971     if exec_cycle = T1 then
 972         fetch_stop;
 973         next_cycle <= T2;
 974     elsif exec_cycle = T2 then
 975         back_oe(sp_cmd, '0');
 976         back_we(sp_cmd, '0');
 977         sp_push_n <= '0';
 978         sp_oe_n <= '0';
 979         r_nw <= '0';
 980         next_cycle <= T0;
 981     end if;
 982 end procedure;
 983
 984 -- A.5.2 pull stack
 985 procedure a52_pull is
 986 begin
 987     if exec_cycle = T1 then
 988         fetch_stop;
 989         next_cycle <= T2;
 990
 991     elsif exec_cycle = T2 then
 992         --stack decrement first.
 993         back_oe(sp_cmd, '0');
 994         back_we(sp_cmd, '0');
 995         sp_pop_n <= '0';
 996         sp_oe_n <= '0';
 997         next_cycle <= T3;
 998
 999     elsif exec_cycle = T3 then
1000         sp_pop_n <= '1';
1001         back_we(sp_cmd, '1');
1002
1003         ---pop data from stack.
1004         back_oe(sp_cmd, '0');
1005         sp_oe_n <= '0';
1006         dbuf_int_oe_n <= '0';
1007         next_cycle <= T0;
1008     end if;
1009 end procedure;
1010
1011
1012 -- A.5.8 branch operations
1013
1014 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
1015 begin
1016     if exec_cycle = T1 then
1017         fetch_next;
1018         if status_reg(int_flg) = br_cond then
1019             d_print("get rel");
1020
1021             --latch rel value.
1022             dbuf_int_oe_n <= '0';
1023             --dl_ah_we_n <= '0';
1024             next_cycle <= T2;
1025         else
1026             d_print("no branch");
1027             next_cycle <= T0;
1028         end if;
1029     elsif exec_cycle = T2 then
1030         d_print("rel ea");
1031         fetch_stop;
1032         dbuf_int_oe_n <= '1';
1033         --dl_ah_we_n <= '1';
1034
1035         --calc relative addr.
1036         rel_calc_n <= '0';
1037         pg_next_n <= '1';
1038         --dl_dh_oe_n <= '0';
1039         back_oe(pcl_cmd, '0');
1040         back_oe(pch_cmd, '0');
1041         back_we(pcl_cmd, '0');
1042
1043         next_cycle <= T0;
1044     elsif (exec_cycle = T0 and ea_carry = '1') then
1045         d_print("page crossed.");
1046         --page crossed. adh calc.
1047         back_we(pcl_cmd, '1');
1048         back_oe(pcl_cmd, '0');
1049         back_oe(pch_cmd, '0');
1050         back_we(pch_cmd, '0');
1051         --dl_dh_oe_n <= '0';
1052
1053         rel_calc_n <= '0';
1054         pg_next_n <= '0';
1055         next_cycle <= T0;
1056     end if;
1057 end  procedure;
1058
1059 -------------------------------------------------------------
1060 -------------------------------------------------------------
1061 ---------------- main state machine start.... ---------------
1062 -------------------------------------------------------------
1063 -------------------------------------------------------------
1064     begin
1065
1066         if (res_n = '0') then
1067             --prevent status revister from broken.
1068             stat_dec_oe_n <= '0';
1069             stat_bus_oe_n <= '1';
1070             stat_set_flg_n <= '1';
1071             stat_flg <= '1';
1072             stat_bus_all_n <= '1';
1073             stat_bus_nz_n <= '1';
1074             stat_alu_we_n <= '1';
1075
1076             --pc l/h is reset vector.
1077             pcl_cmd <= "1110";
1078             pch_cmd <= "1110";
1079             next_cycle <= R0;
1080
1081         elsif (rising_edge(set_clk)) then
1082             d_print(string'("-"));
1083
1084             if (nmi_n = '1') then
1085                 --nmi handle flag reset.
1086                 nmi_handled_n <= '1';
1087             end if;
1088
1089             if rdy = '0' then
1090                 --case dma is runnting.
1091                 disable_pins;
1092                 inst_we_n <= '1';
1093                 ad_oe_n <= '1';
1094                 --dl_al_oe_n <= '1';
1095                 pcl_inc_n <= '1';
1096                 pcl_cmd <= "1111";
1097                 pch_cmd <= "1111";
1098                 r_nw <= 'Z';
1099
1100             elsif (exec_cycle = T0 and ea_carry = '0') then
1101                 --cycle #1
1102                 t0_cycle;
1103
1104             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
1105                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or
1106                 (exec_cycle = T0 and ea_carry = '1') then
1107                 --execute inst.
1108
1109                 ---asyncronous page change might happen.
1110                 back_we(pch_cmd, '1');
1111
1112                 if exec_cycle = T1 then
1113                     d_print("decode and execute inst: "
1114                             & conv_hex8(conv_integer(instruction)));
1115                     --disable pin for jmp instruction
1116                     --dl_al_oe_n <= '1';
1117                     back_we(pcl_cmd, '1');
1118                     front_we(pch_cmd, '1');
1119
1120                     --grab instruction register data.
1121                     inst_we_n <= '1';
1122                 end if;
1123
1124                 --imelementation is wriiten in the order of hardware manual
1125                 --appendix A.
1126
1127                 ----------------------------------------
1128                 --A.1. Single byte instruction.
1129                 ----------------------------------------
1130                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
1131                     --asl acc mode.
1132                     d_print("asl");
1133                     arith_en_n <= '0';
1134                     back_oe(acc_cmd, '0');
1135                     front_we(acc_cmd, '0');
1136                     set_nzc_from_alu;
1137                     single_inst;
1138
1139                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
1140                     d_print("clc");
1141                     set_flag0 ('0');
1142                     single_inst;
1143
1144                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
1145                     d_print("cld");
1146                     set_flag (st_D, '0');
1147                     single_inst;
1148
1149                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
1150                     d_print("cli");
1151                     set_flag (st_I, '0');
1152                     single_inst;
1153
1154                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
1155                     d_print("clv");
1156                     set_flag (st_V, '0');
1157                     single_inst;
1158
1159                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
1160                     d_print("dex");
1161                     arith_en_n <= '0';
1162                     back_oe(x_cmd, '0');
1163                     front_we(x_cmd, '0');
1164                     --set nz bit.
1165                     set_nz_from_bus;
1166                     single_inst;
1167
1168                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
1169                     d_print("dey");
1170                     arith_en_n <= '0';
1171                     back_oe(y_cmd, '0');
1172                     front_we(y_cmd, '0');
1173                     --set nz bit.
1174                     set_nz_from_bus;
1175                     single_inst;
1176
1177                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
1178                     d_print("inx");
1179                     arith_en_n <= '0';
1180                     back_oe(x_cmd, '0');
1181                     front_we(x_cmd, '0');
1182                     --set nz bit.
1183                     set_nz_from_bus;
1184                     single_inst;
1185
1186                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
1187                     d_print("iny");
1188                     arith_en_n <= '0';
1189                     back_oe(y_cmd, '0');
1190                     front_we(y_cmd, '0');
1191                     set_nz_from_bus;
1192                     single_inst;
1193
1194                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
1195                     --lsr acc mode
1196                     d_print("lsr");
1197                     arith_en_n <= '0';
1198                     back_oe(acc_cmd, '0');
1199                     front_we(acc_cmd, '0');
1200                     set_zc_from_alu;
1201                     single_inst;
1202
1203                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
1204                     d_print("nop");
1205                     single_inst;
1206
1207                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
1208                     --rol acc
1209                     d_print("rol");
1210                     arith_en_n <= '0';
1211                     back_oe(acc_cmd, '0');
1212                     front_we(acc_cmd, '0');
1213                     set_nzc_from_alu;
1214                     single_inst;
1215
1216                 elsif instruction = conv_std_logic_vector(16#6a#, dsize) then
1217                     --ror acc
1218                     d_print("ror");
1219                     arith_en_n <= '0';
1220                     back_oe(acc_cmd, '0');
1221                     front_we(acc_cmd, '0');
1222                     set_nzc_from_alu;
1223                     single_inst;
1224
1225                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
1226                     d_print("sec");
1227                     set_flag0 ('1');
1228                     single_inst;
1229
1230                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
1231                     d_print("sed");
1232                     set_flag (st_D, '1');
1233                     single_inst;
1234
1235                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
1236                     d_print("sei");
1237                     set_flag (st_I, '1');
1238                     single_inst;
1239
1240                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
1241                     d_print("tax");
1242                     set_nz_from_bus;
1243                     single_inst;
1244                     front_oe(acc_cmd, '0');
1245                     front_we(x_cmd, '0');
1246
1247                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
1248                     d_print("tay");
1249                     set_nz_from_bus;
1250                     single_inst;
1251                     front_oe(acc_cmd, '0');
1252                     front_we(y_cmd, '0');
1253
1254                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
1255                     d_print("tsx");
1256                     set_nz_from_bus;
1257                     single_inst;
1258                     front_oe(sp_cmd, '0');
1259                     front_we(x_cmd, '0');
1260
1261                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1262                     d_print("txa");
1263                     set_nz_from_bus;
1264                     single_inst;
1265                     front_oe(x_cmd, '0');
1266                     front_we(acc_cmd, '0');
1267
1268                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1269                     d_print("txs");
1270                     set_nz_from_bus;
1271                     single_inst;
1272                     front_oe(x_cmd, '0');
1273                     front_we(sp_cmd, '0');
1274
1275                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1276                     d_print("tya");
1277                     set_nz_from_bus;
1278                     single_inst;
1279                     front_oe(y_cmd, '0');
1280                     front_we(acc_cmd, '0');
1281
1282
1283
1284                 ----------------------------------------
1285                 --A.2. internal execution on memory data
1286                 ----------------------------------------
1287                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1288                     --imm
1289                     d_print("adc");
1290                     fetch_imm;
1291                     arith_en_n <= '0';
1292                     back_oe(acc_cmd, '0');
1293                     back_we(acc_cmd, '0');
1294                     set_nvzc_from_alu;
1295
1296                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1297                     --zp
1298                     d_print("adc");
1299                     a2_zp;
1300                     if exec_cycle = T2 then
1301                         arith_en_n <= '0';
1302                         back_oe(acc_cmd, '0');
1303                         back_we(acc_cmd, '0');
1304                         set_nvzc_from_alu;
1305                     end if;
1306
1307                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1308                     --zp, x
1309                     d_print("adc");
1310                     a2_zp_xy(true);
1311                     if exec_cycle = T3 then
1312                         arith_en_n <= '0';
1313                         back_oe(acc_cmd, '0');
1314                         back_we(acc_cmd, '0');
1315                         set_nvzc_from_alu;
1316                     end if;
1317
1318                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1319                     --abs
1320                     d_print("adc");
1321                     a2_abs;
1322                     if exec_cycle = T3 then
1323                         arith_en_n <= '0';
1324                         back_oe(acc_cmd, '0');
1325                         back_we(acc_cmd, '0');
1326                         set_nvzc_from_alu;
1327                     end if;
1328
1329                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1330                     --abs, x
1331                     d_print("adc");
1332                     a2_abs_xy(true);
1333                     if exec_cycle = T3 or exec_cycle = T0 then
1334                         arith_en_n <= '0';
1335                         back_oe(acc_cmd, '0');
1336                         back_we(acc_cmd, '0');
1337                         set_nvzc_from_alu;
1338                     end if;
1339
1340                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1341                     --abs, y
1342                     d_print("adc");
1343                     a2_abs_xy(false);
1344                     if exec_cycle = T3 or exec_cycle = T0 then
1345                         arith_en_n <= '0';
1346                         back_oe(acc_cmd, '0');
1347                         back_we(acc_cmd, '0');
1348                         set_nvzc_from_alu;
1349                     end if;
1350
1351                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1352                     --(indir, x)
1353                     d_print("adc");
1354                     a2_indir_x;
1355                     if exec_cycle = T5 then
1356                         arith_en_n <= '0';
1357                         back_oe(acc_cmd, '0');
1358                         back_we(acc_cmd, '0');
1359                         set_nvzc_from_alu;
1360                     end if;
1361
1362                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1363                     --(indir), y
1364                     d_print("adc");
1365                     a2_indir_y;
1366                     if exec_cycle = T4 or exec_cycle = T0 then
1367                         arith_en_n <= '0';
1368                         back_oe(acc_cmd, '0');
1369                         back_we(acc_cmd, '0');
1370                         set_nvzc_from_alu;
1371                     end if;
1372
1373                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1374                     --imm
1375                     d_print("and");
1376                     fetch_imm;
1377                     arith_en_n <= '0';
1378                     back_oe(acc_cmd, '0');
1379                     back_we(acc_cmd, '0');
1380                     set_nz_from_alu;
1381
1382                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1383                     --zp
1384                     d_print("and");
1385                     a2_zp;
1386                     if exec_cycle = T2 then
1387                         arith_en_n <= '0';
1388                         back_oe(acc_cmd, '0');
1389                         back_we(acc_cmd, '0');
1390                         set_nz_from_alu;
1391                     end if;
1392
1393                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1394                     --zp, x
1395                     d_print("and");
1396                     a2_zp_xy(true);
1397                     if exec_cycle = T3 then
1398                         arith_en_n <= '0';
1399                         back_oe(acc_cmd, '0');
1400                         back_we(acc_cmd, '0');
1401                         set_nz_from_alu;
1402                     end if;
1403
1404                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1405                     --abs
1406                     d_print("and");
1407                     a2_abs;
1408                     if exec_cycle = T3 then
1409                         arith_en_n <= '0';
1410                         back_oe(acc_cmd, '0');
1411                         back_we(acc_cmd, '0');
1412                         set_nz_from_alu;
1413                     end if;
1414
1415                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1416                     --abs, x
1417                     d_print("and");
1418                     a2_abs_xy(true);
1419                     if exec_cycle = T3 or exec_cycle = T0 then
1420                         arith_en_n <= '0';
1421                         back_oe(acc_cmd, '0');
1422                         back_we(acc_cmd, '0');
1423                         set_nz_from_alu;
1424                     end if;
1425
1426                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1427                     --abs, y
1428                     d_print("and");
1429                     a2_abs_xy(false);
1430                     if exec_cycle = T3 or exec_cycle = T0 then
1431                         arith_en_n <= '0';
1432                         back_oe(acc_cmd, '0');
1433                         back_we(acc_cmd, '0');
1434                         set_nz_from_alu;
1435                     end if;
1436
1437                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1438                     --(indir, x)
1439                     d_print("and");
1440                     a2_indir_x;
1441                     if exec_cycle = T5 then
1442                         arith_en_n <= '0';
1443                         back_oe(acc_cmd, '0');
1444                         back_we(acc_cmd, '0');
1445                         set_nz_from_alu;
1446                     end if;
1447
1448                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1449                     --(indir), y
1450                     d_print("and");
1451                     a2_indir_y;
1452                     if exec_cycle = T4 or exec_cycle = T0 then
1453                         arith_en_n <= '0';
1454                         back_oe(acc_cmd, '0');
1455                         back_we(acc_cmd, '0');
1456                         set_nz_from_alu;
1457                     end if;
1458
1459                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1460                     --zp
1461                     d_print("bit");
1462                     a2_zp;
1463                     if exec_cycle = T2 then
1464                         arith_en_n <= '0';
1465                         back_oe(acc_cmd, '0');
1466                         set_nvz_from_alu;
1467                     end if;
1468
1469                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1470                     --abs
1471                     d_print("bit");
1472                     a2_abs;
1473                     if exec_cycle = T3 then
1474                         arith_en_n <= '0';
1475                         back_oe(acc_cmd, '0');
1476                         set_nvz_from_alu;
1477                     end if;
1478
1479                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1480                     --imm
1481                     d_print("cmp");
1482                     fetch_imm;
1483                     arith_en_n <= '0';
1484                     back_oe(acc_cmd, '0');
1485                     set_nzc_from_alu;
1486
1487                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1488                     --zp
1489                     d_print("cmp");
1490                     a2_zp;
1491                     if exec_cycle = T2 then
1492                         arith_en_n <= '0';
1493                         back_oe(acc_cmd, '0');
1494                         set_nzc_from_alu;
1495                     end if;
1496
1497                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1498                     --zp, x
1499                     d_print("cmp");
1500                     a2_zp_xy(true);
1501                     if exec_cycle = T3 then
1502                         arith_en_n <= '0';
1503                         back_oe(acc_cmd, '0');
1504                         set_nzc_from_alu;
1505                     end if;
1506
1507                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1508                     --abs
1509                     d_print("cmp");
1510                     a2_abs;
1511                     if exec_cycle = T3 then
1512                         arith_en_n <= '0';
1513                         back_oe(acc_cmd, '0');
1514                         set_nzc_from_alu;
1515                     end if;
1516
1517                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1518                     --abs, x
1519                     d_print("cmp");
1520                     a2_abs_xy(true);
1521                     if exec_cycle = T3 or exec_cycle = T0 then
1522                         arith_en_n <= '0';
1523                         back_oe(acc_cmd, '0');
1524                         set_nzc_from_alu;
1525                     end if;
1526
1527                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1528                     --abs, y
1529                     d_print("cmp");
1530                     a2_abs_xy(false);
1531                     if exec_cycle = T3 or exec_cycle = T0 then
1532                         arith_en_n <= '0';
1533                         back_oe(acc_cmd, '0');
1534                         set_nzc_from_alu;
1535                     end if;
1536
1537                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1538                     --(indir, x)
1539                     d_print("cmp");
1540                     a2_indir_x;
1541                     if exec_cycle = T5 then
1542                         arith_en_n <= '0';
1543                         back_oe(acc_cmd, '0');
1544                         set_nzc_from_alu;
1545                     end if;
1546
1547                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1548                     --(indir), y
1549                     d_print("cmp");
1550                     a2_indir_y;
1551                     if exec_cycle = T4 or exec_cycle = T0 then
1552                         arith_en_n <= '0';
1553                         back_oe(acc_cmd, '0');
1554                         set_nzc_from_alu;
1555                     end if;
1556
1557                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1558                     --imm
1559                     d_print("cpx");
1560                     fetch_imm;
1561                     arith_en_n <= '0';
1562                     back_oe(x_cmd, '0');
1563                     set_nzc_from_alu;
1564
1565                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1566                     --zp
1567                     d_print("cpx");
1568                     a2_zp;
1569                     if exec_cycle = T2 then
1570                         arith_en_n <= '0';
1571                         back_oe(x_cmd, '0');
1572                         set_nzc_from_alu;
1573                     end if;
1574
1575                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1576                     --abs
1577                     d_print("cpx");
1578                     a2_abs;
1579                     if exec_cycle = T3 then
1580                         arith_en_n <= '0';
1581                         back_oe(x_cmd, '0');
1582                         set_nzc_from_alu;
1583                     end if;
1584
1585                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1586                     --imm
1587                     d_print("cpy");
1588                     fetch_imm;
1589                     arith_en_n <= '0';
1590                     back_oe(y_cmd, '0');
1591                     set_nzc_from_alu;
1592
1593                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1594                     --zp
1595                     d_print("cpy");
1596                     a2_zp;
1597                     if exec_cycle = T2 then
1598                         arith_en_n <= '0';
1599                         back_oe(y_cmd, '0');
1600                         set_nzc_from_alu;
1601                     end if;
1602
1603                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1604                     --abs
1605                     d_print("cpy");
1606                     a2_abs;
1607                     if exec_cycle = T3 then
1608                         arith_en_n <= '0';
1609                         back_oe(y_cmd, '0');
1610                         set_nzc_from_alu;
1611                     end if;
1612
1613                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1614                     --imm
1615                     d_print("eor");
1616                     fetch_imm;
1617                     arith_en_n <= '0';
1618                     back_oe(acc_cmd, '0');
1619                     back_we(acc_cmd, '0');
1620                     set_nz_from_alu;
1621
1622                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1623                     --zp
1624                     d_print("eor");
1625                     a2_zp;
1626                     if exec_cycle = T2 then
1627                         arith_en_n <= '0';
1628                         back_oe(acc_cmd, '0');
1629                         back_we(acc_cmd, '0');
1630                         set_nz_from_alu;
1631                     end if;
1632
1633                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1634                     --zp, x
1635                     d_print("eor");
1636                     a2_zp_xy(true);
1637                     if exec_cycle = T3 then
1638                         arith_en_n <= '0';
1639                         back_oe(acc_cmd, '0');
1640                         back_we(acc_cmd, '0');
1641                         set_nz_from_alu;
1642                     end if;
1643
1644                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1645                     --abs
1646                     d_print("eor");
1647                     a2_abs;
1648                     if exec_cycle = T3 then
1649                         arith_en_n <= '0';
1650                         back_oe(acc_cmd, '0');
1651                         back_we(acc_cmd, '0');
1652                         set_nz_from_alu;
1653                     end if;
1654
1655                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1656                     --abs, x
1657                     d_print("eor");
1658                     a2_abs_xy(true);
1659                     if exec_cycle = T3 or exec_cycle = T0 then
1660                         arith_en_n <= '0';
1661                         back_oe(acc_cmd, '0');
1662                         back_we(acc_cmd, '0');
1663                         set_nz_from_alu;
1664                     end if;
1665
1666                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1667                     --abs, y
1668                     d_print("eor");
1669                     a2_abs_xy(false);
1670                     if exec_cycle = T3 or exec_cycle = T0 then
1671                         arith_en_n <= '0';
1672                         back_oe(acc_cmd, '0');
1673                         back_we(acc_cmd, '0');
1674                         set_nz_from_alu;
1675                     end if;
1676
1677                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1678                     --(indir, x)
1679                     d_print("eor");
1680                     a2_indir_x;
1681                     if exec_cycle = T5 then
1682                         arith_en_n <= '0';
1683                         back_oe(acc_cmd, '0');
1684                         back_we(acc_cmd, '0');
1685                         set_nz_from_alu;
1686                     end if;
1687
1688                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1689                     --(indir), y
1690                     d_print("eor");
1691                     a2_indir_y;
1692                     if exec_cycle = T4 or exec_cycle = T0 then
1693                         arith_en_n <= '0';
1694                         back_oe(acc_cmd, '0');
1695                         back_we(acc_cmd, '0');
1696                         set_nz_from_alu;
1697                     end if;
1698
1699                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1700                     --imm
1701                     d_print("lda");
1702                     fetch_imm;
1703                     front_we(acc_cmd, '0');
1704                     set_nz_from_bus;
1705
1706                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1707                     --zp
1708                     d_print("lda");
1709                     a2_zp;
1710                     if exec_cycle = T2 then
1711                         front_we(acc_cmd, '0');
1712                         set_nz_from_bus;
1713                     end if;
1714
1715                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1716                     --zp, x
1717                     d_print("lda");
1718                     a2_zp_xy(true);
1719                     if exec_cycle = T3 then
1720                         front_we(acc_cmd, '0');
1721                         set_nz_from_bus;
1722                     end if;
1723
1724                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1725                     --abs
1726                     d_print("lda");
1727                     a2_abs;
1728                     if exec_cycle = T3 then
1729                         set_nz_from_bus;
1730                         front_we(acc_cmd, '0');
1731                     end if;
1732
1733                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1734                     --abs, x
1735                     d_print("lda");
1736                     a2_abs_xy(true);
1737                     if exec_cycle = T3 or exec_cycle = T0 then
1738                         --lda.
1739                         front_we(acc_cmd, '0');
1740                         set_nz_from_bus;
1741                     end if;
1742
1743                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1744                     --abs, y
1745                     d_print("lda");
1746                     a2_abs_xy(false);
1747                     if exec_cycle = T3 or exec_cycle = T0 then
1748                         --lda.
1749                         front_we(acc_cmd, '0');
1750                         set_nz_from_bus;
1751                     end if;
1752
1753                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1754                     --(indir, x)
1755                     d_print("lda");
1756                     a2_indir_x;
1757                     if exec_cycle = T5 then
1758                         front_we(acc_cmd, '0');
1759                         set_nz_from_bus;
1760                     end if;
1761
1762                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1763                     --(indir), y
1764                     d_print("lda");
1765                     a2_indir_y;
1766                     if exec_cycle = T4 or exec_cycle = T0 then
1767                         --lda.
1768                         front_we(acc_cmd, '0');
1769                         set_nz_from_bus;
1770                     end if;
1771
1772                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1773                     --imm
1774                     d_print("ldx");
1775                     fetch_imm;
1776                     set_nz_from_bus;
1777                     front_we(x_cmd, '0');
1778
1779                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1780                     --zp
1781                     d_print("ldx");
1782                     a2_zp;
1783                     if exec_cycle = T2 then
1784                         front_we(x_cmd, '0');
1785                         set_nz_from_bus;
1786                     end if;
1787
1788                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1789                     --zp, y
1790                     d_print("ldx");
1791                     a2_zp_xy(false);
1792                     if exec_cycle = T3 then
1793                         front_we(x_cmd, '0');
1794                         set_nz_from_bus;
1795                     end if;
1796
1797                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1798                     --abs
1799                     d_print("ldx");
1800                     a2_abs;
1801                     if exec_cycle = T3 then
1802                         set_nz_from_bus;
1803                         front_we(x_cmd, '0');
1804                     end if;
1805
1806                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1807                     --abs, y
1808                     d_print("ldx");
1809                     a2_abs_xy(false);
1810                     if exec_cycle = T3 or exec_cycle = T0 then
1811                         front_we(x_cmd, '0');
1812                         set_nz_from_bus;
1813                     end if;
1814
1815                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1816                     --imm
1817                     d_print("ldy");
1818                     fetch_imm;
1819                     set_nz_from_bus;
1820                     front_we(y_cmd, '0');
1821
1822                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1823                     --zp
1824                     d_print("ldy");
1825                     a2_zp;
1826                     if exec_cycle = T2 then
1827                         front_we(y_cmd, '0');
1828                         set_nz_from_bus;
1829                     end if;
1830
1831                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1832                     --zp, x
1833                     d_print("ldy");
1834                     a2_zp_xy(true);
1835                     if exec_cycle = T3 then
1836                         front_we(y_cmd, '0');
1837                         set_nz_from_bus;
1838                     end if;
1839
1840                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1841                     --abs
1842                     d_print("ldy");
1843                     a2_abs;
1844                     if exec_cycle = T3 then
1845                         set_nz_from_bus;
1846                         front_we(y_cmd, '0');
1847                     end if;
1848
1849                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1850                     --abs, x
1851                     d_print("ldy");
1852                     a2_abs_xy(true);
1853                     if exec_cycle = T3 or exec_cycle = T0 then
1854                         set_nz_from_bus;
1855                         front_we(y_cmd, '0');
1856                     end if;
1857
1858                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1859                     --imm
1860                     d_print("ora");
1861                     fetch_imm;
1862                     arith_en_n <= '0';
1863                     back_oe(acc_cmd, '0');
1864                     back_we(acc_cmd, '0');
1865                     set_nz_from_alu;
1866
1867                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1868                     --zp
1869                     d_print("ora");
1870                     a2_zp;
1871                     if exec_cycle = T2 then
1872                         arith_en_n <= '0';
1873                         back_oe(acc_cmd, '0');
1874                         back_we(acc_cmd, '0');
1875                         set_nz_from_alu;
1876                     end if;
1877
1878                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1879                     --zp, x
1880                     d_print("ora");
1881                     a2_zp_xy(true);
1882                     if exec_cycle = T3 then
1883                         arith_en_n <= '0';
1884                         back_oe(acc_cmd, '0');
1885                         back_we(acc_cmd, '0');
1886                         set_nz_from_alu;
1887                     end if;
1888
1889                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1890                     --abs
1891                     d_print("ora");
1892                     a2_abs;
1893                     if exec_cycle = T3 then
1894                         arith_en_n <= '0';
1895                         back_oe(acc_cmd, '0');
1896                         back_we(acc_cmd, '0');
1897                         set_nz_from_alu;
1898                     end if;
1899
1900                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1901                     --abs, x
1902                     d_print("ora");
1903                     a2_abs_xy(true);
1904                     if exec_cycle = T3 or exec_cycle = T0 then
1905                         arith_en_n <= '0';
1906                         back_oe(acc_cmd, '0');
1907                         back_we(acc_cmd, '0');
1908                         set_nz_from_alu;
1909                     end if;
1910
1911                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1912                     --abs, y
1913                     d_print("ora");
1914                     a2_abs_xy(false);
1915                     if exec_cycle = T3 or exec_cycle = T0 then
1916                         arith_en_n <= '0';
1917                         back_oe(acc_cmd, '0');
1918                         back_we(acc_cmd, '0');
1919                         set_nz_from_alu;
1920                     end if;
1921
1922                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
1923                     --(indir, x)
1924                     d_print("ora");
1925                     a2_indir_x;
1926                     if exec_cycle = T5 then
1927                         arith_en_n <= '0';
1928                         back_oe(acc_cmd, '0');
1929                         back_we(acc_cmd, '0');
1930                         set_nz_from_alu;
1931                     end if;
1932
1933                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
1934                     --(indir), y
1935                     d_print("ora");
1936                     a2_indir_y;
1937                     if exec_cycle = T4 or exec_cycle = T0 then
1938                         arith_en_n <= '0';
1939                         back_oe(acc_cmd, '0');
1940                         back_we(acc_cmd, '0');
1941                         set_nz_from_alu;
1942                     end if;
1943
1944                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
1945                     --imm
1946                     d_print("sbc");
1947                     fetch_imm;
1948                     arith_en_n <= '0';
1949                     back_oe(acc_cmd, '0');
1950                     back_we(acc_cmd, '0');
1951                     set_nvzc_from_alu;
1952
1953                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
1954                     --zp
1955                     d_print("sbc");
1956                     a2_zp;
1957                     if exec_cycle = T2 then
1958                         arith_en_n <= '0';
1959                         back_oe(acc_cmd, '0');
1960                         back_we(acc_cmd, '0');
1961                         set_nvzc_from_alu;
1962                     end if;
1963
1964                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
1965                     --zp, x
1966                     d_print("sbc");
1967                     a2_zp_xy(true);
1968                     if exec_cycle = T3 then
1969                         arith_en_n <= '0';
1970                         back_oe(acc_cmd, '0');
1971                         back_we(acc_cmd, '0');
1972                         set_nvzc_from_alu;
1973                     end if;
1974
1975                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
1976                     --abs
1977                     d_print("sbc");
1978                     a2_abs;
1979                     if exec_cycle = T3 then
1980                         arith_en_n <= '0';
1981                         back_oe(acc_cmd, '0');
1982                         back_we(acc_cmd, '0');
1983                         set_nvzc_from_alu;
1984                     end if;
1985
1986                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
1987                     --abs, x
1988                     d_print("sbc");
1989                     a2_abs_xy(true);
1990                     if exec_cycle = T3 or exec_cycle = T0 then
1991                         arith_en_n <= '0';
1992                         back_oe(acc_cmd, '0');
1993                         back_we(acc_cmd, '0');
1994                         set_nvzc_from_alu;
1995                     end if;
1996
1997                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
1998                     --abs, y
1999                     d_print("sbc");
2000                     a2_abs_xy(false);
2001                     if exec_cycle = T3 or exec_cycle = T0 then
2002                         arith_en_n <= '0';
2003                         back_oe(acc_cmd, '0');
2004                         back_we(acc_cmd, '0');
2005                         set_nvzc_from_alu;
2006                     end if;
2007
2008                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
2009                     --(indir, x)
2010                     d_print("sbc");
2011                     a2_indir_x;
2012                     if exec_cycle = T5 then
2013                         arith_en_n <= '0';
2014                         back_oe(acc_cmd, '0');
2015                         back_we(acc_cmd, '0');
2016                         set_nvzc_from_alu;
2017                     end if;
2018
2019                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
2020                     --(indir), y
2021                     d_print("sbc");
2022                     a2_indir_y;
2023                     if exec_cycle = T4 or exec_cycle = T0 then
2024                         arith_en_n <= '0';
2025                         back_oe(acc_cmd, '0');
2026                         back_we(acc_cmd, '0');
2027                         set_nvzc_from_alu;
2028                     end if;
2029
2030
2031
2032                 ----------------------------------------
2033                 ---A.3. store operation.
2034                 ----------------------------------------
2035                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
2036                     --zp
2037                     d_print("sta");
2038                     a3_zp;
2039                     if exec_cycle = T2 then
2040                         front_oe(acc_cmd, '0');
2041                     end if;
2042
2043                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
2044                     --zp, x
2045                     d_print("sta");
2046                     a3_zp_xy(true);
2047                     if exec_cycle = T2 then
2048                         front_oe(acc_cmd, '0');
2049                     end if;
2050
2051                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
2052                     --abs
2053                     d_print("sta");
2054                     a3_abs;
2055                     if exec_cycle = T3 then
2056                         front_oe(acc_cmd, '0');
2057                     end if;
2058
2059                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
2060                     --abs, x
2061                     d_print("sta");
2062                     a3_abs_xy (true);
2063                     if exec_cycle = T4 then
2064                         front_oe(acc_cmd, '0');
2065                     end if;
2066
2067                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
2068                     --abs, y
2069                     d_print("sta");
2070                     a3_abs_xy (false);
2071                     if exec_cycle = T4 then
2072                         front_oe(acc_cmd, '0');
2073                     end if;
2074
2075                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
2076                     --(indir, x)
2077                     d_print("sta");
2078                     a3_indir_x;
2079                     if exec_cycle = T5 then
2080                         front_oe(acc_cmd, '0');
2081                     end if;
2082
2083                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
2084                     --(indir), y
2085                     d_print("sta");
2086                     a3_indir_y;
2087                     if exec_cycle = T5 then
2088                         front_oe(acc_cmd, '0');
2089                     end if;
2090
2091                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
2092                     --zp
2093                     d_print("stx");
2094                     a3_zp;
2095                     if exec_cycle = T2 then
2096                         front_oe(x_cmd, '0');
2097                     end if;
2098
2099                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
2100                     --zp, y
2101                     d_print("stx");
2102                     a3_zp_xy(false);
2103                     if exec_cycle = T2 then
2104                         front_oe(x_cmd, '0');
2105                     end if;
2106
2107                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
2108                     --abs
2109                     d_print("stx");
2110                     a3_abs;
2111                     if exec_cycle = T3 then
2112                         front_oe(x_cmd, '0');
2113                     end if;
2114
2115                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
2116                     --zp
2117                     d_print("sty");
2118                     a3_zp;
2119                     if exec_cycle = T2 then
2120                         front_oe(y_cmd, '0');
2121                     end if;
2122
2123                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
2124                     --zp, x
2125                     d_print("sty");
2126                     a3_zp_xy(true);
2127                     if exec_cycle = T2 then
2128                         front_oe(y_cmd, '0');
2129                     end if;
2130
2131                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
2132                     --abs
2133                     d_print("sty");
2134                     a3_abs;
2135                     if exec_cycle = T3 then
2136                         front_oe(y_cmd, '0');
2137                     end if;
2138
2139
2140                 ----------------------------------------
2141                 ---A.4. read-modify-write operation
2142                 ----------------------------------------
2143                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
2144                     --zp
2145                     d_print("asl");
2146                     a4_zp;
2147                     if exec_cycle = T4 then
2148                         set_nzc_from_alu;
2149                     end if;
2150
2151                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
2152                     --zp, x
2153                     d_print("asl");
2154                     a4_zp_x;
2155                     if exec_cycle = T5 then
2156                         set_nzc_from_alu;
2157                     end if;
2158
2159                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
2160                     --abs
2161                     d_print("asl");
2162                     a4_abs;
2163                     if exec_cycle = T5 then
2164                         set_nzc_from_alu;
2165                     end if;
2166
2167                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
2168                     --abs, x
2169                     d_print("asl");
2170                     a4_abs_x;
2171                     if exec_cycle = T6 then
2172                         set_nzc_from_alu;
2173                     end if;
2174
2175                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
2176                     --zp
2177                     d_print("dec");
2178                     a4_zp;
2179                     if exec_cycle = T4 then
2180                         set_nz_from_bus;
2181                     end if;
2182
2183                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
2184                     --zp, x
2185                     d_print("dec");
2186                     a4_zp_x;
2187                     if exec_cycle = T5 then
2188                         set_nz_from_bus;
2189                     end if;
2190
2191                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
2192                     --abs
2193                     d_print("dec");
2194                     a4_abs;
2195                     if exec_cycle = T5 then
2196                         set_nz_from_bus;
2197                     end if;
2198
2199                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
2200                     --abs, x
2201                     d_print("dec");
2202                     a4_abs_x;
2203                     if exec_cycle = T6 then
2204                         set_nz_from_bus;
2205                     end if;
2206
2207                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
2208                     --zp
2209                     d_print("inc");
2210                     a4_zp;
2211                     if exec_cycle = T4 then
2212                         set_nz_from_bus;
2213                     end if;
2214
2215                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
2216                     --zp, x
2217                     d_print("inc");
2218                     a4_zp_x;
2219                     if exec_cycle = T5 then
2220                         set_nz_from_bus;
2221                     end if;
2222
2223                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
2224                     --abs
2225                     d_print("inc");
2226                     a4_abs;
2227                     if exec_cycle = T5 then
2228                         set_nz_from_bus;
2229                     end if;
2230
2231                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
2232                     --abs, x
2233                     d_print("inc");
2234                     a4_abs_x;
2235                     if exec_cycle = T6 then
2236                         set_nz_from_bus;
2237                     end if;
2238
2239                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
2240                     --zp
2241                     d_print("lsr");
2242                     a4_zp;
2243                     if exec_cycle = T4 then
2244                         set_zc_from_alu;
2245                     end if;
2246
2247                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
2248                     --zp, x
2249                     d_print("lsr");
2250                     a4_zp_x;
2251                     if exec_cycle = T5 then
2252                         set_zc_from_alu;
2253                     end if;
2254
2255                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
2256                     --abs
2257                     d_print("lsr");
2258                     a4_abs;
2259                     if exec_cycle = T5 then
2260                         set_zc_from_alu;
2261                     end if;
2262
2263                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
2264                     --abs, x
2265                     d_print("lsr");
2266                     a4_abs_x;
2267                     if exec_cycle = T6 then
2268                         set_zc_from_alu;
2269                     end if;
2270
2271                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
2272                     --zp
2273                     d_print("rol");
2274                     a4_zp;
2275                     if exec_cycle = T4 then
2276                         set_nzc_from_alu;
2277                     end if;
2278
2279                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
2280                     --zp, x
2281                     d_print("rol");
2282                     a4_zp_x;
2283                     if exec_cycle = T5 then
2284                         set_nzc_from_alu;
2285                     end if;
2286
2287                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
2288                     --abs
2289                     d_print("rol");
2290                     a4_abs;
2291                     if exec_cycle = T5 then
2292                         set_nzc_from_alu;
2293                     end if;
2294
2295                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
2296                     --abs, x
2297                     d_print("rol");
2298                     a4_abs_x;
2299                     if exec_cycle = T6 then
2300                         set_nzc_from_alu;
2301                     end if;
2302
2303                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
2304                     --zp
2305                     d_print("ror");
2306                     a4_zp;
2307                     if exec_cycle = T4 then
2308                         set_nzc_from_alu;
2309                     end if;
2310
2311                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
2312                     --zp, x
2313                     d_print("ror");
2314                     a4_zp_x;
2315                     if exec_cycle = T5 then
2316                         set_nzc_from_alu;
2317                     end if;
2318
2319                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
2320                     --abs
2321                     d_print("ror");
2322                     a4_abs;
2323                     if exec_cycle = T5 then
2324                         set_nzc_from_alu;
2325                     end if;
2326
2327                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
2328                     --abs, x
2329                     d_print("ror");
2330                     a4_abs_x;
2331                     if exec_cycle = T6 then
2332                         set_nzc_from_alu;
2333                     end if;
2334
2335
2336                 ----------------------------------------
2337                 --A.5. miscellaneous oprations.
2338                 ----------------------------------------
2339
2340                 -- A.5.1 push/pull
2341                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
2342                     d_print("php");
2343                     a51_push;
2344                     if exec_cycle = T2 then
2345                         stat_bus_oe_n <= '0';
2346                     end if;
2347
2348                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
2349                     d_print("pha");
2350                     a51_push;
2351                     if exec_cycle = T2 then
2352                         front_oe(acc_cmd, '0');
2353                     end if;
2354
2355                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
2356                     d_print("plp");
2357                     a52_pull;
2358                     if exec_cycle = T3 then
2359                         stat_dec_oe_n <= '1';
2360                         stat_bus_all_n <= '0';
2361                     end if;
2362
2363                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
2364                     d_print("pla");
2365                     a52_pull;
2366                     if exec_cycle = T3 then
2367                         front_we(acc_cmd, '0');
2368                         set_nz_from_bus;
2369                     end if;
2370
2371
2372                 ----------------------------------------
2373                 -- A.5.3 jsr
2374                 ----------------------------------------
2375                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
2376                     if exec_cycle = T1 then
2377                         d_print("jsr abs 2");
2378                         --fetch opcode.
2379                         fetch_next;
2380                         dbuf_int_oe_n <= '0';
2381                         --latch adl
2382                         --dl_al_we_n <= '0';
2383                         next_cycle <= T2;
2384                     elsif exec_cycle = T2 then
2385                         d_print("jsr 3");
2386                         fetch_stop;
2387                         dbuf_int_oe_n <= '1';
2388                         --dl_al_we_n <= '1';
2389
2390                        --push return addr high into stack.
2391                         sp_push_n <= '0';
2392                         sp_oe_n <= '0';
2393                         front_oe(pch_cmd, '0');
2394                         back_oe(sp_cmd, '0');
2395                         back_we(sp_cmd, '0');
2396                         r_nw <= '0';
2397                         next_cycle <= T3;
2398                     elsif exec_cycle = T3 then
2399                         d_print("jsr 4");
2400                         front_oe(pch_cmd, '1');
2401
2402                        --push return addr low into stack.
2403                         sp_push_n <= '0';
2404                         sp_oe_n <= '0';
2405                         front_oe(pcl_cmd, '0');
2406                         back_oe(sp_cmd, '0');
2407                         back_we(sp_cmd, '0');
2408                         r_nw <= '0';
2409
2410                         next_cycle <= T4;
2411                     elsif exec_cycle = T4 then
2412                         d_print("jsr 5");
2413                         sp_push_n <= '1';
2414                         sp_oe_n <= '1';
2415                         front_oe(pcl_cmd, '1');
2416                         back_oe(sp_cmd, '1');
2417                         back_we(sp_cmd, '1');
2418                         r_nw <= '1';
2419
2420                         --fetch last op.
2421                         back_oe(pch_cmd, '0');
2422                         back_oe(pcl_cmd, '0');
2423                         dbuf_int_oe_n <= '0';
2424                         --dl_ah_we_n <= '0';
2425
2426                         next_cycle <= T5;
2427                     elsif exec_cycle = T5 then
2428                         d_print("jsr 6");
2429
2430                         back_oe(pch_cmd, '1');
2431                         back_oe(pcl_cmd, '1');
2432                         dbuf_int_oe_n <= '1';
2433                         --dl_ah_we_n <= '1';
2434
2435                         --load/output  pch
2436                         ad_oe_n <= '1';
2437                         --dl_dh_oe_n <= '0';
2438                         front_we(pch_cmd, '0');
2439
2440                         --load pcl.
2441                         --dl_al_oe_n <= '0';
2442                         back_we(pcl_cmd, '0');
2443
2444                         next_cycle <= T0;
2445                     end if; --if exec_cycle = T1 then
2446
2447                 -- A.5.4 break
2448                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
2449
2450                 ----------------------------------------
2451                 -- A.5.5 return from interrupt
2452                 ----------------------------------------
2453                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
2454                     if exec_cycle = T1 then
2455                         d_print("rti 2");
2456                         fetch_stop;
2457
2458                         --pop stack (decrement only)
2459                         back_oe(sp_cmd, '0');
2460                         back_we(sp_cmd, '0');
2461                         sp_pop_n <= '0';
2462                         sp_oe_n <= '0';
2463
2464                         next_cycle <= T2;
2465                     elsif exec_cycle = T2 then
2466                         d_print("rti 3");
2467
2468                         --pop p (status)
2469                         back_oe(sp_cmd, '0');
2470                         back_we(sp_cmd, '0');
2471                         sp_pop_n <= '0';
2472                         sp_oe_n <= '0';
2473
2474                         --load status reg
2475                         stat_dec_oe_n <= '1';
2476                         dbuf_int_oe_n <= '0';
2477                         stat_bus_all_n <= '0';
2478
2479                         next_cycle <= T3;
2480                     elsif exec_cycle = T3 then
2481                         d_print("rti 4");
2482                         stat_bus_all_n <= '1';
2483
2484                         --pop pcl
2485                         back_oe(sp_cmd, '0');
2486                         back_we(sp_cmd, '0');
2487                         sp_pop_n <= '0';
2488                         sp_oe_n <= '0';
2489
2490                         --load lo addr.
2491                         dbuf_int_oe_n <= '0';
2492                         front_we(pcl_cmd, '0');
2493
2494                         next_cycle <= T4;
2495                     elsif exec_cycle = T4 then
2496                         d_print("rti 5");
2497                         --stack decrement stop.
2498                         back_we(sp_cmd, '1');
2499                         sp_pop_n <= '1';
2500                         front_we(pcl_cmd, '1');
2501
2502                         --pop pch
2503                         back_oe(sp_cmd, '0');
2504                         sp_oe_n <= '0';
2505                         --load hi addr.
2506                         dbuf_int_oe_n <= '0';
2507                         front_we(pch_cmd, '0');
2508
2509                         next_cycle <= T5;
2510                     elsif exec_cycle = T5 then
2511                         d_print("rti 6");
2512                         back_oe(sp_cmd, '1');
2513                         sp_oe_n <= '1';
2514                         --load hi addr.
2515                         dbuf_int_oe_n <= '1';
2516                         front_we(pch_cmd, '1');
2517
2518                         --increment pc.
2519                         next_cycle <= T0;
2520                     end if; --if exec_cycle = T1 then
2521
2522                 ----------------------------------------
2523                 -- A.5.6 jmp
2524                 ----------------------------------------
2525                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
2526                     --abs
2527                     if exec_cycle = T1 then
2528                         d_print("jmp 2");
2529                         --fetch next opcode (abs low).
2530                         fetch_next;
2531
2532                         --latch abs low data.
2533                         dbuf_int_oe_n <= '0';
2534                         --dl_al_we_n <= '0';
2535                         next_cycle <= T2;
2536                     elsif exec_cycle = T2 then
2537                         d_print("jmp 3");
2538                         --dl_al_we_n <= '1';
2539
2540                         --fetch abs hi
2541                         fetch_next;
2542
2543                         --latch  in dlh
2544                         dbuf_int_oe_n <= '0';
2545                         --dl_ah_we_n <= '0';
2546                         ---load pch.
2547                         front_we(pch_cmd, '0');
2548
2549                         next_cycle <= T0;
2550                     end if;
2551
2552                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
2553                     --jmp (indir)
2554                     if exec_cycle = T1 then
2555                         d_print("jmp 2");
2556                         --fetch next opcode (abs low).
2557                         fetch_next;
2558
2559                         --latch abs low data.
2560                         dbuf_int_oe_n <= '0';
2561                         --dl_al_we_n <= '0';
2562                         next_cycle <= T2;
2563                     elsif exec_cycle = T2 then
2564                         d_print("jmp 3");
2565                         --dl_al_we_n <= '1';
2566
2567                         --fetch abs hi
2568                         fetch_next;
2569
2570                         --latch  in dlh
2571                         dbuf_int_oe_n <= '0';
2572                         --dl_ah_we_n <= '0';
2573                         next_cycle <= T3;
2574
2575                     elsif exec_cycle = T3 then
2576                         fetch_stop;
2577                         --dl_ah_we_n <= '1';
2578
2579                         --IAH/IAL > ADL
2580                         --dl_ah_oe_n <= '0';
2581                         --dl_al_oe_n <= '0';
2582                         front_we(pcl_cmd, '0');
2583                         next_cycle <= T4;
2584
2585                     elsif exec_cycle = T4 then
2586                         --dl_ah_oe_n <= '0';
2587                         --dl_al_oe_n <= '0';
2588                         front_we(pcl_cmd, '1');
2589
2590                         --IAH/IAL+1 > ADH
2591                         front_we(pch_cmd, '0');
2592                         indir_n <= '0';
2593
2594                         next_cycle <= T0;
2595
2596                     end if;
2597
2598
2599                 ----------------------------------------
2600                 -- A.5.7 return from soubroutine
2601                 ----------------------------------------
2602                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
2603                     if exec_cycle = T1 then
2604                         d_print("rts 2");
2605                         fetch_stop;
2606
2607                         --pop stack (decrement only)
2608                         back_oe(sp_cmd, '0');
2609                         back_we(sp_cmd, '0');
2610                         sp_pop_n <= '0';
2611                         sp_oe_n <= '0';
2612
2613                         next_cycle <= T2;
2614                     elsif exec_cycle = T2 then
2615                         d_print("rts 3");
2616
2617                         --pop pcl
2618                         back_oe(sp_cmd, '0');
2619                         back_we(sp_cmd, '0');
2620                         sp_pop_n <= '0';
2621                         sp_oe_n <= '0';
2622
2623                         --load lo addr.
2624                         dbuf_int_oe_n <= '0';
2625                         front_we(pcl_cmd, '0');
2626
2627                         next_cycle <= T3;
2628                     elsif exec_cycle = T3 then
2629                         d_print("rts 4");
2630                         --stack decrement stop.
2631                         back_we(sp_cmd, '1');
2632                         sp_pop_n <= '1';
2633                         front_we(pcl_cmd, '1');
2634
2635                         --pop pch
2636                         back_oe(sp_cmd, '0');
2637                         sp_oe_n <= '0';
2638                         --load hi addr.
2639                         dbuf_int_oe_n <= '0';
2640                         front_we(pch_cmd, '0');
2641
2642                         next_cycle <= T4;
2643                     elsif exec_cycle = T4 then
2644                         d_print("rts 5");
2645                         back_oe(sp_cmd, '1');
2646                         sp_oe_n <= '1';
2647                         --load hi addr.
2648                         dbuf_int_oe_n <= '1';
2649                         front_we(pch_cmd, '1');
2650                         --empty cycle.
2651                         --complying h/w manual...
2652                         next_cycle <= T5;
2653                     elsif exec_cycle = T5 then
2654                         d_print("rts 6");
2655
2656                         --increment pc.
2657                         fetch_next;
2658                         next_cycle <= T0;
2659                     end if; --if exec_cycle = T1 then
2660
2661                 ----------------------------------------
2662                 -- A.5.8 branch operations
2663                 ----------------------------------------
2664                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
2665                     d_print("bcc");
2666                     a58_branch (st_C, '0');
2667
2668                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
2669                     d_print("bcs");
2670                     a58_branch (st_C, '1');
2671
2672                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
2673                     d_print("beq");
2674                     a58_branch (st_Z, '1');
2675
2676                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
2677                     d_print("bmi");
2678                     a58_branch (st_N, '1');
2679
2680                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
2681                     d_print("bne");
2682                     a58_branch (st_Z, '0');
2683
2684                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
2685                     d_print("bpl");
2686                     a58_branch (st_N, '0');
2687
2688                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
2689                     d_print("bvc");
2690                     a58_branch (st_V, '0');
2691
2692                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
2693                     d_print("bvs");
2694                     a58_branch (st_V, '1');
2695
2696                 else
2697                     ---unknown instruction!!!!
2698                     assert false
2699                         report "======== unknow instruction "
2700                             & conv_hex8(conv_integer(instruction))
2701                         severity failure;
2702                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
2703
2704             elsif exec_cycle = R0 then
2705                 d_print(string'("reset"));
2706
2707                 --initialize port...
2708                 inst_we_n <= '1';
2709                 ad_oe_n <= '1';
2710                 dbuf_int_oe_n <= '1';
2711                 --dl_al_we_n <= '1';
2712                 --dl_ah_we_n <= '1';
2713                 --dl_al_oe_n <= '1';
2714                 --dl_ah_oe_n <= '1';
2715                 --dl_dh_oe_n <= '1';
2716                 pcl_inc_n <= '1';
2717                 pcl_cmd <= "1111";
2718                 pch_cmd <= "1111";
2719                 sp_cmd <= "1111";
2720                 sp_oe_n <= '1';
2721                 sp_push_n <= '1';
2722                 sp_pop_n <= '1';
2723                 acc_cmd <= "1111";
2724                 x_cmd <= "1111";
2725                 y_cmd <= "1111";
2726
2727                 abs_xy_n <= '1';
2728                 pg_next_n <= '1';
2729                 zp_n <= '1';
2730                 zp_xy_n <= '1';
2731                 rel_calc_n <= '1';
2732                 indir_n <= '1';
2733                 indir_x_n <= '1';
2734                 indir_y_n <= '1';
2735                 arith_en_n <= '1';
2736
2737                 stat_dec_oe_n <= '0';
2738                 stat_bus_oe_n <= '1';
2739                 stat_set_flg_n <= '1';
2740                 stat_flg <= '1';
2741                 stat_bus_all_n <= '1';
2742                 stat_bus_nz_n <= '1';
2743                 stat_alu_we_n <= '1';
2744
2745                 r_vec_oe_n <= '1';
2746                 n_vec_oe_n <= '1';
2747                 i_vec_oe_n <= '1';
2748                 nmi_handled_n <= '1';
2749                 r_nw <= '1';
2750
2751                 next_cycle <= R1;
2752             elsif exec_cycle = R1 or exec_cycle = N1 then
2753                 pcl_cmd <= "1111";
2754                 pcl_inc_n <= '1';
2755                 inst_we_n <= '1';
2756                 --dl_al_oe_n <= '1';
2757
2758                 --push pch.
2759                 d_print("R1");
2760                 ad_oe_n <= '0';
2761                 sp_push_n <= '0';
2762                 sp_oe_n <= '0';
2763                 pch_cmd <= "0111";
2764                 --front_oe(pch_cmd, '0');
2765                 back_oe(sp_cmd, '0');
2766                 back_we(sp_cmd, '0');
2767                 r_nw <= '0';
2768
2769                 if exec_cycle = R1 then
2770                     next_cycle <= R2;
2771                 elsif exec_cycle = N1 then
2772                     next_cycle <= N2;
2773                 end if;
2774
2775             elsif exec_cycle = R2 or exec_cycle = N2 then
2776                 front_oe(pch_cmd, '1');
2777
2778                --push pcl.
2779                 sp_push_n <= '0';
2780                 sp_oe_n <= '0';
2781                 front_oe(pcl_cmd, '0');
2782                 back_oe(sp_cmd, '0');
2783                 back_we(sp_cmd, '0');
2784                 r_nw <= '0';
2785
2786                 if exec_cycle = R2 then
2787                     next_cycle <= R3;
2788                 elsif exec_cycle = N2 then
2789                     next_cycle <= N3;
2790                 end if;
2791
2792             elsif exec_cycle = R3 or exec_cycle = N3 then
2793                 front_oe(pcl_cmd, '1');
2794
2795                --push status.
2796                 sp_push_n <= '0';
2797                 sp_oe_n <= '0';
2798                 stat_bus_oe_n <= '0';
2799                 back_oe(sp_cmd, '0');
2800                 back_we(sp_cmd, '0');
2801                 r_nw <= '0';
2802
2803                 if exec_cycle = R3 then
2804                     next_cycle <= R4;
2805                 elsif exec_cycle = N3 then
2806                     next_cycle <= N4;
2807                 end if;
2808
2809             elsif exec_cycle = R4 or exec_cycle = N4 then
2810                 stat_bus_oe_n <= '1';
2811                 sp_push_n <= '1';
2812                 sp_oe_n <= '1';
2813                 front_oe(pcl_cmd, '1');
2814                 back_oe(sp_cmd, '1');
2815                 back_we(sp_cmd, '1');
2816
2817                 --fetch reset vector low
2818                 r_nw <= '1';
2819                 dbuf_int_oe_n <= '0';
2820                 front_we(pcl_cmd, '0');
2821                 --dl_al_oe_n <= '1';
2822                 --dl_ah_oe_n <= '1';
2823
2824                 if exec_cycle = R4 then
2825                     r_vec_oe_n <= '0';
2826                     n_vec_oe_n <= '1';
2827                     next_cycle <= R5;
2828                 elsif exec_cycle = N4 then
2829                     r_vec_oe_n <= '1';
2830                     n_vec_oe_n <= '0';
2831                     next_cycle <= N5;
2832                 end if;
2833
2834             elsif exec_cycle = R5 or exec_cycle = N5 then
2835                 front_we(pcl_cmd, '1');
2836
2837                 --fetch reset vector hi
2838                 r_nw <= '1';
2839                 dbuf_int_oe_n <= '0';
2840                 front_we(pch_cmd, '0');
2841                 indir_n <= '0';
2842
2843                 if exec_cycle = N5 then
2844                     nmi_handled_n <= '0';
2845                 end if;
2846                 --start execute cycle.
2847                 next_cycle <= T0;
2848
2849             end if; --if rdy = '0' then
2850
2851         end if; -- if (res_n = '0') then
2852
2853     end process;
2854
2855 end rtl;
2856