de1_nes/cpu/decoder.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.conv_std_logic_vector;
   4 use ieee.std_logic_unsigned.conv_integer;
   5 use work.motonesfpga_common.all;
   6
   7 entity decoder is
   8     generic (dsize : integer := 8);
   9     port (
  10             --input lines.
  11             cpu_clk         : in std_logic;
  12             dl_cpu_clk      : in std_logic;
  13             res_n           : in std_logic;
  14             irq_n           : in std_logic;
  15             nmi_n           : in std_logic;
  16             rdy             : in std_logic;
  17             instruction     : in std_logic_vector (dsize - 1 downto 0);
  18             exec_cycle      : in std_logic_vector (5 downto 0);
  19             next_cycle      : out std_logic_vector (5 downto 0);
  20             ea_carry        : in  std_logic;
  21             status_reg      : inout std_logic_vector (dsize - 1 downto 0);
  22
  23             --general control.
  24             inst_we_n       : out std_logic;
  25             ad_oe_n         : out std_logic;
  26             dbuf_int_oe_n   : out std_logic;
  27             r_nw            : out std_logic;
  28
  29             ----control line for dual port registers.
  30             idl_l_cmd       : out std_logic_vector(3 downto 0);
  31             idl_h_cmd       : out std_logic_vector(3 downto 0);
  32             pcl_cmd         : out std_logic_vector(3 downto 0);
  33             pch_cmd         : out std_logic_vector(3 downto 0);
  34             sp_cmd          : out std_logic_vector(3 downto 0);
  35             x_cmd           : out std_logic_vector(3 downto 0);
  36             y_cmd           : out std_logic_vector(3 downto 0);
  37             acc_cmd         : out std_logic_vector(3 downto 0);
  38
  39             --addr calc control
  40             pcl_inc_n       : out std_logic;
  41             sp_oe_n         : out std_logic;
  42             sp_push_n       : out std_logic;
  43             sp_pop_n        : out std_logic;
  44             abs_xy_n        : out std_logic;
  45             pg_next_n       : out std_logic;
  46             zp_n            : out std_logic;
  47             zp_xy_n         : out std_logic;
  48             rel_calc_n      : out std_logic;
  49             indir_n         : out std_logic;
  50             indir_x_n       : out std_logic;
  51             indir_y_n       : out std_logic;
  52             addr_cycle      : out std_logic_vector(2 downto 0);
  53
  54             ---status register
  55             stat_dec_oe_n   : out std_logic;
  56             stat_bus_oe_n   : out std_logic;
  57             stat_set_flg_n  : out std_logic;
  58             stat_flg        : out std_logic;
  59             stat_bus_all_n  : out std_logic;
  60             stat_bus_nz_n   : out std_logic;
  61             stat_alu_we_n   : out std_logic;
  62
  63             --ALU control
  64             arith_en_n      : out std_logic;
  65             alu_cycle       : out std_logic_vector(1 downto 0);
  66
  67             --reset vectors.
  68             r_vec_oe_n      : out std_logic;
  69             n_vec_oe_n      : out std_logic;
  70             i_vec_oe_n      : out std_logic
  71
  72             ;---for parameter check purpose!!!
  73             check_bit     : out std_logic_vector(1 to 5)
  74         );
  75 end decoder;
  76
  77 architecture rtl of decoder is
  78
  79 component d_flip_flop_bit
  80     port (
  81             clk     : in std_logic;
  82             res_n   : in std_logic;
  83             set_n   : in std_logic;
  84             we_n    : in std_logic;
  85             d       : in std_logic;
  86             q       : out std_logic
  87         );
  88 end component;
  89
  90 --cycle bit format
  91 -- bit 5    : special cycle
  92 -- bit 4,3  : cycle type: 00 normal, 01 reset , 10 nmi, 11 irq
  93 -- bit 2-0  : cycle
  94
  95 --00xxx : exec cycle : T0 > T1 > T2 > T3 > T4 > T5 > T6 > T0
  96 constant T0 : std_logic_vector (5 downto 0) := "000000";
  97 constant T1 : std_logic_vector (5 downto 0) := "000001";
  98 constant T2 : std_logic_vector (5 downto 0) := "000010";
  99 constant T3 : std_logic_vector (5 downto 0) := "000011";
 100 constant T4 : std_logic_vector (5 downto 0) := "000100";
 101 constant T5 : std_logic_vector (5 downto 0) := "000101";
 102 constant T6 : std_logic_vector (5 downto 0) := "000110";
 103
 104 --reset cycle:
 105 --R0/T0: hold pc
 106 --R1: hold pc
 107 --R2: push pch
 108 --R3: push pcl
 109 --R4: push p
 110 --R5: fetch vector low
 111 --R6: fetch vector high
 112 --T0: first opcode
 113
 114 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > R6 > T0
 115 constant R0 : std_logic_vector (5 downto 0) := "001000";
 116 constant R1 : std_logic_vector (5 downto 0) := "001001";
 117 constant R2 : std_logic_vector (5 downto 0) := "001010";
 118 constant R3 : std_logic_vector (5 downto 0) := "001011";
 119 constant R4 : std_logic_vector (5 downto 0) := "001100";
 120 constant R5 : std_logic_vector (5 downto 0) := "001101";
 121 constant R6 : std_logic_vector (5 downto 0) := "001110";
 122
 123 --10xxx : nmi cycle : T0 > N1 > N2 > N3 > N4 > N5 > N6 > T0
 124 constant N1 : std_logic_vector (5 downto 0) := "010001";
 125 constant N2 : std_logic_vector (5 downto 0) := "010010";
 126 constant N3 : std_logic_vector (5 downto 0) := "010011";
 127 constant N4 : std_logic_vector (5 downto 0) := "010100";
 128 constant N5 : std_logic_vector (5 downto 0) := "010101";
 129 constant N6 : std_logic_vector (5 downto 0) := "010110";
 130
 131 --11xxx : irq cycle : T0 > I1 > I2 > I3 > I4 > I5 > I6 > T0
 132 constant I1 : std_logic_vector (5 downto 0) := "011001";
 133 constant I2 : std_logic_vector (5 downto 0) := "011010";
 134 constant I3 : std_logic_vector (5 downto 0) := "011011";
 135 constant I4 : std_logic_vector (5 downto 0) := "011100";
 136 constant I5 : std_logic_vector (5 downto 0) := "011101";
 137 constant I6 : std_logic_vector (5 downto 0) := "011110";
 138
 139 constant ERROR_CYCLE : std_logic_vector (5 downto 0) := "111111";
 140
 141 -- SR Flags (bit 7 to bit 0):
 142 --  7   N   ....    Negative
 143 --  6   V   ....    Overflow
 144 --  5   -   ....    ignored
 145 --  4   B   ....    Break
 146 --  3   D   ....    Decimal (use BCD for arithmetics)
 147 --  2   I   ....    Interrupt (IRQ disable)
 148 --  1   Z   ....    Zero
 149 --  0   C   ....    Carry
 150 constant st_N : integer := 7;
 151 constant st_V : integer := 6;
 152 constant st_B : integer := 4;
 153 constant st_D : integer := 3;
 154 constant st_I : integer := 2;
 155 constant st_Z : integer := 1;
 156 constant st_C : integer := 0;
 157
 158 --Address calcuration (indirect addressing) has several stages
 159 constant ADDR_Z  : std_logic_vector (2 downto 0) := "000";
 160 constant ADDR_T2 : std_logic_vector (2 downto 0) := "001";
 161 constant ADDR_T3 : std_logic_vector (2 downto 0) := "010";
 162 constant ADDR_T4 : std_logic_vector (2 downto 0) := "011";
 163 constant ADDR_T5 : std_logic_vector (2 downto 0) := "100";
 164
 165 --ALU cycle (memory to memory operation) has several stages
 166 constant MEM_Z  : std_logic_vector (1 downto 0) := "00";
 167 constant MEM_T1 : std_logic_vector (1 downto 0) := "01";
 168 constant MEM_T2 : std_logic_vector (1 downto 0) := "10";
 169 constant MEM_T3 : std_logic_vector (1 downto 0) := "11";
 170
 171 ---for nmi handling
 172 signal nmi_handled_n : std_logic;
 173 signal ea_carry_reg       : std_logic;
 174
 175 begin
 176
 177     ea_carry_inst: d_flip_flop_bit
 178             port map(dl_cpu_clk, '1', '1', '0', ea_carry, ea_carry_reg);
 179
 180     main_p : process (cpu_clk, res_n, nmi_n)
 181
 182 -------------------------------------------------------------
 183 -------------------------------------------------------------
 184 ----------------------- comon routines ----------------------
 185 -------------------------------------------------------------
 186 -------------------------------------------------------------
 187
 188 ----------gate_cmd format
 189 ------3 : front port oe_n
 190 ------2 : front port we_n
 191 ------1 : back port oe_n
 192 ------0 : back port we_n
 193 procedure front_oe (signal cmd : out std_logic_vector(3 downto 0);
 194     val : in std_logic) is
 195 begin
 196     cmd(3) <= val;
 197 end;
 198 procedure front_we (signal cmd : out std_logic_vector(3 downto 0);
 199     val : in std_logic) is
 200 begin
 201     cmd(2) <= val;
 202 end;
 203 procedure back_oe (signal cmd : out std_logic_vector(3 downto 0);
 204     val : in std_logic) is
 205 begin
 206     cmd(1) <= val;
 207 end;
 208 procedure back_we (signal cmd : out std_logic_vector(3 downto 0);
 209     val : in std_logic) is
 210 begin
 211     cmd(0) <= val;
 212 end;
 213
 214 procedure fetch_next is
 215 begin
 216     pcl_inc_n <= '0';
 217     back_oe(pcl_cmd, '0');
 218     back_oe(pch_cmd, '0');
 219     back_we(pcl_cmd, '0');
 220     back_we(pch_cmd, '0');
 221     if exec_cycle = T1 then
 222         front_we(idl_l_cmd, '0');
 223     elsif exec_cycle = T2 then
 224         front_we(idl_l_cmd, '1');
 225         front_we(idl_h_cmd, '0');
 226     end if;
 227 end procedure;
 228
 229 procedure fetch_stop is
 230 begin
 231     pcl_inc_n <= '1';
 232     back_oe(pcl_cmd, '1');
 233     back_oe(pch_cmd, '1');
 234     back_we(pcl_cmd, '1');
 235     back_we(pch_cmd, '1');
 236     front_we(idl_l_cmd, '1');
 237     front_we(idl_h_cmd, '1');
 238 end procedure;
 239
 240 procedure read_status is
 241 begin
 242     status_reg <= (others => 'Z');
 243     stat_dec_oe_n <= '0';
 244 end  procedure;
 245
 246 procedure init_all_pins is
 247 begin
 248     --initialize port...
 249     inst_we_n <= '1';
 250     ad_oe_n <= '1';
 251     dbuf_int_oe_n <= '1';
 252     r_nw <= '1';
 253
 254     idl_l_cmd <= "1111";
 255     idl_h_cmd <= "1111";
 256     pcl_cmd <= "1111";
 257     pch_cmd <= "1111";
 258     sp_cmd <= "1111";
 259     x_cmd <= "1111";
 260     y_cmd <= "1111";
 261     acc_cmd <= "1111";
 262
 263     pcl_inc_n <= '1';
 264     sp_oe_n <= '1';
 265     sp_push_n <= '1';
 266     sp_pop_n <= '1';
 267     abs_xy_n <= '1';
 268     pg_next_n <= '1';
 269     zp_n <= '1';
 270     zp_xy_n <= '1';
 271     rel_calc_n <= '1';
 272     indir_n <= '1';
 273     indir_x_n <= '1';
 274     indir_y_n <= '1';
 275     addr_cycle <= ADDR_Z;
 276
 277     read_status;
 278     stat_bus_oe_n <= '1';
 279     stat_set_flg_n <= '1';
 280     stat_flg <= '1';
 281     stat_bus_all_n <= '1';
 282     stat_bus_nz_n <= '1';
 283     stat_alu_we_n <= '1';
 284
 285     arith_en_n <= '1';
 286     addr_cycle <= ADDR_Z;
 287
 288     r_vec_oe_n <= '1';
 289     n_vec_oe_n <= '1';
 290     i_vec_oe_n <= '1';
 291
 292     nmi_handled_n <= '1';
 293
 294 end  procedure;
 295
 296 procedure disable_pins is
 297 begin
 298 --following pins are not set in this function.
 299 --            inst_we_n       : out std_logic;
 300 --            ad_oe_n         : out std_logic;
 301 --            pcl_inc_n       : out std_logic;
 302 --            r_nw            : out std_logic
 303
 304     --disable the last opration pins.
 305     dbuf_int_oe_n <= '1';
 306
 307     idl_l_cmd <= "1111";
 308     idl_h_cmd <= "1111";
 309     pcl_cmd   <= "1111";
 310     pch_cmd   <= "1111";
 311     sp_cmd <= "1111";
 312     x_cmd <= "1111";
 313     y_cmd <= "1111";
 314     acc_cmd <= "1111";
 315
 316     sp_oe_n <= '1';
 317     sp_push_n <= '1';
 318     sp_pop_n <= '1';
 319     abs_xy_n <= '1';
 320     pg_next_n <= '1';
 321     zp_n <= '1';
 322     zp_xy_n <= '1';
 323     rel_calc_n <= '1';
 324     indir_n <= '1';
 325     indir_x_n <= '1';
 326     indir_y_n <= '1';
 327     addr_cycle <= ADDR_Z;
 328
 329     read_status;
 330     stat_bus_oe_n <= '1';
 331     stat_set_flg_n <= '1';
 332     stat_flg <= '1';
 333     stat_bus_all_n <= '1';
 334     stat_bus_nz_n <= '1';
 335     stat_alu_we_n <= '1';
 336
 337     arith_en_n <= '1';
 338     alu_cycle <= MEM_Z;
 339
 340     r_vec_oe_n <= '1';
 341     n_vec_oe_n <= '1';
 342     i_vec_oe_n <= '1';
 343
 344 end  procedure;
 345
 346 procedure fetch_inst (pm_pcl_inc_n : in std_logic) is
 347 begin
 348     if (instruction = conv_std_logic_vector(16#4c#, dsize) or
 349         instruction = conv_std_logic_vector(16#20#, dsize)) then
 350         --if prior cycle is jump/jsr instruction,
 351         --fetch opcode from where the latch is pointing to.
 352
 353         --latch > al.
 354         back_oe(idl_l_cmd, '0');
 355         pcl_cmd <= "1110";
 356     else
 357         --fetch opcode and pcl increment.
 358         pcl_cmd <= "1100";
 359     end if;
 360
 361     idl_h_cmd <= "1111";
 362     ad_oe_n <= '0';
 363     pch_cmd <= "1100";
 364     inst_we_n <= '0';
 365     pcl_inc_n <= pm_pcl_inc_n;
 366     r_nw <= '1';
 367
 368     d_print(string'("fetch 1"));
 369 end  procedure;
 370
 371 ---T0 cycle routine
 372 ---(along with the page boundary condition, the last
 373 ---cycle is bypassed and slided to T0.)
 374 procedure t0_cycle is
 375 begin
 376     disable_pins;
 377     if (nmi_n = '0' and nmi_handled_n = '1') then
 378         --start nmi handling...
 379         fetch_inst('1');
 380         next_cycle <= N1;
 381     else
 382         fetch_inst('0');
 383         next_cycle <= T1;
 384     end if;
 385 end  procedure;
 386
 387 ---common routine for single byte instruction.
 388 procedure single_inst is
 389 begin
 390     fetch_stop;
 391     next_cycle <= T0;
 392 end  procedure;
 393
 394 procedure fetch_imm is
 395 begin
 396     d_print("immediate");
 397     fetch_next;
 398     --send data from data bus buffer.
 399     --receiver is instruction dependent.
 400     dbuf_int_oe_n <= '0';
 401     next_cycle <= T0;
 402 end  procedure;
 403
 404 procedure set_nz_from_bus is
 405 begin
 406     --status register n/z bit update.
 407     stat_bus_nz_n <= '0';
 408 end  procedure;
 409
 410 procedure set_zc_from_alu is
 411 begin
 412     --status register n/z bit update.
 413     stat_alu_we_n <= '0';
 414     stat_dec_oe_n <= '1';
 415     status_reg <= "00000011";
 416 end  procedure;
 417
 418 procedure set_nz_from_alu is
 419 begin
 420     --status register n/z/c bit update.
 421     stat_alu_we_n <= '0';
 422     stat_dec_oe_n <= '1';
 423     status_reg <= "10000010";
 424 end  procedure;
 425
 426 procedure set_nzc_from_alu is
 427 begin
 428     --status register n/z/c bit update.
 429     stat_alu_we_n <= '0';
 430     stat_dec_oe_n <= '1';
 431     status_reg <= "10000011";
 432 end  procedure;
 433
 434 procedure set_nvz_from_alu is
 435 begin
 436     --status register n/z/v bit update.
 437     stat_alu_we_n <= '0';
 438     stat_dec_oe_n <= '1';
 439     status_reg <= "11000010";
 440 end  procedure;
 441
 442 procedure set_nvzc_from_alu is
 443 begin
 444     stat_alu_we_n <= '0';
 445     stat_dec_oe_n <= '1';
 446     status_reg <= "11000011";
 447 end  procedure;
 448
 449 --flag on/off instruction
 450 procedure set_flag (int_flg : in integer; val : in std_logic) is
 451 begin
 452     stat_dec_oe_n <= '1';
 453     stat_set_flg_n <= '0';
 454     --specify which to set.
 455     status_reg(7 downto int_flg + 1)
 456         <= (others =>'0');
 457     status_reg(int_flg - 1 downto 0)
 458         <= (others =>'0');
 459     status_reg(int_flg) <= '1';
 460     stat_flg <= val;
 461 end  procedure;
 462
 463 --for sec/clc
 464 procedure set_flag0 (val : in std_logic) is
 465 begin
 466     stat_dec_oe_n <= '1';
 467     stat_set_flg_n <= '0';
 468     status_reg <= "00000001";
 469     stat_flg <= val;
 470 end  procedure;
 471
 472 procedure fetch_low is
 473 begin
 474     d_print("fetch low 2");
 475     --fetch next opcode (abs low).
 476     fetch_next;
 477     --latch abs low data.
 478     dbuf_int_oe_n <= '0';
 479     next_cycle <= T2;
 480 end  procedure;
 481
 482 procedure abs_fetch_high is
 483 begin
 484     d_print("abs (xy) 3");
 485
 486     --latch abs hi data.
 487     fetch_next;
 488     dbuf_int_oe_n <= '0';
 489     next_cycle <= T3;
 490 end  procedure;
 491
 492 procedure abs_latch_out is
 493 begin
 494     --d_print("abs 4");
 495     fetch_stop;
 496
 497     --latch > al/ah.
 498     back_oe(idl_l_cmd, '0');
 499     back_oe(idl_h_cmd, '0');
 500 end  procedure;
 501
 502 procedure ea_x_out is
 503 begin
 504     -----calucurate and output effective addr
 505     back_oe(x_cmd, '0');
 506     abs_xy_n <= '0';
 507 end  procedure;
 508
 509 procedure ea_y_out is
 510 begin
 511     back_oe(y_cmd, '0');
 512     abs_xy_n <= '0';
 513 end  procedure;
 514
 515 --A.2. internal execution on memory data
 516
 517 procedure a2_zp is
 518 begin
 519     if exec_cycle = T1 then
 520         fetch_low;
 521     elsif exec_cycle = T2 then
 522         fetch_stop;
 523         dbuf_int_oe_n <= '0';
 524
 525         --calc zp.
 526         back_oe(idl_l_cmd, '0');
 527         zp_n <= '0';
 528         next_cycle <= T0;
 529     end if;
 530 end  procedure;
 531
 532 procedure a2_abs is
 533 begin
 534     if exec_cycle = T1 then
 535         fetch_low;
 536     elsif exec_cycle = T2 then
 537         abs_fetch_high;
 538     elsif exec_cycle = T3 then
 539         abs_latch_out;
 540         dbuf_int_oe_n <= '0';
 541         next_cycle <= T0;
 542     end if;
 543 end  procedure;
 544
 545 procedure a2_abs_xy (is_x : in boolean) is
 546 begin
 547     if exec_cycle = T1 then
 548         fetch_low;
 549     elsif exec_cycle = T2 then
 550         abs_fetch_high;
 551     elsif exec_cycle = T3 then
 552         --ea calc & lda
 553         pg_next_n <= '1';
 554         abs_latch_out;
 555         if (is_x = true) then
 556             ea_x_out;
 557         else
 558             ea_y_out;
 559         end if;
 560         dbuf_int_oe_n <= '0';
 561
 562         next_cycle <= T0;
 563         d_print("absx step 1");
 564     elsif (exec_cycle = T0 and ea_carry_reg = '1') then
 565         --case page boundary crossed.
 566         --redo inst.
 567         d_print("absx 5 (page boudary crossed.)");
 568         --next page.
 569         pg_next_n <= '0';
 570         next_cycle <= T0;
 571     end if;
 572 end  procedure;
 573
 574 procedure a2_zp_xy (is_x : in boolean) is
 575 begin
 576     if exec_cycle = T1 then
 577         fetch_low;
 578     elsif exec_cycle = T2 then
 579         fetch_stop;
 580         --output BAL only
 581         dbuf_int_oe_n <= '0';
 582
 583         --calc zp.
 584         back_oe(idl_l_cmd, '0');
 585         zp_n <= '0';
 586         next_cycle <= T3;
 587     elsif exec_cycle = T3 then
 588         --t3 zp, xy
 589         zp_xy_n <= '0';
 590         if (is_x = true) then
 591             back_oe(x_cmd, '0');
 592         else
 593             back_oe(y_cmd, '0');
 594         end if;
 595         next_cycle <= T0;
 596     end if;
 597 end  procedure;
 598
 599 procedure a2_indir_y is
 600 begin
 601     if exec_cycle = T1 then
 602         fetch_low;
 603         --get IAL
 604
 605     elsif exec_cycle = T2 then
 606         fetch_stop;
 607
 608         ---address is 00:IAL
 609         --output BAL @IAL
 610         indir_y_n <= '0';
 611         addr_cycle <= ADDR_T2;
 612         back_oe(idl_l_cmd, '0');
 613         dbuf_int_oe_n <= '0';
 614         next_cycle <= T3;
 615
 616     elsif exec_cycle = T3 then
 617         indir_y_n <= '0';
 618         addr_cycle <= ADDR_T3;
 619         back_oe(idl_l_cmd, '0');
 620         --output BAH @IAL+1
 621         dbuf_int_oe_n <= '0';
 622         next_cycle <= T4;
 623
 624     elsif exec_cycle = T4 then
 625         back_oe(idl_l_cmd, '1');
 626         dbuf_int_oe_n <= '1';
 627
 628         --add index y.
 629         pg_next_n <= '1';
 630         back_oe(y_cmd, '0');
 631         indir_y_n <= '0';
 632         addr_cycle <= ADDR_T4;
 633         dbuf_int_oe_n <= '0';
 634
 635         next_cycle <= T0;
 636     elsif (exec_cycle = T0) then
 637         --case page boundary crossed.
 638         --redo inst.
 639         d_print("(indir), y (page boudary crossed.)");
 640         --next page.
 641         indir_y_n <= '0';
 642         pg_next_n <= '0';
 643         addr_cycle <= ADDR_T5;
 644         next_cycle <= T0;
 645     end if;
 646 end  procedure;
 647
 648 procedure a2_indir_x is
 649 begin
 650     if exec_cycle = T1 then
 651         fetch_low;
 652         --get IAL
 653
 654     elsif exec_cycle = T2 then
 655         fetch_stop;
 656
 657         ---address is 00:IAL
 658         --output BAL @IAL, but cycle #2 is discarded
 659         indir_x_n <= '0';
 660         addr_cycle <= ADDR_T2;
 661         back_oe(idl_l_cmd, '0');
 662         next_cycle <= T3;
 663
 664     elsif exec_cycle = T3 then
 665         indir_x_n <= '0';
 666         addr_cycle <= ADDR_T3;
 667         back_oe(idl_l_cmd, '1');
 668
 669         --output BAH @IAL+x
 670         dbuf_int_oe_n <= '0';
 671         back_oe(x_cmd, '0');
 672         next_cycle <= T4;
 673
 674     elsif exec_cycle = T4 then
 675         indir_x_n <= '0';
 676         addr_cycle <= ADDR_T4;
 677
 678         --output BAH @IAL+x+1
 679         dbuf_int_oe_n <= '0';
 680         back_oe(x_cmd, '0');
 681
 682         next_cycle <= T5;
 683     elsif (exec_cycle = T5) then
 684         indir_x_n <= '0';
 685         addr_cycle <= ADDR_T5;
 686         next_cycle <= T0;
 687     end if;
 688 end  procedure;
 689
 690 --A.3. store operation.
 691
 692 procedure a3_zp is
 693 begin
 694     if exec_cycle = T1 then
 695         fetch_low;
 696     elsif exec_cycle = T2 then
 697         fetch_stop;
 698         dbuf_int_oe_n <= '1';
 699
 700         --calc zp.
 701         back_oe(idl_l_cmd, '0');
 702         zp_n <= '0';
 703         r_nw <= '0';
 704         next_cycle <= T0;
 705     end if;
 706 end  procedure;
 707
 708 procedure a3_zp_xy (is_x : in boolean) is
 709 begin
 710     if exec_cycle = T1 then
 711         fetch_low;
 712     elsif exec_cycle = T2 then
 713         fetch_stop;
 714         dbuf_int_oe_n <= '1';
 715
 716         --calc zp.
 717         back_oe(idl_l_cmd, '0');
 718         zp_n <= '0';
 719         next_cycle <= T3;
 720     elsif exec_cycle = T3 then
 721         --calc zp + index.
 722         back_oe(idl_l_cmd, '0');
 723         zp_n <= '0';
 724         zp_xy_n <= '0';
 725         if (is_x = true) then
 726             back_oe(x_cmd, '0');
 727         else
 728             back_oe(y_cmd, '0');
 729         end if;
 730
 731         --write data
 732         r_nw <= '0';
 733         next_cycle <= T0;
 734     end if;
 735 end  procedure;
 736
 737 procedure a3_abs is
 738 begin
 739     if exec_cycle = T1 then
 740         fetch_low;
 741     elsif exec_cycle = T2 then
 742         abs_fetch_high;
 743     elsif exec_cycle = T3 then
 744         abs_latch_out;
 745         dbuf_int_oe_n <= '1';
 746         r_nw <= '0';
 747         next_cycle <= T0;
 748     end if;
 749 end  procedure;
 750
 751 procedure a3_abs_xy (is_x : in boolean) is
 752 begin
 753     if exec_cycle = T1 then
 754         fetch_low;
 755     elsif exec_cycle = T2 then
 756         abs_fetch_high;
 757     elsif exec_cycle = T3 then
 758         --ea calc & lda
 759         pg_next_n <= '1';
 760         abs_latch_out;
 761         dbuf_int_oe_n <= '1';
 762         if (is_x = true) then
 763             ea_x_out;
 764         else
 765             ea_y_out;
 766         end if;
 767         next_cycle <= T4;
 768     elsif exec_cycle = T4 then
 769         if (ea_carry_reg = '1') then
 770             pg_next_n <= '0';
 771         else
 772             pg_next_n <= '1';
 773         end if;
 774         abs_latch_out;
 775         if (is_x = true) then
 776             ea_x_out;
 777         else
 778             ea_y_out;
 779         end if;
 780         r_nw <= '0';
 781         next_cycle <= T0;
 782     end if;
 783 end  procedure;
 784
 785
 786 procedure a3_indir_y is
 787 begin
 788     if exec_cycle = T1 then
 789         fetch_low;
 790         --get IAL
 791
 792     elsif exec_cycle = T2 then
 793         fetch_stop;
 794
 795         ---address is 00:IAL
 796         --output BAL @IAL
 797         indir_y_n <= '0';
 798         addr_cycle <= ADDR_T2;
 799         back_oe(idl_l_cmd, '0');
 800         dbuf_int_oe_n <= '0';
 801         next_cycle <= T3;
 802
 803     elsif exec_cycle = T3 then
 804         indir_y_n <= '0';
 805         addr_cycle <= ADDR_T3;
 806         back_oe(idl_l_cmd, '0');
 807         --output BAH @IAL+1
 808         dbuf_int_oe_n <= '0';
 809         next_cycle <= T4;
 810
 811     elsif exec_cycle = T4 then
 812         back_oe(idl_l_cmd, '1');
 813         dbuf_int_oe_n <= '1';
 814
 815         --add index y.
 816         pg_next_n <= '1';
 817         back_oe(y_cmd, '0');
 818         indir_y_n <= '0';
 819         addr_cycle <= ADDR_T4;
 820         next_cycle <= T5;
 821
 822     elsif exec_cycle = T5 then
 823         --page handling.
 824         back_oe(y_cmd, '1');
 825         indir_y_n <= '0';
 826         addr_cycle <= ADDR_T5;
 827
 828         if (ea_carry_reg = '1') then
 829             pg_next_n <= '0';
 830         else
 831             pg_next_n <= '1';
 832         end if;
 833         r_nw <= '0';
 834         next_cycle <= T0;
 835     end if;
 836 end  procedure;
 837
 838 procedure a3_indir_x is
 839 begin
 840     if exec_cycle = T1 then
 841         fetch_low;
 842         --get IAL
 843
 844     elsif exec_cycle = T2 then
 845         fetch_stop;
 846
 847         ---address is 00:IAL
 848         --output BAL @IAL, but cycle #2 is discarded
 849         indir_x_n <= '0';
 850         addr_cycle <= ADDR_T2;
 851         back_oe(idl_l_cmd, '0');
 852         next_cycle <= T3;
 853
 854     elsif exec_cycle = T3 then
 855         indir_x_n <= '0';
 856         addr_cycle <= ADDR_T3;
 857         back_oe(idl_l_cmd, '1');
 858
 859         --output BAH @IAL+x
 860         dbuf_int_oe_n <= '0';
 861         back_oe(x_cmd, '0');
 862         next_cycle <= T4;
 863
 864     elsif exec_cycle = T4 then
 865         indir_x_n <= '0';
 866         addr_cycle <= ADDR_T4;
 867
 868         --output BAH @IAL+x+1
 869         dbuf_int_oe_n <= '0';
 870         back_oe(x_cmd, '0');
 871
 872         next_cycle <= T5;
 873     elsif (exec_cycle = T5) then
 874         indir_x_n <= '0';
 875         addr_cycle <= ADDR_T5;
 876         dbuf_int_oe_n <= '1';
 877         r_nw <= '0';
 878         next_cycle <= T0;
 879     end if;
 880 end  procedure;
 881
 882 ---A.4. read-modify-write operation
 883
 884 procedure a4_zp is
 885 begin
 886     if exec_cycle = T1 then
 887         fetch_low;
 888     elsif exec_cycle = T2 then
 889         fetch_stop;
 890
 891         --t2 cycle read and,
 892         back_oe(idl_l_cmd, '0');
 893         zp_n <= '0';
 894         --keep data in the alu reg.
 895         arith_en_n <= '0';
 896         alu_cycle <= MEM_T1;
 897         dbuf_int_oe_n <= '0';
 898         next_cycle <= T3;
 899     elsif exec_cycle = T3 then
 900         --t3 fix alu internal register.
 901         back_oe(idl_l_cmd, '0');
 902         zp_n <= '0';
 903         arith_en_n <= '0';
 904         alu_cycle <= MEM_T2;
 905         dbuf_int_oe_n <= '1';
 906         next_cycle <= T4;
 907     elsif exec_cycle = T4 then
 908         --t5 cycle writes modified value.
 909         back_oe(idl_l_cmd, '0');
 910         zp_n <= '0';
 911         r_nw <= '0';
 912         arith_en_n <= '0';
 913         alu_cycle <= MEM_T3;
 914         next_cycle <= T0;
 915     end if;
 916 end  procedure;
 917
 918 procedure a4_zp_x is
 919 begin
 920     if exec_cycle = T1 then
 921         fetch_low;
 922     elsif exec_cycle = T2 then
 923         fetch_stop;
 924         dbuf_int_oe_n <= '1';
 925
 926         --t2 cycle read bal only.
 927         back_oe(idl_l_cmd, '0');
 928         zp_n <= '0';
 929         next_cycle <= T3;
 930     elsif exec_cycle = T3 then
 931         --t3 cycle read bal + x
 932         back_oe(idl_l_cmd, '0');
 933         zp_n <= '0';
 934         zp_xy_n <= '0';
 935         back_oe(x_cmd, '0');
 936
 937         --keep data in the alu reg.
 938         arith_en_n <= '0';
 939         alu_cycle <= MEM_T1;
 940         dbuf_int_oe_n <= '0';
 941
 942         next_cycle <= T4;
 943     elsif exec_cycle = T4 then
 944         back_oe(idl_l_cmd, '0');
 945         zp_n <= '0';
 946         zp_xy_n <= '0';
 947         back_oe(x_cmd, '0');
 948
 949         --fix alu internal register.
 950         arith_en_n <= '0';
 951         alu_cycle <= MEM_T2;
 952         dbuf_int_oe_n <= '1';
 953         next_cycle <= T5;
 954     elsif exec_cycle = T5 then
 955         dbuf_int_oe_n <= '1';
 956
 957         --t5 cycle writes modified value.
 958         back_oe(idl_l_cmd, '0');
 959         zp_n <= '0';
 960         zp_xy_n <= '0';
 961         back_oe(x_cmd, '0');
 962         r_nw <= '0';
 963         arith_en_n <= '0';
 964         alu_cycle <= MEM_T3;
 965         next_cycle <= T0;
 966     end if;
 967 end  procedure;
 968
 969
 970 procedure a4_abs is
 971 begin
 972     if exec_cycle = T1 then
 973         fetch_low;
 974     elsif exec_cycle = T2 then
 975         abs_fetch_high;
 976     elsif exec_cycle = T3 then
 977         abs_latch_out;
 978
 979         --keep data in the alu reg.
 980         arith_en_n <= '0';
 981         alu_cycle <= MEM_T1;
 982         dbuf_int_oe_n <= '0';
 983         next_cycle <= T4;
 984     elsif exec_cycle = T4 then
 985         abs_latch_out;
 986
 987         --fix alu internal register.
 988         arith_en_n <= '0';
 989         alu_cycle <= MEM_T2;
 990         dbuf_int_oe_n <= '1';
 991         next_cycle <= T5;
 992     elsif exec_cycle = T5 then
 993         dbuf_int_oe_n <= '1';
 994
 995         --t5 cycle writes modified value.
 996         r_nw <= '0';
 997         arith_en_n <= '0';
 998         alu_cycle <= MEM_T3;
 999         next_cycle <= T0;
1000     end if;
1001 end  procedure;
1002
1003 procedure a4_abs_x is
1004 begin
1005     if exec_cycle = T1 then
1006         fetch_low;
1007     elsif exec_cycle = T2 then
1008         abs_fetch_high;
1009     elsif exec_cycle = T3 then
1010         --T3 cycle discarded.
1011         pg_next_n <= '1';
1012         abs_latch_out;
1013         ea_x_out;
1014         dbuf_int_oe_n <= '0';
1015         next_cycle <= T4;
1016
1017     elsif exec_cycle = T4 then
1018         abs_latch_out;
1019         ea_x_out;
1020         if (ea_carry_reg = '1') then
1021             pg_next_n <= '0';
1022         else
1023             pg_next_n <= '1';
1024         end if;
1025
1026         --keep data in the alu reg.
1027         arith_en_n <= '0';
1028         alu_cycle <= MEM_T1;
1029         dbuf_int_oe_n <= '0';
1030         next_cycle <= T5;
1031
1032     elsif exec_cycle = T5 then
1033         --fix alu internal register.
1034         arith_en_n <= '0';
1035         alu_cycle <= MEM_T2;
1036         dbuf_int_oe_n <= '1';
1037         next_cycle <= T6;
1038
1039     elsif exec_cycle = T6 then
1040         --t5 cycle writes modified value.
1041         r_nw <= '0';
1042         arith_en_n <= '0';
1043         alu_cycle <= MEM_T3;
1044         next_cycle <= T0;
1045
1046     end if;
1047 end  procedure;
1048
1049
1050 -- A.5.1 push stack
1051 procedure a51_push is
1052 begin
1053     if exec_cycle = T1 then
1054         fetch_stop;
1055         next_cycle <= T2;
1056     elsif exec_cycle = T2 then
1057         back_oe(sp_cmd, '0');
1058         back_we(sp_cmd, '0');
1059         sp_push_n <= '0';
1060         sp_oe_n <= '0';
1061         r_nw <= '0';
1062         next_cycle <= T0;
1063     end if;
1064 end procedure;
1065
1066 -- A.5.2 pull stack
1067 procedure a52_pull is
1068 begin
1069     if exec_cycle = T1 then
1070         fetch_stop;
1071         next_cycle <= T2;
1072
1073     elsif exec_cycle = T2 then
1074         --stack decrement first.
1075         back_oe(sp_cmd, '0');
1076         back_we(sp_cmd, '0');
1077         sp_pop_n <= '0';
1078         sp_oe_n <= '0';
1079         next_cycle <= T3;
1080
1081     elsif exec_cycle = T3 then
1082         sp_pop_n <= '1';
1083         back_we(sp_cmd, '1');
1084
1085         ---pop data from stack.
1086         back_oe(sp_cmd, '0');
1087         sp_oe_n <= '0';
1088         dbuf_int_oe_n <= '0';
1089         next_cycle <= T0;
1090     end if;
1091 end procedure;
1092
1093
1094 -- A.5.8 branch operations
1095
1096 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
1097 begin
1098     if exec_cycle = T1 then
1099         fetch_next;
1100         if status_reg(int_flg) = br_cond then
1101             d_print("get rel");
1102
1103             --latch rel value.
1104             dbuf_int_oe_n <= '0';
1105             front_we(idl_h_cmd, '0');
1106             next_cycle <= T2;
1107         else
1108             d_print("no branch");
1109             next_cycle <= T0;
1110         end if;
1111     elsif exec_cycle = T2 then
1112         d_print("rel ea");
1113         fetch_stop;
1114         dbuf_int_oe_n <= '1';
1115         front_we(idl_h_cmd, '1');
1116
1117         --calc relative addr.
1118         rel_calc_n <= '0';
1119         pg_next_n <= '1';
1120         front_oe(idl_h_cmd, '0');
1121         back_oe(pcl_cmd, '0');
1122         back_oe(pch_cmd, '0');
1123         back_we(pcl_cmd, '0');
1124
1125         next_cycle <= T0;
1126     elsif (exec_cycle = T0 and ea_carry = '1') then
1127         d_print("page crossed.");
1128         --page crossed. adh calc.
1129         back_we(pcl_cmd, '1');
1130         back_oe(pcl_cmd, '0');
1131         back_oe(pch_cmd, '0');
1132         back_we(pch_cmd, '0');
1133         front_oe(idl_h_cmd, '0');
1134
1135         rel_calc_n <= '0';
1136         pg_next_n <= '0';
1137         next_cycle <= T0;
1138     end if;
1139 end  procedure;
1140
1141 -------------------------------------------------------------
1142 -------------------------------------------------------------
1143 ---------------- main state machine start.... ---------------
1144 -------------------------------------------------------------
1145 -------------------------------------------------------------
1146     begin
1147
1148         if (res_n = '0') then
1149             --prevent status revister from broken.
1150             stat_dec_oe_n <= '0';
1151             stat_bus_oe_n <= '1';
1152             stat_set_flg_n <= '1';
1153             stat_flg <= '1';
1154             stat_bus_all_n <= '1';
1155             stat_bus_nz_n <= '1';
1156             stat_alu_we_n <= '1';
1157
1158             --pc l/h is reset vector.
1159             pcl_cmd <= "1110";
1160             pch_cmd <= "1110";
1161             next_cycle <= R0;
1162
1163         elsif (rising_edge(cpu_clk)) then
1164             d_print(string'("-"));
1165
1166             if (nmi_n = '1') then
1167                 --nmi handle flag reset.
1168                 nmi_handled_n <= '1';
1169             end if;
1170
1171             if rdy = '0' then
1172                 --case dma is runnting.
1173                 disable_pins;
1174                 inst_we_n <= '1';
1175                 ad_oe_n <= '1';
1176                 back_oe(idl_l_cmd, '1');
1177                 pcl_inc_n <= '1';
1178                 pcl_cmd <= "1111";
1179                 pch_cmd <= "1111";
1180                 r_nw <= 'Z';
1181
1182             elsif (exec_cycle = T0 and ea_carry = '0') then
1183                 --cycle #1
1184                 t0_cycle;
1185
1186             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or
1187                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or
1188                 (exec_cycle = T0 and ea_carry = '1') then
1189                 --execute inst.
1190
1191                 ---asyncronous page change might happen.
1192                 back_we(pch_cmd, '1');
1193
1194                 if exec_cycle = T1 then
1195                     d_print("decode and execute inst: "
1196                             & conv_hex8(conv_integer(instruction)));
1197                     --disable pin for jmp instruction
1198                     back_oe(idl_l_cmd, '1');
1199                     back_we(pcl_cmd, '1');
1200                     front_we(pch_cmd, '1');
1201
1202                     --grab instruction register data.
1203                     inst_we_n <= '1';
1204                 end if;
1205
1206                 --imelementation is wriiten in the order of hardware manual
1207                 --appendix A.
1208
1209                 ----------------------------------------
1210                 --A.1. Single byte instruction.
1211                 ----------------------------------------
1212                 if instruction = conv_std_logic_vector(16#0a#, dsize) then
1213                     --asl acc mode.
1214                     d_print("asl");
1215                     arith_en_n <= '0';
1216                     back_oe(acc_cmd, '0');
1217                     front_we(acc_cmd, '0');
1218                     set_nzc_from_alu;
1219                     single_inst;
1220
1221                 elsif instruction = conv_std_logic_vector(16#18#, dsize) then
1222                     d_print("clc");
1223                     set_flag0 ('0');
1224                     single_inst;
1225
1226                 elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
1227                     d_print("cld");
1228                     set_flag (st_D, '0');
1229                     single_inst;
1230
1231                 elsif instruction = conv_std_logic_vector(16#58#, dsize) then
1232                     d_print("cli");
1233                     set_flag (st_I, '0');
1234                     single_inst;
1235
1236                 elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
1237                     d_print("clv");
1238                     set_flag (st_V, '0');
1239                     single_inst;
1240
1241                 elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
1242                     d_print("dex");
1243                     arith_en_n <= '0';
1244                     back_oe(x_cmd, '0');
1245                     front_we(x_cmd, '0');
1246                     --set nz bit.
1247                     set_nz_from_bus;
1248                     single_inst;
1249
1250                 elsif instruction = conv_std_logic_vector(16#88#, dsize) then
1251                     d_print("dey");
1252                     arith_en_n <= '0';
1253                     back_oe(y_cmd, '0');
1254                     front_we(y_cmd, '0');
1255                     --set nz bit.
1256                     set_nz_from_bus;
1257                     single_inst;
1258
1259                 elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
1260                     d_print("inx");
1261                     arith_en_n <= '0';
1262                     back_oe(x_cmd, '0');
1263                     front_we(x_cmd, '0');
1264                     --set nz bit.
1265                     set_nz_from_bus;
1266                     single_inst;
1267
1268                 elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
1269                     d_print("iny");
1270                     arith_en_n <= '0';
1271                     back_oe(y_cmd, '0');
1272                     front_we(y_cmd, '0');
1273                     set_nz_from_bus;
1274                     single_inst;
1275
1276                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
1277                     --lsr acc mode
1278                     d_print("lsr");
1279                     arith_en_n <= '0';
1280                     back_oe(acc_cmd, '0');
1281                     front_we(acc_cmd, '0');
1282                     set_zc_from_alu;
1283                     single_inst;
1284
1285                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
1286                     d_print("nop");
1287                     single_inst;
1288
1289                 elsif instruction = conv_std_logic_vector(16#2a#, dsize) then
1290                     --rol acc
1291                     d_print("rol");
1292                     arith_en_n <= '0';
1293                     back_oe(acc_cmd, '0');
1294                     front_we(acc_cmd, '0');
1295                     set_nzc_from_alu;
1296                     single_inst;
1297
1298                 elsif instruction = conv_std_logic_vector(16#6a#, dsize) then
1299                     --ror acc
1300                     d_print("ror");
1301                     arith_en_n <= '0';
1302                     back_oe(acc_cmd, '0');
1303                     front_we(acc_cmd, '0');
1304                     set_nzc_from_alu;
1305                     single_inst;
1306
1307                 elsif instruction = conv_std_logic_vector(16#38#, dsize) then
1308                     d_print("sec");
1309                     set_flag0 ('1');
1310                     single_inst;
1311
1312                 elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
1313                     d_print("sed");
1314                     set_flag (st_D, '1');
1315                     single_inst;
1316
1317                 elsif instruction = conv_std_logic_vector(16#78#, dsize) then
1318                     d_print("sei");
1319                     set_flag (st_I, '1');
1320                     single_inst;
1321
1322                 elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
1323                     d_print("tax");
1324                     set_nz_from_bus;
1325                     single_inst;
1326                     front_oe(acc_cmd, '0');
1327                     front_we(x_cmd, '0');
1328
1329                 elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
1330                     d_print("tay");
1331                     set_nz_from_bus;
1332                     single_inst;
1333                     front_oe(acc_cmd, '0');
1334                     front_we(y_cmd, '0');
1335
1336                 elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
1337                     d_print("tsx");
1338                     set_nz_from_bus;
1339                     single_inst;
1340                     front_oe(sp_cmd, '0');
1341                     front_we(x_cmd, '0');
1342
1343                 elsif instruction = conv_std_logic_vector(16#8a#, dsize) then
1344                     d_print("txa");
1345                     set_nz_from_bus;
1346                     single_inst;
1347                     front_oe(x_cmd, '0');
1348                     front_we(acc_cmd, '0');
1349
1350                 elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
1351                     d_print("txs");
1352                     set_nz_from_bus;
1353                     single_inst;
1354                     front_oe(x_cmd, '0');
1355                     front_we(sp_cmd, '0');
1356
1357                 elsif instruction = conv_std_logic_vector(16#98#, dsize) then
1358                     d_print("tya");
1359                     set_nz_from_bus;
1360                     single_inst;
1361                     front_oe(y_cmd, '0');
1362                     front_we(acc_cmd, '0');
1363
1364
1365
1366                 ----------------------------------------
1367                 --A.2. internal execution on memory data
1368                 ----------------------------------------
1369                 elsif instruction  = conv_std_logic_vector(16#69#, dsize) then
1370                     --imm
1371                     d_print("adc");
1372                     fetch_imm;
1373                     arith_en_n <= '0';
1374                     back_oe(acc_cmd, '0');
1375                     back_we(acc_cmd, '0');
1376                     set_nvzc_from_alu;
1377
1378                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
1379                     --zp
1380                     d_print("adc");
1381                     a2_zp;
1382                     if exec_cycle = T2 then
1383                         arith_en_n <= '0';
1384                         back_oe(acc_cmd, '0');
1385                         back_we(acc_cmd, '0');
1386                         set_nvzc_from_alu;
1387                     end if;
1388
1389                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
1390                     --zp, x
1391                     d_print("adc");
1392                     a2_zp_xy(true);
1393                     if exec_cycle = T3 then
1394                         arith_en_n <= '0';
1395                         back_oe(acc_cmd, '0');
1396                         back_we(acc_cmd, '0');
1397                         set_nvzc_from_alu;
1398                     end if;
1399
1400                 elsif instruction  = conv_std_logic_vector(16#6d#, dsize) then
1401                     --abs
1402                     d_print("adc");
1403                     a2_abs;
1404                     if exec_cycle = T3 then
1405                         arith_en_n <= '0';
1406                         back_oe(acc_cmd, '0');
1407                         back_we(acc_cmd, '0');
1408                         set_nvzc_from_alu;
1409                     end if;
1410
1411                 elsif instruction  = conv_std_logic_vector(16#7d#, dsize) then
1412                     --abs, x
1413                     d_print("adc");
1414                     a2_abs_xy(true);
1415                     if exec_cycle = T3 or exec_cycle = T0 then
1416                         arith_en_n <= '0';
1417                         back_oe(acc_cmd, '0');
1418                         back_we(acc_cmd, '0');
1419                         set_nvzc_from_alu;
1420                     end if;
1421
1422                 elsif instruction  = conv_std_logic_vector(16#79#, dsize) then
1423                     --abs, y
1424                     d_print("adc");
1425                     a2_abs_xy(false);
1426                     if exec_cycle = T3 or exec_cycle = T0 then
1427                         arith_en_n <= '0';
1428                         back_oe(acc_cmd, '0');
1429                         back_we(acc_cmd, '0');
1430                         set_nvzc_from_alu;
1431                     end if;
1432
1433                 elsif instruction  = conv_std_logic_vector(16#61#, dsize) then
1434                     --(indir, x)
1435                     d_print("adc");
1436                     a2_indir_x;
1437                     if exec_cycle = T5 then
1438                         arith_en_n <= '0';
1439                         back_oe(acc_cmd, '0');
1440                         back_we(acc_cmd, '0');
1441                         set_nvzc_from_alu;
1442                     end if;
1443
1444                 elsif instruction  = conv_std_logic_vector(16#71#, dsize) then
1445                     --(indir), y
1446                     d_print("adc");
1447                     a2_indir_y;
1448                     if exec_cycle = T4 or exec_cycle = T0 then
1449                         arith_en_n <= '0';
1450                         back_oe(acc_cmd, '0');
1451                         back_we(acc_cmd, '0');
1452                         set_nvzc_from_alu;
1453                     end if;
1454
1455                 elsif instruction  = conv_std_logic_vector(16#29#, dsize) then
1456                     --imm
1457                     d_print("and");
1458                     fetch_imm;
1459                     arith_en_n <= '0';
1460                     back_oe(acc_cmd, '0');
1461                     back_we(acc_cmd, '0');
1462                     set_nz_from_alu;
1463
1464                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
1465                     --zp
1466                     d_print("and");
1467                     a2_zp;
1468                     if exec_cycle = T2 then
1469                         arith_en_n <= '0';
1470                         back_oe(acc_cmd, '0');
1471                         back_we(acc_cmd, '0');
1472                         set_nz_from_alu;
1473                     end if;
1474
1475                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
1476                     --zp, x
1477                     d_print("and");
1478                     a2_zp_xy(true);
1479                     if exec_cycle = T3 then
1480                         arith_en_n <= '0';
1481                         back_oe(acc_cmd, '0');
1482                         back_we(acc_cmd, '0');
1483                         set_nz_from_alu;
1484                     end if;
1485
1486                 elsif instruction  = conv_std_logic_vector(16#2d#, dsize) then
1487                     --abs
1488                     d_print("and");
1489                     a2_abs;
1490                     if exec_cycle = T3 then
1491                         arith_en_n <= '0';
1492                         back_oe(acc_cmd, '0');
1493                         back_we(acc_cmd, '0');
1494                         set_nz_from_alu;
1495                     end if;
1496
1497                 elsif instruction  = conv_std_logic_vector(16#3d#, dsize) then
1498                     --abs, x
1499                     d_print("and");
1500                     a2_abs_xy(true);
1501                     if exec_cycle = T3 or exec_cycle = T0 then
1502                         arith_en_n <= '0';
1503                         back_oe(acc_cmd, '0');
1504                         back_we(acc_cmd, '0');
1505                         set_nz_from_alu;
1506                     end if;
1507
1508                 elsif instruction  = conv_std_logic_vector(16#39#, dsize) then
1509                     --abs, y
1510                     d_print("and");
1511                     a2_abs_xy(false);
1512                     if exec_cycle = T3 or exec_cycle = T0 then
1513                         arith_en_n <= '0';
1514                         back_oe(acc_cmd, '0');
1515                         back_we(acc_cmd, '0');
1516                         set_nz_from_alu;
1517                     end if;
1518
1519                 elsif instruction  = conv_std_logic_vector(16#21#, dsize) then
1520                     --(indir, x)
1521                     d_print("and");
1522                     a2_indir_x;
1523                     if exec_cycle = T5 then
1524                         arith_en_n <= '0';
1525                         back_oe(acc_cmd, '0');
1526                         back_we(acc_cmd, '0');
1527                         set_nz_from_alu;
1528                     end if;
1529
1530                 elsif instruction  = conv_std_logic_vector(16#31#, dsize) then
1531                     --(indir), y
1532                     d_print("and");
1533                     a2_indir_y;
1534                     if exec_cycle = T4 or exec_cycle = T0 then
1535                         arith_en_n <= '0';
1536                         back_oe(acc_cmd, '0');
1537                         back_we(acc_cmd, '0');
1538                         set_nz_from_alu;
1539                     end if;
1540
1541                 elsif instruction  = conv_std_logic_vector(16#24#, dsize) then
1542                     --zp
1543                     d_print("bit");
1544                     a2_zp;
1545                     if exec_cycle = T2 then
1546                         arith_en_n <= '0';
1547                         back_oe(acc_cmd, '0');
1548                         set_nvz_from_alu;
1549                     end if;
1550
1551                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
1552                     --abs
1553                     d_print("bit");
1554                     a2_abs;
1555                     if exec_cycle = T3 then
1556                         arith_en_n <= '0';
1557                         back_oe(acc_cmd, '0');
1558                         set_nvz_from_alu;
1559                     end if;
1560
1561                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
1562                     --imm
1563                     d_print("cmp");
1564                     fetch_imm;
1565                     arith_en_n <= '0';
1566                     back_oe(acc_cmd, '0');
1567                     set_nzc_from_alu;
1568
1569                 elsif instruction  = conv_std_logic_vector(16#c5#, dsize) then
1570                     --zp
1571                     d_print("cmp");
1572                     a2_zp;
1573                     if exec_cycle = T2 then
1574                         arith_en_n <= '0';
1575                         back_oe(acc_cmd, '0');
1576                         set_nzc_from_alu;
1577                     end if;
1578
1579                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
1580                     --zp, x
1581                     d_print("cmp");
1582                     a2_zp_xy(true);
1583                     if exec_cycle = T3 then
1584                         arith_en_n <= '0';
1585                         back_oe(acc_cmd, '0');
1586                         set_nzc_from_alu;
1587                     end if;
1588
1589                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
1590                     --abs
1591                     d_print("cmp");
1592                     a2_abs;
1593                     if exec_cycle = T3 then
1594                         arith_en_n <= '0';
1595                         back_oe(acc_cmd, '0');
1596                         set_nzc_from_alu;
1597                     end if;
1598
1599                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
1600                     --abs, x
1601                     d_print("cmp");
1602                     a2_abs_xy(true);
1603                     if exec_cycle = T3 or exec_cycle = T0 then
1604                         arith_en_n <= '0';
1605                         back_oe(acc_cmd, '0');
1606                         set_nzc_from_alu;
1607                     end if;
1608
1609                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
1610                     --abs, y
1611                     d_print("cmp");
1612                     a2_abs_xy(false);
1613                     if exec_cycle = T3 or exec_cycle = T0 then
1614                         arith_en_n <= '0';
1615                         back_oe(acc_cmd, '0');
1616                         set_nzc_from_alu;
1617                     end if;
1618
1619                 elsif instruction  = conv_std_logic_vector(16#c1#, dsize) then
1620                     --(indir, x)
1621                     d_print("cmp");
1622                     a2_indir_x;
1623                     if exec_cycle = T5 then
1624                         arith_en_n <= '0';
1625                         back_oe(acc_cmd, '0');
1626                         set_nzc_from_alu;
1627                     end if;
1628
1629                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
1630                     --(indir), y
1631                     d_print("cmp");
1632                     a2_indir_y;
1633                     if exec_cycle = T4 or exec_cycle = T0 then
1634                         arith_en_n <= '0';
1635                         back_oe(acc_cmd, '0');
1636                         set_nzc_from_alu;
1637                     end if;
1638
1639                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
1640                     --imm
1641                     d_print("cpx");
1642                     fetch_imm;
1643                     arith_en_n <= '0';
1644                     back_oe(x_cmd, '0');
1645                     set_nzc_from_alu;
1646
1647                 elsif instruction  = conv_std_logic_vector(16#e4#, dsize) then
1648                     --zp
1649                     d_print("cpx");
1650                     a2_zp;
1651                     if exec_cycle = T2 then
1652                         arith_en_n <= '0';
1653                         back_oe(x_cmd, '0');
1654                         set_nzc_from_alu;
1655                     end if;
1656
1657                 elsif instruction  = conv_std_logic_vector(16#ec#, dsize) then
1658                     --abs
1659                     d_print("cpx");
1660                     a2_abs;
1661                     if exec_cycle = T3 then
1662                         arith_en_n <= '0';
1663                         back_oe(x_cmd, '0');
1664                         set_nzc_from_alu;
1665                     end if;
1666
1667                 elsif instruction  = conv_std_logic_vector(16#c0#, dsize) then
1668                     --imm
1669                     d_print("cpy");
1670                     fetch_imm;
1671                     arith_en_n <= '0';
1672                     back_oe(y_cmd, '0');
1673                     set_nzc_from_alu;
1674
1675                 elsif instruction  = conv_std_logic_vector(16#c4#, dsize) then
1676                     --zp
1677                     d_print("cpy");
1678                     a2_zp;
1679                     if exec_cycle = T2 then
1680                         arith_en_n <= '0';
1681                         back_oe(y_cmd, '0');
1682                         set_nzc_from_alu;
1683                     end if;
1684
1685                 elsif instruction  = conv_std_logic_vector(16#cc#, dsize) then
1686                     --abs
1687                     d_print("cpy");
1688                     a2_abs;
1689                     if exec_cycle = T3 then
1690                         arith_en_n <= '0';
1691                         back_oe(y_cmd, '0');
1692                         set_nzc_from_alu;
1693                     end if;
1694
1695                 elsif instruction  = conv_std_logic_vector(16#49#, dsize) then
1696                     --imm
1697                     d_print("eor");
1698                     fetch_imm;
1699                     arith_en_n <= '0';
1700                     back_oe(acc_cmd, '0');
1701                     back_we(acc_cmd, '0');
1702                     set_nz_from_alu;
1703
1704                 elsif instruction  = conv_std_logic_vector(16#45#, dsize) then
1705                     --zp
1706                     d_print("eor");
1707                     a2_zp;
1708                     if exec_cycle = T2 then
1709                         arith_en_n <= '0';
1710                         back_oe(acc_cmd, '0');
1711                         back_we(acc_cmd, '0');
1712                         set_nz_from_alu;
1713                     end if;
1714
1715                 elsif instruction  = conv_std_logic_vector(16#55#, dsize) then
1716                     --zp, x
1717                     d_print("eor");
1718                     a2_zp_xy(true);
1719                     if exec_cycle = T3 then
1720                         arith_en_n <= '0';
1721                         back_oe(acc_cmd, '0');
1722                         back_we(acc_cmd, '0');
1723                         set_nz_from_alu;
1724                     end if;
1725
1726                 elsif instruction  = conv_std_logic_vector(16#4d#, dsize) then
1727                     --abs
1728                     d_print("eor");
1729                     a2_abs;
1730                     if exec_cycle = T3 then
1731                         arith_en_n <= '0';
1732                         back_oe(acc_cmd, '0');
1733                         back_we(acc_cmd, '0');
1734                         set_nz_from_alu;
1735                     end if;
1736
1737                 elsif instruction  = conv_std_logic_vector(16#5d#, dsize) then
1738                     --abs, x
1739                     d_print("eor");
1740                     a2_abs_xy(true);
1741                     if exec_cycle = T3 or exec_cycle = T0 then
1742                         arith_en_n <= '0';
1743                         back_oe(acc_cmd, '0');
1744                         back_we(acc_cmd, '0');
1745                         set_nz_from_alu;
1746                     end if;
1747
1748                 elsif instruction  = conv_std_logic_vector(16#59#, dsize) then
1749                     --abs, y
1750                     d_print("eor");
1751                     a2_abs_xy(false);
1752                     if exec_cycle = T3 or exec_cycle = T0 then
1753                         arith_en_n <= '0';
1754                         back_oe(acc_cmd, '0');
1755                         back_we(acc_cmd, '0');
1756                         set_nz_from_alu;
1757                     end if;
1758
1759                 elsif instruction  = conv_std_logic_vector(16#41#, dsize) then
1760                     --(indir, x)
1761                     d_print("eor");
1762                     a2_indir_x;
1763                     if exec_cycle = T5 then
1764                         arith_en_n <= '0';
1765                         back_oe(acc_cmd, '0');
1766                         back_we(acc_cmd, '0');
1767                         set_nz_from_alu;
1768                     end if;
1769
1770                 elsif instruction  = conv_std_logic_vector(16#51#, dsize) then
1771                     --(indir), y
1772                     d_print("eor");
1773                     a2_indir_y;
1774                     if exec_cycle = T4 or exec_cycle = T0 then
1775                         arith_en_n <= '0';
1776                         back_oe(acc_cmd, '0');
1777                         back_we(acc_cmd, '0');
1778                         set_nz_from_alu;
1779                     end if;
1780
1781                 elsif instruction  = conv_std_logic_vector(16#a9#, dsize) then
1782                     --imm
1783                     d_print("lda");
1784                     fetch_imm;
1785                     front_we(acc_cmd, '0');
1786                     set_nz_from_bus;
1787
1788                 elsif instruction  = conv_std_logic_vector(16#a5#, dsize) then
1789                     --zp
1790                     d_print("lda");
1791                     a2_zp;
1792                     if exec_cycle = T2 then
1793                         front_we(acc_cmd, '0');
1794                         set_nz_from_bus;
1795                     end if;
1796
1797                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
1798                     --zp, x
1799                     d_print("lda");
1800                     a2_zp_xy(true);
1801                     if exec_cycle = T3 then
1802                         front_we(acc_cmd, '0');
1803                         set_nz_from_bus;
1804                     end if;
1805
1806                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
1807                     --abs
1808                     d_print("lda");
1809                     a2_abs;
1810                     if exec_cycle = T3 then
1811                         set_nz_from_bus;
1812                         front_we(acc_cmd, '0');
1813                     end if;
1814
1815                 elsif instruction  = conv_std_logic_vector(16#bd#, dsize) then
1816                     --abs, x
1817                     d_print("lda");
1818                     a2_abs_xy(true);
1819                     if exec_cycle = T3 or exec_cycle = T0 then
1820                         --lda.
1821                         front_we(acc_cmd, '0');
1822                         set_nz_from_bus;
1823                     end if;
1824
1825                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
1826                     --abs, y
1827                     d_print("lda");
1828                     a2_abs_xy(false);
1829                     if exec_cycle = T3 or exec_cycle = T0 then
1830                         --lda.
1831                         front_we(acc_cmd, '0');
1832                         set_nz_from_bus;
1833                     end if;
1834
1835                 elsif instruction  = conv_std_logic_vector(16#a1#, dsize) then
1836                     --(indir, x)
1837                     d_print("lda");
1838                     a2_indir_x;
1839                     if exec_cycle = T5 then
1840                         front_we(acc_cmd, '0');
1841                         set_nz_from_bus;
1842                     end if;
1843
1844                 elsif instruction  = conv_std_logic_vector(16#b1#, dsize) then
1845                     --(indir), y
1846                     d_print("lda");
1847                     a2_indir_y;
1848                     if exec_cycle = T4 or exec_cycle = T0 then
1849                         --lda.
1850                         front_we(acc_cmd, '0');
1851                         set_nz_from_bus;
1852                     end if;
1853
1854                 elsif instruction  = conv_std_logic_vector(16#a2#, dsize) then
1855                     --imm
1856                     d_print("ldx");
1857                     fetch_imm;
1858                     set_nz_from_bus;
1859                     front_we(x_cmd, '0');
1860
1861                 elsif instruction  = conv_std_logic_vector(16#a6#, dsize) then
1862                     --zp
1863                     d_print("ldx");
1864                     a2_zp;
1865                     if exec_cycle = T2 then
1866                         front_we(x_cmd, '0');
1867                         set_nz_from_bus;
1868                     end if;
1869
1870                 elsif instruction  = conv_std_logic_vector(16#b6#, dsize) then
1871                     --zp, y
1872                     d_print("ldx");
1873                     a2_zp_xy(false);
1874                     if exec_cycle = T3 then
1875                         front_we(x_cmd, '0');
1876                         set_nz_from_bus;
1877                     end if;
1878
1879                 elsif instruction  = conv_std_logic_vector(16#ae#, dsize) then
1880                     --abs
1881                     d_print("ldx");
1882                     a2_abs;
1883                     if exec_cycle = T3 then
1884                         set_nz_from_bus;
1885                         front_we(x_cmd, '0');
1886                     end if;
1887
1888                 elsif instruction  = conv_std_logic_vector(16#be#, dsize) then
1889                     --abs, y
1890                     d_print("ldx");
1891                     a2_abs_xy(false);
1892                     if exec_cycle = T3 or exec_cycle = T0 then
1893                         front_we(x_cmd, '0');
1894                         set_nz_from_bus;
1895                     end if;
1896
1897                 elsif instruction  = conv_std_logic_vector(16#a0#, dsize) then
1898                     --imm
1899                     d_print("ldy");
1900                     fetch_imm;
1901                     set_nz_from_bus;
1902                     front_we(y_cmd, '0');
1903
1904                 elsif instruction  = conv_std_logic_vector(16#a4#, dsize) then
1905                     --zp
1906                     d_print("ldy");
1907                     a2_zp;
1908                     if exec_cycle = T2 then
1909                         front_we(y_cmd, '0');
1910                         set_nz_from_bus;
1911                     end if;
1912
1913                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
1914                     --zp, x
1915                     d_print("ldy");
1916                     a2_zp_xy(true);
1917                     if exec_cycle = T3 then
1918                         front_we(y_cmd, '0');
1919                         set_nz_from_bus;
1920                     end if;
1921
1922                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
1923                     --abs
1924                     d_print("ldy");
1925                     a2_abs;
1926                     if exec_cycle = T3 then
1927                         set_nz_from_bus;
1928                         front_we(y_cmd, '0');
1929                     end if;
1930
1931                 elsif instruction  = conv_std_logic_vector(16#bc#, dsize) then
1932                     --abs, x
1933                     d_print("ldy");
1934                     a2_abs_xy(true);
1935                     if exec_cycle = T3 or exec_cycle = T0 then
1936                         set_nz_from_bus;
1937                         front_we(y_cmd, '0');
1938                     end if;
1939
1940                 elsif instruction  = conv_std_logic_vector(16#09#, dsize) then
1941                     --imm
1942                     d_print("ora");
1943                     fetch_imm;
1944                     arith_en_n <= '0';
1945                     back_oe(acc_cmd, '0');
1946                     back_we(acc_cmd, '0');
1947                     set_nz_from_alu;
1948
1949                 elsif instruction  = conv_std_logic_vector(16#05#, dsize) then
1950                     --zp
1951                     d_print("ora");
1952                     a2_zp;
1953                     if exec_cycle = T2 then
1954                         arith_en_n <= '0';
1955                         back_oe(acc_cmd, '0');
1956                         back_we(acc_cmd, '0');
1957                         set_nz_from_alu;
1958                     end if;
1959
1960                 elsif instruction  = conv_std_logic_vector(16#15#, dsize) then
1961                     --zp, x
1962                     d_print("ora");
1963                     a2_zp_xy(true);
1964                     if exec_cycle = T3 then
1965                         arith_en_n <= '0';
1966                         back_oe(acc_cmd, '0');
1967                         back_we(acc_cmd, '0');
1968                         set_nz_from_alu;
1969                     end if;
1970
1971                 elsif instruction  = conv_std_logic_vector(16#0d#, dsize) then
1972                     --abs
1973                     d_print("ora");
1974                     a2_abs;
1975                     if exec_cycle = T3 then
1976                         arith_en_n <= '0';
1977                         back_oe(acc_cmd, '0');
1978                         back_we(acc_cmd, '0');
1979                         set_nz_from_alu;
1980                     end if;
1981
1982                 elsif instruction  = conv_std_logic_vector(16#1d#, dsize) then
1983                     --abs, x
1984                     d_print("ora");
1985                     a2_abs_xy(true);
1986                     if exec_cycle = T3 or exec_cycle = T0 then
1987                         arith_en_n <= '0';
1988                         back_oe(acc_cmd, '0');
1989                         back_we(acc_cmd, '0');
1990                         set_nz_from_alu;
1991                     end if;
1992
1993                 elsif instruction  = conv_std_logic_vector(16#19#, dsize) then
1994                     --abs, y
1995                     d_print("ora");
1996                     a2_abs_xy(false);
1997                     if exec_cycle = T3 or exec_cycle = T0 then
1998                         arith_en_n <= '0';
1999                         back_oe(acc_cmd, '0');
2000                         back_we(acc_cmd, '0');
2001                         set_nz_from_alu;
2002                     end if;
2003
2004                 elsif instruction  = conv_std_logic_vector(16#01#, dsize) then
2005                     --(indir, x)
2006                     d_print("ora");
2007                     a2_indir_x;
2008                     if exec_cycle = T5 then
2009                         arith_en_n <= '0';
2010                         back_oe(acc_cmd, '0');
2011                         back_we(acc_cmd, '0');
2012                         set_nz_from_alu;
2013                     end if;
2014
2015                 elsif instruction  = conv_std_logic_vector(16#11#, dsize) then
2016                     --(indir), y
2017                     d_print("ora");
2018                     a2_indir_y;
2019                     if exec_cycle = T4 or exec_cycle = T0 then
2020                         arith_en_n <= '0';
2021                         back_oe(acc_cmd, '0');
2022                         back_we(acc_cmd, '0');
2023                         set_nz_from_alu;
2024                     end if;
2025
2026                 elsif instruction  = conv_std_logic_vector(16#e9#, dsize) then
2027                     --imm
2028                     d_print("sbc");
2029                     fetch_imm;
2030                     arith_en_n <= '0';
2031                     back_oe(acc_cmd, '0');
2032                     back_we(acc_cmd, '0');
2033                     set_nvzc_from_alu;
2034
2035                 elsif instruction  = conv_std_logic_vector(16#e5#, dsize) then
2036                     --zp
2037                     d_print("sbc");
2038                     a2_zp;
2039                     if exec_cycle = T2 then
2040                         arith_en_n <= '0';
2041                         back_oe(acc_cmd, '0');
2042                         back_we(acc_cmd, '0');
2043                         set_nvzc_from_alu;
2044                     end if;
2045
2046                 elsif instruction  = conv_std_logic_vector(16#f5#, dsize) then
2047                     --zp, x
2048                     d_print("sbc");
2049                     a2_zp_xy(true);
2050                     if exec_cycle = T3 then
2051                         arith_en_n <= '0';
2052                         back_oe(acc_cmd, '0');
2053                         back_we(acc_cmd, '0');
2054                         set_nvzc_from_alu;
2055                     end if;
2056
2057                 elsif instruction  = conv_std_logic_vector(16#ed#, dsize) then
2058                     --abs
2059                     d_print("sbc");
2060                     a2_abs;
2061                     if exec_cycle = T3 then
2062                         arith_en_n <= '0';
2063                         back_oe(acc_cmd, '0');
2064                         back_we(acc_cmd, '0');
2065                         set_nvzc_from_alu;
2066                     end if;
2067
2068                 elsif instruction  = conv_std_logic_vector(16#fd#, dsize) then
2069                     --abs, x
2070                     d_print("sbc");
2071                     a2_abs_xy(true);
2072                     if exec_cycle = T3 or exec_cycle = T0 then
2073                         arith_en_n <= '0';
2074                         back_oe(acc_cmd, '0');
2075                         back_we(acc_cmd, '0');
2076                         set_nvzc_from_alu;
2077                     end if;
2078
2079                 elsif instruction  = conv_std_logic_vector(16#f9#, dsize) then
2080                     --abs, y
2081                     d_print("sbc");
2082                     a2_abs_xy(false);
2083                     if exec_cycle = T3 or exec_cycle = T0 then
2084                         arith_en_n <= '0';
2085                         back_oe(acc_cmd, '0');
2086                         back_we(acc_cmd, '0');
2087                         set_nvzc_from_alu;
2088                     end if;
2089
2090                 elsif instruction  = conv_std_logic_vector(16#e1#, dsize) then
2091                     --(indir, x)
2092                     d_print("sbc");
2093                     a2_indir_x;
2094                     if exec_cycle = T5 then
2095                         arith_en_n <= '0';
2096                         back_oe(acc_cmd, '0');
2097                         back_we(acc_cmd, '0');
2098                         set_nvzc_from_alu;
2099                     end if;
2100
2101                 elsif instruction  = conv_std_logic_vector(16#f1#, dsize) then
2102                     --(indir), y
2103                     d_print("sbc");
2104                     a2_indir_y;
2105                     if exec_cycle = T4 or exec_cycle = T0 then
2106                         arith_en_n <= '0';
2107                         back_oe(acc_cmd, '0');
2108                         back_we(acc_cmd, '0');
2109                         set_nvzc_from_alu;
2110                     end if;
2111
2112
2113
2114                 ----------------------------------------
2115                 ---A.3. store operation.
2116                 ----------------------------------------
2117                 elsif instruction  = conv_std_logic_vector(16#85#, dsize) then
2118                     --zp
2119                     d_print("sta");
2120                     a3_zp;
2121                     if exec_cycle = T2 then
2122                         front_oe(acc_cmd, '0');
2123                     end if;
2124
2125                 elsif instruction  = conv_std_logic_vector(16#95#, dsize) then
2126                     --zp, x
2127                     d_print("sta");
2128                     a3_zp_xy(true);
2129                     if exec_cycle = T2 then
2130                         front_oe(acc_cmd, '0');
2131                     end if;
2132
2133                 elsif instruction  = conv_std_logic_vector(16#8d#, dsize) then
2134                     --abs
2135                     d_print("sta");
2136                     a3_abs;
2137                     if exec_cycle = T3 then
2138                         front_oe(acc_cmd, '0');
2139                     end if;
2140
2141                 elsif instruction  = conv_std_logic_vector(16#9d#, dsize) then
2142                     --abs, x
2143                     d_print("sta");
2144                     a3_abs_xy (true);
2145                     if exec_cycle = T4 then
2146                         front_oe(acc_cmd, '0');
2147                     end if;
2148
2149                 elsif instruction  = conv_std_logic_vector(16#99#, dsize) then
2150                     --abs, y
2151                     d_print("sta");
2152                     a3_abs_xy (false);
2153                     if exec_cycle = T4 then
2154                         front_oe(acc_cmd, '0');
2155                     end if;
2156
2157                 elsif instruction  = conv_std_logic_vector(16#81#, dsize) then
2158                     --(indir, x)
2159                     d_print("sta");
2160                     a3_indir_x;
2161                     if exec_cycle = T5 then
2162                         front_oe(acc_cmd, '0');
2163                     end if;
2164
2165                 elsif instruction  = conv_std_logic_vector(16#91#, dsize) then
2166                     --(indir), y
2167                     d_print("sta");
2168                     a3_indir_y;
2169                     if exec_cycle = T5 then
2170                         front_oe(acc_cmd, '0');
2171                     end if;
2172
2173                 elsif instruction  = conv_std_logic_vector(16#86#, dsize) then
2174                     --zp
2175                     d_print("stx");
2176                     a3_zp;
2177                     if exec_cycle = T2 then
2178                         front_oe(x_cmd, '0');
2179                     end if;
2180
2181                 elsif instruction  = conv_std_logic_vector(16#96#, dsize) then
2182                     --zp, y
2183                     d_print("stx");
2184                     a3_zp_xy(false);
2185                     if exec_cycle = T2 then
2186                         front_oe(x_cmd, '0');
2187                     end if;
2188
2189                 elsif instruction  = conv_std_logic_vector(16#8e#, dsize) then
2190                     --abs
2191                     d_print("stx");
2192                     a3_abs;
2193                     if exec_cycle = T3 then
2194                         front_oe(x_cmd, '0');
2195                     end if;
2196
2197                 elsif instruction  = conv_std_logic_vector(16#84#, dsize) then
2198                     --zp
2199                     d_print("sty");
2200                     a3_zp;
2201                     if exec_cycle = T2 then
2202                         front_oe(y_cmd, '0');
2203                     end if;
2204
2205                 elsif instruction  = conv_std_logic_vector(16#94#, dsize) then
2206                     --zp, x
2207                     d_print("sty");
2208                     a3_zp_xy(true);
2209                     if exec_cycle = T2 then
2210                         front_oe(y_cmd, '0');
2211                     end if;
2212
2213                 elsif instruction  = conv_std_logic_vector(16#8c#, dsize) then
2214                     --abs
2215                     d_print("sty");
2216                     a3_abs;
2217                     if exec_cycle = T3 then
2218                         front_oe(y_cmd, '0');
2219                     end if;
2220
2221
2222                 ----------------------------------------
2223                 ---A.4. read-modify-write operation
2224                 ----------------------------------------
2225                 elsif instruction  = conv_std_logic_vector(16#06#, dsize) then
2226                     --zp
2227                     d_print("asl");
2228                     a4_zp;
2229                     if exec_cycle = T4 then
2230                         set_nzc_from_alu;
2231                     end if;
2232
2233                 elsif instruction  = conv_std_logic_vector(16#16#, dsize) then
2234                     --zp, x
2235                     d_print("asl");
2236                     a4_zp_x;
2237                     if exec_cycle = T5 then
2238                         set_nzc_from_alu;
2239                     end if;
2240
2241                 elsif instruction  = conv_std_logic_vector(16#0e#, dsize) then
2242                     --abs
2243                     d_print("asl");
2244                     a4_abs;
2245                     if exec_cycle = T5 then
2246                         set_nzc_from_alu;
2247                     end if;
2248
2249                 elsif instruction  = conv_std_logic_vector(16#1e#, dsize) then
2250                     --abs, x
2251                     d_print("asl");
2252                     a4_abs_x;
2253                     if exec_cycle = T6 then
2254                         set_nzc_from_alu;
2255                     end if;
2256
2257                 elsif instruction  = conv_std_logic_vector(16#c6#, dsize) then
2258                     --zp
2259                     d_print("dec");
2260                     a4_zp;
2261                     if exec_cycle = T4 then
2262                         set_nz_from_bus;
2263                     end if;
2264
2265                 elsif instruction  = conv_std_logic_vector(16#d6#, dsize) then
2266                     --zp, x
2267                     d_print("dec");
2268                     a4_zp_x;
2269                     if exec_cycle = T5 then
2270                         set_nz_from_bus;
2271                     end if;
2272
2273                 elsif instruction  = conv_std_logic_vector(16#ce#, dsize) then
2274                     --abs
2275                     d_print("dec");
2276                     a4_abs;
2277                     if exec_cycle = T5 then
2278                         set_nz_from_bus;
2279                     end if;
2280
2281                 elsif instruction  = conv_std_logic_vector(16#de#, dsize) then
2282                     --abs, x
2283                     d_print("dec");
2284                     a4_abs_x;
2285                     if exec_cycle = T6 then
2286                         set_nz_from_bus;
2287                     end if;
2288
2289                 elsif instruction  = conv_std_logic_vector(16#e6#, dsize) then
2290                     --zp
2291                     d_print("inc");
2292                     a4_zp;
2293                     if exec_cycle = T4 then
2294                         set_nz_from_bus;
2295                     end if;
2296
2297                 elsif instruction  = conv_std_logic_vector(16#f6#, dsize) then
2298                     --zp, x
2299                     d_print("inc");
2300                     a4_zp_x;
2301                     if exec_cycle = T5 then
2302                         set_nz_from_bus;
2303                     end if;
2304
2305                 elsif instruction  = conv_std_logic_vector(16#ee#, dsize) then
2306                     --abs
2307                     d_print("inc");
2308                     a4_abs;
2309                     if exec_cycle = T5 then
2310                         set_nz_from_bus;
2311                     end if;
2312
2313                 elsif instruction  = conv_std_logic_vector(16#fe#, dsize) then
2314                     --abs, x
2315                     d_print("inc");
2316                     a4_abs_x;
2317                     if exec_cycle = T6 then
2318                         set_nz_from_bus;
2319                     end if;
2320
2321                 elsif instruction  = conv_std_logic_vector(16#46#, dsize) then
2322                     --zp
2323                     d_print("lsr");
2324                     a4_zp;
2325                     if exec_cycle = T4 then
2326                         set_zc_from_alu;
2327                     end if;
2328
2329                 elsif instruction  = conv_std_logic_vector(16#56#, dsize) then
2330                     --zp, x
2331                     d_print("lsr");
2332                     a4_zp_x;
2333                     if exec_cycle = T5 then
2334                         set_zc_from_alu;
2335                     end if;
2336
2337                 elsif instruction  = conv_std_logic_vector(16#4e#, dsize) then
2338                     --abs
2339                     d_print("lsr");
2340                     a4_abs;
2341                     if exec_cycle = T5 then
2342                         set_zc_from_alu;
2343                     end if;
2344
2345                 elsif instruction  = conv_std_logic_vector(16#5e#, dsize) then
2346                     --abs, x
2347                     d_print("lsr");
2348                     a4_abs_x;
2349                     if exec_cycle = T6 then
2350                         set_zc_from_alu;
2351                     end if;
2352
2353                 elsif instruction  = conv_std_logic_vector(16#26#, dsize) then
2354                     --zp
2355                     d_print("rol");
2356                     a4_zp;
2357                     if exec_cycle = T4 then
2358                         set_nzc_from_alu;
2359                     end if;
2360
2361                 elsif instruction  = conv_std_logic_vector(16#36#, dsize) then
2362                     --zp, x
2363                     d_print("rol");
2364                     a4_zp_x;
2365                     if exec_cycle = T5 then
2366                         set_nzc_from_alu;
2367                     end if;
2368
2369                 elsif instruction  = conv_std_logic_vector(16#2e#, dsize) then
2370                     --abs
2371                     d_print("rol");
2372                     a4_abs;
2373                     if exec_cycle = T5 then
2374                         set_nzc_from_alu;
2375                     end if;
2376
2377                 elsif instruction  = conv_std_logic_vector(16#3e#, dsize) then
2378                     --abs, x
2379                     d_print("rol");
2380                     a4_abs_x;
2381                     if exec_cycle = T6 then
2382                         set_nzc_from_alu;
2383                     end if;
2384
2385                 elsif instruction  = conv_std_logic_vector(16#66#, dsize) then
2386                     --zp
2387                     d_print("ror");
2388                     a4_zp;
2389                     if exec_cycle = T4 then
2390                         set_nzc_from_alu;
2391                     end if;
2392
2393                 elsif instruction  = conv_std_logic_vector(16#76#, dsize) then
2394                     --zp, x
2395                     d_print("ror");
2396                     a4_zp_x;
2397                     if exec_cycle = T5 then
2398                         set_nzc_from_alu;
2399                     end if;
2400
2401                 elsif instruction  = conv_std_logic_vector(16#6e#, dsize) then
2402                     --abs
2403                     d_print("ror");
2404                     a4_abs;
2405                     if exec_cycle = T5 then
2406                         set_nzc_from_alu;
2407                     end if;
2408
2409                 elsif instruction  = conv_std_logic_vector(16#7e#, dsize) then
2410                     --abs, x
2411                     d_print("ror");
2412                     a4_abs_x;
2413                     if exec_cycle = T6 then
2414                         set_nzc_from_alu;
2415                     end if;
2416
2417
2418                 ----------------------------------------
2419                 --A.5. miscellaneous oprations.
2420                 ----------------------------------------
2421
2422                 -- A.5.1 push/pull
2423                 elsif instruction = conv_std_logic_vector(16#08#, dsize) then
2424                     d_print("php");
2425                     a51_push;
2426                     if exec_cycle = T2 then
2427                         stat_bus_oe_n <= '0';
2428                     end if;
2429
2430                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
2431                     d_print("pha");
2432                     a51_push;
2433                     if exec_cycle = T2 then
2434                         front_oe(acc_cmd, '0');
2435                     end if;
2436
2437                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
2438                     d_print("plp");
2439                     a52_pull;
2440                     if exec_cycle = T3 then
2441                         stat_dec_oe_n <= '1';
2442                         stat_bus_all_n <= '0';
2443                     end if;
2444
2445                 elsif instruction = conv_std_logic_vector(16#68#, dsize) then
2446                     d_print("pla");
2447                     a52_pull;
2448                     if exec_cycle = T3 then
2449                         front_we(acc_cmd, '0');
2450                         set_nz_from_bus;
2451                     end if;
2452
2453
2454                 ----------------------------------------
2455                 -- A.5.3 jsr
2456                 ----------------------------------------
2457                 elsif instruction = conv_std_logic_vector(16#20#, dsize) then
2458                     if exec_cycle = T1 then
2459                         d_print("jsr abs 2");
2460                         --fetch opcode.
2461                         fetch_next;
2462                         dbuf_int_oe_n <= '0';
2463                         --latch adl
2464                         next_cycle <= T2;
2465                     elsif exec_cycle = T2 then
2466                         d_print("jsr 3");
2467                         fetch_stop;
2468                         dbuf_int_oe_n <= '1';
2469
2470                        --read sp (discarded).
2471                         sp_oe_n <= '0';
2472                         back_oe(sp_cmd, '0');
2473                         r_nw <= '1';
2474                         next_cycle <= T3;
2475                     elsif exec_cycle = T3 then
2476                         d_print("jsr 4");
2477                         front_oe(pch_cmd, '1');
2478
2479                         --push return addr high into stack.
2480                         sp_push_n <= '0';
2481                         sp_oe_n <= '0';
2482                         front_oe(pch_cmd, '0');
2483                         back_oe(sp_cmd, '0');
2484                         back_we(sp_cmd, '0');
2485                         r_nw <= '0';
2486
2487                         next_cycle <= T4;
2488                     elsif exec_cycle = T4 then
2489                         d_print("jsr 5");
2490                         front_oe(pch_cmd, '1');
2491
2492                         --push return addr low into stack.
2493                         sp_push_n <= '0';
2494                         sp_oe_n <= '0';
2495                         front_oe(pcl_cmd, '0');
2496                         back_oe(sp_cmd, '0');
2497                         back_we(sp_cmd, '0');
2498                         r_nw <= '0';
2499
2500                         next_cycle <= T5;
2501                     elsif exec_cycle = T5 then
2502                         d_print("jsr 6");
2503                         sp_push_n <= '1';
2504                         sp_oe_n <= '1';
2505                         front_oe(pcl_cmd, '1');
2506                         back_oe(sp_cmd, '1');
2507                         back_we(sp_cmd, '1');
2508                         r_nw <= '1';
2509
2510                         --fetch pch.
2511                         dbuf_int_oe_n <= '0';
2512                         back_oe(pch_cmd, '0');
2513                         back_oe(pcl_cmd, '0');
2514                         front_we(pch_cmd, '0');
2515
2516                         next_cycle <= T0;
2517                     end if; --if exec_cycle = T1 then
2518
2519                 -- A.5.4 break
2520                 elsif instruction = conv_std_logic_vector(16#00#, dsize) then
2521
2522                 ----------------------------------------
2523                 -- A.5.5 return from interrupt
2524                 ----------------------------------------
2525                 elsif instruction = conv_std_logic_vector(16#40#, dsize) then
2526                     if exec_cycle = T1 then
2527                         d_print("rti 2");
2528                         fetch_stop;
2529
2530                         --pop stack (decrement only)
2531                         back_oe(sp_cmd, '0');
2532                         back_we(sp_cmd, '0');
2533                         sp_pop_n <= '0';
2534                         sp_oe_n <= '0';
2535
2536                         next_cycle <= T2;
2537                     elsif exec_cycle = T2 then
2538                         d_print("rti 3");
2539
2540                         --pop p (status)
2541                         back_oe(sp_cmd, '0');
2542                         back_we(sp_cmd, '0');
2543                         sp_pop_n <= '0';
2544                         sp_oe_n <= '0';
2545
2546                         --load status reg
2547                         stat_dec_oe_n <= '1';
2548                         dbuf_int_oe_n <= '0';
2549                         stat_bus_all_n <= '0';
2550
2551                         next_cycle <= T3;
2552                     elsif exec_cycle = T3 then
2553                         d_print("rti 4");
2554                         stat_bus_all_n <= '1';
2555
2556                         --pop pcl
2557                         back_oe(sp_cmd, '0');
2558                         back_we(sp_cmd, '0');
2559                         sp_pop_n <= '0';
2560                         sp_oe_n <= '0';
2561
2562                         --load lo addr.
2563                         dbuf_int_oe_n <= '0';
2564                         front_we(pcl_cmd, '0');
2565
2566                         next_cycle <= T4;
2567                     elsif exec_cycle = T4 then
2568                         d_print("rti 5");
2569                         --stack decrement stop.
2570                         back_we(sp_cmd, '1');
2571                         sp_pop_n <= '1';
2572                         front_we(pcl_cmd, '1');
2573
2574                         --pop pch
2575                         back_oe(sp_cmd, '0');
2576                         sp_oe_n <= '0';
2577                         --load hi addr.
2578                         dbuf_int_oe_n <= '0';
2579                         front_we(pch_cmd, '0');
2580
2581                         next_cycle <= T5;
2582                     elsif exec_cycle = T5 then
2583                         d_print("rti 6");
2584                         back_oe(sp_cmd, '1');
2585                         sp_oe_n <= '1';
2586                         --load hi addr.
2587                         dbuf_int_oe_n <= '1';
2588                         front_we(pch_cmd, '1');
2589
2590                         --increment pc.
2591                         next_cycle <= T0;
2592                     end if; --if exec_cycle = T1 then
2593
2594                 ----------------------------------------
2595                 -- A.5.6 jmp
2596                 ----------------------------------------
2597                 elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
2598                     --abs
2599                     if exec_cycle = T1 then
2600                         d_print("jmp 2");
2601                         --fetch next opcode (abs low).
2602                         fetch_next;
2603
2604                         --latch abs low data.
2605                         dbuf_int_oe_n <= '0';
2606                         next_cycle <= T2;
2607                     elsif exec_cycle = T2 then
2608                         d_print("jmp 3");
2609
2610                         --fetch abs hi
2611                         fetch_next;
2612
2613                         --latch  in dlh
2614                         dbuf_int_oe_n <= '0';
2615                         ---load pch.
2616                         front_we(pch_cmd, '0');
2617
2618                         next_cycle <= T0;
2619                     end if;
2620
2621                 elsif instruction = conv_std_logic_vector(16#6c#, dsize) then
2622                     --jmp (indir)
2623                     if exec_cycle = T1 then
2624                         d_print("jmp 2");
2625                         --fetch next opcode (abs low).
2626                         fetch_next;
2627
2628                         --latch abs low data.
2629                         dbuf_int_oe_n <= '0';
2630                         next_cycle <= T2;
2631                     elsif exec_cycle = T2 then
2632                         d_print("jmp 3");
2633
2634                         --fetch abs hi
2635                         fetch_next;
2636
2637                         --latch  in dlh
2638                         dbuf_int_oe_n <= '0';
2639                         next_cycle <= T3;
2640
2641                     elsif exec_cycle = T3 then
2642                         fetch_stop;
2643
2644                         --IAH/IAL > ADL
2645                         back_oe(idl_h_cmd, '0');
2646                         back_oe(idl_l_cmd, '0');
2647                         front_we(pcl_cmd, '0');
2648                         next_cycle <= T4;
2649
2650                     elsif exec_cycle = T4 then
2651                         back_oe(idl_h_cmd, '0');
2652                         back_oe(idl_l_cmd, '0');
2653                         front_we(pcl_cmd, '1');
2654
2655                         --IAH/IAL+1 > ADH
2656                         front_we(pch_cmd, '0');
2657                         indir_n <= '0';
2658
2659                         next_cycle <= T0;
2660
2661                     end if;
2662
2663
2664                 ----------------------------------------
2665                 -- A.5.7 return from soubroutine
2666                 ----------------------------------------
2667                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
2668                     if exec_cycle = T1 then
2669                         d_print("rts 2");
2670                         fetch_stop;
2671
2672                         --pop stack (decrement only)
2673                         back_oe(sp_cmd, '0');
2674                         back_we(sp_cmd, '0');
2675                         sp_pop_n <= '0';
2676                         sp_oe_n <= '0';
2677
2678                         next_cycle <= T2;
2679                     elsif exec_cycle = T2 then
2680                         d_print("rts 3");
2681
2682                         --pop pcl
2683                         back_oe(sp_cmd, '0');
2684                         back_we(sp_cmd, '0');
2685                         sp_pop_n <= '0';
2686                         sp_oe_n <= '0';
2687
2688                         --load lo addr.
2689                         dbuf_int_oe_n <= '0';
2690                         front_we(pcl_cmd, '0');
2691
2692                         next_cycle <= T3;
2693                     elsif exec_cycle = T3 then
2694                         d_print("rts 4");
2695                         --stack decrement stop.
2696                         back_we(sp_cmd, '1');
2697                         sp_pop_n <= '1';
2698                         front_we(pcl_cmd, '1');
2699
2700                         --pop pch
2701                         back_oe(sp_cmd, '0');
2702                         sp_oe_n <= '0';
2703                         --load hi addr.
2704                         dbuf_int_oe_n <= '0';
2705                         front_we(pch_cmd, '0');
2706
2707                         next_cycle <= T4;
2708                     elsif exec_cycle = T4 then
2709                         d_print("rts 5");
2710                         back_oe(sp_cmd, '1');
2711                         sp_oe_n <= '1';
2712                         --load hi addr.
2713                         dbuf_int_oe_n <= '1';
2714                         front_we(pch_cmd, '1');
2715                         --empty cycle.
2716                         --complying h/w manual...
2717                         next_cycle <= T5;
2718                     elsif exec_cycle = T5 then
2719                         d_print("rts 6");
2720
2721                         --increment pc.
2722                         fetch_next;
2723                         next_cycle <= T0;
2724                     end if; --if exec_cycle = T1 then
2725
2726                 ----------------------------------------
2727                 -- A.5.8 branch operations
2728                 ----------------------------------------
2729                 elsif instruction = conv_std_logic_vector(16#90#, dsize) then
2730                     d_print("bcc");
2731                     a58_branch (st_C, '0');
2732
2733                 elsif instruction = conv_std_logic_vector(16#b0#, dsize) then
2734                     d_print("bcs");
2735                     a58_branch (st_C, '1');
2736
2737                 elsif instruction = conv_std_logic_vector(16#f0#, dsize) then
2738                     d_print("beq");
2739                     a58_branch (st_Z, '1');
2740
2741                 elsif instruction = conv_std_logic_vector(16#30#, dsize) then
2742                     d_print("bmi");
2743                     a58_branch (st_N, '1');
2744
2745                 elsif instruction = conv_std_logic_vector(16#d0#, dsize) then
2746                     d_print("bne");
2747                     a58_branch (st_Z, '0');
2748
2749                 elsif instruction = conv_std_logic_vector(16#10#, dsize) then
2750                     d_print("bpl");
2751                     a58_branch (st_N, '0');
2752
2753                 elsif instruction = conv_std_logic_vector(16#50#, dsize) then
2754                     d_print("bvc");
2755                     a58_branch (st_V, '0');
2756
2757                 elsif instruction = conv_std_logic_vector(16#70#, dsize) then
2758                     d_print("bvs");
2759                     a58_branch (st_V, '1');
2760
2761                 else
2762                     ---unknown instruction!!!!
2763                     assert false
2764                         report "======== unknow instruction "
2765                             & conv_hex8(conv_integer(instruction))
2766                         severity failure;
2767                 end if; --if instruction = conv_std_logic_vector(16#0a#, dsize)
2768
2769             elsif exec_cycle = R0 then
2770                 d_print(string'("reset"));
2771                 init_all_pins;
2772
2773                 next_cycle <= R1;
2774             elsif exec_cycle = R1 or exec_cycle = N1 then
2775                 init_all_pins;
2776
2777                 if exec_cycle = R1 then
2778                     next_cycle <= R2;
2779                 elsif exec_cycle = N1 then
2780                     next_cycle <= N2;
2781                 end if;
2782             elsif exec_cycle = R2 or exec_cycle = N2 then
2783                 pcl_cmd <= "1111";
2784                 pcl_inc_n <= '1';
2785                 inst_we_n <= '1';
2786                 back_oe(idl_l_cmd, '1');
2787
2788                 --push pch.
2789                 d_print("R2");
2790                 ad_oe_n <= '0';
2791                 sp_push_n <= '0';
2792                 sp_oe_n <= '0';
2793                 pch_cmd <= "0111";
2794                 --front_oe(pch_cmd, '0');
2795                 back_oe(sp_cmd, '0');
2796                 back_we(sp_cmd, '0');
2797                 r_nw <= '0';
2798
2799                 if exec_cycle = R2 then
2800                     next_cycle <= R3;
2801                 elsif exec_cycle = N2 then
2802                     next_cycle <= N3;
2803                 end if;
2804
2805             elsif exec_cycle = R3 or exec_cycle = N3 then
2806                 front_oe(pch_cmd, '1');
2807
2808                --push pcl.
2809                 sp_push_n <= '0';
2810                 sp_oe_n <= '0';
2811                 front_oe(pcl_cmd, '0');
2812                 back_oe(sp_cmd, '0');
2813                 back_we(sp_cmd, '0');
2814                 r_nw <= '0';
2815
2816                 if exec_cycle = R3 then
2817                     next_cycle <= R4;
2818                 elsif exec_cycle = N3 then
2819                     next_cycle <= N4;
2820                 end if;
2821
2822             elsif exec_cycle = R4 or exec_cycle = N4 then
2823                 front_oe(pcl_cmd, '1');
2824
2825                --push status.
2826                 sp_push_n <= '0';
2827                 sp_oe_n <= '0';
2828                 stat_bus_oe_n <= '0';
2829                 back_oe(sp_cmd, '0');
2830                 back_we(sp_cmd, '0');
2831                 r_nw <= '0';
2832
2833                 if exec_cycle = R4 then
2834                     next_cycle <= R5;
2835                 elsif exec_cycle = N4 then
2836                     next_cycle <= N5;
2837                 end if;
2838
2839             elsif exec_cycle = R5 or exec_cycle = N5 then
2840                 stat_bus_oe_n <= '1';
2841                 sp_push_n <= '1';
2842                 sp_oe_n <= '1';
2843                 front_oe(pcl_cmd, '1');
2844                 back_oe(sp_cmd, '1');
2845                 back_we(sp_cmd, '1');
2846
2847                 --fetch reset vector low
2848                 r_nw <= '1';
2849                 dbuf_int_oe_n <= '0';
2850                 front_we(pcl_cmd, '0');
2851                 back_oe(idl_l_cmd, '1');
2852                 back_oe(idl_h_cmd, '1');
2853
2854                 if exec_cycle = R5 then
2855                     r_vec_oe_n <= '0';
2856                     n_vec_oe_n <= '1';
2857                     next_cycle <= R6;
2858                 elsif exec_cycle = N5 then
2859                     r_vec_oe_n <= '1';
2860                     n_vec_oe_n <= '0';
2861                     next_cycle <= N6;
2862                 end if;
2863
2864             elsif exec_cycle = R6 or exec_cycle = N6 then
2865                 front_we(pcl_cmd, '1');
2866
2867                 --fetch reset vector hi
2868                 r_nw <= '1';
2869                 dbuf_int_oe_n <= '0';
2870                 front_we(pch_cmd, '0');
2871                 addr_cycle <= ADDR_T2;
2872
2873                 if exec_cycle = N6 then
2874                     nmi_handled_n <= '0';
2875                 end if;
2876                 --start execute cycle.
2877                 next_cycle <= T0;
2878
2879             end if; --if rdy = '0' then
2880
2881         end if; -- if (res_n = '0') then
2882
2883     end process;
2884
2885 end rtl;
2886