1 # Copyright (C) 1991-2007 Altera Corporation
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2 # Your use of Altera Corporation's design tools, logic functions
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3 # and other software and tools, and its AMPP partner logic
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4 # functions, and any output files from any of the foregoing
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5 # (including device programming or simulation files), and any
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6 # associated documentation or information are expressly subject
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7 # to the terms and conditions of the Altera Program License
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8 # Subscription Agreement, Altera MegaCore Function License
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9 # Agreement, or other applicable license agreement, including,
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10 # without limitation, that your use is for the sole purpose of
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11 # programming logic devices manufactured by Altera and sold by
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12 # Altera or its authorized distributors. Please refer to the
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13 # applicable agreement for further details.
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16 # The default values for assignments are stored in the file
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17 # de1_nes_assignment_defaults.qdf
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18 # If this file doesn't exist, and for assignments not listed, see file
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19 # assignment_defaults.qdf
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21 # Altera recommends that you do not modify this file. This
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22 # file is updated automatically by the Quartus II software
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23 # and any changes you make may be lost or overwritten.
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26 set_global_assignment -name FAMILY "Cyclone II"
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27 set_global_assignment -name DEVICE EP2C20F484C7
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28 set_global_assignment -name TOP_LEVEL_ENTITY de1_nes
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29 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
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30 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:06:40 SEPTEMBER 01, 2013"
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31 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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32 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
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33 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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34 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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35 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
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36 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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37 set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
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38 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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39 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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40 set_location_assignment PIN_D12 -to base_clk
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41 set_location_assignment PIN_R22 -to rst_n
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42 set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE de1_nes.vwf
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43 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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44 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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45 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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46 set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_motones_sim -section_id eda_simulation
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47 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_motones_sim -section_id eda_simulation
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48 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME sim_board -section_id testbench_motones_sim
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49 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_motones_sim -section_id testbench_motones_sim
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50 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_clock_divider -section_id eda_simulation
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51 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME dut -section_id testbench_clock_divider
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52 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_clock_divider -section_id testbench_clock_divider
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53 set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 us" -section_id testbench_motones_sim
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54 set_global_assignment -name EDA_TEST_BENCH_FILE testbench_motones_sim.vhd -section_id testbench_motones_sim
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55 set_global_assignment -name EDA_TEST_BENCH_FILE testbench_clock_divider.vhd -section_id testbench_clock_divider
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56 set_location_assignment LCCOMB_X22_Y13_N8 -to "mos6502:cpu_inst|alu:alu_inst|alu_core:alu_inst|Equal8~65"
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57 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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58 set_global_assignment -name VHDL_FILE motonesfpga_common.vhd
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59 set_global_assignment -name VHDL_FILE ppu/vga.vhd
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60 set_global_assignment -name VHDL_FILE mem/prg_rom.vhd
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61 set_global_assignment -name VHDL_FILE mem/chr_rom.vhd
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62 set_global_assignment -name VHDL_FILE mem/ram.vhd
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63 set_global_assignment -name VHDL_FILE address_decoder.vhd
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64 set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd
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65 set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd
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66 set_global_assignment -name VHDL_FILE clock/clock_divider.vhd
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67 set_global_assignment -name VHDL_FILE apu/apu.vhd
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68 set_global_assignment -name VHDL_FILE ppu/ppu.vhd
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69 set_global_assignment -name VHDL_FILE ppu/render.vhd
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70 set_global_assignment -name VHDL_FILE cpu/decoder.vhd
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71 set_global_assignment -name VHDL_FILE cpu/alu.vhd
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72 set_global_assignment -name VHDL_FILE cpu/mos6502.vhd
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73 set_global_assignment -name VHDL_FILE de1_nes.vhd
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74 set_global_assignment -name VECTOR_WAVEFORM_FILE de1_nes.vwf
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75 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top