de1_nes/de1_nes.qsf

   1 # Copyright (C) 1991-2007 Altera Corporation\r
   2 # Your use of Altera Corporation's design tools, logic functions \r
   3 # and other software and tools, and its AMPP partner logic \r
   4 # functions, and any output files from any of the foregoing \r
   5 # (including device programming or simulation files), and any \r
   6 # associated documentation or information are expressly subject \r
   7 # to the terms and conditions of the Altera Program License \r
   8 # Subscription Agreement, Altera MegaCore Function License \r
   9 # Agreement, or other applicable license agreement, including, \r
  10 # without limitation, that your use is for the sole purpose of \r
  11 # programming logic devices manufactured by Altera and sold by \r
  12 # Altera or its authorized distributors.  Please refer to the \r
  13 # applicable agreement for further details.\r
  14 \r
  15 \r
  16 # The default values for assignments are stored in the file\r
  17 #               de1_nes_assignment_defaults.qdf\r
  18 # If this file doesn't exist, and for assignments not listed, see file\r
  19 #               assignment_defaults.qdf\r
  20 \r
  21 # Altera recommends that you do not modify this file. This\r
  22 # file is updated automatically by the Quartus II software\r
  23 # and any changes you make may be lost or overwritten.\r
  24 \r
  25 \r
  26 set_global_assignment -name FAMILY "Cyclone II"\r
  27 set_global_assignment -name DEVICE EP2C20F484C7\r
  28 set_global_assignment -name TOP_LEVEL_ENTITY de1_nes\r
  29 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2\r
  30 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:06:40  SEPTEMBER 01, 2013"\r
  31 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"\r
  32 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace\r
  33 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA\r
  34 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484\r
  35 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7\r
  36 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
  37 set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top\r
  38 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"\r
  39 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"\r
  40 set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE de1_nes.vwf\r
  41 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"\r
  42 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation\r
  43 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation\r
  44 set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_motones_sim -section_id eda_simulation\r
  45 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_motones_sim -section_id eda_simulation\r
  46 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME sim_board -section_id testbench_motones_sim\r
  47 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_motones_sim -section_id testbench_motones_sim\r
  48 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_clock_divider -section_id eda_simulation\r
  49 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME dut -section_id testbench_clock_divider\r
  50 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_clock_divider -section_id testbench_clock_divider\r
  51 set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 us" -section_id testbench_motones_sim\r
  52 set_global_assignment -name EDA_TEST_BENCH_FILE testbench_motones_sim.vhd -section_id testbench_motones_sim\r
  53 set_global_assignment -name EDA_TEST_BENCH_FILE testbench_clock_divider.vhd -section_id testbench_clock_divider\r
  54 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\r
  55 \r
  56 ##set_location_assignment LCCOMB_X22_Y13_N8 -to "mos6502:cpu_inst|alu:alu_inst|alu_core:alu_inst|Equal8~65"\r
  57 \r
  58 ##VGA\r
  59 set_location_assignment PIN_D9 -to r[0]\r
  60 set_location_assignment PIN_C9 -to r[1]\r
  61 set_location_assignment PIN_A7 -to r[2]\r
  62 set_location_assignment PIN_B7 -to r[3]\r
  63 set_location_assignment PIN_B8 -to g[0]\r
  64 set_location_assignment PIN_C10 -to g[1]\r
  65 set_location_assignment PIN_B9 -to g[2]\r
  66 set_location_assignment PIN_A8 -to g[3]\r
  67 set_location_assignment PIN_A9 -to b[0]\r
  68 set_location_assignment PIN_D11 -to b[1]\r
  69 set_location_assignment PIN_A10 -to b[2]\r
  70 set_location_assignment PIN_B10 -to b[3]\r
  71 set_location_assignment PIN_A11 -to h_sync_n\r
  72 set_location_assignment PIN_B11 -to v_sync_n\r
  73 \r
  74 #other\r
  75 set_location_assignment PIN_L1 -to base_clk\r
  76 set_location_assignment PIN_R22 -to rst_n\r
  77 \r
  78 ##DRAM\r
  79 set_location_assignment PIN_W4 -to dram_addr[0]\r
  80 set_location_assignment PIN_W5 -to dram_addr[1]\r
  81 set_location_assignment PIN_Y3 -to dram_addr[2]\r
  82 set_location_assignment PIN_Y4 -to dram_addr[3]\r
  83 set_location_assignment PIN_R6 -to dram_addr[4]\r
  84 set_location_assignment PIN_R5 -to dram_addr[5]\r
  85 set_location_assignment PIN_P6 -to dram_addr[6]\r
  86 set_location_assignment PIN_P5 -to dram_addr[7]\r
  87 set_location_assignment PIN_P3 -to dram_addr[8]\r
  88 set_location_assignment PIN_N4 -to dram_addr[9]\r
  89 set_location_assignment PIN_W3 -to dram_addr[10]\r
  90 set_location_assignment PIN_N6 -to dram_addr[11]\r
  91 set_location_assignment PIN_U3 -to dram_bank[0]\r
  92 set_location_assignment PIN_V4 -to dram_bank[1]\r
  93 set_location_assignment PIN_T3 -to dram_cas_n\r
  94 set_location_assignment PIN_N3 -to dram_cke\r
  95 set_location_assignment PIN_U4 -to dram_clk\r
  96 set_location_assignment PIN_T6 -to dram_cs_n\r
  97 set_location_assignment PIN_U1 -to dram_dq[0]\r
  98 set_location_assignment PIN_U2 -to dram_dq[1]\r
  99 set_location_assignment PIN_V1 -to dram_dq[2]\r
 100 set_location_assignment PIN_V2 -to dram_dq[3]\r
 101 set_location_assignment PIN_W1 -to dram_dq[4]\r
 102 set_location_assignment PIN_W2 -to dram_dq[5]\r
 103 set_location_assignment PIN_Y1 -to dram_dq[6]\r
 104 set_location_assignment PIN_Y2 -to dram_dq[7]\r
 105 set_location_assignment PIN_N1 -to dram_dq[8]\r
 106 set_location_assignment PIN_N2 -to dram_dq[9]\r
 107 set_location_assignment PIN_P1 -to dram_dq[10]\r
 108 set_location_assignment PIN_P2 -to dram_dq[11]\r
 109 set_location_assignment PIN_R1 -to dram_dq[12]\r
 110 set_location_assignment PIN_R2 -to dram_dq[13]\r
 111 set_location_assignment PIN_T1 -to dram_dq[14]\r
 112 set_location_assignment PIN_T2 -to dram_dq[15]\r
 113 set_location_assignment PIN_R7 -to dram_ldqm\r
 114 set_location_assignment PIN_T5 -to dram_ras_n\r
 115 set_location_assignment PIN_M5 -to dram_udqm\r
 116 set_location_assignment PIN_R8 -to dram_we_n\r
 117 \r
 118 \r
 119 #set_global_assignment -name VHDL_FILE apu/apu.vhd\r
 120 set_global_assignment -name VHDL_FILE address_decoder.vhd\r
 121 set_global_assignment -name VHDL_FILE motonesfpga_common.vhd\r
 122 set_global_assignment -name VHDL_FILE clock/clock_divider.vhd\r
 123 set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r
 124 set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
 125 set_global_assignment -name VHDL_FILE mem/ram.vhd\r
 126 set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd\r
 127 set_global_assignment -name VHDL_FILE ppu/vga.vhd\r
 128 set_global_assignment -name VHDL_FILE ppu/render.vhd\r
 129 set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
 130 set_global_assignment -name VHDL_FILE cpu/alu.vhd\r
 131 set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd\r
 132 set_global_assignment -name VHDL_FILE cpu/decoder.vhd\r
 133 set_global_assignment -name VHDL_FILE cpu/mos6502.vhd\r
 134 set_global_assignment -name VHDL_FILE de1_nes.vhd\r
 135 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"\r
 136 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\r
 137 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\r
 138 set_global_assignment -name DEVICE_MIGRATION_LIST EP2C20F484C7\r
 139 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top