2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
13 signal dbg_cpu_clk : out std_logic;
14 signal dbg_ppu_clk : out std_logic;
15 signal dbg_mem_clk : out std_logic;
16 signal dbg_r_nw : out std_logic;
17 signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
18 signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
19 signal dbg_vram_ad : out std_logic_vector (7 downto 0);
20 signal dbg_vram_a : out std_logic_vector (13 downto 8);
23 signal dbg_instruction : out std_logic_vector(7 downto 0);
24 signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
25 signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
26 signal dbg_ea_carry : out std_logic;
27 -- signal dbg_index_bus : out std_logic_vector(7 downto 0);
28 -- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
29 signal dbg_status : out std_logic_vector(7 downto 0);
30 -- signal dbg_pcl, dbg_pch : out std_logic_vector(7 downto 0);
31 signal dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
32 signal dbg_dec_oe_n : out std_logic;
33 signal dbg_dec_val : out std_logic_vector (7 downto 0);
34 signal dbg_int_dbus : out std_logic_vector (7 downto 0);
35 -- signal dbg_status_val : out std_logic_vector (7 downto 0);
36 -- signal dbg_stat_we_n : out std_logic;
37 -- signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : out std_logic_vector (7 downto 0);
40 signal dbg_ppu_ce_n : out std_logic;
41 signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
42 signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
43 signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
44 signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
45 signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
46 signal dbg_nmi : out std_logic;
49 base_clk : in std_logic;
51 joypad1 : in std_logic_vector(7 downto 0);
52 joypad2 : in std_logic_vector(7 downto 0);
53 h_sync_n : out std_logic;
54 v_sync_n : out std_logic;
55 r : out std_logic_vector(3 downto 0);
56 g : out std_logic_vector(3 downto 0);
57 b : out std_logic_vector(3 downto 0);
58 nt_v_mirror : in std_logic
\r
62 architecture rtl of de1_nes is
64 generic ( dsize : integer := 8;
68 signal dbg_instruction : out std_logic_vector(7 downto 0);
69 signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
70 signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
71 signal dbg_ea_carry : out std_logic;
72 -- signal dbg_index_bus : out std_logic_vector(7 downto 0);
73 -- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
74 signal dbg_status : out std_logic_vector(7 downto 0);
75 signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
76 signal dbg_dec_oe_n : out std_logic;
77 signal dbg_dec_val : out std_logic_vector (7 downto 0);
78 signal dbg_int_dbus : out std_logic_vector (7 downto 0);
79 -- signal dbg_status_val : out std_logic_vector (7 downto 0);
80 signal dbg_stat_we_n : out std_logic;
81 signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : out std_logic_vector (7 downto 0);
83 input_clk : in std_logic; --phi0 input pin.
92 addr : out std_logic_vector ( asize - 1 downto 0);
93 d_io : inout std_logic_vector ( dsize - 1 downto 0)
97 component clock_divider
98 port ( base_clk : in std_logic;
99 reset_n : in std_logic;
100 cpu_clk : out std_logic;
101 ppu_clk : out std_logic;
102 mem_clk : out std_logic;
103 vga_clk : out std_logic
107 component address_decoder
108 generic (abus_size : integer := 16; dbus_size : integer := 8);
109 port ( phi2 : in std_logic;
110 mem_clk : in std_logic;
112 addr : in std_logic_vector (abus_size - 1 downto 0);
113 rom_ce_n : out std_logic;
114 ram_ce_n : out std_logic;
115 ppu_ce_n : out std_logic;
116 apu_ce_n : out std_logic
121 generic (abus_size : integer := 16; dbus_size : integer := 8);
124 ce_n, oe_n, we_n : in std_logic; --select pin active low.
125 addr : in std_logic_vector (abus_size - 1 downto 0);
126 d_io : inout std_logic_vector (dbus_size - 1 downto 0)
131 generic (abus_size : integer := 15; dbus_size : integer := 8);
134 ce_n : in std_logic; --active low.
135 addr : in std_logic_vector (abus_size - 1 downto 0);
136 data : out std_logic_vector (dbus_size - 1 downto 0)
141 signal dbg_ppu_ce_n : out std_logic;
142 signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
143 signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
144 signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
146 signal dbg_ppu_clk : out std_logic;
147 signal dbg_vga_clk : out std_logic;
148 signal dbg_nes_x : out std_logic_vector (8 downto 0);
149 signal dbg_vga_x : out std_logic_vector (9 downto 0);
150 signal dbg_nes_y : out std_logic_vector (8 downto 0);
151 signal dbg_vga_y : out std_logic_vector (9 downto 0);
152 signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
153 signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
154 signal dbg_plt_ce_rn_wn : out std_logic_vector (2 downto 0);
155 signal dbg_plt_addr : out std_logic_vector (4 downto 0);
156 signal dbg_plt_data : out std_logic_vector (7 downto 0);
157 signal dbg_p_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
158 signal dbg_p_oam_addr : out std_logic_vector (7 downto 0);
159 signal dbg_p_oam_data : out std_logic_vector (7 downto 0);
160 signal dbg_s_oam_ce_rn_wn : out std_logic_vector (2 downto 0);
161 signal dbg_s_oam_addr : out std_logic_vector (4 downto 0);
162 signal dbg_s_oam_data : out std_logic_vector (7 downto 0);
163 signal dbg_emu_ppu_clk : out std_logic;
165 signal dbg_ppu_addr_we_n : out std_logic;
166 signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0);
168 ppu_clk : in std_logic;
169 mem_clk : in std_logic;
171 rst_n : in std_logic;
173 cpu_addr : in std_logic_vector (2 downto 0);
174 cpu_d : inout std_logic_vector (7 downto 0);
176 vblank_n : out std_logic;
177 rd_n : out std_logic;
178 wr_n : out std_logic;
180 vram_ad : inout std_logic_vector (7 downto 0);
181 vram_a : out std_logic_vector (13 downto 8);
183 vga_clk : in std_logic;
184 h_sync_n : out std_logic;
185 v_sync_n : out std_logic;
186 r : out std_logic_vector(3 downto 0);
187 g : out std_logic_vector(3 downto 0);
188 b : out std_logic_vector(3 downto 0)
192 component v_address_decoder
193 generic (abus_size : integer := 14; dbus_size : integer := 8);
194 port ( clk : in std_logic;
195 mem_clk : in std_logic;
199 v_addr : in std_logic_vector (13 downto 0);
200 v_data : in std_logic_vector (7 downto 0);
201 nt_v_mirror : in std_logic;
202 pt_ce_n : out std_logic;
203 nt0_ce_n : out std_logic;
204 nt1_ce_n : out std_logic
209 generic (abus_size : integer := 13; dbus_size : integer := 8);
212 ce_n : in std_logic; --active low.
213 addr : in std_logic_vector (abus_size - 1 downto 0);
214 data : out std_logic_vector (dbus_size - 1 downto 0)
222 port ( c : in std_logic;
225 d : in std_logic_vector(dsize - 1 downto 0);
226 q : out std_logic_vector(dsize - 1 downto 0)
231 port ( clk : in std_logic;
233 rst_n : in std_logic;
234 r_nw : inout std_logic;
235 cpu_addr : inout std_logic_vector (15 downto 0);
236 cpu_d : inout std_logic_vector (7 downto 0);
241 constant data_size : integer := 8;
242 constant addr_size : integer := 16;
243 constant vram_size14 : integer := 14;
245 constant ram_2k : integer := 11; --2k = 11 bit width.
246 constant rom_32k : integer := 15; --32k = 15 bit width.
247 constant rom_8k : integer := 13; --8k = 13 bit width. (for test use)
248 constant vram_1k : integer := 10; --1k = 10 bit width.
249 constant chr_rom_8k : integer := 13; --32k = 15 bit width.
251 signal cpu_clk : std_logic;
252 signal ppu_clk : std_logic;
253 signal mem_clk : std_logic;
254 signal vga_clk : std_logic;
256 signal rdy, irq_n, nmi_n, dbe, r_nw : std_logic;
257 signal phi1, phi2 : std_logic;
258 signal addr : std_logic_vector( addr_size - 1 downto 0);
259 signal d_io : std_logic_vector( data_size - 1 downto 0);
261 signal rom_ce_n : std_logic;
262 signal ram_ce_n : std_logic;
263 signal ram_oe_n : std_logic;
264 signal ppu_ce_n : std_logic;
265 signal apu_ce_n : std_logic;
267 signal rd_n : std_logic;
268 signal wr_n : std_logic;
269 signal ale : std_logic;
270 signal vram_ad : std_logic_vector (7 downto 0);
271 signal vram_a : std_logic_vector (13 downto 8);
272 signal v_addr : std_logic_vector (13 downto 0);
273 signal pt_ce_n : std_logic;
274 signal nt0_ce_n : std_logic;
275 signal nt1_ce_n : std_logic;
277 signal ale_n : std_logic;
279 -- signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0);
280 -- signal dbg_disp_ptn_h, dbg_disp_ptn_l : std_logic_vector (15 downto 0);
281 signal dbg_pcl, dbg_pch : std_logic_vector(7 downto 0);
282 signal dbg_stat_we_n : std_logic;
283 signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : std_logic_vector (7 downto 0);
285 signal dbg_vga_clk : std_logic;
286 signal dbg_ppu_addr_we_n : std_logic;
287 signal dbg_ppu_clk_cnt : std_logic_vector(1 downto 0);
288 signal dbg_ppu_addr_dummy : std_logic_vector (13 downto 0);
289 signal dbg_nes_x : std_logic_vector (8 downto 0);
290 signal dbg_vga_x : std_logic_vector (9 downto 0);
291 signal dbg_nes_y : std_logic_vector (8 downto 0);
292 signal dbg_vga_y : std_logic_vector (9 downto 0);
293 signal dbg_plt_ce_rn_wn : std_logic_vector (2 downto 0);
294 signal dbg_plt_addr : std_logic_vector (4 downto 0);
295 signal dbg_plt_data : std_logic_vector (7 downto 0);
296 signal dbg_p_oam_ce_rn_wn : std_logic_vector (2 downto 0);
297 signal dbg_p_oam_addr : std_logic_vector (7 downto 0);
298 signal dbg_p_oam_data : std_logic_vector (7 downto 0);
299 signal dbg_s_oam_ce_rn_wn : std_logic_vector (2 downto 0);
300 signal dbg_s_oam_addr : std_logic_vector (4 downto 0);
301 signal dbg_s_oam_data : std_logic_vector (7 downto 0);
302 signal dbg_emu_ppu_clk : std_logic;
303 signal dbg_ppu_data_dummy : std_logic_vector (7 downto 0);
304 signal dbg_ppu_status_dummy : std_logic_vector (7 downto 0);
305 signal dbg_ppu_scrl_x_dummy : std_logic_vector (7 downto 0);
306 signal dbg_ppu_scrl_y_dummy : std_logic_vector (7 downto 0);
307 signal dbg_disp_ptn_h_dummy, dbg_disp_ptn_l_dummy : std_logic_vector (15 downto 0);
309 signal dbg_instruction_dummy : std_logic_vector(7 downto 0);
310 signal dbg_int_d_bus_dummy : std_logic_vector(7 downto 0);
311 signal dbg_exec_cycle_dummy : std_logic_vector (5 downto 0);
312 signal dbg_ea_carry_dummy : std_logic;
313 signal dbg_status_dummy : std_logic_vector(7 downto 0);
314 signal dbg_sp_dummy, dbg_x_dummy, dbg_y_dummy, dbg_acc_dummy : std_logic_vector(7 downto 0);
\r
320 --ppu/cpu clock generator
321 clock_inst : clock_divider port map
322 (base_clk, rst_n, cpu_clk, ppu_clk, mem_clk, vga_clk);
324 addr_dec_inst : address_decoder generic map (addr_size, data_size)
\r
325 port map (phi2, mem_clk, r_nw, addr, rom_ce_n, ram_ce_n, ppu_ce_n, apu_ce_n);
\r
327 --mos 6502 cpu instance
328 cpu_inst : mos6502 generic map (data_size, addr_size)
330 dbg_instruction_dummy,
332 dbg_exec_cycle_dummy,
337 dbg_pcl, dbg_pch, dbg_sp_dummy, dbg_x_dummy, dbg_y, dbg_acc,
343 dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w,
346 rst_n, irq_n, nmi_n, dbe, r_nw,
347 phi1, phi2, addr, d_io);
349 --main ROM/RAM instance
350 -- prg_rom_inst : prg_rom generic map (rom_32k, data_size)
351 -- port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);
353 prg_rom_inst : prg_rom generic map (rom_8k, data_size)
354 port map (mem_clk, rom_ce_n, addr(rom_8k - 1 downto 0), d_io);
356 ram_oe_n <= not R_nW;
357 prg_ram_inst : ram generic map (ram_2k, data_size)
358 port map (mem_clk, ram_ce_n, ram_oe_n, R_nW, addr(ram_2k - 1 downto 0), d_io);
361 ppu_inst: ppu port map (
363 dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
365 dbg_ppu_data, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y_dummy ,
373 dbg_disp_nt, dbg_disp_attr ,
374 dbg_disp_ptn_h, dbg_disp_ptn_l_dummy ,
412 ppu_addr_decoder : v_address_decoder generic map (vram_size14, data_size)
413 port map (ppu_clk, mem_clk, rd_n, wr_n, ale, v_addr, vram_ad,
414 nt_v_mirror, pt_ce_n, nt0_ce_n, nt1_ce_n);
416 ---VRAM/CHR ROM instances
417 v_addr (13 downto 8) <= vram_a;
419 --transparent d-latch
420 --ale=1 >> addr latch
\r
421 --ale=0 >> addr output.
\r
423 vram_latch : ls373 generic map (data_size)
424 port map(vga_clk, ale_n, ale, vram_ad, v_addr(7 downto 0));
426 vchr_rom : chr_rom generic map (chr_rom_8k, data_size)
427 port map (mem_clk, pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad);
429 --name table/attr table
430 vram_nt0 : ram generic map (vram_1k, data_size)
431 port map (mem_clk, nt0_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
433 vram_nt1 : ram generic map (vram_1k, data_size)
434 port map (mem_clk, nt1_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
438 port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
442 -----------------------------------------------------------
\r
443 -----------------------------------------------------------
\r
444 ------------------debug pin setting....--------------------
445 -----------------------------------------------------------
\r
446 -----------------------------------------------------------
\r
448 -- dbg_exec_cycle(2 downto 1) <= dbg_vga_x(9 downto 8);
\r
449 dbg_int_d_bus(4 downto 0) <= dbg_s_oam_addr(4 downto 0);
\r
450 dbg_ppu_scrl_y <= dbg_s_oam_data;
\r
451 dbg_exec_cycle(0) <= dbg_nes_x(8);
\r
452 dbg_instruction <= dbg_nes_x(7 downto 0);
\r
453 dbg_exec_cycle(3) <= dbg_emu_ppu_clk;
\r
455 dbg_exec_cycle(4) <= dbg_nes_y(8);
\r
456 dbg_status <= dbg_nes_y(7 downto 0);
\r
458 dbg_ppu_scrl_x(0) <= ale;
\r
459 dbg_ppu_scrl_x(1) <= rd_n;
\r
460 dbg_ppu_scrl_x(2) <= wr_n;
\r
461 dbg_ppu_scrl_x(3) <= nt0_ce_n;
\r
463 -- dbg_ppu_scrl_x(4) <= vga_clk;
\r
464 -- dbg_ppu_scrl_x(5) <= rom_ce_n;
\r
465 -- dbg_ppu_scrl_x(6) <= ram_ce_n;
\r
466 -- dbg_ppu_scrl_x(7) <= addr(15);
\r
467 -- dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);
\r
468 -- dbg_ppu_scrl_y(5 downto 3) <= dbg_plt_ce_rn_wn(2 downto 0);
\r
469 dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;
\r
470 dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;
\r
472 dbg_cpu_clk <= cpu_clk;
\r
473 dbg_mem_clk <= mem_clk;
\r
477 dbg_vram_ad <= vram_ad ;
\r
478 dbg_vram_a <= vram_a ;
\r
480 dbg_sp(7 downto 6) <= dbg_ppu_clk_cnt;
\r
483 -- nmi_n <= dummy_nmi;
\r
484 -- dbg_ppu_ctrl <= dbg_pcl;
\r
485 -- dbg_ppu_mask <= dbg_pch;
\r