2 -- MOTO NES FPGA Common Routines
5 -------------------------------------------------------------
6 -------------------------------------------------------------
7 -------------------- package declaration --------------------
8 -------------------------------------------------------------
9 -------------------------------------------------------------
12 use ieee.std_logic_1164.all;
14 package motonesfpga_common is
16 procedure d_print(msg : string);
18 function conv_hex8(ival : integer) return string;
20 function conv_hex8(ival : std_logic_vector) return string;
22 function conv_hex16(ival : integer) return string;
24 function conv_hex16(ival : std_logic_vector) return string;
26 end motonesfpga_common;
29 -------------------------------------------------------------
30 -------------------------------------------------------------
31 ----------------------- package body ------------------------
32 -------------------------------------------------------------
33 -------------------------------------------------------------
35 package body motonesfpga_common is
37 use ieee.std_logic_unsigned.conv_integer;
39 procedure d_print(msg : string) is
41 --use ieee.std_logic_textio.all;
42 --variable out_l : line;
45 -- writeline(output, out_l);
48 ---ival : 0x0000 - 0xffff
49 function conv_hex8(ival : integer) return string is
50 variable tmp1, tmp2 : integer;
51 variable hex_chr: string (1 to 16) := "0123456789abcdef";
53 tmp2 := (ival mod 16 ** 2) / 16 ** 1;
54 tmp1 := ival mod 16 ** 1;
55 return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
58 function conv_hex8(ival : std_logic_vector) return string is
60 return conv_hex8(conv_integer(ival));
63 function conv_hex16(ival : integer) return string is
64 variable tmp1, tmp2 : integer;
65 variable hex_chr: string (1 to 16) := "0123456789abcdef";
69 return conv_hex8(tmp2) & conv_hex8(tmp1);
72 function conv_hex16(ival : std_logic_vector) return string is
74 return conv_hex16(conv_integer(ival));
77 end motonesfpga_common;
79 -------------------------------------------------------------
80 -------------------------------------------------------------
81 -------------------------------------------------------------
82 ------------------ other common modules ---------------------
83 -------------------------------------------------------------
84 -------------------------------------------------------------
85 -------------------------------------------------------------
87 ----------------------------------------
88 --- d-flipflop with set/reset
89 ----------------------------------------
92 use ieee.std_logic_1164.all;
100 res_n : in std_logic;
101 set_n : in std_logic;
103 d : in std_logic_vector (dsize - 1 downto 0);
104 q : out std_logic_vector (dsize - 1 downto 0)
108 architecture rtl of d_flip_flop is
111 process (clk, res_n, set_n, d)
113 if (res_n = '0') then
114 q <= (others => '0');
115 elsif (set_n = '0') then
117 elsif (rising_edge(clk)) then
126 --------- 1 bit d-flipflop.
128 use ieee.std_logic_1164.all;
130 entity d_flip_flop_bit is
133 res_n : in std_logic;
134 set_n : in std_logic;
141 architecture rtl of d_flip_flop_bit is
144 process (clk, res_n, set_n, d)
146 if (res_n = '0') then
148 elsif (set_n = '0') then
150 elsif (rising_edge(clk)) then
158 ----------------------------------------
160 ----------------------------------------
163 use ieee.std_logic_1164.all;
165 entity tri_state_buffer is
171 d : in std_logic_vector (dsize - 1 downto 0);
172 q : out std_logic_vector (dsize - 1 downto 0)
174 end tri_state_buffer;
176 architecture rtl of tri_state_buffer is
178 q <= d when oe_n = '0' else
182 -------------------------------
183 ------ count up registers -----
184 -------------------------------
186 use ieee.std_logic_1164.all;
188 entity counter_register is
190 dsize : integer := 8;
193 port ( clk : in std_logic;
194 rst_n : in std_logic;
197 d : in std_logic_vector(dsize - 1 downto 0);
198 q : out std_logic_vector(dsize - 1 downto 0)
200 end counter_register;
202 architecture rtl of counter_register is
204 use ieee.std_logic_unsigned.all;
209 clk_p : process (clk, rst_n)
210 variable q_out : std_logic_vector(dsize - 1 downto 0);
212 if (rst_n = '0') then
213 q_out := (others => '0');
214 elsif (rising_edge(clk)) then
217 elsif (ce_n = '0') then
218 q_out := q_out + inc;