de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do

   1 transcript on\r
   2 if {[file exists gate_work]} {\r
   3         vdel -lib gate_work -all\r
   4 }\r
   5 vlib gate_work\r
   6 vmap work gate_work\r
   7 \r
   8 vcom -93 -work work {de1_nes.vho}\r
   9 \r
  10 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/de1_nes/testbench_motones_sim.vhd}\r
  11 \r
  12 vsim -t 10ps +transport_int_delays +transport_path_delays -sdftyp /sim_board=de1_nes_vhd.sdo -L cycloneii -L gate_work -L work testbench_motones_sim\r
  13 \r
  14 #add wave *\r
  15 \r
  16 add wave sim:/testbench_motones_sim/sim_board/rst_n\r
  17 \r
  18 add wave -divider cpu\r
  19 \r
  20 ##add wave sim:/testbench_motones_sim/sim_board/dbg_ppu_clk\r
  21 ##add wave  sim:/testbench_motones_sim/sim_board/dbg_mem_clk\r
  22 \r
  23 add wave sim:/testbench_motones_sim/sim_board/dbg_r_nw\r
  24 \r
  25 add wave sim:/testbench_motones_sim/sim_board/dbg_cpu_clk\r
  26 \r
  27 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_addr\r
  28 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_d_io\r
  29 \r
  30 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_instruction\r
  31 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_int_d_bus\r
  32 \r
  33 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_exec_cycle\r
  34 \r
  35 add wave -divider regs\r
  36 \r
  37 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_index_bus;\r
  38 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc_bus;\r
  39 ##    dbg_pcl, dbg_pch, \r
  40 \r
  41 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
  42 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp\r
  43 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
  44 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_x\r
  45 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_y\r
  46 \r
  47 \r
  48 add wave -divider ppu\r
  49 \r
  50 add wave sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n\r
  51 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
  52 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
  53 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
  54 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr \r
  55 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
  56 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x\r
  57 add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y\r
  58 \r
  59 \r
  60 add wave -divider debug\r
  61 \r
  62 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_idl_h\r
  63 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_idl_l\r
  64 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_dbb_r\r
  65 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_dbb_w\r
  66 \r
  67 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_dec_oe_n\r
  68 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_dec_val\r
  69 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_int_dbus\r
  70 \r
  71 #add wave -divider debug2\r
  72 \r
  73 \r
  74 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_status_val\r
  75 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_stat_we_n\r
  76 \r
  77 view structure\r
  78 view signals\r
  79 #run -all\r
  80 run 10 us\r
  81 \r
  82 #wave zoom range 3339700 ps 5138320 ps\r
  83 wave zoom full\r
  84 \r
  85 #run 12 us\r
  86 \r
  87 #run 1000 us\r
  88 \r
  89 ##wave addcursor 907923400 ps\r
  90 \r