de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do

   1 transcript on\r
   2 if {[file exists gate_work]} {\r
   3         vdel -lib gate_work -all\r
   4 }\r
   5 vlib gate_work\r
   6 vmap work gate_work\r
   7 \r
   8 vcom -93 -work work {de1_nes.vho}\r
   9 \r
  10 vcom -93 -work work {../../testbench_motones_sim.vhd}\r
  11 \r
  12 vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /sim_board=de1_nes_vhd.sdo -L cycloneii -L gate_work -L work testbench_motones_sim\r
  13 \r
  14 #add wave *\r
  15 \r
  16 \r
  17 add wave -divider cpu\r
  18 add wave -label rst_n       sim:/testbench_motones_sim/sim_board/rst_n\r
  19 add wave -label cpu_clk       sim:/testbench_motones_sim/sim_board/dbg_cpu_clk\r
  20 #add wave -label vga_clk   sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(4)\r
  21 #add wave -label mem_clk sim:/testbench_motones_sim/sim_board/dbg_mem_clk\r
  22 \r
  23 \r
  24 \r
  25 add wave -label r_nw       sim:/testbench_motones_sim/sim_board/dbg_r_nw\r
  26 add wave -label addr       -radix hex sim:/testbench_motones_sim/sim_board/dbg_addr\r
  27 add wave -label d_io       -radix hex sim:/testbench_motones_sim/sim_board/dbg_d_io\r
  28 add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/dbg_instruction\r
  29 \r
  30 \r
  31 add wave -divider ce-pins\r
  32 add wave -label rom_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(5)\r
  33 add wave -label ram_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(6)\r
  34 \r
  35 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_int_d_bus\r
  36 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_exec_cycle\r
  37 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ea_carry     \r
  38 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_wait_a58_branch_next     \r
  39 \r
  40 \r
  41 #add wave -divider regs\r
  42 \r
  43 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
  44 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp\r
  45 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
  46 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_x\r
  47 #add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_y\r
  48 \r
  49 \r
  50 add wave -divider ppu\r
  51 add wave -label ppu_clk    sim:/testbench_motones_sim/sim_board/dbg_ppu_clk\r
  52 add wave -label ppu_ce_n          sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n\r
  53 add wave -label ppu_ctrl  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
  54 add wave -label ppu_mask  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
  55 #add wave -label ppu_status   -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
  56 add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
  57 add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
  58 \r
  59 \r
  60 add wave -divider vga_pos\r
  61 #add wave -label nes_x           -radix decimal -unsigned  sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
  62 add wave -label dbg_disp_nt     -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
  63 add wave -label dbg_disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
  64 #add wave -label dbg_disp_ptn_h  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
  65 #add wave -label dbg_disp_ptn_l  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
  66 \r
  67 add wave -divider vram\r
  68 add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0)\r
  69 add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1)\r
  70 add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)\r
  71 add wave -label nt0_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(3)\r
  72 \r
  73 add wave  -radix hex -label v_addr sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
  74 add wave  -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad\r
  75 \r
  76 \r
  77 add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)\r
  78 add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)\r
  79 add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)\r
  80 add wave  -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}\r
  81 add wave  -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}\r
  82 \r
  83 \r
  84 \r
  85 add wave -divider vga_out\r
  86 add wave -label h_sync_n    sim:/testbench_motones_sim/sim_board/v_sync_n\r
  87 add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/h_sync_n\r
  88 add wave -label r           -radix hex sim:/testbench_motones_sim/sim_board/r\r
  89 add wave -label g           -radix hex sim:/testbench_motones_sim/sim_board/g\r
  90 add wave -label b           -radix hex sim:/testbench_motones_sim/sim_board/b\r
  91 \r
  92 \r
  93 view structure\r
  94 view signals\r
  95 #run -all\r
  96 run 8 us\r
  97 \r
  98 #wave zoom range 3339700 ps 5138320 ps\r
  99 wave zoom full\r
 100 \r
 101 #run 12 us\r
 102 \r
 103 #run 1000 us\r
 104 \r
 105 ##wave addcursor 907923400 ps\r
 106 \r