de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do

   1 ##\r
   2 ## run this script on modelsim\r
   3 ## > do de1_nes_run_msim_rtl_vhdl.do\r
   4 ##\r
   5 \r
   6 \r
   7 transcript on\r
   8 if {[file exists rtl_work]} {\r
   9         vdel -lib rtl_work -all\r
  10 }\r
  11 vlib rtl_work\r
  12 vmap work rtl_work\r
  13 \r
  14 vcom -93 -work work {../../motonesfpga_common.vhd}\r
  15 vcom -93 -work work {../../address_decoder.vhd}\r
  16 vcom -93 -work work {../../clock/clock_divider.vhd}\r
  17 vcom -93 -work work {../../mem/ram.vhd}\r
  18 vcom -93 -work work {../../apu/apu.vhd}\r
  19 \r
  20 #ppu block...\r
  21 #vcom -93 -work work {../../mem/chr_rom.vhd}\r
  22 #vcom -93 -work work {../../ppu/ppu.vhd}\r
  23 #vcom -93 -work work {../../ppu/ppu_registers.vhd}\r
  24 #vcom -93 -work work {../../ppu/vga_ppu.vhd}\r
  25 vcom -93 -work work {../../dummy-ppu.vhd}\r
  26 \r
  27 #cpu block...\r
  28 vcom -93 -work work {../../mem/prg_rom.vhd}\r
  29 vcom -93 -work work {../../cpu/cpu_registers.vhd}\r
  30 vcom -93 -work work {../../cpu/alu.vhd}\r
  31 vcom -93 -work work {../../cpu/decoder.vhd}\r
  32 vcom -93 -work work {../../cpu/mos6502.vhd}\r
  33 \r
  34 #vcom -93 -work work {../../dummy-mos6502.vhd}\r
  35 \r
  36 vcom -93 -work work {../../de1_nes.vhd}\r
  37 \r
  38 vcom -93 -work work {../../testbench_motones_sim.vhd}\r
  39 \r
  40 vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L rtl_work -L work testbench_motones_sim\r
  41 \r
  42 \r
  43 add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n;\r
  44 add wave -label nmi_n sim:/testbench_motones_sim/sim_board/cpu_inst/nmi_n;\r
  45 add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw;\r
  46 add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/cpu_clk\r
  47 add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr\r
  48 add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io\r
  49 \r
  50 add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction\r
  51 add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
  52 add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
  53 \r
  54 add wave -divider regs\r
  55 add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
  56 add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
  57 add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q\r
  58 add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
  59 add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
  60 \r
  61 \r
  62 ##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg\r
  63 \r
  64 #add wave -divider ppu\r
  65 #add wave  -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
  66 #add wave  -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
  67 #add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
  68 ##add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
  69 ##add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
  70 #add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
  71 #add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
  72 #add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
  73 ##add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
  74 ##add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
  75 ##add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
  76 ##add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
  77 ##add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
  78 #add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
  79 #add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
  80 #\r
  81 #\r
  82 #add wave -divider ppu_scrl\r
  83 ##add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
  84 ##add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
  85 ##add wave -label ppu_scroll_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt\r
  86 ##add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
  87 ##\r
  88 ##add wave -label ppu_scroll_cnt_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt_ce_n\r
  89 ##add wave -label ppu_scroll_x_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x_we_n\r
  90 ##add wave -label ppu_scroll_y_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y_we_n\r
  91 #add wave -label ppu_scr_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x\r
  92 #add wave -label ppu_scr_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y\r
  93 #\r
  94 #\r
  95 #add wave -divider render\r
  96 ##add wave -label vba_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_x\r
  97 #add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_x\r
  98 ##add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_y\r
  99 #add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_y\r
 100 #\r
 101 #add wave -label ale sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ale\r
 102 #add wave -label rd_n sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/rd_n\r
 103 #add wave -label wr_n sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/wr_n\r
 104 \r
 105 #add wave -label cur_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_x\r
 106 #add wave -label prf_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/prf_x\r
 107 #add wave -label cur_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_y\r
 108 #add wave -label prf_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/prf_y\r
 109 #\r
 110 #add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_nt\r
 111 #add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_attr\r
 112 #add wave -label attr_val -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/attr_val\r
 113 \r
 114 \r
 115 #add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/nes_r \\r
 116 #sim:/testbench_motones_sim/sim_board/ppu_inst/nes_g \\r
 117 #sim:/testbench_motones_sim/sim_board/ppu_inst/nes_b\r
 118 \r
 119 #add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
 120 #add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
 121 \r
 122 \r
 123 \r
 124 #add wave -divider apu\r
 125 #add wave  -label cpu_addr sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
 126 #add wave  -label dma_next_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_next_status\r
 127 #add wave  -label dma_status -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_status\r
 128 #add wave  -label dma_cnt_ce sim:/testbench_motones_sim/sim_board/apu_inst/dma_cnt_ce\r
 129 #add wave  -label rdy sim:/testbench_motones_sim/sim_board/apu_inst/rdy\r
 130 #add wave  -label dma_write_we_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_write_we_n\r
 131 #add wave  -label dma_addr -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/dma_addr\r
 132 #add wave  -label dma_start_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_start_n\r
 133 #add wave  -label dma_end_n sim:/testbench_motones_sim/sim_board/apu_inst/dma_end_n\r
 134 \r
 135 \r
 136 \r
 137 view structure\r
 138 view signals\r
 139 \r
 140 run 8 us\r
 141 #run 1000 us\r
 142 wave zoom full\r
 143 #run 10000 us\r
 144 \r
 145 \r