2 vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L rtl_work -L work testbench_motones_sim
\r
5 add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n;
\r
6 add wave -label nmi_n sim:/testbench_motones_sim/sim_board/cpu_inst/nmi_n;
\r
7 add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw;
\r
8 add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/cpu_clk
\r
9 add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr
\r
10 add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io
\r
13 #add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction
\r
14 #add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus
\r
15 #add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle
\r
16 #add wave -label ea_carry -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/dec_inst/ea_carry
\r
18 #add wave -divider cpu_regs
\r
19 #add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q
\r
20 #add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val
\r
21 #add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q
\r
22 #add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q
\r
23 #add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q
\r
25 #add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pcl_inst/q
\r
26 #add wave -label pch -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pch_inst/q
\r
27 #add wave -label idl_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/idl_l/q
\r
30 add wave -divider ppu
\r
31 #add wave -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr
\r
32 #add wave -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d
\r
33 add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk
\r
34 add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n
\r
35 add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl
\r
36 add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask
\r
37 add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status
\r
38 add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr
\r
39 add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data
\r
40 add wave -label oam_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/oam_addr
\r
41 add wave -label oam_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/oam_data
\r
42 add wave -label ppu_scr_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x
\r
43 add wave -label ppu_scr_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y
\r
45 add wave -divider vram
\r
46 add wave -label emu_ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/emu_ppu_clk
\r
47 add wave -label ale_n sim:/testbench_motones_sim/sim_board/ppu_inst/ale_n
\r
48 add wave -label rd_n sim:/testbench_motones_sim/sim_board/ppu_inst/rd_n
\r
49 add wave -label wr_n sim:/testbench_motones_sim/sim_board/ppu_inst/wr_n
\r
50 add wave -label v_addr -radix hex sim:/testbench_motones_sim/sim_board/v_addr
\r
51 add wave -label v_data -radix hex sim:/testbench_motones_sim/sim_board/v_data
\r
53 add wave -divider render
\r
54 #add wave -label vba_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_x
\r
55 add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_x
\r
56 #add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_y
\r
57 add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_y
\r
58 #add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_nt
\r
59 #add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_attr
\r
60 #add wave -label attr_val -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/attr_val
\r
63 #add wave -divider vga
\r
64 #add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n
\r
65 #add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n
\r
66 #add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/r
\r
67 #add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/g
\r
68 #add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/b
\r
73 #add wave -radix hex sim:/testbench_motones_sim/sim_board/clock_inst/*
\r
75 #add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/dec_inst/*
\r
77 #add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/ad_calc_inst/*
\r
79 #add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/alu_inst/*
\r
81 #add wave -divider apu
\r
82 #add wave -radix hex sim:/testbench_motones_sim/sim_board/apu_inst/*
\r
84 #add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_addr_decoder/*
\r
85 #add wave -radix hex sim:/testbench_motones_sim/sim_board/vram_nt0/*
\r
87 add wave -divider ppu
\r
88 #add wave -label emu_ppu_mem_clk sim:/testbench_motones_sim/sim_board/emu_ppu_mem_clk
\r
92 #add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/*
\r
93 #add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/*
\r
96 #add wave -radix hex sim:/testbench_motones_sim/sim_board/vram_latch/*
\r
97 #add wave -label v_addr_ppu -radix hex sim:/testbench_motones_sim/sim_board/v_addr_ppu
\r