de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do

   1 \r
   2 vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L rtl_work -L work testbench_motones_sim\r
   3 \r
   4 \r
   5 add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n;\r
   6 add wave -label nmi_n sim:/testbench_motones_sim/sim_board/cpu_inst/nmi_n;\r
   7 add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw;\r
   8 add wave -label cpu_clk sim:/testbench_motones_sim/sim_board/cpu_clk\r
   9 add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr\r
  10 add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io\r
  11 \r
  12 #cpu debug...\r
  13 #add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction\r
  14 #add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
  15 #add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
  16 #add wave -label ea_carry -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/dec_inst/ea_carry\r
  17 \r
  18 #add wave -divider cpu_regs\r
  19 #add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
  20 #add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
  21 #add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q\r
  22 #add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
  23 #add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
  24 #\r
  25 #add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pcl_inst/q\r
  26 #add wave -label pch -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pch_inst/q\r
  27 #add wave -label idl_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/idl_l/q\r
  28 \r
  29 \r
  30 add wave -divider ppu\r
  31 #add wave -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
  32 #add wave -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
  33 add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
  34 add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
  35 add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
  36 add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
  37 add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
  38 add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
  39 add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
  40 add wave -label oam_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/oam_addr\r
  41 add wave -label oam_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/oam_data\r
  42 add wave -label ppu_scr_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x\r
  43 add wave -label ppu_scr_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y\r
  44 \r
  45 add wave -divider vram\r
  46 add wave -label emu_ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/emu_ppu_clk\r
  47 add wave -label ale sim:/testbench_motones_sim/sim_board/ppu_inst/ale\r
  48 add wave -label rd_n sim:/testbench_motones_sim/sim_board/ppu_inst/rd_n\r
  49 add wave -label wr_n sim:/testbench_motones_sim/sim_board/ppu_inst/wr_n\r
  50 add wave -label vram_a -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vram_a\r
  51 add wave -label vram_ad -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vram_ad\r
  52 add wave -label v_addr -radix hex sim:/testbench_motones_sim/sim_board/v_addr\r
  53 \r
  54 \r
  55 #add wave -divider render\r
  56 ##add wave -label vba_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_x\r
  57 #add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_x\r
  58 ##add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_y\r
  59 #add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_y\r
  60 ##add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_nt\r
  61 ##add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_attr\r
  62 ##add wave -label attr_val -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/attr_val\r
  63 #\r
  64 #\r
  65 #add wave -divider vga\r
  66 #add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
  67 #add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
  68 #add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/r\r
  69 #add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/g\r
  70 #add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/b\r
  71 \r
  72 \r
  73 \r
  74 #add wave -divider\r
  75 #add wave -radix hex  sim:/testbench_motones_sim/sim_board/clock_inst/*\r
  76 #add wave -divider\r
  77 #add wave -radix hex  sim:/testbench_motones_sim/sim_board/cpu_inst/dec_inst/*\r
  78 #add wave -divider\r
  79 #add wave -radix hex  sim:/testbench_motones_sim/sim_board/cpu_inst/ad_calc_inst/*\r
  80 #add wave -divider\r
  81 #add wave -radix hex  sim:/testbench_motones_sim/sim_board/cpu_inst/alu_inst/*\r
  82 \r
  83 #add wave -divider apu\r
  84 #add wave  -radix hex  sim:/testbench_motones_sim/sim_board/apu_inst/*\r
  85 \r
  86 add wave -divider ppu\r
  87 #add wave  -radix hex  sim:/testbench_motones_sim/sim_board/ppu_inst/*\r
  88 \r
  89 #add wave -label reset_n  sim:/testbench_motones_sim/sim_board/clock_inst/reset_n\r
  90 #add wave -label base_clk  sim:/testbench_motones_sim/sim_board/clock_inst/base_clk\r
  91 #add wave -label vga_clk  sim:/testbench_motones_sim/sim_board/clock_inst/vga_clk\r
  92 #add wave -label ppu_clk  sim:/testbench_motones_sim/sim_board/clock_inst/ppu_clk\r
  93 #add wave -label loop16  -radix hex  sim:/testbench_motones_sim/sim_board/clock_inst/loop16\r
  94 #add wave -label emu_ppu_clk  sim:/testbench_motones_sim/sim_board/clock_inst/emu_ppu_clk\r
  95 #add wave -label cpu_clk  sim:/testbench_motones_sim/sim_board/clock_inst/cpu_clk\r
  96 #add wave -label cpu_mem_clk  sim:/testbench_motones_sim/sim_board/clock_inst/cpu_mem_clk\r
  97 #add wave -label cpu_recv_clk  sim:/testbench_motones_sim/sim_board/clock_inst/cpu_recv_clk\r
  98 \r
  99 view structure\r
 100 view signals\r
 101 \r
 102 run 6 us\r
 103 wave zoom full\r
 104 run 60 us\r
 105 \r