[motonesfpga/motonesfpga.git] / de1_nes / simulation / modelsim / motones_modelsim.mpf

; Copyright 1991-2009 Mentor Graphics Corporation\r
;\r
; All Rights Reserved.\r
;\r
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF \r
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\r
;   \r
\r
[Library]\r
std = $MODEL_TECH/../std\r
ieee = $MODEL_TECH/../ieee\r
verilog = $MODEL_TECH/../verilog\r
vital2000 = $MODEL_TECH/../vital2000\r
std_developerskit = $MODEL_TECH/../std_developerskit\r
synopsys = $MODEL_TECH/../synopsys\r
modelsim_lib = $MODEL_TECH/../modelsim_lib\r
sv_std = $MODEL_TECH/../sv_std\r
\r
; Altera Primitive libraries\r
;\r
; VHDL Section\r
;\r
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf\r
altera = $MODEL_TECH/../altera/vhdl/altera\r
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim\r
lpm = $MODEL_TECH/../altera/vhdl/220model\r
220model = $MODEL_TECH/../altera/vhdl/220model\r
max = $MODEL_TECH/../altera/vhdl/max\r
maxii = $MODEL_TECH/../altera/vhdl/maxii\r
maxv = $MODEL_TECH/../altera/vhdl/maxv\r
stratix = $MODEL_TECH/../altera/vhdl/stratix\r
stratixii = $MODEL_TECH/../altera/vhdl/stratixii\r
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx\r
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii\r
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii\r
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv\r
cyclone = $MODEL_TECH/../altera/vhdl/cyclone\r
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii\r
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii\r
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils\r
sgate = $MODEL_TECH/../altera/vhdl/sgate\r
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx\r
altgxb = $MODEL_TECH/../altera/vhdl/altgxb\r
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb\r
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi\r
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi\r
arriaii = $MODEL_TECH/../altera/vhdl/arriaii\r
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi\r
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip\r
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz\r
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi\r
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip\r
arriagx = $MODEL_TECH/../altera/vhdl/arriagx\r
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb\r
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv\r
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi\r
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip\r
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv\r
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi\r
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip\r
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive\r
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi\r
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip\r
stratixv = $MODEL_TECH/../altera/vhdl/stratixv\r
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi\r
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip\r
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz\r
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi\r
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip\r
arriav = $MODEL_TECH/../altera/vhdl/arriav\r
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev\r
;\r
; Verilog Section\r
;\r
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf\r
altera_ver = $MODEL_TECH/../altera/verilog/altera\r
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim\r
lpm_ver = $MODEL_TECH/../altera/verilog/220model\r
220model_ver = $MODEL_TECH/../altera/verilog/220model\r
max_ver = $MODEL_TECH/../altera/verilog/max\r
maxii_ver = $MODEL_TECH/../altera/verilog/maxii\r
maxv_ver = $MODEL_TECH/../altera/verilog/maxv\r
stratix_ver = $MODEL_TECH/../altera/verilog/stratix\r
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii\r
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx\r
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx\r
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii\r
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii\r
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv\r
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone\r
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii\r
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii\r
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils\r
sgate_ver = $MODEL_TECH/../altera/verilog/sgate\r
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx\r
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb\r
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb\r
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi\r
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi\r
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii\r
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi\r
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip\r
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz\r
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi\r
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip\r
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii\r
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii\r
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv\r
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi\r
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip\r
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv\r
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi\r
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip\r
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz\r
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi\r
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip\r
arriav_ver = $MODEL_TECH/../altera/verilog/arriav\r
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi\r
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip\r
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev\r
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi\r
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip\r
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv\r
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi\r
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip\r
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive\r
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\r
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\r
\r
work = gate_work\r
[vcom]\r
; VHDL93 variable selects language version as the default. \r
; Default is VHDL-2002.\r
; Value of 0 or 1987 for VHDL-1987.\r
; Value of 1 or 1993 for VHDL-1993.\r
; Default or value of 2 or 2002 for VHDL-2002.\r
; Default or value of 3 or 2008 for VHDL-2008.\r
VHDL93 = 2002\r
\r
; Show source line containing error. Default is off.\r
; Show_source = 1\r
\r
; Turn off unbound-component warnings. Default is on.\r
; Show_Warning1 = 0\r
\r
; Turn off process-without-a-wait-statement warnings. Default is on.\r
; Show_Warning2 = 0\r
\r
; Turn off null-range warnings. Default is on.\r
; Show_Warning3 = 0\r
\r
; Turn off no-space-in-time-literal warnings. Default is on.\r
; Show_Warning4 = 0\r
\r
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\r
; Show_Warning5 = 0\r
\r
; Turn off optimization for IEEE std_logic_1164 package. Default is on.\r
; Optimize_1164 = 0\r
\r
; Turn on resolving of ambiguous function overloading in favor of the\r
; "explicit" function declaration (not the one automatically created by\r
; the compiler for each type declaration). Default is off.\r
; The .ini file has Explicit enabled so that std_logic_signed/unsigned\r
; will match the behavior of synthesis tools.\r
Explicit = 1\r
\r
; Turn off acceleration of the VITAL packages. Default is to accelerate.\r
; NoVital = 1\r
\r
; Turn off VITAL compliance checking. Default is checking on.\r
; NoVitalCheck = 1\r
\r
; Ignore VITAL compliance checking errors. Default is to not ignore.\r
; IgnoreVitalErrors = 1\r
\r
; Turn off VITAL compliance checking warnings. Default is to show warnings.\r
; Show_VitalChecksWarnings = 0\r
\r
; Keep silent about case statement static warnings.\r
; Default is to give a warning.\r
; NoCaseStaticError = 1\r
\r
; Keep silent about warnings caused by aggregates that are not locally static.\r
; Default is to give a warning.\r
; NoOthersStaticError = 1\r
\r
; Turn off inclusion of debugging info within design units.\r
; Default is to include debugging info.\r
; NoDebug = 1\r
\r
; Turn off "Loading..." messages. Default is messages on.\r
; Quiet = 1\r
\r
; Turn on some limited synthesis rule compliance checking. Checks only:\r
;    -- signals used (read) by a process must be in the sensitivity list\r
; CheckSynthesis = 1\r
\r
; Activate optimizations on expressions that do not involve signals,\r
; waits, or function/procedure/task invocations. Default is off.\r
; ScalarOpts = 1\r
\r
; Require the user to specify a configuration for all bindings,\r
; and do not generate a compile time default binding for the\r
; component. This will result in an elaboration error of\r
; 'component not bound' if the user fails to do so. Avoids the rare\r
; issue of a false dependency upon the unused default binding.\r
; RequireConfigForAllDefaultBinding = 1\r
\r
; Inhibit range checking on subscripts of arrays. Range checking on\r
; scalars defined with subtypes is inhibited by default.\r
; NoIndexCheck = 1\r
\r
; Inhibit range checks on all (implicit and explicit) assignments to\r
; scalar objects defined with subtypes.\r
; NoRangeCheck = 1\r
\r
[vlog]\r
\r
; Turn off inclusion of debugging info within design units.\r
; Default is to include debugging info.\r
; NoDebug = 1\r
\r
; Turn off "loading..." messages. Default is messages on.\r
; Quiet = 1\r
\r
; Turn on Verilog hazard checking (order-dependent accessing of global vars).\r
; Default is off.\r
; Hazard = 1\r
\r
; Turn on converting regular Verilog identifiers to uppercase. Allows case\r
; insensitivity for module names. Default is no conversion.\r
; UpCase = 1\r
\r
; Turn on incremental compilation of modules. Default is off.\r
; Incremental = 1\r
\r
; Turns on lint-style checking.\r
; Show_Lint = 1\r
\r
[vsim]\r
; Simulator resolution\r
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\r
Resolution = ps\r
\r
; User time unit for run commands\r
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\r
; unit specified for Resolution. For example, if Resolution is 100ps,\r
; then UserTimeUnit defaults to ps.\r
; Should generally be set to default.\r
UserTimeUnit = default\r
\r
; Default run length\r
RunLength = 80 ps\r
\r
; Maximum iterations that can be run without advancing simulation time\r
IterationLimit = 5000\r
\r
; Directive to license manager:\r
; vhdl          Immediately reserve a VHDL license\r
; vlog          Immediately reserve a Verilog license\r
; plus          Immediately reserve a VHDL and Verilog license\r
; nomgc         Do not look for Mentor Graphics Licenses\r
; nomti         Do not look for Model Technology Licenses\r
; noqueue       Do not wait in the license queue when a license isn't available\r
; viewsim       Try for viewer license but accept simulator license(s) instead\r
;               of queuing for viewer license\r
; License = plus\r
\r
; Stop the simulator after a VHDL/Verilog assertion message\r
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal\r
BreakOnAssertion = 3\r
\r
; Assertion Message Format\r
; %S - Severity Level \r
; %R - Report Message\r
; %T - Time of assertion\r
; %D - Delta\r
; %I - Instance or Region pathname (if available)\r
; %% - print '%' character\r
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"\r
\r
; Assertion File - alternate file for storing VHDL/Verilog assertion messages\r
; AssertFile = assert.log\r
\r
; Default radix for all windows and commands...\r
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\r
DefaultRadix = symbolic\r
\r
; VSIM Startup command\r
; Startup = do startup.do\r
\r
; File for saving command transcript\r
TranscriptFile = transcript\r
\r
; File for saving command history\r
; CommandHistory = cmdhist.log\r
\r
; Specify whether paths in simulator commands should be described\r
; in VHDL or Verilog format.\r
; For VHDL, PathSeparator = /\r
; For Verilog, PathSeparator = .\r
; Must not be the same character as DatasetSeparator.\r
PathSeparator = /\r
\r
; Specify the dataset separator for fully rooted contexts.\r
; The default is ':'. For example, sim:/top\r
; Must not be the same character as PathSeparator.\r
DatasetSeparator = :\r
\r
; Disable VHDL assertion messages\r
; IgnoreNote = 1\r
; IgnoreWarning = 1\r
; IgnoreError = 1\r
; IgnoreFailure = 1\r
\r
; Default force kind. May be freeze, drive, deposit, or default\r
; or in other terms, fixed, wired, or charged.\r
; A value of "default" will use the signal kind to determine the\r
; force kind, drive for resolved signals, freeze for unresolved signals\r
; DefaultForceKind = freeze\r
\r
; If zero, open files when elaborated; otherwise, open files on\r
; first read or write.  Default is 0.\r
; DelayFileOpen = 1\r
\r
; Control VHDL files opened for write.\r
;   0 = Buffered, 1 = Unbuffered\r
UnbufferedOutput = 0\r
\r
; Control the number of VHDL files open concurrently.\r
; This number should always be less than the current ulimit\r
; setting for max file descriptors.\r
;   0 = unlimited\r
ConcurrentFileLimit = 40\r
\r
; Control the number of hierarchical regions displayed as\r
; part of a signal name shown in the Wave window.\r
; A value of zero tells VSIM to display the full name.\r
; The default is 0.\r
; WaveSignalNameWidth = 0\r
\r
; Turn off warnings from the std_logic_arith, std_logic_unsigned\r
; and std_logic_signed packages.\r
; StdArithNoWarnings = 1\r
\r
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\r
; NumericStdNoWarnings = 1\r
\r
; Control the format of the (VHDL) FOR generate statement label\r
; for each iteration.  Do not quote it.\r
; The format string here must contain the conversion codes %s and %d,\r
; in that order, and no other conversion codes.  The %s represents\r
; the generate_label; the %d represents the generate parameter value\r
; at a particular generate iteration (this is the position number if\r
; the generate parameter is of an enumeration type).  Embedded whitespace\r
; is allowed (but discouraged); leading and trailing whitespace is ignored.\r
; Application of the format must result in a unique scope name over all\r
; such names in the design so that name lookup can function properly.\r
; GenerateFormat = %s__%d\r
\r
; Specify whether checkpoint files should be compressed.\r
; The default is 1 (compressed).\r
; CheckpointCompressMode = 0\r
\r
; List of dynamically loaded objects for Verilog PLI applications\r
; Veriuser = veriuser.sl\r
\r
; Specify default options for the restart command. Options can be one\r
; or more of: -force -nobreakpoint -nolist -nolog -nowave\r
; DefaultRestartOptions = -force\r
\r
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\r
; (> 500 megabyte memory footprint). Default is disabled.\r
; Specify number of megabytes to lock.\r
; LockedMemory = 1000\r
\r
; Turn on (1) or off (0) WLF file compression.\r
; The default is 1 (compress WLF file).\r
; WLFCompress = 0\r
\r
; Specify whether to save all design hierarchy (1) in the WLF file\r
; or only regions containing logged signals (0).\r
; The default is 0 (save only regions with logged signals).\r
; WLFSaveAllRegions = 1\r
\r
; WLF file time limit.  Limit WLF file by time, as closely as possible,\r
; to the specified amount of simulation time.  When the limit is exceeded\r
; the earliest times get truncated from the file.\r
; If both time and size limits are specified the most restrictive is used.\r
; UserTimeUnits are used if time units are not specified.\r
; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}\r
; WLFTimeLimit = 0\r
\r
; WLF file size limit.  Limit WLF file size, as closely as possible,\r
; to the specified number of megabytes.  If both time and size limits\r
; are specified then the most restrictive is used.\r
; The default is 0 (no limit).\r
; WLFSizeLimit = 1000\r
\r
; Specify whether or not a WLF file should be deleted when the\r
; simulation ends.  A value of 1 will cause the WLF file to be deleted.\r
; The default is 0 (do not delete WLF file when simulation ends).\r
WLFDeleteOnQuit = 1\r
\r
; Automatic SDF compilation\r
; Disables automatic compilation of SDF files in flows that support it.\r
; Default is on, uncomment to turn off.\r
; NoAutoSDFCompile = 1\r
\r
[lmc]\r
\r
[msg_system]\r
; Change a message severity or suppress a message.\r
; The format is: <msg directive> = <msg number>[,<msg number>...]\r
; Examples:\r
;   note = 3009\r
;   warning = 3033\r
;   error = 3010,3016\r
;   fatal = 3016,3033\r
;   suppress = 3009,3016,3043\r
; The command verror <msg number> can be used to get the complete\r
; description of a message.\r
\r
; Control transcripting of elaboration/runtime messages.\r
; The default is to have messages appear in the transcript and \r
; recorded in the wlf file (messages that are recorded in the\r
; wlf file can be viewed in the MsgViewer).  The other settings\r
; are to send messages only to the transcript or only to the \r
; wlf file.  The valid values are\r
;    both  {default}\r
;    tran  {transcript only}\r
;    wlf   {wlf file only}\r
; msgmode = both\r
[Project]\r
; Warning -- Do not edit the project properties directly.\r
;            Property names are dynamic in nature and property\r
;            values have special syntax.  Changing property data directly\r
;            can result in a corrupt MPF file.  All project properties\r
;            can be modified through project window dialogs.\r
Project_Version = 6\r
Project_DefaultLib = work\r
Project_SortMethod = unused\r
Project_Files_Count = 1\r
Project_File_0 = D:/daisuke/nes/repo/motonesfpga/de1_nes/simulation/modelsim/de1_nes.vho\r
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002\r
Project_Sim_Count = 0\r
Project_Folder_Count = 0\r
Echo_Compile_Output = 0\r
Save_Compile_Report = 1\r
Project_Opt_Count = 0\r
ForceSoftPaths = 0\r
ProjectStatusDelay = 5000\r
VERILOG_DoubleClick = Edit\r
VERILOG_CustomDoubleClick = \r
SYSTEMVERILOG_DoubleClick = Edit\r
SYSTEMVERILOG_CustomDoubleClick = \r
VHDL_DoubleClick = Edit\r
VHDL_CustomDoubleClick = \r
PSL_DoubleClick = Edit\r
PSL_CustomDoubleClick = \r
TEXT_DoubleClick = Edit\r
TEXT_CustomDoubleClick = \r
SYSTEMC_DoubleClick = Edit\r
SYSTEMC_CustomDoubleClick = \r
TCL_DoubleClick = Edit\r
TCL_CustomDoubleClick = \r
MACRO_DoubleClick = Edit\r
MACRO_CustomDoubleClick = \r
VCD_DoubleClick = Edit\r
VCD_CustomDoubleClick = \r
SDF_DoubleClick = Edit\r
SDF_CustomDoubleClick = \r
XML_DoubleClick = Edit\r
XML_CustomDoubleClick = \r
LOGFILE_DoubleClick = Edit\r
LOGFILE_CustomDoubleClick = \r
UCDB_DoubleClick = Edit\r
UCDB_CustomDoubleClick = \r
UPF_DoubleClick = Edit\r
UPF_CustomDoubleClick = \r
PCF_DoubleClick = Edit\r
PCF_CustomDoubleClick = \r
PROJECT_DoubleClick = Edit\r
PROJECT_CustomDoubleClick = \r
VRM_DoubleClick = Edit\r
VRM_CustomDoubleClick = \r
DEBUGDATABASE_DoubleClick = Edit\r
DEBUGDATABASE_CustomDoubleClick = \r
DEBUGARCHIVE_DoubleClick = Edit\r
DEBUGARCHIVE_CustomDoubleClick = \r
Project_Major_Version = 10\r
Project_Minor_Version = 1\r