disas/nanomips.cpp

   1 /*
   2  *  Source file for nanoMIPS disassembler component of QEMU
   3  *
   4  *  Copyright (C) 2018  Wave Computing, Inc.
   5  *  Copyright (C) 2018  Matthew Fortune <matthew.fortune@mips.com>
   6  *  Copyright (C) 2018  Aleksandar Markovic <amarkovic@wavecomp.com>
   7  *
   8  *  This program is free software: you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation, either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
  20  *
  21  */
  22
  23 /*
  24  *  Documentation used while implementing this component:
  25  *
  26  *  [1] "MIPS® Architecture Base: nanoMIPS32(tm) Instruction Set Technical
  27  *      Reference Manual", Revision 01.01, April 27, 2018
  28  */
  29
  30 extern "C" {
  31 #include "qemu/osdep.h"
  32 #include "disas/bfd.h"
  33 }
  34
  35 #include <cstring>
  36 #include <stdexcept>
  37 #include <sstream>
  38 #include <stdio.h>
  39 #include <stdarg.h>
  40
  41 #include "nanomips.h"
  42
  43 #define IMGASSERTONCE(test)
  44
  45
  46 int nanomips_dis(char *buf,
  47                  unsigned address,
  48                  unsigned short one,
  49                  unsigned short two,
  50                  unsigned short three)
  51 {
  52     std::string disasm;
  53     uint16 bits[3] = {one, two, three};
  54
  55     NMD::TABLE_ENTRY_TYPE type;
  56     NMD d(address, NMD::ALL_ATTRIBUTES);
  57     int size = d.Disassemble(bits, disasm, type);
  58
  59     strcpy(buf, disasm.c_str());
  60     return size;
  61 }
  62
  63 int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info)
  64 {
  65     int status;
  66     bfd_byte buffer[2];
  67     uint16_t insn1 = 0, insn2 = 0, insn3 = 0;
  68     char buf[200];
  69
  70     info->bytes_per_chunk = 2;
  71     info->display_endian = info->endian;
  72     info->insn_info_valid = 1;
  73     info->branch_delay_insns = 0;
  74     info->data_size = 0;
  75     info->insn_type = dis_nonbranch;
  76     info->target = 0;
  77     info->target2 = 0;
  78
  79     status = (*info->read_memory_func)(memaddr, buffer, 2, info);
  80     if (status != 0) {
  81         (*info->memory_error_func)(status, memaddr, info);
  82         return -1;
  83     }
  84
  85     if (info->endian == BFD_ENDIAN_BIG) {
  86         insn1 = bfd_getb16(buffer);
  87     } else {
  88         insn1 = bfd_getl16(buffer);
  89     }
  90     (*info->fprintf_func)(info->stream, "%04x ", insn1);
  91
  92     /* Handle 32-bit opcodes.  */
  93     if ((insn1 & 0x1000) == 0) {
  94         status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info);
  95         if (status != 0) {
  96             (*info->memory_error_func)(status, memaddr + 2, info);
  97             return -1;
  98         }
  99
 100         if (info->endian == BFD_ENDIAN_BIG) {
 101             insn2 = bfd_getb16(buffer);
 102         } else {
 103             insn2 = bfd_getl16(buffer);
 104         }
 105         (*info->fprintf_func)(info->stream, "%04x ", insn2);
 106     } else {
 107         (*info->fprintf_func)(info->stream, "     ");
 108     }
 109     /* Handle 48-bit opcodes.  */
 110     if ((insn1 >> 10) == 0x18) {
 111         status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info);
 112         if (status != 0) {
 113             (*info->memory_error_func)(status, memaddr + 4, info);
 114             return -1;
 115         }
 116
 117         if (info->endian == BFD_ENDIAN_BIG) {
 118             insn3 = bfd_getb16(buffer);
 119         } else {
 120             insn3 = bfd_getl16(buffer);
 121         }
 122         (*info->fprintf_func)(info->stream, "%04x ", insn3);
 123     } else {
 124         (*info->fprintf_func)(info->stream, "     ");
 125     }
 126
 127     int length = nanomips_dis(buf, memaddr, insn1, insn2, insn3);
 128
 129     /* FIXME: Should probably use a hash table on the major opcode here.  */
 130
 131     (*info->fprintf_func) (info->stream, "%s", buf);
 132     if (length > 0) {
 133         return length / 8;
 134     }
 135
 136     info->insn_type = dis_noninsn;
 137
 138     return insn3 ? 6 : insn2 ? 4 : 2;
 139 }
 140
 141
 142 namespace img
 143 {
 144     address addr32(address a)
 145     {
 146         return a;
 147     }
 148
 149     std::string format(const char *format, ...)
 150     {
 151         char buffer[256];
 152         va_list args;
 153         va_start(args, format);
 154         int err = vsprintf(buffer, format, args);
 155         if (err < 0) {
 156             perror(buffer);
 157         }
 158         va_end(args);
 159         return buffer;
 160     }
 161
 162     std::string format(const char *format,
 163                        std::string s)
 164     {
 165         char buffer[256];
 166
 167         sprintf(buffer, format, s.c_str());
 168
 169         return buffer;
 170     }
 171
 172     std::string format(const char *format,
 173                        std::string s1,
 174                        std::string s2)
 175     {
 176         char buffer[256];
 177
 178         sprintf(buffer, format, s1.c_str(), s2.c_str());
 179
 180         return buffer;
 181     }
 182
 183     std::string format(const char *format,
 184                        std::string s1,
 185                        std::string s2,
 186                        std::string s3)
 187     {
 188         char buffer[256];
 189
 190         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str());
 191
 192         return buffer;
 193     }
 194
 195     std::string format(const char *format,
 196                        std::string s1,
 197                        std::string s2,
 198                        std::string s3,
 199                        std::string s4)
 200     {
 201         char buffer[256];
 202
 203         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),
 204                                 s4.c_str());
 205
 206         return buffer;
 207     }
 208
 209     std::string format(const char *format,
 210                        std::string s1,
 211                        std::string s2,
 212                        std::string s3,
 213                        std::string s4,
 214                        std::string s5)
 215     {
 216         char buffer[256];
 217
 218         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),
 219                                 s4.c_str(), s5.c_str());
 220
 221         return buffer;
 222     }
 223
 224     std::string format(const char *format,
 225                        uint64 d,
 226                        std::string s2)
 227     {
 228         char buffer[256];
 229
 230         sprintf(buffer, format, d, s2.c_str());
 231
 232         return buffer;
 233     }
 234
 235     std::string format(const char *format,
 236                        std::string s1,
 237                        uint64 d,
 238                        std::string s2)
 239     {
 240         char buffer[256];
 241
 242         sprintf(buffer, format, s1.c_str(), d, s2.c_str());
 243
 244         return buffer;
 245     }
 246
 247     std::string format(const char *format,
 248                        std::string s1,
 249                        std::string s2,
 250                        uint64 d)
 251     {
 252         char buffer[256];
 253
 254         sprintf(buffer, format, s1.c_str(), s2.c_str(), d);
 255
 256         return buffer;
 257     }
 258
 259     char as_char(int c)
 260     {
 261         return static_cast<char>(c);
 262     }
 263 };
 264
 265
 266 std::string to_string(img::address a)
 267 {
 268     char buffer[256];
 269     sprintf(buffer, "0x%" PRIx64, a);
 270     return buffer;
 271 }
 272
 273
 274 uint64 extract_bits(uint64 data, uint32 bit_offset, uint32 bit_size)
 275 {
 276     return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size);
 277 }
 278
 279
 280 int64 sign_extend(int64 data, int msb)
 281 {
 282     uint64 shift = 63 - msb;
 283     return (data << shift) >> shift;
 284 }
 285
 286
 287 uint64 NMD::renumber_registers(uint64 index, uint64 *register_list,
 288                                size_t register_list_size)
 289 {
 290     if (index < register_list_size) {
 291         return register_list[index];
 292     }
 293
 294     throw std::runtime_error(img::format(
 295                    "Invalid register mapping index %" PRIu64
 296                    ", size of list = %zu",
 297                    index, register_list_size));
 298 }
 299
 300
 301 /*
 302  * NMD::decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type
 303  *
 304  *   Map a 4-bit code to the 5-bit register space according to this pattern:
 305  *
 306  *                              1                   0
 307  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 308  *                    | | | | | | | | | | | | | | | |
 309  *                    | | | | | | | | | | | | | | | |
 310  *                    | | | | | | | | | | | └---------------┐
 311  *                    | | | | | | | | | | └---------------┐ |
 312  *                    | | | | | | | | | └---------------┐ | |
 313  *                    | | | | | | | | └---------------┐ | | |
 314  *                    | | | | | | | |         | | | | | | | |
 315  *                    | | | | | | | |         | | | | | | | |
 316  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 317  *      3                   2                   1                   0
 318  *
 319  *   Used in handling following instructions:
 320  *
 321  *     - ADDU[4X4]
 322  *     - LW[4X4]
 323  *     - MOVEP[REV]
 324  *     - MUL[4X4]
 325  *     - SW[4X4]
 326  */
 327 uint64 NMD::decode_gpr_gpr4(uint64 d)
 328 {
 329     static uint64 register_list[] = {  8,  9, 10, 11,  4,  5,  6,  7,
 330                                       16, 17, 18, 19, 20, 21, 22, 23 };
 331     return renumber_registers(d, register_list,
 332                sizeof(register_list) / sizeof(register_list[0]));
 333 }
 334
 335
 336 /*
 337  * NMD::decode_gpr_gpr4_zero() - decoder for 'gpr4.zero' gpr encoding type
 338  *
 339  *   Map a 4-bit code to the 5-bit register space according to this pattern:
 340  *
 341  *                              1                   0
 342  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 343  *                    | | | | | | | | | | | | | | | |
 344  *                    | | | | | | | | | | | | └---------------------┐
 345  *                    | | | | | | | | | | | └---------------┐       |
 346  *                    | | | | | | | | | | └---------------┐ |       |
 347  *                    | | | | | | | | | └---------------┐ | |       |
 348  *                    | | | | | | | | └---------------┐ | | |       |
 349  *                    | | | | | | | |           | | | | | | |       |
 350  *                    | | | | | | | |           | | | | | | |       |
 351  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 352  *      3                   2                   1                   0
 353  *
 354  *   This pattern is the same one used for 'gpr4' gpr encoding type, except for
 355  * the input value 3, that is mapped to the output value 0 instead of 11.
 356  *
 357  *   Used in handling following instructions:
 358  *
 359  *     - MOVE.BALC
 360  *     - MOVEP
 361  *     - SW[4X4]
 362  */
 363 uint64 NMD::decode_gpr_gpr4_zero(uint64 d)
 364 {
 365     static uint64 register_list[] = {  8,  9, 10,  0,  4,  5,  6,  7,
 366                                       16, 17, 18, 19, 20, 21, 22, 23 };
 367     return renumber_registers(d, register_list,
 368                sizeof(register_list) / sizeof(register_list[0]));
 369 }
 370
 371
 372 /*
 373  * NMD::decode_gpr_gpr3() - decoder for 'gpr3' gpr encoding type
 374  *
 375  *   Map a 3-bit code to the 5-bit register space according to this pattern:
 376  *
 377  *                            7 6 5 4 3 2 1 0
 378  *                            | | | | | | | |
 379  *                            | | | | | | | |
 380  *                            | | | └-----------------------┐
 381  *                            | | └-----------------------┐ |
 382  *                            | └-----------------------┐ | |
 383  *                            └-----------------------┐ | | |
 384  *                                    | | | |         | | | |
 385  *                            ┌-------┘ | | |         | | | |
 386  *                            | ┌-------┘ | |         | | | |
 387  *                            | | ┌-------┘ |         | | | |
 388  *                            | | | ┌-------┘         | | | |
 389  *                            | | | |                 | | | |
 390  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 391  *      3                   2                   1                   0
 392  *
 393  *   Used in handling following instructions:
 394  *
 395  *     - ADDIU[R1.SP]
 396  *     - ADDIU[R2]
 397  *     - ADDU[16]
 398  *     - AND[16]
 399  *     - ANDI[16]
 400  *     - BEQC[16]
 401  *     - BEQZC[16]
 402  *     - BNEC[16]
 403  *     - BNEZC[16]
 404  *     - LB[16]
 405  *     - LBU[16]
 406  *     - LH[16]
 407  *     - LHU[16]
 408  *     - LI[16]
 409  *     - LW[16]
 410  *     - LW[GP16]
 411  *     - LWXS[16]
 412  *     - NOT[16]
 413  *     - OR[16]
 414  *     - SB[16]
 415  *     - SH[16]
 416  *     - SLL[16]
 417  *     - SRL[16]
 418  *     - SUBU[16]
 419  *     - SW[16]
 420  *     - XOR[16]
 421  */
 422 uint64 NMD::decode_gpr_gpr3(uint64 d)
 423 {
 424     static uint64 register_list[] = { 16, 17, 18, 19,  4,  5,  6,  7 };
 425     return renumber_registers(d, register_list,
 426                sizeof(register_list) / sizeof(register_list[0]));
 427 }
 428
 429
 430 /*
 431  * NMD::decode_gpr_gpr3_src_store() - decoder for 'gpr3.src.store' gpr encoding
 432  *     type
 433  *
 434  *   Map a 3-bit code to the 5-bit register space according to this pattern:
 435  *
 436  *                            7 6 5 4 3 2 1 0
 437  *                            | | | | | | | |
 438  *                            | | | | | | | └-----------------------┐
 439  *                            | | | └-----------------------┐       |
 440  *                            | | └-----------------------┐ |       |
 441  *                            | └-----------------------┐ | |       |
 442  *                            └-----------------------┐ | | |       |
 443  *                                    | | |           | | | |       |
 444  *                            ┌-------┘ | |           | | | |       |
 445  *                            | ┌-------┘ |           | | | |       |
 446  *                            | | ┌-------┘           | | | |       |
 447  *                            | | |                   | | | |       |
 448  *                            | | |                   | | | |       |
 449  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 450  *      3                   2                   1                   0
 451  *
 452  *   This pattern is the same one used for 'gpr3' gpr encoding type, except for
 453  * the input value 0, that is mapped to the output value 0 instead of 16.
 454  *
 455  *   Used in handling following instructions:
 456  *
 457  *     - SB[16]
 458  *     - SH[16]
 459  *     - SW[16]
 460  *     - SW[GP16]
 461  */
 462 uint64 NMD::decode_gpr_gpr3_src_store(uint64 d)
 463 {
 464     static uint64 register_list[] = {  0, 17, 18, 19,  4,  5,  6,  7 };
 465     return renumber_registers(d, register_list,
 466                sizeof(register_list) / sizeof(register_list[0]));
 467 }
 468
 469
 470 /*
 471  * NMD::decode_gpr_gpr2_reg1() - decoder for 'gpr2.reg1' gpr encoding type
 472  *
 473  *   Map a 2-bit code to the 5-bit register space according to this pattern:
 474  *
 475  *                                3 2 1 0
 476  *                                | | | |
 477  *                                | | | |
 478  *                                | | | └-------------------┐
 479  *                                | | └-------------------┐ |
 480  *                                | └-------------------┐ | |
 481  *                                └-------------------┐ | | |
 482  *                                                    | | | |
 483  *                                                    | | | |
 484  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 485  *      3                   2                   1                   0
 486  *
 487  *   Used in handling following instructions:
 488  *
 489  *     - MOVEP
 490  *     - MOVEP[REV]
 491  */
 492 uint64 NMD::decode_gpr_gpr2_reg1(uint64 d)
 493 {
 494     static uint64 register_list[] = {  4,  5,  6,  7 };
 495     return renumber_registers(d, register_list,
 496                sizeof(register_list) / sizeof(register_list[0]));
 497 }
 498
 499
 500 /*
 501  * NMD::decode_gpr_gpr2_reg2() - decoder for 'gpr2.reg2' gpr encoding type
 502  *
 503  *   Map a 2-bit code to the 5-bit register space according to this pattern:
 504  *
 505  *                                3 2 1 0
 506  *                                | | | |
 507  *                                | | | |
 508  *                                | | | └-----------------┐
 509  *                                | | └-----------------┐ |
 510  *                                | └-----------------┐ | |
 511  *                                └-----------------┐ | | |
 512  *                                                  | | | |
 513  *                                                  | | | |
 514  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 515  *      3                   2                   1                   0
 516  *
 517  *   Used in handling following instructions:
 518  *
 519  *     - MOVEP
 520  *     - MOVEP[REV]
 521  */
 522 uint64 NMD::decode_gpr_gpr2_reg2(uint64 d)
 523 {
 524     static uint64 register_list[] = {  5,  6,  7,  8 };
 525     return renumber_registers(d, register_list,
 526                sizeof(register_list) / sizeof(register_list[0]));
 527 }
 528
 529
 530 /*
 531  * NMD::decode_gpr_gpr1() - decoder for 'gpr1' gpr encoding type
 532  *
 533  *   Map a 1-bit code to the 5-bit register space according to this pattern:
 534  *
 535  *                                  1 0
 536  *                                  | |
 537  *                                  | |
 538  *                                  | └---------------------┐
 539  *                                  └---------------------┐ |
 540  *                                                        | |
 541  *                                                        | |
 542  *                                                        | |
 543  *                                                        | |
 544  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 545  *      3                   2                   1                   0
 546  *
 547  *   Used in handling following instruction:
 548  *
 549  *     - MOVE.BALC
 550  */
 551 uint64 NMD::decode_gpr_gpr1(uint64 d)
 552 {
 553     static uint64 register_list[] = {  4,  5 };
 554     return renumber_registers(d, register_list,
 555                sizeof(register_list) / sizeof(register_list[0]));
 556 }
 557
 558
 559 uint64 NMD::copy(uint64 d)
 560 {
 561     return d;
 562 }
 563
 564
 565 int64 NMD::copy(int64 d)
 566 {
 567     return d;
 568 }
 569
 570
 571 int64 NMD::neg_copy(uint64 d)
 572 {
 573     return 0ll - d;
 574 }
 575
 576
 577 int64 NMD::neg_copy(int64 d)
 578 {
 579     return -d;
 580 }
 581
 582
 583 /* strange wrapper around  gpr3 */
 584 uint64 NMD::encode_rs3_and_check_rs3_ge_rt3(uint64 d)
 585 {
 586 return decode_gpr_gpr3(d);
 587 }
 588
 589
 590 /* strange wrapper around  gpr3 */
 591 uint64 NMD::encode_rs3_and_check_rs3_lt_rt3(uint64 d)
 592 {
 593     return decode_gpr_gpr3(d);
 594 }
 595
 596
 597 /* nop - done by extraction function */
 598 uint64 NMD::encode_s_from_address(uint64 d)
 599 {
 600     return d;
 601 }
 602
 603
 604 /* nop - done by extraction function */
 605 uint64 NMD::encode_u_from_address(uint64 d)
 606 {
 607     return d;
 608 }
 609
 610
 611 /* nop - done by extraction function */
 612 uint64 NMD::encode_s_from_s_hi(uint64 d)
 613 {
 614     return d;
 615 }
 616
 617
 618 uint64 NMD::encode_count3_from_count(uint64 d)
 619 {
 620     IMGASSERTONCE(d < 8);
 621     return d == 0ull ? 8ull : d;
 622 }
 623
 624
 625 uint64 NMD::encode_shift3_from_shift(uint64 d)
 626 {
 627     IMGASSERTONCE(d < 8);
 628     return d == 0ull ? 8ull : d;
 629 }
 630
 631
 632 /* special value for load literal */
 633 int64 NMD::encode_eu_from_s_li16(uint64 d)
 634 {
 635     IMGASSERTONCE(d < 128);
 636     return d == 127 ? -1 : (int64)d;
 637 }
 638
 639
 640 uint64 NMD::encode_msbd_from_size(uint64 d)
 641 {
 642     IMGASSERTONCE(d < 32);
 643     return d + 1;
 644 }
 645
 646
 647 uint64 NMD::encode_eu_from_u_andi16(uint64 d)
 648 {
 649     IMGASSERTONCE(d < 16);
 650     if (d == 12) {
 651         return 0x00ffull;
 652     }
 653     if (d == 13) {
 654         return 0xffffull;
 655     }
 656     return d;
 657 }
 658
 659
 660 uint64 NMD::encode_msbd_from_pos_and_size(uint64 d)
 661 {
 662     IMGASSERTONCE(0);
 663     return d;
 664 }
 665
 666
 667 /* save16 / restore16   ???? */
 668 uint64 NMD::encode_rt1_from_rt(uint64 d)
 669 {
 670     return d ? 31 : 30;
 671 }
 672
 673
 674 /* ? */
 675 uint64 NMD::encode_lsb_from_pos_and_size(uint64 d)
 676 {
 677     return d;
 678 }
 679
 680
 681 std::string NMD::save_restore_list(uint64 rt, uint64 count, uint64 gp)
 682 {
 683     std::string str;
 684
 685     for (uint64 counter = 0; counter != count; counter++) {
 686         bool use_gp = gp && (counter == count - 1);
 687         uint64 this_rt = use_gp ? 28 : ((rt & 0x10) | (rt + counter)) & 0x1f;
 688         str += img::format(",%s", GPR(this_rt));
 689     }
 690
 691     return str;
 692 }
 693
 694
 695 std::string NMD::GPR(uint64 reg)
 696 {
 697     static const char *gpr_reg[32] = {
 698         "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
 699         "a4",   "a5",   "a6",   "a7",   "r12",  "r13",  "r14",  "r15",
 700         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
 701         "r24",  "r25",  "k0",   "k1",   "gp",   "sp",   "fp",   "ra"
 702     };
 703
 704     if (reg < 32) {
 705         return gpr_reg[reg];
 706     }
 707
 708     throw std::runtime_error(img::format("Invalid GPR register index %" PRIu64,
 709                                          reg));
 710 }
 711
 712
 713 std::string NMD::FPR(uint64 reg)
 714 {
 715     static const char *fpr_reg[32] = {
 716         "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
 717         "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
 718         "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
 719         "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
 720     };
 721
 722     if (reg < 32) {
 723         return fpr_reg[reg];
 724     }
 725
 726     throw std::runtime_error(img::format("Invalid FPR register index %" PRIu64,
 727                                          reg));
 728 }
 729
 730
 731 std::string NMD::AC(uint64 reg)
 732 {
 733     static const char *ac_reg[4] = {
 734         "ac0",  "ac1",  "ac2",  "ac3"
 735     };
 736
 737     if (reg < 4) {
 738         return ac_reg[reg];
 739     }
 740
 741     throw std::runtime_error(img::format("Invalid AC register index %" PRIu64,
 742                                          reg));
 743 }
 744
 745
 746 std::string NMD::IMMEDIATE(uint64 value)
 747 {
 748     return img::format("0x%" PRIx64, value);
 749 }
 750
 751
 752 std::string NMD::IMMEDIATE(int64 value)
 753 {
 754     return img::format("%" PRId64, value);
 755 }
 756
 757
 758 std::string NMD::CPR(uint64 reg)
 759 {
 760     /* needs more work */
 761     return img::format("CP%" PRIu64, reg);
 762 }
 763
 764
 765 std::string NMD::ADDRESS(uint64 value, int instruction_size)
 766 {
 767     /* token for string replace */
 768     /* const char TOKEN_REPLACE = (char)0xa2; */
 769     img::address address = m_pc + value + instruction_size;
 770     /* symbol replacement */
 771     /* return img::as_char(TOKEN_REPLACE) + to_string(address); */
 772     return to_string(address);
 773 }
 774
 775
 776 uint64 NMD::extract_op_code_value(const uint16 * data, int size)
 777 {
 778     switch (size) {
 779     case 16:
 780         return data[0];
 781     case 32:
 782         return ((uint64)data[0] << 16) | data[1];
 783     case 48:
 784         return ((uint64)data[0] << 32) | ((uint64)data[1] << 16) | data[2];
 785     default:
 786         return data[0];
 787     }
 788 }
 789
 790
 791 int NMD::Disassemble(const uint16 * data, std::string & dis,
 792                      NMD::TABLE_ENTRY_TYPE & type)
 793 {
 794     return Disassemble(data, dis, type, MAJOR, 2);
 795 }
 796
 797
 798 /*
 799  * Recurse through tables until the instruction is found then return
 800  * the string and size
 801  *
 802  * inputs:
 803  *      pointer to a word stream,
 804  *      disassember table and size
 805  * returns:
 806  *      instruction size    - negative is error
 807  *      disassembly string  - on error will constain error string
 808  */
 809 int NMD::Disassemble(const uint16 * data, std::string & dis,
 810                      NMD::TABLE_ENTRY_TYPE & type, const Pool *table,
 811                      int table_size)
 812 {
 813     try
 814     {
 815         for (int i = 0; i < table_size; i++) {
 816             uint64 op_code = extract_op_code_value(data,
 817                                  table[i].instructions_size);
 818             if ((op_code & table[i].mask) == table[i].value) {
 819                 /* possible match */
 820                 conditional_function cond = table[i].condition;
 821                 if ((cond == 0) || (this->*cond)(op_code)) {
 822                     try
 823                     {
 824                         if (table[i].type == pool) {
 825                             return Disassemble(data, dis, type,
 826                                                table[i].next_table,
 827                                                table[i].next_table_size);
 828                         } else if ((table[i].type == instruction) ||
 829                                    (table[i].type == call_instruction) ||
 830                                    (table[i].type == branch_instruction) ||
 831                                    (table[i].type == return_instruction)) {
 832                             if ((table[i].attributes != 0) &&
 833                                 (m_requested_instruction_categories &
 834                                  table[i].attributes) == 0) {
 835                                 /*
 836                                  * failed due to instruction having
 837                                  * an ASE attribute and the requested version
 838                                  * not having that attribute
 839                                  */
 840                                 dis = "ASE attribute missmatch";
 841                                 return -5;
 842                             }
 843                             disassembly_function dis_fn = table[i].disassembly;
 844                             if (dis_fn == 0) {
 845                                 dis = "disassembler failure - bad table entry";
 846                                 return -6;
 847                             }
 848                             type = table[i].type;
 849                             dis = (this->*dis_fn)(op_code);
 850                             return table[i].instructions_size;
 851                         } else {
 852                             dis = "reserved instruction";
 853                             return -2;
 854                         }
 855                     }
 856                     catch (std::runtime_error & e)
 857                     {
 858                         dis = e.what();
 859                         return -3;          /* runtime error */
 860                     }
 861                 }
 862             }
 863         }
 864     }
 865     catch (std::exception & e)
 866     {
 867         dis = e.what();
 868         return -4;          /* runtime error */
 869     }
 870
 871     dis = "failed to disassemble";
 872     return -1;      /* failed to disassemble        */
 873 }
 874
 875
 876 uint64 NMD::extract_code_18_to_0(uint64 instruction)
 877 {
 878     uint64 value = 0;
 879     value |= extract_bits(instruction, 0, 19);
 880     return value;
 881 }
 882
 883
 884 uint64 NMD::extract_shift3_2_1_0(uint64 instruction)
 885 {
 886     uint64 value = 0;
 887     value |= extract_bits(instruction, 0, 3);
 888     return value;
 889 }
 890
 891
 892 uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction)
 893 {
 894     uint64 value = 0;
 895     value |= extract_bits(instruction, 3, 9) << 3;
 896     return value;
 897 }
 898
 899
 900 uint64 NMD::extract_count_3_2_1_0(uint64 instruction)
 901 {
 902     uint64 value = 0;
 903     value |= extract_bits(instruction, 0, 4);
 904     return value;
 905 }
 906
 907
 908 uint64 NMD::extract_rtz3_9_8_7(uint64 instruction)
 909 {
 910     uint64 value = 0;
 911     value |= extract_bits(instruction, 7, 3);
 912     return value;
 913 }
 914
 915
 916 uint64 NMD::extract_u_17_to_1__s1(uint64 instruction)
 917 {
 918     uint64 value = 0;
 919     value |= extract_bits(instruction, 1, 17) << 1;
 920     return value;
 921 }
 922
 923
 924 int64 NMD::extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction)
 925 {
 926     int64 value = 0;
 927     value |= extract_bits(instruction, 11, 10);
 928     value = sign_extend(value, 9);
 929     return value;
 930 }
 931
 932
 933 int64 NMD::extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction)
 934 {
 935     int64 value = 0;
 936     value |= extract_bits(instruction, 0, 1) << 11;
 937     value |= extract_bits(instruction, 1, 10) << 1;
 938     value = sign_extend(value, 11);
 939     return value;
 940 }
 941
 942
 943 uint64 NMD::extract_u_10(uint64 instruction)
 944 {
 945     uint64 value = 0;
 946     value |= extract_bits(instruction, 10, 1);
 947     return value;
 948 }
 949
 950
 951 uint64 NMD::extract_rtz4_27_26_25_23_22_21(uint64 instruction)
 952 {
 953     uint64 value = 0;
 954     value |= extract_bits(instruction, 21, 3);
 955     value |= extract_bits(instruction, 25, 1) << 3;
 956     return value;
 957 }
 958
 959
 960 uint64 NMD::extract_sa_15_14_13_12_11(uint64 instruction)
 961 {
 962     uint64 value = 0;
 963     value |= extract_bits(instruction, 11, 5);
 964     return value;
 965 }
 966
 967
 968 uint64 NMD::extract_shift_4_3_2_1_0(uint64 instruction)
 969 {
 970     uint64 value = 0;
 971     value |= extract_bits(instruction, 0, 5);
 972     return value;
 973 }
 974
 975
 976 uint64 NMD::extract_shiftx_10_9_8_7__s1(uint64 instruction)
 977 {
 978     uint64 value = 0;
 979     value |= extract_bits(instruction, 7, 4) << 1;
 980     return value;
 981 }
 982
 983
 984 uint64 NMD::extract_hint_25_24_23_22_21(uint64 instruction)
 985 {
 986     uint64 value = 0;
 987     value |= extract_bits(instruction, 21, 5);
 988     return value;
 989 }
 990
 991
 992 uint64 NMD::extract_count3_14_13_12(uint64 instruction)
 993 {
 994     uint64 value = 0;
 995     value |= extract_bits(instruction, 12, 3);
 996     return value;
 997 }
 998
 999
1000 int64 NMD::extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction)
1001 {
1002     int64 value = 0;
1003     value |= extract_bits(instruction, 0, 1) << 31;
1004     value |= extract_bits(instruction, 2, 10) << 21;
1005     value |= extract_bits(instruction, 12, 9) << 12;
1006     value = sign_extend(value, 31);
1007     return value;
1008 }
1009
1010
1011 int64 NMD::extract_s__se7_0_6_5_4_3_2_1_s1(uint64 instruction)
1012 {
1013     int64 value = 0;
1014     value |= extract_bits(instruction, 0, 1) << 7;
1015     value |= extract_bits(instruction, 1, 6) << 1;
1016     value = sign_extend(value, 7);
1017     return value;
1018 }
1019
1020
1021 uint64 NMD::extract_u2_10_9(uint64 instruction)
1022 {
1023     uint64 value = 0;
1024     value |= extract_bits(instruction, 9, 2);
1025     return value;
1026 }
1027
1028
1029 uint64 NMD::extract_code_25_24_23_22_21_20_19_18_17_16(uint64 instruction)
1030 {
1031     uint64 value = 0;
1032     value |= extract_bits(instruction, 16, 10);
1033     return value;
1034 }
1035
1036
1037 uint64 NMD::extract_rs_20_19_18_17_16(uint64 instruction)
1038 {
1039     uint64 value = 0;
1040     value |= extract_bits(instruction, 16, 5);
1041     return value;
1042 }
1043
1044
1045 uint64 NMD::extract_u_2_1__s1(uint64 instruction)
1046 {
1047     uint64 value = 0;
1048     value |= extract_bits(instruction, 1, 2) << 1;
1049     return value;
1050 }
1051
1052
1053 uint64 NMD::extract_stripe_6(uint64 instruction)
1054 {
1055     uint64 value = 0;
1056     value |= extract_bits(instruction, 6, 1);
1057     return value;
1058 }
1059
1060
1061 uint64 NMD::extract_ac_15_14(uint64 instruction)
1062 {
1063     uint64 value = 0;
1064     value |= extract_bits(instruction, 14, 2);
1065     return value;
1066 }
1067
1068
1069 uint64 NMD::extract_shift_20_19_18_17_16(uint64 instruction)
1070 {
1071     uint64 value = 0;
1072     value |= extract_bits(instruction, 16, 5);
1073     return value;
1074 }
1075
1076
1077 uint64 NMD::extract_rdl_25_24(uint64 instruction)
1078 {
1079     uint64 value = 0;
1080     value |= extract_bits(instruction, 24, 1);
1081     return value;
1082 }
1083
1084
1085 int64 NMD::extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(uint64 instruction)
1086 {
1087     int64 value = 0;
1088     value |= extract_bits(instruction, 0, 1) << 10;
1089     value |= extract_bits(instruction, 1, 9) << 1;
1090     value = sign_extend(value, 10);
1091     return value;
1092 }
1093
1094
1095 uint64 NMD::extract_eu_6_5_4_3_2_1_0(uint64 instruction)
1096 {
1097     uint64 value = 0;
1098     value |= extract_bits(instruction, 0, 7);
1099     return value;
1100 }
1101
1102
1103 uint64 NMD::extract_shift_5_4_3_2_1_0(uint64 instruction)
1104 {
1105     uint64 value = 0;
1106     value |= extract_bits(instruction, 0, 6);
1107     return value;
1108 }
1109
1110
1111 uint64 NMD::extract_count_19_18_17_16(uint64 instruction)
1112 {
1113     uint64 value = 0;
1114     value |= extract_bits(instruction, 16, 4);
1115     return value;
1116 }
1117
1118
1119 uint64 NMD::extract_code_2_1_0(uint64 instruction)
1120 {
1121     uint64 value = 0;
1122     value |= extract_bits(instruction, 0, 3);
1123     return value;
1124 }
1125
1126
1127 uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction)
1128 {
1129     uint64 value = 0;
1130     value |= extract_bits(instruction, 0, 12);
1131     return value;
1132 }
1133
1134
1135 uint64 NMD::extract_rs_4_3_2_1_0(uint64 instruction)
1136 {
1137     uint64 value = 0;
1138     value |= extract_bits(instruction, 0, 5);
1139     return value;
1140 }
1141
1142
1143 uint64 NMD::extract_u_20_to_3__s3(uint64 instruction)
1144 {
1145     uint64 value = 0;
1146     value |= extract_bits(instruction, 3, 18) << 3;
1147     return value;
1148 }
1149
1150
1151 uint64 NMD::extract_u_3_2_1_0__s2(uint64 instruction)
1152 {
1153     uint64 value = 0;
1154     value |= extract_bits(instruction, 0, 4) << 2;
1155     return value;
1156 }
1157
1158
1159 uint64 NMD::extract_cofun_25_24_23(uint64 instruction)
1160 {
1161     uint64 value = 0;
1162     value |= extract_bits(instruction, 3, 23);
1163     return value;
1164 }
1165
1166
1167 uint64 NMD::extract_u_2_1_0__s2(uint64 instruction)
1168 {
1169     uint64 value = 0;
1170     value |= extract_bits(instruction, 0, 3) << 2;
1171     return value;
1172 }
1173
1174
1175 uint64 NMD::extract_rd3_3_2_1(uint64 instruction)
1176 {
1177     uint64 value = 0;
1178     value |= extract_bits(instruction, 1, 3);
1179     return value;
1180 }
1181
1182
1183 uint64 NMD::extract_sa_15_14_13_12(uint64 instruction)
1184 {
1185     uint64 value = 0;
1186     value |= extract_bits(instruction, 12, 4);
1187     return value;
1188 }
1189
1190
1191 uint64 NMD::extract_rt_25_24_23_22_21(uint64 instruction)
1192 {
1193     uint64 value = 0;
1194     value |= extract_bits(instruction, 21, 5);
1195     return value;
1196 }
1197
1198
1199 uint64 NMD::extract_ru_7_6_5_4_3(uint64 instruction)
1200 {
1201     uint64 value = 0;
1202     value |= extract_bits(instruction, 3, 5);
1203     return value;
1204 }
1205
1206
1207 uint64 NMD::extract_u_17_to_0(uint64 instruction)
1208 {
1209     uint64 value = 0;
1210     value |= extract_bits(instruction, 0, 18);
1211     return value;
1212 }
1213
1214
1215 uint64 NMD::extract_rsz4_4_2_1_0(uint64 instruction)
1216 {
1217     uint64 value = 0;
1218     value |= extract_bits(instruction, 0, 3);
1219     value |= extract_bits(instruction, 4, 1) << 3;
1220     return value;
1221 }
1222
1223
1224 int64 NMD::extract_s__se21_0_20_to_1_s1(uint64 instruction)
1225 {
1226     int64 value = 0;
1227     value |= extract_bits(instruction, 0, 1) << 21;
1228     value |= extract_bits(instruction, 1, 20) << 1;
1229     value = sign_extend(value, 21);
1230     return value;
1231 }
1232
1233
1234 uint64 NMD::extract_op_25_to_3(uint64 instruction)
1235 {
1236     uint64 value = 0;
1237     value |= extract_bits(instruction, 3, 23);
1238     return value;
1239 }
1240
1241
1242 uint64 NMD::extract_rs4_4_2_1_0(uint64 instruction)
1243 {
1244     uint64 value = 0;
1245     value |= extract_bits(instruction, 0, 3);
1246     value |= extract_bits(instruction, 4, 1) << 3;
1247     return value;
1248 }
1249
1250
1251 uint64 NMD::extract_bit_23_22_21(uint64 instruction)
1252 {
1253     uint64 value = 0;
1254     value |= extract_bits(instruction, 21, 3);
1255     return value;
1256 }
1257
1258
1259 uint64 NMD::extract_rt_41_40_39_38_37(uint64 instruction)
1260 {
1261     uint64 value = 0;
1262     value |= extract_bits(instruction, 37, 5);
1263     return value;
1264 }
1265
1266
1267 int64 NMD::extract_shift__se5_21_20_19_18_17_16(uint64 instruction)
1268 {
1269     int64 value = 0;
1270     value |= extract_bits(instruction, 16, 6);
1271     value = sign_extend(value, 5);
1272     return value;
1273 }
1274
1275
1276 uint64 NMD::extract_rd2_3_8(uint64 instruction)
1277 {
1278     uint64 value = 0;
1279     value |= extract_bits(instruction, 3, 1) << 1;
1280     value |= extract_bits(instruction, 8, 1);
1281     return value;
1282 }
1283
1284
1285 uint64 NMD::extract_code_17_to_0(uint64 instruction)
1286 {
1287     uint64 value = 0;
1288     value |= extract_bits(instruction, 0, 18);
1289     return value;
1290 }
1291
1292
1293 uint64 NMD::extract_size_20_19_18_17_16(uint64 instruction)
1294 {
1295     uint64 value = 0;
1296     value |= extract_bits(instruction, 16, 5);
1297     return value;
1298 }
1299
1300
1301 int64 NMD::extract_s__se8_15_7_6_5_4_3_2_s2(uint64 instruction)
1302 {
1303     int64 value = 0;
1304     value |= extract_bits(instruction, 2, 6) << 2;
1305     value |= extract_bits(instruction, 15, 1) << 8;
1306     value = sign_extend(value, 8);
1307     return value;
1308 }
1309
1310
1311 uint64 NMD::extract_u_15_to_0(uint64 instruction)
1312 {
1313     uint64 value = 0;
1314     value |= extract_bits(instruction, 0, 16);
1315     return value;
1316 }
1317
1318
1319 uint64 NMD::extract_fs_20_19_18_17_16(uint64 instruction)
1320 {
1321     uint64 value = 0;
1322     value |= extract_bits(instruction, 16, 5);
1323     return value;
1324 }
1325
1326
1327 int64 NMD::extract_s__se8_15_7_6_5_4_3_2_1_0(uint64 instruction)
1328 {
1329     int64 value = 0;
1330     value |= extract_bits(instruction, 0, 8);
1331     value |= extract_bits(instruction, 15, 1) << 8;
1332     value = sign_extend(value, 8);
1333     return value;
1334 }
1335
1336
1337 uint64 NMD::extract_stype_20_19_18_17_16(uint64 instruction)
1338 {
1339     uint64 value = 0;
1340     value |= extract_bits(instruction, 16, 5);
1341     return value;
1342 }
1343
1344
1345 uint64 NMD::extract_rtl_11(uint64 instruction)
1346 {
1347     uint64 value = 0;
1348     value |= extract_bits(instruction, 9, 1);
1349     return value;
1350 }
1351
1352
1353 uint64 NMD::extract_hs_20_19_18_17_16(uint64 instruction)
1354 {
1355     uint64 value = 0;
1356     value |= extract_bits(instruction, 16, 5);
1357     return value;
1358 }
1359
1360
1361 uint64 NMD::extract_sel_13_12_11(uint64 instruction)
1362 {
1363     uint64 value = 0;
1364     value |= extract_bits(instruction, 11, 3);
1365     return value;
1366 }
1367
1368
1369 uint64 NMD::extract_lsb_4_3_2_1_0(uint64 instruction)
1370 {
1371     uint64 value = 0;
1372     value |= extract_bits(instruction, 0, 5);
1373     return value;
1374 }
1375
1376
1377 uint64 NMD::extract_gp_2(uint64 instruction)
1378 {
1379     uint64 value = 0;
1380     value |= extract_bits(instruction, 2, 1);
1381     return value;
1382 }
1383
1384
1385 uint64 NMD::extract_rt3_9_8_7(uint64 instruction)
1386 {
1387     uint64 value = 0;
1388     value |= extract_bits(instruction, 7, 3);
1389     return value;
1390 }
1391
1392
1393 uint64 NMD::extract_ft_25_24_23_22_21(uint64 instruction)
1394 {
1395     uint64 value = 0;
1396     value |= extract_bits(instruction, 21, 5);
1397     return value;
1398 }
1399
1400
1401 uint64 NMD::extract_u_17_16_15_14_13_12_11(uint64 instruction)
1402 {
1403     uint64 value = 0;
1404     value |= extract_bits(instruction, 11, 7);
1405     return value;
1406 }
1407
1408
1409 uint64 NMD::extract_cs_20_19_18_17_16(uint64 instruction)
1410 {
1411     uint64 value = 0;
1412     value |= extract_bits(instruction, 16, 5);
1413     return value;
1414 }
1415
1416
1417 uint64 NMD::extract_rt4_9_7_6_5(uint64 instruction)
1418 {
1419     uint64 value = 0;
1420     value |= extract_bits(instruction, 5, 3);
1421     value |= extract_bits(instruction, 9, 1) << 3;
1422     return value;
1423 }
1424
1425
1426 uint64 NMD::extract_msbt_10_9_8_7_6(uint64 instruction)
1427 {
1428     uint64 value = 0;
1429     value |= extract_bits(instruction, 6, 5);
1430     return value;
1431 }
1432
1433
1434 uint64 NMD::extract_u_5_4_3_2_1_0__s2(uint64 instruction)
1435 {
1436     uint64 value = 0;
1437     value |= extract_bits(instruction, 0, 6) << 2;
1438     return value;
1439 }
1440
1441
1442 uint64 NMD::extract_sa_15_14_13(uint64 instruction)
1443 {
1444     uint64 value = 0;
1445     value |= extract_bits(instruction, 13, 3);
1446     return value;
1447 }
1448
1449
1450 int64 NMD::extract_s__se14_0_13_to_1_s1(uint64 instruction)
1451 {
1452     int64 value = 0;
1453     value |= extract_bits(instruction, 0, 1) << 14;
1454     value |= extract_bits(instruction, 1, 13) << 1;
1455     value = sign_extend(value, 14);
1456     return value;
1457 }
1458
1459
1460 uint64 NMD::extract_rs3_6_5_4(uint64 instruction)
1461 {
1462     uint64 value = 0;
1463     value |= extract_bits(instruction, 4, 3);
1464     return value;
1465 }
1466
1467
1468 uint64 NMD::extract_u_31_to_0__s32(uint64 instruction)
1469 {
1470     uint64 value = 0;
1471     value |= extract_bits(instruction, 0, 32) << 32;
1472     return value;
1473 }
1474
1475
1476 uint64 NMD::extract_shift_10_9_8_7_6(uint64 instruction)
1477 {
1478     uint64 value = 0;
1479     value |= extract_bits(instruction, 6, 5);
1480     return value;
1481 }
1482
1483
1484 uint64 NMD::extract_cs_25_24_23_22_21(uint64 instruction)
1485 {
1486     uint64 value = 0;
1487     value |= extract_bits(instruction, 21, 5);
1488     return value;
1489 }
1490
1491
1492 uint64 NMD::extract_shiftx_11_10_9_8_7_6(uint64 instruction)
1493 {
1494     uint64 value = 0;
1495     value |= extract_bits(instruction, 6, 6);
1496     return value;
1497 }
1498
1499
1500 uint64 NMD::extract_rt_9_8_7_6_5(uint64 instruction)
1501 {
1502     uint64 value = 0;
1503     value |= extract_bits(instruction, 5, 5);
1504     return value;
1505 }
1506
1507
1508 uint64 NMD::extract_op_25_24_23_22_21(uint64 instruction)
1509 {
1510     uint64 value = 0;
1511     value |= extract_bits(instruction, 21, 5);
1512     return value;
1513 }
1514
1515
1516 uint64 NMD::extract_u_6_5_4_3_2_1_0__s2(uint64 instruction)
1517 {
1518     uint64 value = 0;
1519     value |= extract_bits(instruction, 0, 7) << 2;
1520     return value;
1521 }
1522
1523
1524 uint64 NMD::extract_bit_16_15_14_13_12_11(uint64 instruction)
1525 {
1526     uint64 value = 0;
1527     value |= extract_bits(instruction, 11, 6);
1528     return value;
1529 }
1530
1531
1532 uint64 NMD::extract_mask_20_19_18_17_16_15_14(uint64 instruction)
1533 {
1534     uint64 value = 0;
1535     value |= extract_bits(instruction, 14, 7);
1536     return value;
1537 }
1538
1539
1540 uint64 NMD::extract_eu_3_2_1_0(uint64 instruction)
1541 {
1542     uint64 value = 0;
1543     value |= extract_bits(instruction, 0, 4);
1544     return value;
1545 }
1546
1547
1548 uint64 NMD::extract_u_7_6_5_4__s4(uint64 instruction)
1549 {
1550     uint64 value = 0;
1551     value |= extract_bits(instruction, 4, 4) << 4;
1552     return value;
1553 }
1554
1555
1556 int64 NMD::extract_s__se8_15_7_6_5_4_3_s3(uint64 instruction)
1557 {
1558     int64 value = 0;
1559     value |= extract_bits(instruction, 3, 5) << 3;
1560     value |= extract_bits(instruction, 15, 1) << 8;
1561     value = sign_extend(value, 8);
1562     return value;
1563 }
1564
1565
1566 uint64 NMD::extract_ft_15_14_13_12_11(uint64 instruction)
1567 {
1568     uint64 value = 0;
1569     value |= extract_bits(instruction, 11, 5);
1570     return value;
1571 }
1572
1573
1574 int64 NMD::extract_s__se31_15_to_0_31_to_16(uint64 instruction)
1575 {
1576     int64 value = 0;
1577     value |= extract_bits(instruction, 0, 16) << 16;
1578     value |= extract_bits(instruction, 16, 16);
1579     value = sign_extend(value, 31);
1580     return value;
1581 }
1582
1583
1584 uint64 NMD::extract_u_20_19_18_17_16_15_14_13(uint64 instruction)
1585 {
1586     uint64 value = 0;
1587     value |= extract_bits(instruction, 13, 8);
1588     return value;
1589 }
1590
1591
1592 uint64 NMD::extract_u_17_to_2__s2(uint64 instruction)
1593 {
1594     uint64 value = 0;
1595     value |= extract_bits(instruction, 2, 16) << 2;
1596     return value;
1597 }
1598
1599
1600 uint64 NMD::extract_rd_15_14_13_12_11(uint64 instruction)
1601 {
1602     uint64 value = 0;
1603     value |= extract_bits(instruction, 11, 5);
1604     return value;
1605 }
1606
1607
1608 uint64 NMD::extract_c0s_20_19_18_17_16(uint64 instruction)
1609 {
1610     uint64 value = 0;
1611     value |= extract_bits(instruction, 16, 5);
1612     return value;
1613 }
1614
1615
1616 uint64 NMD::extract_code_1_0(uint64 instruction)
1617 {
1618     uint64 value = 0;
1619     value |= extract_bits(instruction, 0, 2);
1620     return value;
1621 }
1622
1623
1624 int64 NMD::extract_s__se25_0_24_to_1_s1(uint64 instruction)
1625 {
1626     int64 value = 0;
1627     value |= extract_bits(instruction, 0, 1) << 25;
1628     value |= extract_bits(instruction, 1, 24) << 1;
1629     value = sign_extend(value, 25);
1630     return value;
1631 }
1632
1633
1634 uint64 NMD::extract_u_1_0(uint64 instruction)
1635 {
1636     uint64 value = 0;
1637     value |= extract_bits(instruction, 0, 2);
1638     return value;
1639 }
1640
1641
1642 uint64 NMD::extract_u_3_8__s2(uint64 instruction)
1643 {
1644     uint64 value = 0;
1645     value |= extract_bits(instruction, 3, 1) << 3;
1646     value |= extract_bits(instruction, 8, 1) << 2;
1647     return value;
1648 }
1649
1650
1651 uint64 NMD::extract_fd_15_14_13_12_11(uint64 instruction)
1652 {
1653     uint64 value = 0;
1654     value |= extract_bits(instruction, 11, 5);
1655     return value;
1656 }
1657
1658
1659 uint64 NMD::extract_u_4_3_2_1_0__s2(uint64 instruction)
1660 {
1661     uint64 value = 0;
1662     value |= extract_bits(instruction, 0, 5) << 2;
1663     return value;
1664 }
1665
1666
1667 uint64 NMD::extract_rtz4_9_7_6_5(uint64 instruction)
1668 {
1669     uint64 value = 0;
1670     value |= extract_bits(instruction, 5, 3);
1671     value |= extract_bits(instruction, 9, 1) << 3;
1672     return value;
1673 }
1674
1675
1676 uint64 NMD::extract_sel_15_14_13_12_11(uint64 instruction)
1677 {
1678     uint64 value = 0;
1679     value |= extract_bits(instruction, 11, 5);
1680     return value;
1681 }
1682
1683
1684 uint64 NMD::extract_ct_25_24_23_22_21(uint64 instruction)
1685 {
1686     uint64 value = 0;
1687     value |= extract_bits(instruction, 21, 5);
1688     return value;
1689 }
1690
1691
1692 uint64 NMD::extract_u_20_to_2__s2(uint64 instruction)
1693 {
1694     uint64 value = 0;
1695     value |= extract_bits(instruction, 2, 19) << 2;
1696     return value;
1697 }
1698
1699
1700 int64 NMD::extract_s__se3_4_2_1_0(uint64 instruction)
1701 {
1702     int64 value = 0;
1703     value |= extract_bits(instruction, 0, 3);
1704     value |= extract_bits(instruction, 4, 1) << 3;
1705     value = sign_extend(value, 3);
1706     return value;
1707 }
1708
1709
1710 uint64 NMD::extract_u_3_2_1_0__s1(uint64 instruction)
1711 {
1712     uint64 value = 0;
1713     value |= extract_bits(instruction, 0, 4) << 1;
1714     return value;
1715 }
1716
1717
1718
1719 bool NMD::ADDIU_32__cond(uint64 instruction)
1720 {
1721     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1722     return rt != 0;
1723 }
1724
1725
1726 bool NMD::ADDIU_RS5__cond(uint64 instruction)
1727 {
1728     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1729     return rt != 0;
1730 }
1731
1732
1733 bool NMD::BALRSC_cond(uint64 instruction)
1734 {
1735     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1736     return rt != 0;
1737 }
1738
1739
1740 bool NMD::BEQC_16__cond(uint64 instruction)
1741 {
1742     uint64 rs3 = extract_rs3_6_5_4(instruction);
1743     uint64 rt3 = extract_rt3_9_8_7(instruction);
1744     uint64 u = extract_u_3_2_1_0__s1(instruction);
1745     return rs3 < rt3 && u != 0;
1746 }
1747
1748
1749 bool NMD::BNEC_16__cond(uint64 instruction)
1750 {
1751     uint64 rs3 = extract_rs3_6_5_4(instruction);
1752     uint64 rt3 = extract_rt3_9_8_7(instruction);
1753     uint64 u = extract_u_3_2_1_0__s1(instruction);
1754     return rs3 >= rt3 && u != 0;
1755 }
1756
1757
1758 bool NMD::MOVE_cond(uint64 instruction)
1759 {
1760     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1761     return rt != 0;
1762 }
1763
1764
1765 bool NMD::P16_BR1_cond(uint64 instruction)
1766 {
1767     uint64 u = extract_u_3_2_1_0__s1(instruction);
1768     return u != 0;
1769 }
1770
1771
1772 bool NMD::PREF_S9__cond(uint64 instruction)
1773 {
1774     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1775     return hint != 31;
1776 }
1777
1778
1779 bool NMD::PREFE_cond(uint64 instruction)
1780 {
1781     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1782     return hint != 31;
1783 }
1784
1785
1786 bool NMD::SLTU_cond(uint64 instruction)
1787 {
1788     uint64 rd = extract_rd_15_14_13_12_11(instruction);
1789     return rd != 0;
1790 }
1791
1792
1793
1794 /*
1795  * ABS.D fd, fs - Floating Point Absolute Value
1796  *
1797  *   3         2         1
1798  *  10987654321098765432109876543210
1799  *  010001     00000          000101
1800  *    fmt -----
1801  *               fs -----
1802  *                    fd -----
1803  */
1804 std::string NMD::ABS_D(uint64 instruction)
1805 {
1806     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1807     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1808
1809     std::string fs = FPR(copy(fs_value));
1810     std::string fd = FPR(copy(fd_value));
1811
1812     return img::format("ABS.D %s, %s", fd, fs);
1813 }
1814
1815
1816 /*
1817  * ABS.S fd, fs - Floating Point Absolute Value
1818  *
1819  *   3         2         1
1820  *  10987654321098765432109876543210
1821  *  010001     00000          000101
1822  *    fmt -----
1823  *               fd -----
1824  *                    fs -----
1825  */
1826 std::string NMD::ABS_S(uint64 instruction)
1827 {
1828     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1829     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1830
1831     std::string fs = FPR(copy(fs_value));
1832     std::string fd = FPR(copy(fd_value));
1833
1834     return img::format("ABS.S %s, %s", fd, fs);
1835 }
1836
1837
1838 /*
1839  * [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
1840  *         with 16-bit saturation
1841  *
1842  *   3         2         1
1843  *  10987654321098765432109876543210
1844  *  001000          0001000100111111
1845  *     rt -----
1846  *          rs -----
1847  */
1848 std::string NMD::ABSQ_S_PH(uint64 instruction)
1849 {
1850     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1851     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1852
1853     std::string rt = GPR(copy(rt_value));
1854     std::string rs = GPR(copy(rs_value));
1855
1856     return img::format("ABSQ_S.PH %s, %s", rt, rs);
1857 }
1858
1859
1860 /*
1861  * [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
1862  *         with 8-bit saturation
1863  *
1864  *   3         2         1
1865  *  10987654321098765432109876543210
1866  *  001000          0000000100111111
1867  *     rt -----
1868  *          rs -----
1869  */
1870 std::string NMD::ABSQ_S_QB(uint64 instruction)
1871 {
1872     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1873     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1874
1875     std::string rt = GPR(copy(rt_value));
1876     std::string rs = GPR(copy(rs_value));
1877
1878     return img::format("ABSQ_S.QB %s, %s", rt, rs);
1879 }
1880
1881
1882 /*
1883  * [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
1884  *         saturation
1885  *
1886  *   3         2         1
1887  *  10987654321098765432109876543210
1888  *  001000          0010000100111111
1889  *     rt -----
1890  *          rs -----
1891  */
1892 std::string NMD::ABSQ_S_W(uint64 instruction)
1893 {
1894     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1895     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1896
1897     std::string rt = GPR(copy(rt_value));
1898     std::string rs = GPR(copy(rs_value));
1899
1900     return img::format("ABSQ_S.W %s, %s", rt, rs);
1901 }
1902
1903
1904 /*
1905  *
1906  *
1907  *   3         2         1
1908  *  10987654321098765432109876543210
1909  *  001000          0010000100111111
1910  *     rt -----
1911  *          rs -----
1912  */
1913 std::string NMD::ACLR(uint64 instruction)
1914 {
1915     uint64 bit_value = extract_bit_23_22_21(instruction);
1916     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1917     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
1918
1919     std::string bit = IMMEDIATE(copy(bit_value));
1920     std::string s = IMMEDIATE(copy(s_value));
1921     std::string rs = GPR(copy(rs_value));
1922
1923     return img::format("ACLR %s, %s(%s)", bit, s, rs);
1924 }
1925
1926
1927 /*
1928  *
1929  *
1930  *   3         2         1
1931  *  10987654321098765432109876543210
1932  *  001000          0010000100111111
1933  *     rt -----
1934  *          rs -----
1935  */
1936 std::string NMD::ADD(uint64 instruction)
1937 {
1938     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1939     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1940     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1941
1942     std::string rd = GPR(copy(rd_value));
1943     std::string rs = GPR(copy(rs_value));
1944     std::string rt = GPR(copy(rt_value));
1945
1946     return img::format("ADD %s, %s, %s", rd, rs, rt);
1947 }
1948
1949
1950 /*
1951  * ADD.D fd, fs, ft - Floating Point Add
1952  *
1953  *   3         2         1
1954  *  10987654321098765432109876543210
1955  *  010001                    000101
1956  *    fmt -----
1957  *          ft -----
1958  *               fs -----
1959  *                    fd -----
1960  */
1961 std::string NMD::ADD_D(uint64 instruction)
1962 {
1963     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1964     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1965     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1966
1967     std::string ft = FPR(copy(ft_value));
1968     std::string fs = FPR(copy(fs_value));
1969     std::string fd = FPR(copy(fd_value));
1970
1971     return img::format("ADD.D %s, %s, %s", fd, fs, ft);
1972 }
1973
1974
1975 /*
1976  * ADD.S fd, fs, ft - Floating Point Add
1977  *
1978  *   3         2         1
1979  *  10987654321098765432109876543210
1980  *  010001                    000101
1981  *    fmt -----
1982  *          ft -----
1983  *               fs -----
1984  *                    fd -----
1985  */
1986 std::string NMD::ADD_S(uint64 instruction)
1987 {
1988     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1989     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1990     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1991
1992     std::string ft = FPR(copy(ft_value));
1993     std::string fs = FPR(copy(fs_value));
1994     std::string fd = FPR(copy(fd_value));
1995
1996     return img::format("ADD.S %s, %s, %s", fd, fs, ft);
1997 }
1998
1999
2000 /*
2001  *
2002  *
2003  *   3         2         1
2004  *  10987654321098765432109876543210
2005  *  001000          0010000100111111
2006  *     rt -----
2007  *          rs -----
2008  */
2009 std::string NMD::ADDIU_32_(uint64 instruction)
2010 {
2011     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2012     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2013     uint64 u_value = extract_u_15_to_0(instruction);
2014
2015     std::string rt = GPR(copy(rt_value));
2016     std::string rs = GPR(copy(rs_value));
2017     std::string u = IMMEDIATE(copy(u_value));
2018
2019     return img::format("ADDIU %s, %s, %s", rt, rs, u);
2020 }
2021
2022
2023 /*
2024  *
2025  *
2026  *   3         2         1
2027  *  10987654321098765432109876543210
2028  *  001000          0010000100111111
2029  *     rt -----
2030  *          rs -----
2031  */
2032 std::string NMD::ADDIU_48_(uint64 instruction)
2033 {
2034     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2035     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
2036
2037     std::string rt = GPR(copy(rt_value));
2038     std::string s = IMMEDIATE(copy(s_value));
2039
2040     return img::format("ADDIU %s, %s", rt, s);
2041 }
2042
2043
2044 /*
2045  *
2046  *
2047  *   3         2         1
2048  *  10987654321098765432109876543210
2049  *  001000          0010000100111111
2050  *     rt -----
2051  *          rs -----
2052  */
2053 std::string NMD::ADDIU_GP48_(uint64 instruction)
2054 {
2055     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2056     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
2057
2058     std::string rt = GPR(copy(rt_value));
2059     std::string s = IMMEDIATE(copy(s_value));
2060
2061     return img::format("ADDIU %s, $%d, %s", rt, 28, s);
2062 }
2063
2064
2065 /*
2066  *
2067  *
2068  *   3         2         1
2069  *  10987654321098765432109876543210
2070  *  001000          0010000100111111
2071  *     rt -----
2072  *          rs -----
2073  */
2074 std::string NMD::ADDIU_GP_B_(uint64 instruction)
2075 {
2076     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2077     uint64 u_value = extract_u_17_to_0(instruction);
2078
2079     std::string rt = GPR(copy(rt_value));
2080     std::string u = IMMEDIATE(copy(u_value));
2081
2082     return img::format("ADDIU %s, $%d, %s", rt, 28, u);
2083 }
2084
2085
2086 /*
2087  *
2088  *
2089  *   3         2         1
2090  *  10987654321098765432109876543210
2091  *  001000          0010000100111111
2092  *     rt -----
2093  *          rs -----
2094  */
2095 std::string NMD::ADDIU_GP_W_(uint64 instruction)
2096 {
2097     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2098     uint64 u_value = extract_u_20_to_2__s2(instruction);
2099
2100     std::string rt = GPR(copy(rt_value));
2101     std::string u = IMMEDIATE(copy(u_value));
2102
2103     return img::format("ADDIU %s, $%d, %s", rt, 28, u);
2104 }
2105
2106
2107 /*
2108  *
2109  *
2110  *   3         2         1
2111  *  10987654321098765432109876543210
2112  *  001000          0010000100111111
2113  *     rt -----
2114  *          rs -----
2115  */
2116 std::string NMD::ADDIU_NEG_(uint64 instruction)
2117 {
2118     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2119     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2120     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2121
2122     std::string rt = GPR(copy(rt_value));
2123     std::string rs = GPR(copy(rs_value));
2124     std::string u = IMMEDIATE(neg_copy(u_value));
2125
2126     return img::format("ADDIU %s, %s, %s", rt, rs, u);
2127 }
2128
2129
2130 /*
2131  *
2132  *
2133  *   3         2         1
2134  *  10987654321098765432109876543210
2135  *  001000          0010000100111111
2136  *     rt -----
2137  *          rs -----
2138  */
2139 std::string NMD::ADDIU_R1_SP_(uint64 instruction)
2140 {
2141     uint64 u_value = extract_u_5_4_3_2_1_0__s2(instruction);
2142     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2143
2144     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2145     std::string u = IMMEDIATE(copy(u_value));
2146
2147     return img::format("ADDIU %s, $%d, %s", rt3, 29, u);
2148 }
2149
2150
2151 /*
2152  *
2153  *
2154  *   3         2         1
2155  *  10987654321098765432109876543210
2156  *  001000          0010000100111111
2157  *     rt -----
2158  *          rs -----
2159  */
2160 std::string NMD::ADDIU_R2_(uint64 instruction)
2161 {
2162     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2163     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2164     uint64 u_value = extract_u_2_1_0__s2(instruction);
2165
2166     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2167     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2168     std::string u = IMMEDIATE(copy(u_value));
2169
2170     return img::format("ADDIU %s, %s, %s", rt3, rs3, u);
2171 }
2172
2173
2174 /*
2175  * ADDIU[RS5] rt, s5 - Add Signed Word and Set Carry Bit
2176  *
2177  *  5432109876543210
2178  *  100100      1
2179  *     rt -----
2180  *           s - ---
2181  */
2182 std::string NMD::ADDIU_RS5_(uint64 instruction)
2183 {
2184     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
2185     int64 s_value = extract_s__se3_4_2_1_0(instruction);
2186
2187     std::string rt = GPR(copy(rt_value));
2188     std::string s = IMMEDIATE(copy(s_value));
2189
2190     return img::format("ADDIU %s, %s", rt, s);
2191 }
2192
2193
2194 /*
2195  *
2196  *
2197  *   3         2         1
2198  *  10987654321098765432109876543210
2199  *  001000               x1110000101
2200  *     rt -----
2201  *          rs -----
2202  *               rd -----
2203  */
2204 std::string NMD::ADDIUPC_32_(uint64 instruction)
2205 {
2206     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2207     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
2208
2209     std::string rt = GPR(copy(rt_value));
2210     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2211
2212     return img::format("ADDIUPC %s, %s", rt, s);
2213 }
2214
2215
2216 /*
2217  *
2218  *
2219  *   3         2         1
2220  *  10987654321098765432109876543210
2221  *  001000               x1110000101
2222  *     rt -----
2223  *          rs -----
2224  *               rd -----
2225  */
2226 std::string NMD::ADDIUPC_48_(uint64 instruction)
2227 {
2228     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2229     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
2230
2231     std::string rt = GPR(copy(rt_value));
2232     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
2233
2234     return img::format("ADDIUPC %s, %s", rt, s);
2235 }
2236
2237
2238 /*
2239  * [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
2240  *
2241  *   3         2         1
2242  *  10987654321098765432109876543210
2243  *  001000               00000001101
2244  *     rt -----
2245  *          rs -----
2246  *               rd -----
2247  */
2248 std::string NMD::ADDQ_PH(uint64 instruction)
2249 {
2250     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2251     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2252     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2253
2254     std::string rd = GPR(copy(rd_value));
2255     std::string rs = GPR(copy(rs_value));
2256     std::string rt = GPR(copy(rt_value));
2257
2258     return img::format("ADDQ.PH %s, %s, %s", rd, rs, rt);
2259 }
2260
2261
2262 /*
2263  * [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
2264  *         saturation
2265  *
2266  *   3         2         1
2267  *  10987654321098765432109876543210
2268  *  001000               10000001101
2269  *     rt -----
2270  *          rs -----
2271  *               rd -----
2272  */
2273 std::string NMD::ADDQ_S_PH(uint64 instruction)
2274 {
2275     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2276     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2277     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2278
2279     std::string rd = GPR(copy(rd_value));
2280     std::string rs = GPR(copy(rs_value));
2281     std::string rt = GPR(copy(rt_value));
2282
2283     return img::format("ADDQ_S.PH %s, %s, %s", rd, rs, rt);
2284 }
2285
2286
2287 /*
2288  * [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
2289  *
2290  *   3         2         1
2291  *  10987654321098765432109876543210
2292  *  001000               x1100000101
2293  *     rt -----
2294  *          rs -----
2295  *               rd -----
2296  */
2297 std::string NMD::ADDQ_S_W(uint64 instruction)
2298 {
2299     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2300     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2301     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2302
2303     std::string rd = GPR(copy(rd_value));
2304     std::string rs = GPR(copy(rs_value));
2305     std::string rt = GPR(copy(rt_value));
2306
2307     return img::format("ADDQ_S.W %s, %s, %s", rd, rs, rt);
2308 }
2309
2310
2311 /*
2312  * [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
2313  *         right to halve results
2314  *
2315  *   3         2         1
2316  *  10987654321098765432109876543210
2317  *  001000               00001001101
2318  *     rt -----
2319  *          rs -----
2320  *               rd -----
2321  */
2322 std::string NMD::ADDQH_PH(uint64 instruction)
2323 {
2324     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2325     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2326     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2327
2328     std::string rd = GPR(copy(rd_value));
2329     std::string rs = GPR(copy(rs_value));
2330     std::string rt = GPR(copy(rt_value));
2331
2332     return img::format("ADDQH.PH %s, %s, %s", rd, rs, rt);
2333 }
2334
2335
2336 /*
2337  * [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
2338  *         right to halve results with rounding
2339  *
2340  *   3         2         1
2341  *  10987654321098765432109876543210
2342  *  001000               10001001101
2343  *     rt -----
2344  *          rs -----
2345  *               rd -----
2346  */
2347 std::string NMD::ADDQH_R_PH(uint64 instruction)
2348 {
2349     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2350     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2351     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2352
2353     std::string rd = GPR(copy(rd_value));
2354     std::string rs = GPR(copy(rs_value));
2355     std::string rt = GPR(copy(rt_value));
2356
2357     return img::format("ADDQH_R.PH %s, %s, %s", rd, rs, rt);
2358 }
2359
2360
2361 /*
2362  * [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
2363  *         results with rounding
2364  *
2365  *   3         2         1
2366  *  10987654321098765432109876543210
2367  *  001000               00010001101
2368  *     rt -----
2369  *          rs -----
2370  *               rd -----
2371  */
2372 std::string NMD::ADDQH_R_W(uint64 instruction)
2373 {
2374     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2375     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2376     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2377
2378     std::string rd = GPR(copy(rd_value));
2379     std::string rs = GPR(copy(rs_value));
2380     std::string rt = GPR(copy(rt_value));
2381
2382     return img::format("ADDQH_R.W %s, %s, %s", rd, rs, rt);
2383 }
2384
2385
2386 /*
2387  * [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
2388  *         results
2389  *
2390  *   3         2         1
2391  *  10987654321098765432109876543210
2392  *  001000               10010001101
2393  *     rt -----
2394  *          rs -----
2395  *               rd -----
2396  */
2397 std::string NMD::ADDQH_W(uint64 instruction)
2398 {
2399     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2400     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2401     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2402
2403     std::string rd = GPR(copy(rd_value));
2404     std::string rs = GPR(copy(rs_value));
2405     std::string rt = GPR(copy(rt_value));
2406
2407     return img::format("ADDQH.W %s, %s, %s", rd, rs, rt);
2408 }
2409
2410
2411 /*
2412  * [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
2413  *
2414  *   3         2         1
2415  *  10987654321098765432109876543210
2416  *  001000               x1110000101
2417  *     rt -----
2418  *          rs -----
2419  *               rd -----
2420  */
2421 std::string NMD::ADDSC(uint64 instruction)
2422 {
2423     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2424     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2425     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2426
2427     std::string rd = GPR(copy(rd_value));
2428     std::string rs = GPR(copy(rs_value));
2429     std::string rt = GPR(copy(rt_value));
2430
2431     return img::format("ADDSC %s, %s, %s", rd, rs, rt);
2432 }
2433
2434
2435 /*
2436  * ADDU[16] rd3, rs3, rt3 -
2437  *
2438  *  5432109876543210
2439  *  101100         0
2440  *    rt3 ---
2441  *       rs3 ---
2442  *          rd3 ---
2443  */
2444 std::string NMD::ADDU_16_(uint64 instruction)
2445 {
2446     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2447     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2448     uint64 rd3_value = extract_rd3_3_2_1(instruction);
2449
2450     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2451     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2452     std::string rd3 = GPR(decode_gpr_gpr3(rd3_value));
2453
2454     return img::format("ADDU %s, %s, %s", rd3, rs3, rt3);
2455 }
2456
2457
2458 /*
2459  *
2460  *
2461  *   3         2         1
2462  *  10987654321098765432109876543210
2463  *  001000               x1110000101
2464  *     rt -----
2465  *          rs -----
2466  *               rd -----
2467  */
2468 std::string NMD::ADDU_32_(uint64 instruction)
2469 {
2470     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2471     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2472     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2473
2474     std::string rd = GPR(copy(rd_value));
2475     std::string rs = GPR(copy(rs_value));
2476     std::string rt = GPR(copy(rt_value));
2477
2478     return img::format("ADDU %s, %s, %s", rd, rs, rt);
2479 }
2480
2481
2482 /*
2483  *
2484  *
2485  *   3         2         1
2486  *  10987654321098765432109876543210
2487  *  001000               x1110000101
2488  *     rt -----
2489  *          rs -----
2490  *               rd -----
2491  */
2492 std::string NMD::ADDU_4X4_(uint64 instruction)
2493 {
2494     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
2495     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
2496
2497     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
2498     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
2499
2500     return img::format("ADDU %s, %s", rs4, rt4);
2501 }
2502
2503
2504 /*
2505  * [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
2506  *
2507  *   3         2         1
2508  *  10987654321098765432109876543210
2509  *  001000               00100001101
2510  *     rt -----
2511  *          rs -----
2512  *               rd -----
2513  */
2514 std::string NMD::ADDU_PH(uint64 instruction)
2515 {
2516     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2517     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2518     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2519
2520     std::string rd = GPR(copy(rd_value));
2521     std::string rs = GPR(copy(rs_value));
2522     std::string rt = GPR(copy(rt_value));
2523
2524     return img::format("ADDU.PH %s, %s, %s", rd, rs, rt);
2525 }
2526
2527
2528 /*
2529  * ADDU.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2530  *
2531  *   3         2         1
2532  *  10987654321098765432109876543210
2533  *  001000               00011001101
2534  *     rt -----
2535  *          rs -----
2536  *               rd -----
2537  */
2538 std::string NMD::ADDU_QB(uint64 instruction)
2539 {
2540     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2541     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2542     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2543
2544     std::string rd = GPR(copy(rd_value));
2545     std::string rs = GPR(copy(rs_value));
2546     std::string rt = GPR(copy(rt_value));
2547
2548     return img::format("ADDU.QB %s, %s, %s", rd, rs, rt);
2549 }
2550
2551
2552 /*
2553  * [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
2554  *         saturation
2555  *
2556  *   3         2         1
2557  *  10987654321098765432109876543210
2558  *  001000               10100001101
2559  *     rt -----
2560  *          rs -----
2561  *               rd -----
2562  */
2563 std::string NMD::ADDU_S_PH(uint64 instruction)
2564 {
2565     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2566     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2567     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2568
2569     std::string rd = GPR(copy(rd_value));
2570     std::string rs = GPR(copy(rs_value));
2571     std::string rt = GPR(copy(rt_value));
2572
2573     return img::format("ADDU_S.PH %s, %s, %s", rd, rs, rt);
2574 }
2575
2576
2577 /*
2578  * ADDU_S.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2579  *
2580  *   3         2         1
2581  *  10987654321098765432109876543210
2582  *  001000               10011001101
2583  *     rt -----
2584  *          rs -----
2585  *               rd -----
2586  */
2587 std::string NMD::ADDU_S_QB(uint64 instruction)
2588 {
2589     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2590     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2591     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2592
2593     std::string rd = GPR(copy(rd_value));
2594     std::string rs = GPR(copy(rs_value));
2595     std::string rt = GPR(copy(rt_value));
2596
2597     return img::format("ADDU_S.QB %s, %s, %s", rd, rs, rt);
2598 }
2599
2600
2601 /*
2602  * ADDUH.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2603  *                       to Halve Results
2604  *
2605  *   3         2         1
2606  *  10987654321098765432109876543210
2607  *  001000               00101001101
2608  *     rt -----
2609  *          rs -----
2610  *               rd -----
2611  */
2612 std::string NMD::ADDUH_QB(uint64 instruction)
2613 {
2614     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2615     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2616     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2617
2618     std::string rd = GPR(copy(rd_value));
2619     std::string rs = GPR(copy(rs_value));
2620     std::string rt = GPR(copy(rt_value));
2621
2622     return img::format("ADDUH.QB %s, %s, %s", rd, rs, rt);
2623 }
2624
2625
2626 /*
2627  * ADDUH_R.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2628  *                         to Halve Results
2629  *
2630  *   3         2         1
2631  *  10987654321098765432109876543210
2632  *  001000               10101001101
2633  *     rt -----
2634  *          rs -----
2635  *               rd -----
2636  */
2637 std::string NMD::ADDUH_R_QB(uint64 instruction)
2638 {
2639     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2640     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2641     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2642
2643     std::string rd = GPR(copy(rd_value));
2644     std::string rs = GPR(copy(rs_value));
2645     std::string rt = GPR(copy(rt_value));
2646
2647     return img::format("ADDUH_R.QB %s, %s, %s", rd, rs, rt);
2648 }
2649
2650 /*
2651  * ADDWC rd, rt, rs - Add Word with Carry Bit
2652  *
2653  *   3         2         1
2654  *  10987654321098765432109876543210
2655  *  001000               x1111000101
2656  *     rt -----
2657  *          rs -----
2658  *               rd -----
2659  */
2660 std::string NMD::ADDWC(uint64 instruction)
2661 {
2662     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2663     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2664     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2665
2666     std::string rd = GPR(copy(rd_value));
2667     std::string rs = GPR(copy(rs_value));
2668     std::string rt = GPR(copy(rt_value));
2669
2670     return img::format("ADDWC %s, %s, %s", rd, rs, rt);
2671 }
2672
2673
2674 /*
2675  *
2676  *
2677  *   3         2         1
2678  *  10987654321098765432109876543210
2679  *  001000               x1110000101
2680  *     rt -----
2681  *          rs -----
2682  *               rd -----
2683  */
2684 std::string NMD::ALUIPC(uint64 instruction)
2685 {
2686     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2687     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
2688
2689     std::string rt = GPR(copy(rt_value));
2690     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2691
2692     return img::format("ALUIPC %s, %%pcrel_hi(%s)", rt, s);
2693 }
2694
2695
2696 /*
2697  * AND[16] rt3, rs3 -
2698  *
2699  *  5432109876543210
2700  *  101100
2701  *    rt3 ---
2702  *       rs3 ---
2703  *           eu ----
2704  */
2705 std::string NMD::AND_16_(uint64 instruction)
2706 {
2707     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2708     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2709
2710     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2711     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2712
2713     return img::format("AND %s, %s", rs3, rt3);
2714 }
2715
2716
2717 /*
2718  *
2719  *
2720  *   3         2         1
2721  *  10987654321098765432109876543210
2722  *  001000               x1110000101
2723  *     rt -----
2724  *          rs -----
2725  *               rd -----
2726  */
2727 std::string NMD::AND_32_(uint64 instruction)
2728 {
2729     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2730     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2731     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2732
2733     std::string rd = GPR(copy(rd_value));
2734     std::string rs = GPR(copy(rs_value));
2735     std::string rt = GPR(copy(rt_value));
2736
2737     return img::format("AND %s, %s, %s", rd, rs, rt);
2738 }
2739
2740
2741 /*
2742  * ANDI rt, rs, u -
2743  *
2744  *  5432109876543210
2745  *  101100
2746  *    rt3 ---
2747  *       rs3 ---
2748  *           eu ----
2749  */
2750 std::string NMD::ANDI_16_(uint64 instruction)
2751 {
2752     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2753     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2754     uint64 eu_value = extract_eu_3_2_1_0(instruction);
2755
2756     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2757     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2758     std::string eu = IMMEDIATE(encode_eu_from_u_andi16(eu_value));
2759
2760     return img::format("ANDI %s, %s, %s", rt3, rs3, eu);
2761 }
2762
2763
2764 /*
2765  *
2766  *
2767  *   3         2         1
2768  *  10987654321098765432109876543210
2769  *  001000               x1110000101
2770  *     rt -----
2771  *          rs -----
2772  *               rd -----
2773  */
2774 std::string NMD::ANDI_32_(uint64 instruction)
2775 {
2776     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2777     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2778     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2779
2780     std::string rt = GPR(copy(rt_value));
2781     std::string rs = GPR(copy(rs_value));
2782     std::string u = IMMEDIATE(copy(u_value));
2783
2784     return img::format("ANDI %s, %s, %s", rt, rs, u);
2785 }
2786
2787
2788 /*
2789  *
2790  *
2791  *   3         2         1
2792  *  10987654321098765432109876543210
2793  *  001000               x1110000101
2794  *     rt -----
2795  *          rs -----
2796  *               rd -----
2797  */
2798 std::string NMD::APPEND(uint64 instruction)
2799 {
2800     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2801     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2802     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
2803
2804     std::string rt = GPR(copy(rt_value));
2805     std::string rs = GPR(copy(rs_value));
2806     std::string sa = IMMEDIATE(copy(sa_value));
2807
2808     return img::format("APPEND %s, %s, %s", rt, rs, sa);
2809 }
2810
2811
2812 /*
2813  *
2814  *
2815  *   3         2         1
2816  *  10987654321098765432109876543210
2817  *  001000               x1110000101
2818  *     rt -----
2819  *          rs -----
2820  *               rd -----
2821  */
2822 std::string NMD::ASET(uint64 instruction)
2823 {
2824     uint64 bit_value = extract_bit_23_22_21(instruction);
2825     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2826     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
2827
2828     std::string bit = IMMEDIATE(copy(bit_value));
2829     std::string s = IMMEDIATE(copy(s_value));
2830     std::string rs = GPR(copy(rs_value));
2831
2832     return img::format("ASET %s, %s(%s)", bit, s, rs);
2833 }
2834
2835
2836 /*
2837  *
2838  *
2839  *   3         2         1
2840  *  10987654321098765432109876543210
2841  *  001000               x1110000101
2842  *     rt -----
2843  *          rs -----
2844  *               rd -----
2845  */
2846 std::string NMD::BALC_16_(uint64 instruction)
2847 {
2848     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2849
2850     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
2851
2852     return img::format("BALC %s", s);
2853 }
2854
2855
2856 /*
2857  *
2858  *
2859  *   3         2         1
2860  *  10987654321098765432109876543210
2861  *  001000               x1110000101
2862  *     rt -----
2863  *          rs -----
2864  *               rd -----
2865  */
2866 std::string NMD::BALC_32_(uint64 instruction)
2867 {
2868     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2869
2870     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2871
2872     return img::format("BALC %s", s);
2873 }
2874
2875
2876 /*
2877  *
2878  *
2879  *   3         2         1
2880  *  10987654321098765432109876543210
2881  *  001000               x1110000101
2882  *     rt -----
2883  *          rs -----
2884  *               rd -----
2885  */
2886 std::string NMD::BALRSC(uint64 instruction)
2887 {
2888     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2889     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2890
2891     std::string rt = GPR(copy(rt_value));
2892     std::string rs = GPR(copy(rs_value));
2893
2894     return img::format("BALRSC %s, %s", rt, rs);
2895 }
2896
2897
2898 /*
2899  *
2900  *
2901  *   3         2         1
2902  *  10987654321098765432109876543210
2903  *  001000               x1110000101
2904  *     rt -----
2905  *          rs -----
2906  *               rd -----
2907  */
2908 std::string NMD::BBEQZC(uint64 instruction)
2909 {
2910     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2911     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2912     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2913
2914     std::string rt = GPR(copy(rt_value));
2915     std::string bit = IMMEDIATE(copy(bit_value));
2916     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2917
2918     return img::format("BBEQZC %s, %s, %s", rt, bit, s);
2919 }
2920
2921
2922 /*
2923  *
2924  *
2925  *   3         2         1
2926  *  10987654321098765432109876543210
2927  *  001000               x1110000101
2928  *     rt -----
2929  *          rs -----
2930  *               rd -----
2931  */
2932 std::string NMD::BBNEZC(uint64 instruction)
2933 {
2934     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2935     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2936     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2937
2938     std::string rt = GPR(copy(rt_value));
2939     std::string bit = IMMEDIATE(copy(bit_value));
2940     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2941
2942     return img::format("BBNEZC %s, %s, %s", rt, bit, s);
2943 }
2944
2945
2946 /*
2947  *
2948  *
2949  *   3         2         1
2950  *  10987654321098765432109876543210
2951  *  001000               x1110000101
2952  *     rt -----
2953  *          rs -----
2954  *               rd -----
2955  */
2956 std::string NMD::BC_16_(uint64 instruction)
2957 {
2958     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2959
2960     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
2961
2962     return img::format("BC %s", s);
2963 }
2964
2965
2966 /*
2967  *
2968  *
2969  *   3         2         1
2970  *  10987654321098765432109876543210
2971  *  001000               x1110000101
2972  *     rt -----
2973  *          rs -----
2974  *               rd -----
2975  */
2976 std::string NMD::BC_32_(uint64 instruction)
2977 {
2978     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2979
2980     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2981
2982     return img::format("BC %s", s);
2983 }
2984
2985
2986 /*
2987  *
2988  *
2989  *   3         2         1
2990  *  10987654321098765432109876543210
2991  *  001000               x1110000101
2992  *     rt -----
2993  *          rs -----
2994  *               rd -----
2995  */
2996 std::string NMD::BC1EQZC(uint64 instruction)
2997 {
2998     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
2999     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3000
3001     std::string ft = FPR(copy(ft_value));
3002     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3003
3004     return img::format("BC1EQZC %s, %s", ft, s);
3005 }
3006
3007
3008 /*
3009  *
3010  *
3011  *   3         2         1
3012  *  10987654321098765432109876543210
3013  *  001000               x1110000101
3014  *     rt -----
3015  *          rs -----
3016  *               rd -----
3017  */
3018 std::string NMD::BC1NEZC(uint64 instruction)
3019 {
3020     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3021     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3022
3023     std::string ft = FPR(copy(ft_value));
3024     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3025
3026     return img::format("BC1NEZC %s, %s", ft, s);
3027 }
3028
3029
3030 /*
3031  *
3032  *
3033  *   3         2         1
3034  *  10987654321098765432109876543210
3035  *  001000               x1110000101
3036  *     rt -----
3037  *          rs -----
3038  *               rd -----
3039  */
3040 std::string NMD::BC2EQZC(uint64 instruction)
3041 {
3042     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
3043     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3044
3045     std::string ct = CPR(copy(ct_value));
3046     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3047
3048     return img::format("BC2EQZC %s, %s", ct, s);
3049 }
3050
3051
3052 /*
3053  *
3054  *
3055  *   3         2         1
3056  *  10987654321098765432109876543210
3057  *  001000               x1110000101
3058  *     rt -----
3059  *          rs -----
3060  *               rd -----
3061  */
3062 std::string NMD::BC2NEZC(uint64 instruction)
3063 {
3064     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
3065     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3066
3067     std::string ct = CPR(copy(ct_value));
3068     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3069
3070     return img::format("BC2NEZC %s, %s", ct, s);
3071 }
3072
3073
3074 /*
3075  *
3076  *
3077  *   3         2         1
3078  *  10987654321098765432109876543210
3079  *  001000               x1110000101
3080  *     rt -----
3081  *          rs -----
3082  *               rd -----
3083  */
3084 std::string NMD::BEQC_16_(uint64 instruction)
3085 {
3086     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3087     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3088     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
3089
3090     std::string rs3 = GPR(encode_rs3_and_check_rs3_lt_rt3(rs3_value));
3091     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3092     std::string u = ADDRESS(encode_u_from_address(u_value), 2);
3093
3094     return img::format("BEQC %s, %s, %s", rs3, rt3, u);
3095 }
3096
3097
3098 /*
3099  *
3100  *
3101  *   3         2         1
3102  *  10987654321098765432109876543210
3103  *  001000               x1110000101
3104  *     rt -----
3105  *          rs -----
3106  *               rd -----
3107  */
3108 std::string NMD::BEQC_32_(uint64 instruction)
3109 {
3110     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3111     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3112     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3113
3114     std::string rs = GPR(copy(rs_value));
3115     std::string rt = GPR(copy(rt_value));
3116     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3117
3118     return img::format("BEQC %s, %s, %s", rs, rt, s);
3119 }
3120
3121
3122 /*
3123  *
3124  *
3125  *   3         2         1
3126  *  10987654321098765432109876543210
3127  *  001000               x1110000101
3128  *     rt -----
3129  *          rs -----
3130  *               rd -----
3131  */
3132 std::string NMD::BEQIC(uint64 instruction)
3133 {
3134     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3135     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3136     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3137
3138     std::string rt = GPR(copy(rt_value));
3139     std::string u = IMMEDIATE(copy(u_value));
3140     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3141
3142     return img::format("BEQIC %s, %s, %s", rt, u, s);
3143 }
3144
3145
3146 /*
3147  *
3148  *
3149  *   3         2         1
3150  *  10987654321098765432109876543210
3151  *  001000               x1110000101
3152  *     rt -----
3153  *          rs -----
3154  *               rd -----
3155  */
3156 std::string NMD::BEQZC_16_(uint64 instruction)
3157 {
3158     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3159     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
3160
3161     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3162     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
3163
3164     return img::format("BEQZC %s, %s", rt3, s);
3165 }
3166
3167
3168 /*
3169  *
3170  *
3171  *   3         2         1
3172  *  10987654321098765432109876543210
3173  *  001000               x1110000101
3174  *     rt -----
3175  *          rs -----
3176  *               rd -----
3177  */
3178 std::string NMD::BGEC(uint64 instruction)
3179 {
3180     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3181     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3182     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3183
3184     std::string rs = GPR(copy(rs_value));
3185     std::string rt = GPR(copy(rt_value));
3186     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3187
3188     return img::format("BGEC %s, %s, %s", rs, rt, s);
3189 }
3190
3191
3192 /*
3193  *
3194  *
3195  *   3         2         1
3196  *  10987654321098765432109876543210
3197  *  001000               x1110000101
3198  *     rt -----
3199  *          rs -----
3200  *               rd -----
3201  */
3202 std::string NMD::BGEIC(uint64 instruction)
3203 {
3204     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3205     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3206     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3207
3208     std::string rt = GPR(copy(rt_value));
3209     std::string u = IMMEDIATE(copy(u_value));
3210     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3211
3212     return img::format("BGEIC %s, %s, %s", rt, u, s);
3213 }
3214
3215
3216 /*
3217  *
3218  *
3219  *   3         2         1
3220  *  10987654321098765432109876543210
3221  *  001000               x1110000101
3222  *     rt -----
3223  *          rs -----
3224  *               rd -----
3225  */
3226 std::string NMD::BGEIUC(uint64 instruction)
3227 {
3228     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3229     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3230     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3231
3232     std::string rt = GPR(copy(rt_value));
3233     std::string u = IMMEDIATE(copy(u_value));
3234     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3235
3236     return img::format("BGEIUC %s, %s, %s", rt, u, s);
3237 }
3238
3239
3240 /*
3241  *
3242  *
3243  *   3         2         1
3244  *  10987654321098765432109876543210
3245  *  001000               x1110000101
3246  *     rt -----
3247  *          rs -----
3248  *               rd -----
3249  */
3250 std::string NMD::BGEUC(uint64 instruction)
3251 {
3252     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3253     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3254     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3255
3256     std::string rs = GPR(copy(rs_value));
3257     std::string rt = GPR(copy(rt_value));
3258     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3259
3260     return img::format("BGEUC %s, %s, %s", rs, rt, s);
3261 }
3262
3263
3264 /*
3265  *
3266  *
3267  *   3         2         1
3268  *  10987654321098765432109876543210
3269  *  001000               x1110000101
3270  *     rt -----
3271  *          rs -----
3272  *               rd -----
3273  */
3274 std::string NMD::BLTC(uint64 instruction)
3275 {
3276     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3277     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3278     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3279
3280     std::string rs = GPR(copy(rs_value));
3281     std::string rt = GPR(copy(rt_value));
3282     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3283
3284     return img::format("BLTC %s, %s, %s", rs, rt, s);
3285 }
3286
3287
3288 /*
3289  *
3290  *
3291  *   3         2         1
3292  *  10987654321098765432109876543210
3293  *  001000               x1110000101
3294  *     rt -----
3295  *          rs -----
3296  *               rd -----
3297  */
3298 std::string NMD::BLTIC(uint64 instruction)
3299 {
3300     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3301     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3302     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3303
3304     std::string rt = GPR(copy(rt_value));
3305     std::string u = IMMEDIATE(copy(u_value));
3306     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3307
3308     return img::format("BLTIC %s, %s, %s", rt, u, s);
3309 }
3310
3311
3312 /*
3313  *
3314  *
3315  *   3         2         1
3316  *  10987654321098765432109876543210
3317  *  001000               x1110000101
3318  *     rt -----
3319  *          rs -----
3320  *               rd -----
3321  */
3322 std::string NMD::BLTIUC(uint64 instruction)
3323 {
3324     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3325     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3326     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3327
3328     std::string rt = GPR(copy(rt_value));
3329     std::string u = IMMEDIATE(copy(u_value));
3330     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3331
3332     return img::format("BLTIUC %s, %s, %s", rt, u, s);
3333 }
3334
3335
3336 /*
3337  *
3338  *
3339  *   3         2         1
3340  *  10987654321098765432109876543210
3341  *  001000               x1110000101
3342  *     rt -----
3343  *          rs -----
3344  *               rd -----
3345  */
3346 std::string NMD::BLTUC(uint64 instruction)
3347 {
3348     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3349     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3350     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3351
3352     std::string rs = GPR(copy(rs_value));
3353     std::string rt = GPR(copy(rt_value));
3354     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3355
3356     return img::format("BLTUC %s, %s, %s", rs, rt, s);
3357 }
3358
3359
3360 /*
3361  *
3362  *
3363  *   3         2         1
3364  *  10987654321098765432109876543210
3365  *  001000               x1110000101
3366  *     rt -----
3367  *          rs -----
3368  *               rd -----
3369  */
3370 std::string NMD::BNEC_16_(uint64 instruction)
3371 {
3372     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3373     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3374     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
3375
3376     std::string rs3 = GPR(encode_rs3_and_check_rs3_ge_rt3(rs3_value));
3377     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3378     std::string u = ADDRESS(encode_u_from_address(u_value), 2);
3379
3380     return img::format("BNEC %s, %s, %s", rs3, rt3, u);
3381 }
3382
3383
3384 /*
3385  *
3386  *
3387  *   3         2         1
3388  *  10987654321098765432109876543210
3389  *  001000               x1110000101
3390  *     rt -----
3391  *          rs -----
3392  *               rd -----
3393  */
3394 std::string NMD::BNEC_32_(uint64 instruction)
3395 {
3396     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3397     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3398     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3399
3400     std::string rs = GPR(copy(rs_value));
3401     std::string rt = GPR(copy(rt_value));
3402     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3403
3404     return img::format("BNEC %s, %s, %s", rs, rt, s);
3405 }
3406
3407
3408 /*
3409  *
3410  *
3411  *   3         2         1
3412  *  10987654321098765432109876543210
3413  *  001000               x1110000101
3414  *     rt -----
3415  *          rs -----
3416  *               rd -----
3417  */
3418 std::string NMD::BNEIC(uint64 instruction)
3419 {
3420     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3421     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3422     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3423
3424     std::string rt = GPR(copy(rt_value));
3425     std::string u = IMMEDIATE(copy(u_value));
3426     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3427
3428     return img::format("BNEIC %s, %s, %s", rt, u, s);
3429 }
3430
3431
3432 /*
3433  *
3434  *
3435  *   3         2         1
3436  *  10987654321098765432109876543210
3437  *  001000               x1110000101
3438  *     rt -----
3439  *          rs -----
3440  *               rd -----
3441  */
3442 std::string NMD::BNEZC_16_(uint64 instruction)
3443 {
3444     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3445     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
3446
3447     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3448     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
3449
3450     return img::format("BNEZC %s, %s", rt3, s);
3451 }
3452
3453
3454 /*
3455  * [DSP] BPOSGE32C offset - Branch on greater than or equal to value 32 in
3456  *   DSPControl Pos field
3457  *
3458  *   3         2         1
3459  *  10987654321098765432109876543210
3460  *  100010xxxxx0010001
3461  *            s[13:1] -------------
3462  *                           s[14] -
3463  */
3464 std::string NMD::BPOSGE32C(uint64 instruction)
3465 {
3466     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3467
3468     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3469
3470     return img::format("BPOSGE32C %s", s);
3471 }
3472
3473
3474 /*
3475  *
3476  *
3477  *   3         2         1
3478  *  10987654321098765432109876543210
3479  *  001000               x1110000101
3480  *     rt -----
3481  *          rs -----
3482  *               rd -----
3483  */
3484 std::string NMD::BREAK_16_(uint64 instruction)
3485 {
3486     uint64 code_value = extract_code_2_1_0(instruction);
3487
3488     std::string code = IMMEDIATE(copy(code_value));
3489
3490     return img::format("BREAK %s", code);
3491 }
3492
3493
3494 /*
3495  * BREAK code - Break. Cause a Breakpoint exception
3496  *
3497  *   3         2         1
3498  *  10987654321098765432109876543210
3499  *  001000               x1110000101
3500  *     rt -----
3501  *          rs -----
3502  *               rd -----
3503  */
3504 std::string NMD::BREAK_32_(uint64 instruction)
3505 {
3506     uint64 code_value = extract_code_18_to_0(instruction);
3507
3508     std::string code = IMMEDIATE(copy(code_value));
3509
3510     return img::format("BREAK %s", code);
3511 }
3512
3513
3514 /*
3515  *
3516  *
3517  *   3         2         1
3518  *  10987654321098765432109876543210
3519  *  001000               x1110000101
3520  *     rt -----
3521  *          rs -----
3522  *               rd -----
3523  */
3524 std::string NMD::BRSC(uint64 instruction)
3525 {
3526     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3527
3528     std::string rs = GPR(copy(rs_value));
3529
3530     return img::format("BRSC %s", rs);
3531 }
3532
3533
3534 /*
3535  *
3536  *
3537  *   3         2         1
3538  *  10987654321098765432109876543210
3539  *  001000               x1110000101
3540  *     rt -----
3541  *          rs -----
3542  *               rd -----
3543  */
3544 std::string NMD::CACHE(uint64 instruction)
3545 {
3546     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3547     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3548     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3549
3550     std::string op = IMMEDIATE(copy(op_value));
3551     std::string s = IMMEDIATE(copy(s_value));
3552     std::string rs = GPR(copy(rs_value));
3553
3554     return img::format("CACHE %s, %s(%s)", op, s, rs);
3555 }
3556
3557
3558 /*
3559  *
3560  *
3561  *   3         2         1
3562  *  10987654321098765432109876543210
3563  *  001000               x1110000101
3564  *     rt -----
3565  *          rs -----
3566  *               rd -----
3567  */
3568 std::string NMD::CACHEE(uint64 instruction)
3569 {
3570     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3571     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3572     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3573
3574     std::string op = IMMEDIATE(copy(op_value));
3575     std::string s = IMMEDIATE(copy(s_value));
3576     std::string rs = GPR(copy(rs_value));
3577
3578     return img::format("CACHEE %s, %s(%s)", op, s, rs);
3579 }
3580
3581
3582 /*
3583  *
3584  *
3585  *   3         2         1
3586  *  10987654321098765432109876543210
3587  *  001000               x1110000101
3588  *     rt -----
3589  *          rs -----
3590  *               rd -----
3591  */
3592 std::string NMD::CEIL_L_D(uint64 instruction)
3593 {
3594     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3595     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3596
3597     std::string ft = FPR(copy(ft_value));
3598     std::string fs = FPR(copy(fs_value));
3599
3600     return img::format("CEIL.L.D %s, %s", ft, fs);
3601 }
3602
3603
3604 /*
3605  *
3606  *
3607  *   3         2         1
3608  *  10987654321098765432109876543210
3609  *  001000               x1110000101
3610  *     rt -----
3611  *          rs -----
3612  *               rd -----
3613  */
3614 std::string NMD::CEIL_L_S(uint64 instruction)
3615 {
3616     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3617     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3618
3619     std::string ft = FPR(copy(ft_value));
3620     std::string fs = FPR(copy(fs_value));
3621
3622     return img::format("CEIL.L.S %s, %s", ft, fs);
3623 }
3624
3625
3626 /*
3627  *
3628  *
3629  *   3         2         1
3630  *  10987654321098765432109876543210
3631  *  001000               x1110000101
3632  *     rt -----
3633  *          rs -----
3634  *               rd -----
3635  */
3636 std::string NMD::CEIL_W_D(uint64 instruction)
3637 {
3638     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3639     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3640
3641     std::string ft = FPR(copy(ft_value));
3642     std::string fs = FPR(copy(fs_value));
3643
3644     return img::format("CEIL.W.D %s, %s", ft, fs);
3645 }
3646
3647
3648 /*
3649  *
3650  *
3651  *   3         2         1
3652  *  10987654321098765432109876543210
3653  *  001000               x1110000101
3654  *     rt -----
3655  *          rs -----
3656  *               rd -----
3657  */
3658 std::string NMD::CEIL_W_S(uint64 instruction)
3659 {
3660     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3661     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3662
3663     std::string ft = FPR(copy(ft_value));
3664     std::string fs = FPR(copy(fs_value));
3665
3666     return img::format("CEIL.W.S %s, %s", ft, fs);
3667 }
3668
3669
3670 /*
3671  *
3672  *
3673  *   3         2         1
3674  *  10987654321098765432109876543210
3675  *  001000               x1110000101
3676  *     rt -----
3677  *          rs -----
3678  *               rd -----
3679  */
3680 std::string NMD::CFC1(uint64 instruction)
3681 {
3682     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3683     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3684
3685     std::string rt = GPR(copy(rt_value));
3686     std::string cs = CPR(copy(cs_value));
3687
3688     return img::format("CFC1 %s, %s", rt, cs);
3689 }
3690
3691
3692 /*
3693  *
3694  *
3695  *   3         2         1
3696  *  10987654321098765432109876543210
3697  *  001000               x1110000101
3698  *     rt -----
3699  *          rs -----
3700  *               rd -----
3701  */
3702 std::string NMD::CFC2(uint64 instruction)
3703 {
3704     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3705     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3706
3707     std::string rt = GPR(copy(rt_value));
3708     std::string cs = CPR(copy(cs_value));
3709
3710     return img::format("CFC2 %s, %s", rt, cs);
3711 }
3712
3713
3714 /*
3715  *
3716  *
3717  *   3         2         1
3718  *  10987654321098765432109876543210
3719  *  001000               x1110000101
3720  *     rt -----
3721  *          rs -----
3722  *               rd -----
3723  */
3724 std::string NMD::CLASS_D(uint64 instruction)
3725 {
3726     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3727     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3728
3729     std::string ft = FPR(copy(ft_value));
3730     std::string fs = FPR(copy(fs_value));
3731
3732     return img::format("CLASS.D %s, %s", ft, fs);
3733 }
3734
3735
3736 /*
3737  *
3738  *
3739  *   3         2         1
3740  *  10987654321098765432109876543210
3741  *  001000               x1110000101
3742  *     rt -----
3743  *          rs -----
3744  *               rd -----
3745  */
3746 std::string NMD::CLASS_S(uint64 instruction)
3747 {
3748     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3749     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3750
3751     std::string ft = FPR(copy(ft_value));
3752     std::string fs = FPR(copy(fs_value));
3753
3754     return img::format("CLASS.S %s, %s", ft, fs);
3755 }
3756
3757
3758 /*
3759  *
3760  *
3761  *   3         2         1
3762  *  10987654321098765432109876543210
3763  *  001000               x1110000101
3764  *     rt -----
3765  *          rs -----
3766  *               rd -----
3767  */
3768 std::string NMD::CLO(uint64 instruction)
3769 {
3770     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3771     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3772
3773     std::string rt = GPR(copy(rt_value));
3774     std::string rs = GPR(copy(rs_value));
3775
3776     return img::format("CLO %s, %s", rt, rs);
3777 }
3778
3779
3780 /*
3781  *
3782  *
3783  *   3         2         1
3784  *  10987654321098765432109876543210
3785  *  001000               x1110000101
3786  *     rt -----
3787  *          rs -----
3788  *               rd -----
3789  */
3790 std::string NMD::CLZ(uint64 instruction)
3791 {
3792     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3793     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3794
3795     std::string rt = GPR(copy(rt_value));
3796     std::string rs = GPR(copy(rs_value));
3797
3798     return img::format("CLZ %s, %s", rt, rs);
3799 }
3800
3801
3802 /*
3803  *
3804  *
3805  *   3         2         1
3806  *  10987654321098765432109876543210
3807  *  001000               x1110000101
3808  *     rt -----
3809  *          rs -----
3810  *               rd -----
3811  */
3812 std::string NMD::CMP_AF_D(uint64 instruction)
3813 {
3814     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3815     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3816     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3817
3818     std::string fd = FPR(copy(fd_value));
3819     std::string fs = FPR(copy(fs_value));
3820     std::string ft = FPR(copy(ft_value));
3821
3822     return img::format("CMP.AF.D %s, %s, %s", fd, fs, ft);
3823 }
3824
3825
3826 /*
3827  *
3828  *
3829  *   3         2         1
3830  *  10987654321098765432109876543210
3831  *  001000               x1110000101
3832  *     rt -----
3833  *          rs -----
3834  *               rd -----
3835  */
3836 std::string NMD::CMP_AF_S(uint64 instruction)
3837 {
3838     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3839     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3840     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3841
3842     std::string fd = FPR(copy(fd_value));
3843     std::string fs = FPR(copy(fs_value));
3844     std::string ft = FPR(copy(ft_value));
3845
3846     return img::format("CMP.AF.S %s, %s, %s", fd, fs, ft);
3847 }
3848
3849
3850 /*
3851  *
3852  *
3853  *   3         2         1
3854  *  10987654321098765432109876543210
3855  *  001000               x1110000101
3856  *     rt -----
3857  *          rs -----
3858  *               rd -----
3859  */
3860 std::string NMD::CMP_EQ_D(uint64 instruction)
3861 {
3862     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3863     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3864     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3865
3866     std::string fd = FPR(copy(fd_value));
3867     std::string fs = FPR(copy(fs_value));
3868     std::string ft = FPR(copy(ft_value));
3869
3870     return img::format("CMP.EQ.D %s, %s, %s", fd, fs, ft);
3871 }
3872
3873
3874 /*
3875  * [DSP] CMP.EQ.PH rs, rt - Compare vectors of signed integer halfword values
3876  *
3877  *   3         2         1
3878  *  10987654321098765432109876543210
3879  *  001000          xxxxxx0000000101
3880  *     rt -----
3881  *          rs -----
3882  */
3883 std::string NMD::CMP_EQ_PH(uint64 instruction)
3884 {
3885     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3886     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3887
3888     std::string rs = GPR(copy(rs_value));
3889     std::string rt = GPR(copy(rt_value));
3890
3891     return img::format("CMP.EQ.PH %s, %s", rs, rt);
3892 }
3893
3894
3895 /*
3896  *
3897  *
3898  *   3         2         1
3899  *  10987654321098765432109876543210
3900  *  001000               x1110000101
3901  *     rt -----
3902  *          rs -----
3903  *               rd -----
3904  */
3905 std::string NMD::CMP_EQ_S(uint64 instruction)
3906 {
3907     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3908     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3909     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3910
3911     std::string fd = FPR(copy(fd_value));
3912     std::string fs = FPR(copy(fs_value));
3913     std::string ft = FPR(copy(ft_value));
3914
3915     return img::format("CMP.EQ.S %s, %s, %s", fd, fs, ft);
3916 }
3917
3918
3919 /*
3920  *
3921  *
3922  *   3         2         1
3923  *  10987654321098765432109876543210
3924  *  001000               x1110000101
3925  *     rt -----
3926  *          rs -----
3927  *               rd -----
3928  */
3929 std::string NMD::CMP_LE_D(uint64 instruction)
3930 {
3931     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3932     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3933     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3934
3935     std::string fd = FPR(copy(fd_value));
3936     std::string fs = FPR(copy(fs_value));
3937     std::string ft = FPR(copy(ft_value));
3938
3939     return img::format("CMP.LE.D %s, %s, %s", fd, fs, ft);
3940 }
3941
3942
3943 /*
3944  * [DSP] CMP.LE.PH rs, rt - Compare vectors of signed integer halfword values
3945  *
3946  *   3         2         1
3947  *  10987654321098765432109876543210
3948  *  001000          xxxxxx0010000101
3949  *     rt -----
3950  *          rs -----
3951  */
3952 std::string NMD::CMP_LE_PH(uint64 instruction)
3953 {
3954     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3955     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3956
3957     std::string rs = GPR(copy(rs_value));
3958     std::string rt = GPR(copy(rt_value));
3959
3960     return img::format("CMP.LE.PH %s, %s", rs, rt);
3961 }
3962
3963
3964 /*
3965  *
3966  *
3967  *   3         2         1
3968  *  10987654321098765432109876543210
3969  *  001000               x1110000101
3970  *     rt -----
3971  *          rs -----
3972  *               rd -----
3973  */
3974 std::string NMD::CMP_LE_S(uint64 instruction)
3975 {
3976     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3977     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3978     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3979
3980     std::string fd = FPR(copy(fd_value));
3981     std::string fs = FPR(copy(fs_value));
3982     std::string ft = FPR(copy(ft_value));
3983
3984     return img::format("CMP.LE.S %s, %s, %s", fd, fs, ft);
3985 }
3986
3987
3988 /*
3989  *
3990  *
3991  *   3         2         1
3992  *  10987654321098765432109876543210
3993  *  001000               x1110000101
3994  *     rt -----
3995  *          rs -----
3996  *               rd -----
3997  */
3998 std::string NMD::CMP_LT_D(uint64 instruction)
3999 {
4000     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4001     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4002     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4003
4004     std::string fd = FPR(copy(fd_value));
4005     std::string fs = FPR(copy(fs_value));
4006     std::string ft = FPR(copy(ft_value));
4007
4008     return img::format("CMP.LT.D %s, %s, %s", fd, fs, ft);
4009 }
4010
4011
4012 /*
4013  * [DSP] CMP.LT.PH rs, rt - Compare vectors of signed integer halfword values
4014  *
4015  *   3         2         1
4016  *  10987654321098765432109876543210
4017  *  001000          xxxxxx0001000101
4018  *     rt -----
4019  *          rs -----
4020  */
4021 std::string NMD::CMP_LT_PH(uint64 instruction)
4022 {
4023     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4024     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4025
4026     std::string rs = GPR(copy(rs_value));
4027     std::string rt = GPR(copy(rt_value));
4028
4029     return img::format("CMP.LT.PH %s, %s", rs, rt);
4030 }
4031
4032
4033 /*
4034  *
4035  *
4036  *   3         2         1
4037  *  10987654321098765432109876543210
4038  *  001000               x1110000101
4039  *     rt -----
4040  *          rs -----
4041  *               rd -----
4042  */
4043 std::string NMD::CMP_LT_S(uint64 instruction)
4044 {
4045     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4046     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4047     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4048
4049     std::string fd = FPR(copy(fd_value));
4050     std::string fs = FPR(copy(fs_value));
4051     std::string ft = FPR(copy(ft_value));
4052
4053     return img::format("CMP.LT.S %s, %s, %s", fd, fs, ft);
4054 }
4055
4056
4057 /*
4058  *
4059  *
4060  *   3         2         1
4061  *  10987654321098765432109876543210
4062  *  001000               x1110000101
4063  *     rt -----
4064  *          rs -----
4065  *               rd -----
4066  */
4067 std::string NMD::CMP_NE_D(uint64 instruction)
4068 {
4069     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4070     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4071     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4072
4073     std::string fd = FPR(copy(fd_value));
4074     std::string fs = FPR(copy(fs_value));
4075     std::string ft = FPR(copy(ft_value));
4076
4077     return img::format("CMP.NE.D %s, %s, %s", fd, fs, ft);
4078 }
4079
4080
4081 /*
4082  *
4083  *
4084  *   3         2         1
4085  *  10987654321098765432109876543210
4086  *  001000               x1110000101
4087  *     rt -----
4088  *          rs -----
4089  *               rd -----
4090  */
4091 std::string NMD::CMP_NE_S(uint64 instruction)
4092 {
4093     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4094     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4095     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4096
4097     std::string fd = FPR(copy(fd_value));
4098     std::string fs = FPR(copy(fs_value));
4099     std::string ft = FPR(copy(ft_value));
4100
4101     return img::format("CMP.NE.S %s, %s, %s", fd, fs, ft);
4102 }
4103
4104
4105 /*
4106  *
4107  *
4108  *   3         2         1
4109  *  10987654321098765432109876543210
4110  *  001000               x1110000101
4111  *     rt -----
4112  *          rs -----
4113  *               rd -----
4114  */
4115 std::string NMD::CMP_OR_D(uint64 instruction)
4116 {
4117     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4118     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4119     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4120
4121     std::string fd = FPR(copy(fd_value));
4122     std::string fs = FPR(copy(fs_value));
4123     std::string ft = FPR(copy(ft_value));
4124
4125     return img::format("CMP.OR.D %s, %s, %s", fd, fs, ft);
4126 }
4127
4128
4129 /*
4130  *
4131  *
4132  *   3         2         1
4133  *  10987654321098765432109876543210
4134  *  001000               x1110000101
4135  *     rt -----
4136  *          rs -----
4137  *               rd -----
4138  */
4139 std::string NMD::CMP_OR_S(uint64 instruction)
4140 {
4141     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4142     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4143     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4144
4145     std::string fd = FPR(copy(fd_value));
4146     std::string fs = FPR(copy(fs_value));
4147     std::string ft = FPR(copy(ft_value));
4148
4149     return img::format("CMP.OR.S %s, %s, %s", fd, fs, ft);
4150 }
4151
4152
4153 /*
4154  *
4155  *
4156  *   3         2         1
4157  *  10987654321098765432109876543210
4158  *  001000               x1110000101
4159  *     rt -----
4160  *          rs -----
4161  *               rd -----
4162  */
4163 std::string NMD::CMP_SAF_D(uint64 instruction)
4164 {
4165     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4166     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4167     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4168
4169     std::string fd = FPR(copy(fd_value));
4170     std::string fs = FPR(copy(fs_value));
4171     std::string ft = FPR(copy(ft_value));
4172
4173     return img::format("CMP.SAF.D %s, %s, %s", fd, fs, ft);
4174 }
4175
4176
4177 /*
4178  *
4179  *
4180  *   3         2         1
4181  *  10987654321098765432109876543210
4182  *  001000               x1110000101
4183  *     rt -----
4184  *          rs -----
4185  *               rd -----
4186  */
4187 std::string NMD::CMP_SAF_S(uint64 instruction)
4188 {
4189     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4190     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4191     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4192
4193     std::string fd = FPR(copy(fd_value));
4194     std::string fs = FPR(copy(fs_value));
4195     std::string ft = FPR(copy(ft_value));
4196
4197     return img::format("CMP.SAF.S %s, %s, %s", fd, fs, ft);
4198 }
4199
4200
4201 /*
4202  *
4203  *
4204  *   3         2         1
4205  *  10987654321098765432109876543210
4206  *  001000               x1110000101
4207  *     rt -----
4208  *          rs -----
4209  *               rd -----
4210  */
4211 std::string NMD::CMP_SEQ_D(uint64 instruction)
4212 {
4213     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4214     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4215     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4216
4217     std::string fd = FPR(copy(fd_value));
4218     std::string fs = FPR(copy(fs_value));
4219     std::string ft = FPR(copy(ft_value));
4220
4221     return img::format("CMP.SEQ.D %s, %s, %s", fd, fs, ft);
4222 }
4223
4224
4225 /*
4226  *
4227  *
4228  *   3         2         1
4229  *  10987654321098765432109876543210
4230  *  001000               x1110000101
4231  *     rt -----
4232  *          rs -----
4233  *               rd -----
4234  */
4235 std::string NMD::CMP_SEQ_S(uint64 instruction)
4236 {
4237     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4238     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4239     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4240
4241     std::string fd = FPR(copy(fd_value));
4242     std::string fs = FPR(copy(fs_value));
4243     std::string ft = FPR(copy(ft_value));
4244
4245     return img::format("CMP.SEQ.S %s, %s, %s", fd, fs, ft);
4246 }
4247
4248
4249 /*
4250  *
4251  *
4252  *   3         2         1
4253  *  10987654321098765432109876543210
4254  *  001000               x1110000101
4255  *     rt -----
4256  *          rs -----
4257  *               rd -----
4258  */
4259 std::string NMD::CMP_SLE_D(uint64 instruction)
4260 {
4261     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4262     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4263     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4264
4265     std::string fd = FPR(copy(fd_value));
4266     std::string fs = FPR(copy(fs_value));
4267     std::string ft = FPR(copy(ft_value));
4268
4269     return img::format("CMP.SLE.D %s, %s, %s", fd, fs, ft);
4270 }
4271
4272
4273 /*
4274  *
4275  *
4276  *   3         2         1
4277  *  10987654321098765432109876543210
4278  *  001000               x1110000101
4279  *     rt -----
4280  *          rs -----
4281  *               rd -----
4282  */
4283 std::string NMD::CMP_SLE_S(uint64 instruction)
4284 {
4285     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4286     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4287     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4288
4289     std::string fd = FPR(copy(fd_value));
4290     std::string fs = FPR(copy(fs_value));
4291     std::string ft = FPR(copy(ft_value));
4292
4293     return img::format("CMP.SLE.S %s, %s, %s", fd, fs, ft);
4294 }
4295
4296
4297 /*
4298  *
4299  *
4300  *   3         2         1
4301  *  10987654321098765432109876543210
4302  *  001000               x1110000101
4303  *     rt -----
4304  *          rs -----
4305  *               rd -----
4306  */
4307 std::string NMD::CMP_SLT_D(uint64 instruction)
4308 {
4309     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4310     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4311     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4312
4313     std::string fd = FPR(copy(fd_value));
4314     std::string fs = FPR(copy(fs_value));
4315     std::string ft = FPR(copy(ft_value));
4316
4317     return img::format("CMP.SLT.D %s, %s, %s", fd, fs, ft);
4318 }
4319
4320
4321 /*
4322  *
4323  *
4324  *   3         2         1
4325  *  10987654321098765432109876543210
4326  *  001000               x1110000101
4327  *     rt -----
4328  *          rs -----
4329  *               rd -----
4330  */
4331 std::string NMD::CMP_SLT_S(uint64 instruction)
4332 {
4333     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4334     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4335     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4336
4337     std::string fd = FPR(copy(fd_value));
4338     std::string fs = FPR(copy(fs_value));
4339     std::string ft = FPR(copy(ft_value));
4340
4341     return img::format("CMP.SLT.S %s, %s, %s", fd, fs, ft);
4342 }
4343
4344
4345 /*
4346  *
4347  *
4348  *   3         2         1
4349  *  10987654321098765432109876543210
4350  *  001000               x1110000101
4351  *     rt -----
4352  *          rs -----
4353  *               rd -----
4354  */
4355 std::string NMD::CMP_SNE_D(uint64 instruction)
4356 {
4357     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4358     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4359     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4360
4361     std::string fd = FPR(copy(fd_value));
4362     std::string fs = FPR(copy(fs_value));
4363     std::string ft = FPR(copy(ft_value));
4364
4365     return img::format("CMP.SNE.D %s, %s, %s", fd, fs, ft);
4366 }
4367
4368
4369 /*
4370  *
4371  *
4372  *   3         2         1
4373  *  10987654321098765432109876543210
4374  *  001000               x1110000101
4375  *     rt -----
4376  *          rs -----
4377  *               rd -----
4378  */
4379 std::string NMD::CMP_SNE_S(uint64 instruction)
4380 {
4381     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4382     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4383     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4384
4385     std::string fd = FPR(copy(fd_value));
4386     std::string fs = FPR(copy(fs_value));
4387     std::string ft = FPR(copy(ft_value));
4388
4389     return img::format("CMP.SNE.S %s, %s, %s", fd, fs, ft);
4390 }
4391
4392
4393 /*
4394  *
4395  *
4396  *   3         2         1
4397  *  10987654321098765432109876543210
4398  *  001000               x1110000101
4399  *     rt -----
4400  *          rs -----
4401  *               rd -----
4402  */
4403 std::string NMD::CMP_SOR_D(uint64 instruction)
4404 {
4405     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4406     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4407     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4408
4409     std::string fd = FPR(copy(fd_value));
4410     std::string fs = FPR(copy(fs_value));
4411     std::string ft = FPR(copy(ft_value));
4412
4413     return img::format("CMP.SOR.D %s, %s, %s", fd, fs, ft);
4414 }
4415
4416
4417 /*
4418  *
4419  *
4420  *   3         2         1
4421  *  10987654321098765432109876543210
4422  *  001000               x1110000101
4423  *     rt -----
4424  *          rs -----
4425  *               rd -----
4426  */
4427 std::string NMD::CMP_SOR_S(uint64 instruction)
4428 {
4429     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4430     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4431     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4432
4433     std::string fd = FPR(copy(fd_value));
4434     std::string fs = FPR(copy(fs_value));
4435     std::string ft = FPR(copy(ft_value));
4436
4437     return img::format("CMP.SOR.S %s, %s, %s", fd, fs, ft);
4438 }
4439
4440
4441 /*
4442  *
4443  *
4444  *   3         2         1
4445  *  10987654321098765432109876543210
4446  *  001000               x1110000101
4447  *     rt -----
4448  *          rs -----
4449  *               rd -----
4450  */
4451 std::string NMD::CMP_SUEQ_D(uint64 instruction)
4452 {
4453     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4454     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4455     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4456
4457     std::string fd = FPR(copy(fd_value));
4458     std::string fs = FPR(copy(fs_value));
4459     std::string ft = FPR(copy(ft_value));
4460
4461     return img::format("CMP.SUEQ.D %s, %s, %s", fd, fs, ft);
4462 }
4463
4464
4465 /*
4466  *
4467  *
4468  *   3         2         1
4469  *  10987654321098765432109876543210
4470  *  001000               x1110000101
4471  *     rt -----
4472  *          rs -----
4473  *               rd -----
4474  */
4475 std::string NMD::CMP_SUEQ_S(uint64 instruction)
4476 {
4477     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4478     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4479     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4480
4481     std::string fd = FPR(copy(fd_value));
4482     std::string fs = FPR(copy(fs_value));
4483     std::string ft = FPR(copy(ft_value));
4484
4485     return img::format("CMP.SUEQ.S %s, %s, %s", fd, fs, ft);
4486 }
4487
4488
4489 /*
4490  *
4491  *
4492  *   3         2         1
4493  *  10987654321098765432109876543210
4494  *  001000               x1110000101
4495  *     rt -----
4496  *          rs -----
4497  *               rd -----
4498  */
4499 std::string NMD::CMP_SULE_D(uint64 instruction)
4500 {
4501     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4502     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4503     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4504
4505     std::string fd = FPR(copy(fd_value));
4506     std::string fs = FPR(copy(fs_value));
4507     std::string ft = FPR(copy(ft_value));
4508
4509     return img::format("CMP.SULE.D %s, %s, %s", fd, fs, ft);
4510 }
4511
4512
4513 /*
4514  *
4515  *
4516  *   3         2         1
4517  *  10987654321098765432109876543210
4518  *  001000               x1110000101
4519  *     rt -----
4520  *          rs -----
4521  *               rd -----
4522  */
4523 std::string NMD::CMP_SULE_S(uint64 instruction)
4524 {
4525     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4526     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4527     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4528
4529     std::string fd = FPR(copy(fd_value));
4530     std::string fs = FPR(copy(fs_value));
4531     std::string ft = FPR(copy(ft_value));
4532
4533     return img::format("CMP.SULE.S %s, %s, %s", fd, fs, ft);
4534 }
4535
4536
4537 /*
4538  *
4539  *
4540  *   3         2         1
4541  *  10987654321098765432109876543210
4542  *  001000               x1110000101
4543  *     rt -----
4544  *          rs -----
4545  *               rd -----
4546  */
4547 std::string NMD::CMP_SULT_D(uint64 instruction)
4548 {
4549     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4550     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4551     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4552
4553     std::string fd = FPR(copy(fd_value));
4554     std::string fs = FPR(copy(fs_value));
4555     std::string ft = FPR(copy(ft_value));
4556
4557     return img::format("CMP.SULT.D %s, %s, %s", fd, fs, ft);
4558 }
4559
4560
4561 /*
4562  *
4563  *
4564  *   3         2         1
4565  *  10987654321098765432109876543210
4566  *  001000               x1110000101
4567  *     rt -----
4568  *          rs -----
4569  *               rd -----
4570  */
4571 std::string NMD::CMP_SULT_S(uint64 instruction)
4572 {
4573     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4574     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4575     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4576
4577     std::string fd = FPR(copy(fd_value));
4578     std::string fs = FPR(copy(fs_value));
4579     std::string ft = FPR(copy(ft_value));
4580
4581     return img::format("CMP.SULT.S %s, %s, %s", fd, fs, ft);
4582 }
4583
4584
4585 /*
4586  *
4587  *
4588  *   3         2         1
4589  *  10987654321098765432109876543210
4590  *  001000               x1110000101
4591  *     rt -----
4592  *          rs -----
4593  *               rd -----
4594  */
4595 std::string NMD::CMP_SUN_D(uint64 instruction)
4596 {
4597     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4598     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4599     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4600
4601     std::string fd = FPR(copy(fd_value));
4602     std::string fs = FPR(copy(fs_value));
4603     std::string ft = FPR(copy(ft_value));
4604
4605     return img::format("CMP.SUN.D %s, %s, %s", fd, fs, ft);
4606 }
4607
4608
4609 /*
4610  *
4611  *
4612  *   3         2         1
4613  *  10987654321098765432109876543210
4614  *  001000               x1110000101
4615  *     rt -----
4616  *          rs -----
4617  *               rd -----
4618  */
4619 std::string NMD::CMP_SUNE_D(uint64 instruction)
4620 {
4621     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4622     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4623     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4624
4625     std::string fd = FPR(copy(fd_value));
4626     std::string fs = FPR(copy(fs_value));
4627     std::string ft = FPR(copy(ft_value));
4628
4629     return img::format("CMP.SUNE.D %s, %s, %s", fd, fs, ft);
4630 }
4631
4632
4633 /*
4634  *
4635  *
4636  *   3         2         1
4637  *  10987654321098765432109876543210
4638  *  001000               x1110000101
4639  *     rt -----
4640  *          rs -----
4641  *               rd -----
4642  */
4643 std::string NMD::CMP_SUNE_S(uint64 instruction)
4644 {
4645     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4646     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4647     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4648
4649     std::string fd = FPR(copy(fd_value));
4650     std::string fs = FPR(copy(fs_value));
4651     std::string ft = FPR(copy(ft_value));
4652
4653     return img::format("CMP.SUNE.S %s, %s, %s", fd, fs, ft);
4654 }
4655
4656
4657 /*
4658  *
4659  *
4660  *   3         2         1
4661  *  10987654321098765432109876543210
4662  *  001000               x1110000101
4663  *     rt -----
4664  *          rs -----
4665  *               rd -----
4666  */
4667 std::string NMD::CMP_SUN_S(uint64 instruction)
4668 {
4669     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4670     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4671     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4672
4673     std::string fd = FPR(copy(fd_value));
4674     std::string fs = FPR(copy(fs_value));
4675     std::string ft = FPR(copy(ft_value));
4676
4677     return img::format("CMP.SUN.S %s, %s, %s", fd, fs, ft);
4678 }
4679
4680
4681 /*
4682  *
4683  *
4684  *   3         2         1
4685  *  10987654321098765432109876543210
4686  *  001000               x1110000101
4687  *     rt -----
4688  *          rs -----
4689  *               rd -----
4690  */
4691 std::string NMD::CMP_UEQ_D(uint64 instruction)
4692 {
4693     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4694     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4695     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4696
4697     std::string fd = FPR(copy(fd_value));
4698     std::string fs = FPR(copy(fs_value));
4699     std::string ft = FPR(copy(ft_value));
4700
4701     return img::format("CMP.UEQ.D %s, %s, %s", fd, fs, ft);
4702 }
4703
4704
4705 /*
4706  *
4707  *
4708  *   3         2         1
4709  *  10987654321098765432109876543210
4710  *  001000               x1110000101
4711  *     rt -----
4712  *          rs -----
4713  *               rd -----
4714  */
4715 std::string NMD::CMP_UEQ_S(uint64 instruction)
4716 {
4717     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4718     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4719     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4720
4721     std::string fd = FPR(copy(fd_value));
4722     std::string fs = FPR(copy(fs_value));
4723     std::string ft = FPR(copy(ft_value));
4724
4725     return img::format("CMP.UEQ.S %s, %s, %s", fd, fs, ft);
4726 }
4727
4728
4729 /*
4730  *
4731  *
4732  *   3         2         1
4733  *  10987654321098765432109876543210
4734  *  001000               x1110000101
4735  *     rt -----
4736  *          rs -----
4737  *               rd -----
4738  */
4739 std::string NMD::CMP_ULE_D(uint64 instruction)
4740 {
4741     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4742     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4743     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4744
4745     std::string fd = FPR(copy(fd_value));
4746     std::string fs = FPR(copy(fs_value));
4747     std::string ft = FPR(copy(ft_value));
4748
4749     return img::format("CMP.ULE.D %s, %s, %s", fd, fs, ft);
4750 }
4751
4752
4753 /*
4754  *
4755  *
4756  *   3         2         1
4757  *  10987654321098765432109876543210
4758  *  001000               x1110000101
4759  *     rt -----
4760  *          rs -----
4761  *               rd -----
4762  */
4763 std::string NMD::CMP_ULE_S(uint64 instruction)
4764 {
4765     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4766     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4767     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4768
4769     std::string fd = FPR(copy(fd_value));
4770     std::string fs = FPR(copy(fs_value));
4771     std::string ft = FPR(copy(ft_value));
4772
4773     return img::format("CMP.ULE.S %s, %s, %s", fd, fs, ft);
4774 }
4775
4776
4777 /*
4778  *
4779  *
4780  *   3         2         1
4781  *  10987654321098765432109876543210
4782  *  001000               x1110000101
4783  *     rt -----
4784  *          rs -----
4785  *               rd -----
4786  */
4787 std::string NMD::CMP_ULT_D(uint64 instruction)
4788 {
4789     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4790     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4791     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4792
4793     std::string fd = FPR(copy(fd_value));
4794     std::string fs = FPR(copy(fs_value));
4795     std::string ft = FPR(copy(ft_value));
4796
4797     return img::format("CMP.ULT.D %s, %s, %s", fd, fs, ft);
4798 }
4799
4800
4801 /*
4802  *
4803  *
4804  *   3         2         1
4805  *  10987654321098765432109876543210
4806  *  001000               x1110000101
4807  *     rt -----
4808  *          rs -----
4809  *               rd -----
4810  */
4811 std::string NMD::CMP_ULT_S(uint64 instruction)
4812 {
4813     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4814     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4815     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4816
4817     std::string fd = FPR(copy(fd_value));
4818     std::string fs = FPR(copy(fs_value));
4819     std::string ft = FPR(copy(ft_value));
4820
4821     return img::format("CMP.ULT.S %s, %s, %s", fd, fs, ft);
4822 }
4823
4824
4825 /*
4826  *
4827  *
4828  *   3         2         1
4829  *  10987654321098765432109876543210
4830  *  001000               x1110000101
4831  *     rt -----
4832  *          rs -----
4833  *               rd -----
4834  */
4835 std::string NMD::CMP_UN_D(uint64 instruction)
4836 {
4837     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4838     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4839     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4840
4841     std::string fd = FPR(copy(fd_value));
4842     std::string fs = FPR(copy(fs_value));
4843     std::string ft = FPR(copy(ft_value));
4844
4845     return img::format("CMP.UN.D %s, %s, %s", fd, fs, ft);
4846 }
4847
4848
4849 /*
4850  *
4851  *
4852  *   3         2         1
4853  *  10987654321098765432109876543210
4854  *  001000               x1110000101
4855  *     rt -----
4856  *          rs -----
4857  *               rd -----
4858  */
4859 std::string NMD::CMP_UNE_D(uint64 instruction)
4860 {
4861     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4862     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4863     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4864
4865     std::string fd = FPR(copy(fd_value));
4866     std::string fs = FPR(copy(fs_value));
4867     std::string ft = FPR(copy(ft_value));
4868
4869     return img::format("CMP.UNE.D %s, %s, %s", fd, fs, ft);
4870 }
4871
4872
4873 /*
4874  *
4875  *
4876  *   3         2         1
4877  *  10987654321098765432109876543210
4878  *  001000               x1110000101
4879  *     rt -----
4880  *          rs -----
4881  *               rd -----
4882  */
4883 std::string NMD::CMP_UNE_S(uint64 instruction)
4884 {
4885     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4886     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4887     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4888
4889     std::string fd = FPR(copy(fd_value));
4890     std::string fs = FPR(copy(fs_value));
4891     std::string ft = FPR(copy(ft_value));
4892
4893     return img::format("CMP.UNE.S %s, %s, %s", fd, fs, ft);
4894 }
4895
4896
4897 /*
4898  *
4899  *
4900  *   3         2         1
4901  *  10987654321098765432109876543210
4902  *  001000               x1110000101
4903  *     rt -----
4904  *          rs -----
4905  *               rd -----
4906  */
4907 std::string NMD::CMP_UN_S(uint64 instruction)
4908 {
4909     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4910     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4911     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4912
4913     std::string fd = FPR(copy(fd_value));
4914     std::string fs = FPR(copy(fs_value));
4915     std::string ft = FPR(copy(ft_value));
4916
4917     return img::format("CMP.UN.S %s, %s, %s", fd, fs, ft);
4918 }
4919
4920
4921 /*
4922  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4923  *   four bytes and write result to GPR and DSPControl
4924  *
4925  *   3         2         1
4926  *  10987654321098765432109876543210
4927  *  001000               x0110000101
4928  *     rt -----
4929  *          rs -----
4930  *               rd -----
4931  */
4932 std::string NMD::CMPGDU_EQ_QB(uint64 instruction)
4933 {
4934     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4935     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4936     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4937
4938     std::string rd = GPR(copy(rd_value));
4939     std::string rs = GPR(copy(rs_value));
4940     std::string rt = GPR(copy(rt_value));
4941
4942     return img::format("CMPGDU.EQ.QB %s, %s, %s", rd, rs, rt);
4943 }
4944
4945
4946 /*
4947  * [DSP] CMPGDU.LE.QB rd, rs, rt - Compare unsigned vector of
4948  *   four bytes and write result to GPR and DSPControl
4949  *
4950  *   3         2         1
4951  *  10987654321098765432109876543210
4952  *  001000               x1000000101
4953  *     rt -----
4954  *          rs -----
4955  *               rd -----
4956  */
4957 std::string NMD::CMPGDU_LE_QB(uint64 instruction)
4958 {
4959     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4960     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4961     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4962
4963     std::string rd = GPR(copy(rd_value));
4964     std::string rs = GPR(copy(rs_value));
4965     std::string rt = GPR(copy(rt_value));
4966
4967     return img::format("CMPGDU.LE.QB %s, %s, %s", rd, rs, rt);
4968 }
4969
4970
4971 /*
4972  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4973  *   four bytes and write result to GPR and DSPControl
4974  *
4975  *   3         2         1
4976  *  10987654321098765432109876543210
4977  *  001000               x0111000101
4978  *     rt -----
4979  *          rs -----
4980  *               rd -----
4981  */
4982 std::string NMD::CMPGDU_LT_QB(uint64 instruction)
4983 {
4984     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4985     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4986     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4987
4988     std::string rd = GPR(copy(rd_value));
4989     std::string rs = GPR(copy(rs_value));
4990     std::string rt = GPR(copy(rt_value));
4991
4992     return img::format("CMPGDU.LT.QB %s, %s, %s", rd, rs, rt);
4993 }
4994
4995
4996 /*
4997  * [DSP] CMPGU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4998  *   byte values and write result to a GPR
4999  *
5000  *   3         2         1
5001  *  10987654321098765432109876543210
5002  *  001000               x0011000101
5003  *     rt -----
5004  *          rs -----
5005  *               rd -----
5006  */
5007 std::string NMD::CMPGU_EQ_QB(uint64 instruction)
5008 {
5009     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5010     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5011     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5012
5013     std::string rd = GPR(copy(rd_value));
5014     std::string rs = GPR(copy(rs_value));
5015     std::string rt = GPR(copy(rt_value));
5016
5017     return img::format("CMPGU.EQ.QB %s, %s, %s", rd, rs, rt);
5018 }
5019
5020
5021 /*
5022  * [DSP] CMPGU.LE.QB rd, rs, rt - Compare vectors of unsigned
5023  *   byte values and write result to a GPR
5024  *
5025  *   3         2         1
5026  *  10987654321098765432109876543210
5027  *  001000               x0101000101
5028  *     rt -----
5029  *          rs -----
5030  *               rd -----
5031  */
5032 std::string NMD::CMPGU_LE_QB(uint64 instruction)
5033 {
5034     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5035     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5036     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5037
5038     std::string rd = GPR(copy(rd_value));
5039     std::string rs = GPR(copy(rs_value));
5040     std::string rt = GPR(copy(rt_value));
5041
5042     return img::format("CMPGU.LE.QB %s, %s, %s", rd, rs, rt);
5043 }
5044
5045
5046 /*
5047  * [DSP] CMPGU.LT.QB rd, rs, rt - Compare vectors of unsigned
5048  *   byte values and write result to a GPR
5049  *
5050  *   3         2         1
5051  *  10987654321098765432109876543210
5052  *  001000               x0100000101
5053  *     rt -----
5054  *          rs -----
5055  *               rd -----
5056  */
5057 std::string NMD::CMPGU_LT_QB(uint64 instruction)
5058 {
5059     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5060     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5061     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5062
5063     std::string rd = GPR(copy(rd_value));
5064     std::string rs = GPR(copy(rs_value));
5065     std::string rt = GPR(copy(rt_value));
5066
5067     return img::format("CMPGU.LT.QB %s, %s, %s", rd, rs, rt);
5068 }
5069
5070
5071 /*
5072  * [DSP] CMPU.EQ.QB rd, rs, rt - Compare vectors of unsigned
5073  *   byte values
5074  *
5075  *   3         2         1
5076  *  10987654321098765432109876543210
5077  *  001000          xxxxxx1001000101
5078  *     rt -----
5079  *          rs -----
5080  */
5081 std::string NMD::CMPU_EQ_QB(uint64 instruction)
5082 {
5083     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5084     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5085
5086     std::string rs = GPR(copy(rs_value));
5087     std::string rt = GPR(copy(rt_value));
5088
5089     return img::format("CMPU.EQ.QB %s, %s", rs, rt);
5090 }
5091
5092
5093 /*
5094  * [DSP] CMPU.LE.QB rd, rs, rt - Compare vectors of unsigned
5095  *   byte values
5096  *
5097  *   3         2         1
5098  *  10987654321098765432109876543210
5099  *  001000          xxxxxx1011000101
5100  *     rt -----
5101  *          rs -----
5102  */
5103 std::string NMD::CMPU_LE_QB(uint64 instruction)
5104 {
5105     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5106     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5107
5108     std::string rs = GPR(copy(rs_value));
5109     std::string rt = GPR(copy(rt_value));
5110
5111     return img::format("CMPU.LE.QB %s, %s", rs, rt);
5112 }
5113
5114
5115 /*
5116  * [DSP] CMPU.LT.QB rd, rs, rt - Compare vectors of unsigned
5117  *   byte values
5118  *
5119  *   3         2         1
5120  *  10987654321098765432109876543210
5121  *  001000          xxxxxx1010000101
5122  *     rt -----
5123  *          rs -----
5124  */
5125 std::string NMD::CMPU_LT_QB(uint64 instruction)
5126 {
5127     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5128     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5129
5130     std::string rs = GPR(copy(rs_value));
5131     std::string rt = GPR(copy(rt_value));
5132
5133     return img::format("CMPU.LT.QB %s, %s", rs, rt);
5134 }
5135
5136
5137 /*
5138  *
5139  *
5140  *   3         2         1
5141  *  10987654321098765432109876543210
5142  *  001000               x1110000101
5143  *     rt -----
5144  *          rs -----
5145  *               rd -----
5146  */
5147 std::string NMD::COP2_1(uint64 instruction)
5148 {
5149     uint64 cofun_value = extract_cofun_25_24_23(instruction);
5150
5151     std::string cofun = IMMEDIATE(copy(cofun_value));
5152
5153     return img::format("COP2_1 %s", cofun);
5154 }
5155
5156
5157 /*
5158  *
5159  *
5160  *   3         2         1
5161  *  10987654321098765432109876543210
5162  *  001000               x1110000101
5163  *     rt -----
5164  *          rs -----
5165  *               rd -----
5166  */
5167 std::string NMD::CTC1(uint64 instruction)
5168 {
5169     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5170     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5171
5172     std::string rt = GPR(copy(rt_value));
5173     std::string cs = CPR(copy(cs_value));
5174
5175     return img::format("CTC1 %s, %s", rt, cs);
5176 }
5177
5178
5179 /*
5180  *
5181  *
5182  *   3         2         1
5183  *  10987654321098765432109876543210
5184  *  001000               x1110000101
5185  *     rt -----
5186  *          rs -----
5187  *               rd -----
5188  */
5189 std::string NMD::CTC2(uint64 instruction)
5190 {
5191     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5192     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5193
5194     std::string rt = GPR(copy(rt_value));
5195     std::string cs = CPR(copy(cs_value));
5196
5197     return img::format("CTC2 %s, %s", rt, cs);
5198 }
5199
5200
5201 /*
5202  *
5203  *
5204  *   3         2         1
5205  *  10987654321098765432109876543210
5206  *  001000               x1110000101
5207  *     rt -----
5208  *          rs -----
5209  *               rd -----
5210  */
5211 std::string NMD::CVT_D_L(uint64 instruction)
5212 {
5213     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5214     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5215
5216     std::string ft = FPR(copy(ft_value));
5217     std::string fs = FPR(copy(fs_value));
5218
5219     return img::format("CVT.D.L %s, %s", ft, fs);
5220 }
5221
5222
5223 /*
5224  *
5225  *
5226  *   3         2         1
5227  *  10987654321098765432109876543210
5228  *  001000               x1110000101
5229  *     rt -----
5230  *          rs -----
5231  *               rd -----
5232  */
5233 std::string NMD::CVT_D_S(uint64 instruction)
5234 {
5235     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5236     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5237
5238     std::string ft = FPR(copy(ft_value));
5239     std::string fs = FPR(copy(fs_value));
5240
5241     return img::format("CVT.D.S %s, %s", ft, fs);
5242 }
5243
5244
5245 /*
5246  *
5247  *
5248  *   3         2         1
5249  *  10987654321098765432109876543210
5250  *  001000               x1110000101
5251  *     rt -----
5252  *          rs -----
5253  *               rd -----
5254  */
5255 std::string NMD::CVT_D_W(uint64 instruction)
5256 {
5257     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5258     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5259
5260     std::string ft = FPR(copy(ft_value));
5261     std::string fs = FPR(copy(fs_value));
5262
5263     return img::format("CVT.D.W %s, %s", ft, fs);
5264 }
5265
5266
5267 /*
5268  *
5269  *
5270  *   3         2         1
5271  *  10987654321098765432109876543210
5272  *  001000               x1110000101
5273  *     rt -----
5274  *          rs -----
5275  *               rd -----
5276  */
5277 std::string NMD::CVT_L_D(uint64 instruction)
5278 {
5279     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5280     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5281
5282     std::string ft = FPR(copy(ft_value));
5283     std::string fs = FPR(copy(fs_value));
5284
5285     return img::format("CVT.L.D %s, %s", ft, fs);
5286 }
5287
5288
5289 /*
5290  *
5291  *
5292  *   3         2         1
5293  *  10987654321098765432109876543210
5294  *  001000               x1110000101
5295  *     rt -----
5296  *          rs -----
5297  *               rd -----
5298  */
5299 std::string NMD::CVT_L_S(uint64 instruction)
5300 {
5301     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5302     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5303
5304     std::string ft = FPR(copy(ft_value));
5305     std::string fs = FPR(copy(fs_value));
5306
5307     return img::format("CVT.L.S %s, %s", ft, fs);
5308 }
5309
5310
5311 /*
5312  *
5313  *
5314  *   3         2         1
5315  *  10987654321098765432109876543210
5316  *  001000               x1110000101
5317  *     rt -----
5318  *          rs -----
5319  *               rd -----
5320  */
5321 std::string NMD::CVT_S_D(uint64 instruction)
5322 {
5323     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5324     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5325
5326     std::string ft = FPR(copy(ft_value));
5327     std::string fs = FPR(copy(fs_value));
5328
5329     return img::format("CVT.S.D %s, %s", ft, fs);
5330 }
5331
5332
5333 /*
5334  *
5335  *
5336  *   3         2         1
5337  *  10987654321098765432109876543210
5338  *  001000               x1110000101
5339  *     rt -----
5340  *          rs -----
5341  *               rd -----
5342  */
5343 std::string NMD::CVT_S_L(uint64 instruction)
5344 {
5345     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5346     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5347
5348     std::string ft = FPR(copy(ft_value));
5349     std::string fs = FPR(copy(fs_value));
5350
5351     return img::format("CVT.S.L %s, %s", ft, fs);
5352 }
5353
5354
5355 /*
5356  *
5357  *
5358  *   3         2         1
5359  *  10987654321098765432109876543210
5360  *  001000               x1110000101
5361  *     rt -----
5362  *          rs -----
5363  *               rd -----
5364  */
5365 std::string NMD::CVT_S_PL(uint64 instruction)
5366 {
5367     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5368     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5369
5370     std::string ft = FPR(copy(ft_value));
5371     std::string fs = FPR(copy(fs_value));
5372
5373     return img::format("CVT.S.PL %s, %s", ft, fs);
5374 }
5375
5376
5377 /*
5378  *
5379  *
5380  *   3         2         1
5381  *  10987654321098765432109876543210
5382  *  001000               x1110000101
5383  *     rt -----
5384  *          rs -----
5385  *               rd -----
5386  */
5387 std::string NMD::CVT_S_PU(uint64 instruction)
5388 {
5389     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5390     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5391
5392     std::string ft = FPR(copy(ft_value));
5393     std::string fs = FPR(copy(fs_value));
5394
5395     return img::format("CVT.S.PU %s, %s", ft, fs);
5396 }
5397
5398
5399 /*
5400  *
5401  *
5402  *   3         2         1
5403  *  10987654321098765432109876543210
5404  *  001000               x1110000101
5405  *     rt -----
5406  *          rs -----
5407  *               rd -----
5408  */
5409 std::string NMD::CVT_S_W(uint64 instruction)
5410 {
5411     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5412     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5413
5414     std::string ft = FPR(copy(ft_value));
5415     std::string fs = FPR(copy(fs_value));
5416
5417     return img::format("CVT.S.W %s, %s", ft, fs);
5418 }
5419
5420
5421 /*
5422  *
5423  *
5424  *   3         2         1
5425  *  10987654321098765432109876543210
5426  *  001000               x1110000101
5427  *     rt -----
5428  *          rs -----
5429  *               rd -----
5430  */
5431 std::string NMD::CVT_W_D(uint64 instruction)
5432 {
5433     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5434     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5435
5436     std::string ft = FPR(copy(ft_value));
5437     std::string fs = FPR(copy(fs_value));
5438
5439     return img::format("CVT.W.D %s, %s", ft, fs);
5440 }
5441
5442
5443 /*
5444  *
5445  *
5446  *   3         2         1
5447  *  10987654321098765432109876543210
5448  *  001000               x1110000101
5449  *     rt -----
5450  *          rs -----
5451  *               rd -----
5452  */
5453 std::string NMD::CVT_W_S(uint64 instruction)
5454 {
5455     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5456     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5457
5458     std::string ft = FPR(copy(ft_value));
5459     std::string fs = FPR(copy(fs_value));
5460
5461     return img::format("CVT.W.S %s, %s", ft, fs);
5462 }
5463
5464
5465 /*
5466  *
5467  *
5468  *   3         2         1
5469  *  10987654321098765432109876543210
5470  *  001000               x1110000101
5471  *     rt -----
5472  *          rs -----
5473  *               rd -----
5474  */
5475 std::string NMD::DADDIU_48_(uint64 instruction)
5476 {
5477     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
5478     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
5479
5480     std::string rt = GPR(copy(rt_value));
5481     std::string s = IMMEDIATE(copy(s_value));
5482
5483     return img::format("DADDIU %s, %s", rt, s);
5484 }
5485
5486
5487 /*
5488  *
5489  *
5490  *   3         2         1
5491  *  10987654321098765432109876543210
5492  *  001000               x1110000101
5493  *     rt -----
5494  *          rs -----
5495  *               rd -----
5496  */
5497 std::string NMD::DADDIU_NEG_(uint64 instruction)
5498 {
5499     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5500     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5501     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5502
5503     std::string rt = GPR(copy(rt_value));
5504     std::string rs = GPR(copy(rs_value));
5505     std::string u = IMMEDIATE(neg_copy(u_value));
5506
5507     return img::format("DADDIU %s, %s, %s", rt, rs, u);
5508 }
5509
5510
5511 /*
5512  *
5513  *
5514  *   3         2         1
5515  *  10987654321098765432109876543210
5516  *  001000               x1110000101
5517  *     rt -----
5518  *          rs -----
5519  *               rd -----
5520  */
5521 std::string NMD::DADDIU_U12_(uint64 instruction)
5522 {
5523     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5524     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5525     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5526
5527     std::string rt = GPR(copy(rt_value));
5528     std::string rs = GPR(copy(rs_value));
5529     std::string u = IMMEDIATE(copy(u_value));
5530
5531     return img::format("DADDIU %s, %s, %s", rt, rs, u);
5532 }
5533
5534
5535 /*
5536  *
5537  *
5538  *   3         2         1
5539  *  10987654321098765432109876543210
5540  *  001000               x1110000101
5541  *     rt -----
5542  *          rs -----
5543  *               rd -----
5544  */
5545 std::string NMD::DADD(uint64 instruction)
5546 {
5547     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5548     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5549     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5550
5551     std::string rd = GPR(copy(rd_value));
5552     std::string rs = GPR(copy(rs_value));
5553     std::string rt = GPR(copy(rt_value));
5554
5555     return img::format("DADD %s, %s, %s", rd, rs, rt);
5556 }
5557
5558
5559 /*
5560  *
5561  *
5562  *   3         2         1
5563  *  10987654321098765432109876543210
5564  *  001000               x1110000101
5565  *     rt -----
5566  *          rs -----
5567  *               rd -----
5568  */
5569 std::string NMD::DADDU(uint64 instruction)
5570 {
5571     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5572     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5573     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5574
5575     std::string rd = GPR(copy(rd_value));
5576     std::string rs = GPR(copy(rs_value));
5577     std::string rt = GPR(copy(rt_value));
5578
5579     return img::format("DADDU %s, %s, %s", rd, rs, rt);
5580 }
5581
5582
5583 /*
5584  *
5585  *
5586  *   3         2         1
5587  *  10987654321098765432109876543210
5588  *  001000               x1110000101
5589  *     rt -----
5590  *          rs -----
5591  *               rd -----
5592  */
5593 std::string NMD::DCLO(uint64 instruction)
5594 {
5595     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5596     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5597
5598     std::string rt = GPR(copy(rt_value));
5599     std::string rs = GPR(copy(rs_value));
5600
5601     return img::format("DCLO %s, %s", rt, rs);
5602 }
5603
5604
5605 /*
5606  *
5607  *
5608  *   3         2         1
5609  *  10987654321098765432109876543210
5610  *  001000               x1110000101
5611  *     rt -----
5612  *          rs -----
5613  *               rd -----
5614  */
5615 std::string NMD::DCLZ(uint64 instruction)
5616 {
5617     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5618     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5619
5620     std::string rt = GPR(copy(rt_value));
5621     std::string rs = GPR(copy(rs_value));
5622
5623     return img::format("DCLZ %s, %s", rt, rs);
5624 }
5625
5626
5627 /*
5628  *
5629  *
5630  *   3         2         1
5631  *  10987654321098765432109876543210
5632  *  001000               x1110000101
5633  *     rt -----
5634  *          rs -----
5635  *               rd -----
5636  */
5637 std::string NMD::DDIV(uint64 instruction)
5638 {
5639     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5640     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5641     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5642
5643     std::string rd = GPR(copy(rd_value));
5644     std::string rs = GPR(copy(rs_value));
5645     std::string rt = GPR(copy(rt_value));
5646
5647     return img::format("DDIV %s, %s, %s", rd, rs, rt);
5648 }
5649
5650
5651 /*
5652  *
5653  *
5654  *   3         2         1
5655  *  10987654321098765432109876543210
5656  *  001000               x1110000101
5657  *     rt -----
5658  *          rs -----
5659  *               rd -----
5660  */
5661 std::string NMD::DDIVU(uint64 instruction)
5662 {
5663     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5664     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5665     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5666
5667     std::string rd = GPR(copy(rd_value));
5668     std::string rs = GPR(copy(rs_value));
5669     std::string rt = GPR(copy(rt_value));
5670
5671     return img::format("DDIVU %s, %s, %s", rd, rs, rt);
5672 }
5673
5674
5675 /*
5676  *
5677  *
5678  *   3         2         1
5679  *  10987654321098765432109876543210
5680  *  001000               x1110000101
5681  *     rt -----
5682  *          rs -----
5683  *               rd -----
5684  */
5685 std::string NMD::DERET(uint64 instruction)
5686 {
5687     (void)instruction;
5688
5689     return "DERET ";
5690 }
5691
5692
5693 /*
5694  *
5695  *
5696  *   3         2         1
5697  *  10987654321098765432109876543210
5698  *  001000               x1110000101
5699  *     rt -----
5700  *          rs -----
5701  *               rd -----
5702  */
5703 std::string NMD::DEXTM(uint64 instruction)
5704 {
5705     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5706     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5707     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5708     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5709
5710     std::string rt = GPR(copy(rt_value));
5711     std::string rs = GPR(copy(rs_value));
5712     std::string lsb = IMMEDIATE(copy(lsb_value));
5713     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5714
5715     return img::format("DEXTM %s, %s, %s, %s", rt, rs, lsb, msbd);
5716 }
5717
5718
5719 /*
5720  *
5721  *
5722  *   3         2         1
5723  *  10987654321098765432109876543210
5724  *  001000               x1110000101
5725  *     rt -----
5726  *          rs -----
5727  *               rd -----
5728  */
5729 std::string NMD::DEXT(uint64 instruction)
5730 {
5731     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5732     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5733     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5734     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5735
5736     std::string rt = GPR(copy(rt_value));
5737     std::string rs = GPR(copy(rs_value));
5738     std::string lsb = IMMEDIATE(copy(lsb_value));
5739     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5740
5741     return img::format("DEXT %s, %s, %s, %s", rt, rs, lsb, msbd);
5742 }
5743
5744
5745 /*
5746  *
5747  *
5748  *   3         2         1
5749  *  10987654321098765432109876543210
5750  *  001000               x1110000101
5751  *     rt -----
5752  *          rs -----
5753  *               rd -----
5754  */
5755 std::string NMD::DEXTU(uint64 instruction)
5756 {
5757     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5758     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5759     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5760     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5761
5762     std::string rt = GPR(copy(rt_value));
5763     std::string rs = GPR(copy(rs_value));
5764     std::string lsb = IMMEDIATE(copy(lsb_value));
5765     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5766
5767     return img::format("DEXTU %s, %s, %s, %s", rt, rs, lsb, msbd);
5768 }
5769
5770
5771 /*
5772  *
5773  *
5774  *   3         2         1
5775  *  10987654321098765432109876543210
5776  *  001000               x1110000101
5777  *     rt -----
5778  *          rs -----
5779  *               rd -----
5780  */
5781 std::string NMD::DINSM(uint64 instruction)
5782 {
5783     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5784     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5785     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5786     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5787
5788     std::string rt = GPR(copy(rt_value));
5789     std::string rs = GPR(copy(rs_value));
5790     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5791     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5792     /* !!!!!!!!!! - no conversion function */
5793
5794     return img::format("DINSM %s, %s, %s, %s", rt, rs, pos, size);
5795     /* hand edited */
5796 }
5797
5798
5799 /*
5800  *
5801  *
5802  *   3         2         1
5803  *  10987654321098765432109876543210
5804  *  001000               x1110000101
5805  *     rt -----
5806  *          rs -----
5807  *               rd -----
5808  */
5809 std::string NMD::DINS(uint64 instruction)
5810 {
5811     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5812     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5813     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5814     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5815
5816     std::string rt = GPR(copy(rt_value));
5817     std::string rs = GPR(copy(rs_value));
5818     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5819     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5820     /* !!!!!!!!!! - no conversion function */
5821
5822     return img::format("DINS %s, %s, %s, %s", rt, rs, pos, size);
5823     /* hand edited */
5824 }
5825
5826
5827 /*
5828  *
5829  *
5830  *   3         2         1
5831  *  10987654321098765432109876543210
5832  *  001000               x1110000101
5833  *     rt -----
5834  *          rs -----
5835  *               rd -----
5836  */
5837 std::string NMD::DINSU(uint64 instruction)
5838 {
5839     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5840     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5841     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5842     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5843
5844     std::string rt = GPR(copy(rt_value));
5845     std::string rs = GPR(copy(rs_value));
5846     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5847     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5848     /* !!!!!!!!!! - no conversion function */
5849
5850     return img::format("DINSU %s, %s, %s, %s", rt, rs, pos, size);
5851     /* hand edited */
5852 }
5853
5854
5855 /*
5856  *
5857  *
5858  *   3         2         1
5859  *  10987654321098765432109876543210
5860  *  001000               x1110000101
5861  *     rt -----
5862  *          rs -----
5863  *               rd -----
5864  */
5865 std::string NMD::DI(uint64 instruction)
5866 {
5867     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5868
5869     std::string rt = GPR(copy(rt_value));
5870
5871     return img::format("DI %s", rt);
5872 }
5873
5874
5875 /*
5876  *
5877  *
5878  *   3         2         1
5879  *  10987654321098765432109876543210
5880  *  001000               x1110000101
5881  *     rt -----
5882  *          rs -----
5883  *               rd -----
5884  */
5885 std::string NMD::DIV(uint64 instruction)
5886 {
5887     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5888     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5889     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5890
5891     std::string rd = GPR(copy(rd_value));
5892     std::string rs = GPR(copy(rs_value));
5893     std::string rt = GPR(copy(rt_value));
5894
5895     return img::format("DIV %s, %s, %s", rd, rs, rt);
5896 }
5897
5898
5899 /*
5900  *
5901  *
5902  *   3         2         1
5903  *  10987654321098765432109876543210
5904  *  001000               x1110000101
5905  *     rt -----
5906  *          rs -----
5907  *               rd -----
5908  */
5909 std::string NMD::DIV_D(uint64 instruction)
5910 {
5911     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5912     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5913     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5914
5915     std::string fd = FPR(copy(fd_value));
5916     std::string fs = FPR(copy(fs_value));
5917     std::string ft = FPR(copy(ft_value));
5918
5919     return img::format("DIV.D %s, %s, %s", fd, fs, ft);
5920 }
5921
5922
5923 /*
5924  *
5925  *
5926  *   3         2         1
5927  *  10987654321098765432109876543210
5928  *  001000               x1110000101
5929  *     rt -----
5930  *          rs -----
5931  *               rd -----
5932  */
5933 std::string NMD::DIV_S(uint64 instruction)
5934 {
5935     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5936     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5937     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5938
5939     std::string fd = FPR(copy(fd_value));
5940     std::string fs = FPR(copy(fs_value));
5941     std::string ft = FPR(copy(ft_value));
5942
5943     return img::format("DIV.S %s, %s, %s", fd, fs, ft);
5944 }
5945
5946
5947 /*
5948  *
5949  *
5950  *   3         2         1
5951  *  10987654321098765432109876543210
5952  *  001000               x1110000101
5953  *     rt -----
5954  *          rs -----
5955  *               rd -----
5956  */
5957 std::string NMD::DIVU(uint64 instruction)
5958 {
5959     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5960     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5961     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5962
5963     std::string rd = GPR(copy(rd_value));
5964     std::string rs = GPR(copy(rs_value));
5965     std::string rt = GPR(copy(rt_value));
5966
5967     return img::format("DIVU %s, %s, %s", rd, rs, rt);
5968 }
5969
5970
5971 /*
5972  *
5973  *
5974  *   3         2         1
5975  *  10987654321098765432109876543210
5976  *  001000               x1110000101
5977  *     rt -----
5978  *          rs -----
5979  *               rd -----
5980  */
5981 std::string NMD::DLSA(uint64 instruction)
5982 {
5983     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5984     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5985     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5986     uint64 u2_value = extract_u2_10_9(instruction);
5987
5988     std::string rd = GPR(copy(rd_value));
5989     std::string rs = GPR(copy(rs_value));
5990     std::string rt = GPR(copy(rt_value));
5991     std::string u2 = IMMEDIATE(copy(u2_value));
5992
5993     return img::format("DLSA %s, %s, %s, %s", rd, rs, rt, u2);
5994 }
5995
5996
5997 /*
5998  *
5999  *
6000  *   3         2         1
6001  *  10987654321098765432109876543210
6002  *  001000               x1110000101
6003  *     rt -----
6004  *          rs -----
6005  *               rd -----
6006  */
6007 std::string NMD::DLUI_48_(uint64 instruction)
6008 {
6009     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
6010     uint64 u_value = extract_u_31_to_0__s32(instruction);
6011
6012     std::string rt = GPR(copy(rt_value));
6013     std::string u = IMMEDIATE(copy(u_value));
6014
6015     return img::format("DLUI %s, %s", rt, u);
6016 }
6017
6018
6019 /*
6020  *
6021  *
6022  *   3         2         1
6023  *  10987654321098765432109876543210
6024  *  001000               x1110000101
6025  *     rt -----
6026  *          rs -----
6027  *               rd -----
6028  */
6029 std::string NMD::DMFC0(uint64 instruction)
6030 {
6031     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6032     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6033     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6034
6035     std::string rt = GPR(copy(rt_value));
6036     std::string c0s = CPR(copy(c0s_value));
6037     std::string sel = IMMEDIATE(copy(sel_value));
6038
6039     return img::format("DMFC0 %s, %s, %s", rt, c0s, sel);
6040 }
6041
6042
6043 /*
6044  *
6045  *
6046  *   3         2         1
6047  *  10987654321098765432109876543210
6048  *  001000               x1110000101
6049  *     rt -----
6050  *          rs -----
6051  *               rd -----
6052  */
6053 std::string NMD::DMFC1(uint64 instruction)
6054 {
6055     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6056     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
6057
6058     std::string rt = GPR(copy(rt_value));
6059     std::string fs = FPR(copy(fs_value));
6060
6061     return img::format("DMFC1 %s, %s", rt, fs);
6062 }
6063
6064
6065 /*
6066  *
6067  *
6068  *   3         2         1
6069  *  10987654321098765432109876543210
6070  *  001000               x1110000101
6071  *     rt -----
6072  *          rs -----
6073  *               rd -----
6074  */
6075 std::string NMD::DMFC2(uint64 instruction)
6076 {
6077     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6078     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
6079
6080     std::string rt = GPR(copy(rt_value));
6081     std::string cs = CPR(copy(cs_value));
6082
6083     return img::format("DMFC2 %s, %s", rt, cs);
6084 }
6085
6086
6087 /*
6088  *
6089  *
6090  *   3         2         1
6091  *  10987654321098765432109876543210
6092  *  001000               x1110000101
6093  *     rt -----
6094  *          rs -----
6095  *               rd -----
6096  */
6097 std::string NMD::DMFGC0(uint64 instruction)
6098 {
6099     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6100     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6101     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6102
6103     std::string rt = GPR(copy(rt_value));
6104     std::string c0s = CPR(copy(c0s_value));
6105     std::string sel = IMMEDIATE(copy(sel_value));
6106
6107     return img::format("DMFGC0 %s, %s, %s", rt, c0s, sel);
6108 }
6109
6110
6111 /*
6112  *
6113  *
6114  *   3         2         1
6115  *  10987654321098765432109876543210
6116  *  001000               x1110000101
6117  *     rt -----
6118  *          rs -----
6119  *               rd -----
6120  */
6121 std::string NMD::DMOD(uint64 instruction)
6122 {
6123     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6124     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6125     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6126
6127     std::string rd = GPR(copy(rd_value));
6128     std::string rs = GPR(copy(rs_value));
6129     std::string rt = GPR(copy(rt_value));
6130
6131     return img::format("DMOD %s, %s, %s", rd, rs, rt);
6132 }
6133
6134
6135 /*
6136  *
6137  *
6138  *   3         2         1
6139  *  10987654321098765432109876543210
6140  *  001000               x1110000101
6141  *     rt -----
6142  *          rs -----
6143  *               rd -----
6144  */
6145 std::string NMD::DMODU(uint64 instruction)
6146 {
6147     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6148     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6149     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6150
6151     std::string rd = GPR(copy(rd_value));
6152     std::string rs = GPR(copy(rs_value));
6153     std::string rt = GPR(copy(rt_value));
6154
6155     return img::format("DMODU %s, %s, %s", rd, rs, rt);
6156 }
6157
6158
6159 /*
6160  *
6161  *
6162  *   3         2         1
6163  *  10987654321098765432109876543210
6164  *  001000               x1110000101
6165  *     rt -----
6166  *          rs -----
6167  *               rd -----
6168  */
6169 std::string NMD::DMTC0(uint64 instruction)
6170 {
6171     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6172     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6173     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6174
6175     std::string rt = GPR(copy(rt_value));
6176     std::string c0s = CPR(copy(c0s_value));
6177     std::string sel = IMMEDIATE(copy(sel_value));
6178
6179     return img::format("DMTC0 %s, %s, %s", rt, c0s, sel);
6180 }
6181
6182
6183 /*
6184  *
6185  *
6186  *   3         2         1
6187  *  10987654321098765432109876543210
6188  *  001000               x1110000101
6189  *     rt -----
6190  *          rs -----
6191  *               rd -----
6192  */
6193 std::string NMD::DMTC1(uint64 instruction)
6194 {
6195     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6196     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
6197
6198     std::string rt = GPR(copy(rt_value));
6199     std::string fs = FPR(copy(fs_value));
6200
6201     return img::format("DMTC1 %s, %s", rt, fs);
6202 }
6203
6204
6205 /*
6206  *
6207  *
6208  *   3         2         1
6209  *  10987654321098765432109876543210
6210  *  001000               x1110000101
6211  *     rt -----
6212  *          rs -----
6213  *               rd -----
6214  */
6215 std::string NMD::DMTC2(uint64 instruction)
6216 {
6217     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6218     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
6219
6220     std::string rt = GPR(copy(rt_value));
6221     std::string cs = CPR(copy(cs_value));
6222
6223     return img::format("DMTC2 %s, %s", rt, cs);
6224 }
6225
6226
6227 /*
6228  *
6229  *
6230  *   3         2         1
6231  *  10987654321098765432109876543210
6232  *  001000               x1110000101
6233  *     rt -----
6234  *          rs -----
6235  *               rd -----
6236  */
6237 std::string NMD::DMTGC0(uint64 instruction)
6238 {
6239     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6240     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6241     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6242
6243     std::string rt = GPR(copy(rt_value));
6244     std::string c0s = CPR(copy(c0s_value));
6245     std::string sel = IMMEDIATE(copy(sel_value));
6246
6247     return img::format("DMTGC0 %s, %s, %s", rt, c0s, sel);
6248 }
6249
6250
6251 /*
6252  *
6253  *
6254  *   3         2         1
6255  *  10987654321098765432109876543210
6256  *  001000               x1110000101
6257  *     rt -----
6258  *          rs -----
6259  *               rd -----
6260  */
6261 std::string NMD::DMT(uint64 instruction)
6262 {
6263     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6264
6265     std::string rt = GPR(copy(rt_value));
6266
6267     return img::format("DMT %s", rt);
6268 }
6269
6270
6271 /*
6272  *
6273  *
6274  *   3         2         1
6275  *  10987654321098765432109876543210
6276  *  001000               x1110000101
6277  *     rt -----
6278  *          rs -----
6279  *               rd -----
6280  */
6281 std::string NMD::DMUH(uint64 instruction)
6282 {
6283     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6284     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6285     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6286
6287     std::string rd = GPR(copy(rd_value));
6288     std::string rs = GPR(copy(rs_value));
6289     std::string rt = GPR(copy(rt_value));
6290
6291     return img::format("DMUH %s, %s, %s", rd, rs, rt);
6292 }
6293
6294
6295 /*
6296  *
6297  *
6298  *   3         2         1
6299  *  10987654321098765432109876543210
6300  *  001000               x1110000101
6301  *     rt -----
6302  *          rs -----
6303  *               rd -----
6304  */
6305 std::string NMD::DMUHU(uint64 instruction)
6306 {
6307     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6308     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6309     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6310
6311     std::string rd = GPR(copy(rd_value));
6312     std::string rs = GPR(copy(rs_value));
6313     std::string rt = GPR(copy(rt_value));
6314
6315     return img::format("DMUHU %s, %s, %s", rd, rs, rt);
6316 }
6317
6318
6319 /*
6320  *
6321  *
6322  *   3         2         1
6323  *  10987654321098765432109876543210
6324  *  001000               x1110000101
6325  *     rt -----
6326  *          rs -----
6327  *               rd -----
6328  */
6329 std::string NMD::DMUL(uint64 instruction)
6330 {
6331     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6332     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6333     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6334
6335     std::string rd = GPR(copy(rd_value));
6336     std::string rs = GPR(copy(rs_value));
6337     std::string rt = GPR(copy(rt_value));
6338
6339     return img::format("DMUL %s, %s, %s", rd, rs, rt);
6340 }
6341
6342
6343 /*
6344  *
6345  *
6346  *   3         2         1
6347  *  10987654321098765432109876543210
6348  *  001000               x1110000101
6349  *     rt -----
6350  *          rs -----
6351  *               rd -----
6352  */
6353 std::string NMD::DMULU(uint64 instruction)
6354 {
6355     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6356     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6357     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6358
6359     std::string rd = GPR(copy(rd_value));
6360     std::string rs = GPR(copy(rs_value));
6361     std::string rt = GPR(copy(rt_value));
6362
6363     return img::format("DMULU %s, %s, %s", rd, rs, rt);
6364 }
6365
6366
6367 /*
6368  * [DSP] DPA.W.PH ac, rs, rt - Dot product with accumulate on
6369  *   vector integer halfword elements
6370  *
6371  *   3         2         1
6372  *  10987654321098765432109876543210
6373  *  001000            00000010111111
6374  *     rt -----
6375  *          rs -----
6376  *               ac --
6377  */
6378 std::string NMD::DPA_W_PH(uint64 instruction)
6379 {
6380     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6381     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6382     uint64 ac_value = extract_ac_15_14(instruction);
6383
6384     std::string ac = AC(copy(ac_value));
6385     std::string rs = GPR(copy(rs_value));
6386     std::string rt = GPR(copy(rt_value));
6387
6388     return img::format("DPA.W.PH %s, %s, %s", ac, rs, rt);
6389 }
6390
6391
6392 /*
6393  *
6394  *
6395  *   3         2         1
6396  *  10987654321098765432109876543210
6397  *  001000               x1110000101
6398  *     rt -----
6399  *          rs -----
6400  *               rd -----
6401  */
6402 std::string NMD::DPAQ_SA_L_W(uint64 instruction)
6403 {
6404     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6405     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6406     uint64 ac_value = extract_ac_15_14(instruction);
6407
6408     std::string ac = AC(copy(ac_value));
6409     std::string rs = GPR(copy(rs_value));
6410     std::string rt = GPR(copy(rt_value));
6411
6412     return img::format("DPAQ_SA.L.W %s, %s, %s", ac, rs, rt);
6413 }
6414
6415
6416 /*
6417  *
6418  *
6419  *   3         2         1
6420  *  10987654321098765432109876543210
6421  *  001000               x1110000101
6422  *     rt -----
6423  *          rs -----
6424  *               rd -----
6425  */
6426 std::string NMD::DPAQ_S_W_PH(uint64 instruction)
6427 {
6428     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6429     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6430     uint64 ac_value = extract_ac_15_14(instruction);
6431
6432     std::string ac = AC(copy(ac_value));
6433     std::string rs = GPR(copy(rs_value));
6434     std::string rt = GPR(copy(rt_value));
6435
6436     return img::format("DPAQ_S.W.PH %s, %s, %s", ac, rs, rt);
6437 }
6438
6439
6440 /*
6441  *
6442  *
6443  *   3         2         1
6444  *  10987654321098765432109876543210
6445  *  001000               x1110000101
6446  *     rt -----
6447  *          rs -----
6448  *               rd -----
6449  */
6450 std::string NMD::DPAQX_SA_W_PH(uint64 instruction)
6451 {
6452     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6453     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6454     uint64 ac_value = extract_ac_15_14(instruction);
6455
6456     std::string ac = AC(copy(ac_value));
6457     std::string rs = GPR(copy(rs_value));
6458     std::string rt = GPR(copy(rt_value));
6459
6460     return img::format("DPAQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6461 }
6462
6463
6464 /*
6465  *
6466  *
6467  *   3         2         1
6468  *  10987654321098765432109876543210
6469  *  001000               x1110000101
6470  *     rt -----
6471  *          rs -----
6472  *               rd -----
6473  */
6474 std::string NMD::DPAQX_S_W_PH(uint64 instruction)
6475 {
6476     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6477     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6478     uint64 ac_value = extract_ac_15_14(instruction);
6479
6480     std::string ac = AC(copy(ac_value));
6481     std::string rs = GPR(copy(rs_value));
6482     std::string rt = GPR(copy(rt_value));
6483
6484     return img::format("DPAQX_S.W.PH %s, %s, %s", ac, rs, rt);
6485 }
6486
6487
6488 /*
6489  *
6490  *
6491  *   3         2         1
6492  *  10987654321098765432109876543210
6493  *  001000               x1110000101
6494  *     rt -----
6495  *          rs -----
6496  *               rd -----
6497  */
6498 std::string NMD::DPAU_H_QBL(uint64 instruction)
6499 {
6500     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6501     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6502     uint64 ac_value = extract_ac_15_14(instruction);
6503
6504     std::string ac = AC(copy(ac_value));
6505     std::string rs = GPR(copy(rs_value));
6506     std::string rt = GPR(copy(rt_value));
6507
6508     return img::format("DPAU.H.QBL %s, %s, %s", ac, rs, rt);
6509 }
6510
6511
6512 /*
6513  *
6514  *
6515  *   3         2         1
6516  *  10987654321098765432109876543210
6517  *  001000               x1110000101
6518  *     rt -----
6519  *          rs -----
6520  *               rd -----
6521  */
6522 std::string NMD::DPAU_H_QBR(uint64 instruction)
6523 {
6524     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6525     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6526     uint64 ac_value = extract_ac_15_14(instruction);
6527
6528     std::string ac = AC(copy(ac_value));
6529     std::string rs = GPR(copy(rs_value));
6530     std::string rt = GPR(copy(rt_value));
6531
6532     return img::format("DPAU.H.QBR %s, %s, %s", ac, rs, rt);
6533 }
6534
6535
6536 /*
6537  *
6538  *
6539  *   3         2         1
6540  *  10987654321098765432109876543210
6541  *  001000               x1110000101
6542  *     rt -----
6543  *          rs -----
6544  *               rd -----
6545  */
6546 std::string NMD::DPAX_W_PH(uint64 instruction)
6547 {
6548     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6549     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6550     uint64 ac_value = extract_ac_15_14(instruction);
6551
6552     std::string ac = AC(copy(ac_value));
6553     std::string rs = GPR(copy(rs_value));
6554     std::string rt = GPR(copy(rt_value));
6555
6556     return img::format("DPAX.W.PH %s, %s, %s", ac, rs, rt);
6557 }
6558
6559
6560 /*
6561  *
6562  *
6563  *   3         2         1
6564  *  10987654321098765432109876543210
6565  *  001000               x1110000101
6566  *     rt -----
6567  *          rs -----
6568  *               rd -----
6569  */
6570 std::string NMD::DPS_W_PH(uint64 instruction)
6571 {
6572     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6573     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6574     uint64 ac_value = extract_ac_15_14(instruction);
6575
6576     std::string ac = AC(copy(ac_value));
6577     std::string rs = GPR(copy(rs_value));
6578     std::string rt = GPR(copy(rt_value));
6579
6580     return img::format("DPS.W.PH %s, %s, %s", ac, rs, rt);
6581 }
6582
6583
6584 /*
6585  *
6586  *
6587  *   3         2         1
6588  *  10987654321098765432109876543210
6589  *  001000               x1110000101
6590  *     rt -----
6591  *          rs -----
6592  *               rd -----
6593  */
6594 std::string NMD::DPSQ_SA_L_W(uint64 instruction)
6595 {
6596     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6597     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6598     uint64 ac_value = extract_ac_15_14(instruction);
6599
6600     std::string ac = AC(copy(ac_value));
6601     std::string rs = GPR(copy(rs_value));
6602     std::string rt = GPR(copy(rt_value));
6603
6604     return img::format("DPSQ_SA.L.W %s, %s, %s", ac, rs, rt);
6605 }
6606
6607
6608 /*
6609  *
6610  *
6611  *   3         2         1
6612  *  10987654321098765432109876543210
6613  *  001000               x1110000101
6614  *     rt -----
6615  *          rs -----
6616  *               rd -----
6617  */
6618 std::string NMD::DPSQ_S_W_PH(uint64 instruction)
6619 {
6620     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6621     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6622     uint64 ac_value = extract_ac_15_14(instruction);
6623
6624     std::string ac = AC(copy(ac_value));
6625     std::string rs = GPR(copy(rs_value));
6626     std::string rt = GPR(copy(rt_value));
6627
6628     return img::format("DPSQ_S.W.PH %s, %s, %s", ac, rs, rt);
6629 }
6630
6631
6632 /*
6633  *
6634  *
6635  *   3         2         1
6636  *  10987654321098765432109876543210
6637  *  001000               x1110000101
6638  *     rt -----
6639  *          rs -----
6640  *               rd -----
6641  */
6642 std::string NMD::DPSQX_SA_W_PH(uint64 instruction)
6643 {
6644     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6645     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6646     uint64 ac_value = extract_ac_15_14(instruction);
6647
6648     std::string ac = AC(copy(ac_value));
6649     std::string rs = GPR(copy(rs_value));
6650     std::string rt = GPR(copy(rt_value));
6651
6652     return img::format("DPSQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6653 }
6654
6655
6656 /*
6657  *
6658  *
6659  *   3         2         1
6660  *  10987654321098765432109876543210
6661  *  001000               x1110000101
6662  *     rt -----
6663  *          rs -----
6664  *               rd -----
6665  */
6666 std::string NMD::DPSQX_S_W_PH(uint64 instruction)
6667 {
6668     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6669     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6670     uint64 ac_value = extract_ac_15_14(instruction);
6671
6672     std::string ac = AC(copy(ac_value));
6673     std::string rs = GPR(copy(rs_value));
6674     std::string rt = GPR(copy(rt_value));
6675
6676     return img::format("DPSQX_S.W.PH %s, %s, %s", ac, rs, rt);
6677 }
6678
6679
6680 /*
6681  *
6682  *
6683  *   3         2         1
6684  *  10987654321098765432109876543210
6685  *  001000               x1110000101
6686  *     rt -----
6687  *          rs -----
6688  *               rd -----
6689  */
6690 std::string NMD::DPSU_H_QBL(uint64 instruction)
6691 {
6692     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6693     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6694     uint64 ac_value = extract_ac_15_14(instruction);
6695
6696     std::string ac = AC(copy(ac_value));
6697     std::string rs = GPR(copy(rs_value));
6698     std::string rt = GPR(copy(rt_value));
6699
6700     return img::format("DPSU.H.QBL %s, %s, %s", ac, rs, rt);
6701 }
6702
6703
6704 /*
6705  *
6706  *
6707  *   3         2         1
6708  *  10987654321098765432109876543210
6709  *  001000               x1110000101
6710  *     rt -----
6711  *          rs -----
6712  *               rd -----
6713  */
6714 std::string NMD::DPSU_H_QBR(uint64 instruction)
6715 {
6716     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6717     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6718     uint64 ac_value = extract_ac_15_14(instruction);
6719
6720     std::string ac = AC(copy(ac_value));
6721     std::string rs = GPR(copy(rs_value));
6722     std::string rt = GPR(copy(rt_value));
6723
6724     return img::format("DPSU.H.QBR %s, %s, %s", ac, rs, rt);
6725 }
6726
6727
6728 /*
6729  *
6730  *
6731  *   3         2         1
6732  *  10987654321098765432109876543210
6733  *  001000               x1110000101
6734  *     rt -----
6735  *          rs -----
6736  *               rd -----
6737  */
6738 std::string NMD::DPSX_W_PH(uint64 instruction)
6739 {
6740     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6741     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6742     uint64 ac_value = extract_ac_15_14(instruction);
6743
6744     std::string ac = AC(copy(ac_value));
6745     std::string rs = GPR(copy(rs_value));
6746     std::string rt = GPR(copy(rt_value));
6747
6748     return img::format("DPSX.W.PH %s, %s, %s", ac, rs, rt);
6749 }
6750
6751
6752 /*
6753  * DROTR -
6754  *
6755  *   3         2         1
6756  *  10987654321098765432109876543210
6757  *  001000               x1110000101
6758  *     rt -----
6759  *          rs -----
6760  *               rd -----
6761  */
6762 std::string NMD::DROTR(uint64 instruction)
6763 {
6764     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6765     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6766     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6767
6768     std::string rt = GPR(copy(rt_value));
6769     std::string rs = GPR(copy(rs_value));
6770     std::string shift = IMMEDIATE(copy(shift_value));
6771
6772     return img::format("DROTR %s, %s, %s", rt, rs, shift);
6773 }
6774
6775
6776 /*
6777  * DROTR[32] -
6778  *
6779  *   3         2         1
6780  *  10987654321098765432109876543210
6781  *  10o000          1100xxx0110
6782  *     rt -----
6783  *          rs -----
6784  *                       shift -----
6785  */
6786 std::string NMD::DROTR32(uint64 instruction)
6787 {
6788     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6789     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6790     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6791
6792     std::string rt = GPR(copy(rt_value));
6793     std::string rs = GPR(copy(rs_value));
6794     std::string shift = IMMEDIATE(copy(shift_value));
6795
6796     return img::format("DROTR32 %s, %s, %s", rt, rs, shift);
6797 }
6798
6799
6800 /*
6801  *
6802  *
6803  *   3         2         1
6804  *  10987654321098765432109876543210
6805  *  001000               x1110000101
6806  *     rt -----
6807  *          rs -----
6808  *               rd -----
6809  */
6810 std::string NMD::DROTRV(uint64 instruction)
6811 {
6812     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6813     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6814     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6815
6816     std::string rd = GPR(copy(rd_value));
6817     std::string rs = GPR(copy(rs_value));
6818     std::string rt = GPR(copy(rt_value));
6819
6820     return img::format("DROTRV %s, %s, %s", rd, rs, rt);
6821 }
6822
6823
6824 /*
6825  *
6826  *
6827  *   3         2         1
6828  *  10987654321098765432109876543210
6829  *  001000               x1110000101
6830  *     rt -----
6831  *          rs -----
6832  *               rd -----
6833  */
6834 std::string NMD::DROTX(uint64 instruction)
6835 {
6836     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6837     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6838     uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction);
6839     uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction);
6840
6841     std::string rt = GPR(copy(rt_value));
6842     std::string rs = GPR(copy(rs_value));
6843     std::string shift = IMMEDIATE(copy(shift_value));
6844     std::string shiftx = IMMEDIATE(copy(shiftx_value));
6845
6846     return img::format("DROTX %s, %s, %s, %s", rt, rs, shift, shiftx);
6847 }
6848
6849
6850 /*
6851  * DSLL -
6852  *
6853  *   3         2         1
6854  *  10987654321098765432109876543210
6855  *  10o000          1100xxx0000
6856  *     rt -----
6857  *          rs -----
6858  *                       shift -----
6859  */
6860 std::string NMD::DSLL(uint64 instruction)
6861 {
6862     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6863     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6864     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6865
6866     std::string rt = GPR(copy(rt_value));
6867     std::string rs = GPR(copy(rs_value));
6868     std::string shift = IMMEDIATE(copy(shift_value));
6869
6870     return img::format("DSLL %s, %s, %s", rt, rs, shift);
6871 }
6872
6873
6874 /*
6875  * DSLL[32] -
6876  *
6877  *   3         2         1
6878  *  10987654321098765432109876543210
6879  *  10o000          1100xxx0000
6880  *     rt -----
6881  *          rs -----
6882  *                       shift -----
6883  */
6884 std::string NMD::DSLL32(uint64 instruction)
6885 {
6886     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6887     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6888     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6889
6890     std::string rt = GPR(copy(rt_value));
6891     std::string rs = GPR(copy(rs_value));
6892     std::string shift = IMMEDIATE(copy(shift_value));
6893
6894     return img::format("DSLL32 %s, %s, %s", rt, rs, shift);
6895 }
6896
6897
6898 /*
6899  *
6900  *
6901  *   3         2         1
6902  *  10987654321098765432109876543210
6903  *  001000               x1110000101
6904  *     rt -----
6905  *          rs -----
6906  *               rd -----
6907  */
6908 std::string NMD::DSLLV(uint64 instruction)
6909 {
6910     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6911     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6912     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6913
6914     std::string rd = GPR(copy(rd_value));
6915     std::string rs = GPR(copy(rs_value));
6916     std::string rt = GPR(copy(rt_value));
6917
6918     return img::format("DSLLV %s, %s, %s", rd, rs, rt);
6919 }
6920
6921
6922 /*
6923  * DSRA -
6924  *
6925  *   3         2         1
6926  *  10987654321098765432109876543210
6927  *  10o000          1100xxx0100
6928  *     rt -----
6929  *          rs -----
6930  *                       shift -----
6931  */
6932 std::string NMD::DSRA(uint64 instruction)
6933 {
6934     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6935     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6936     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6937
6938     std::string rt = GPR(copy(rt_value));
6939     std::string rs = GPR(copy(rs_value));
6940     std::string shift = IMMEDIATE(copy(shift_value));
6941
6942     return img::format("DSRA %s, %s, %s", rt, rs, shift);
6943 }
6944
6945
6946 /*
6947  * DSRA[32] -
6948  *
6949  *   3         2         1
6950  *  10987654321098765432109876543210
6951  *  10o000          1100xxx0100
6952  *     rt -----
6953  *          rs -----
6954  *                       shift -----
6955  */
6956 std::string NMD::DSRA32(uint64 instruction)
6957 {
6958     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6959     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6960     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6961
6962     std::string rt = GPR(copy(rt_value));
6963     std::string rs = GPR(copy(rs_value));
6964     std::string shift = IMMEDIATE(copy(shift_value));
6965
6966     return img::format("DSRA32 %s, %s, %s", rt, rs, shift);
6967 }
6968
6969
6970 /*
6971  *
6972  *
6973  *   3         2         1
6974  *  10987654321098765432109876543210
6975  *  001000               x1110000101
6976  *     rt -----
6977  *          rs -----
6978  *               rd -----
6979  */
6980 std::string NMD::DSRAV(uint64 instruction)
6981 {
6982     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6983     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6984     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6985
6986     std::string rd = GPR(copy(rd_value));
6987     std::string rs = GPR(copy(rs_value));
6988     std::string rt = GPR(copy(rt_value));
6989
6990     return img::format("DSRAV %s, %s, %s", rd, rs, rt);
6991 }
6992
6993
6994 /*
6995  * DSRL -
6996  *
6997  *   3         2         1
6998  *  10987654321098765432109876543210
6999  *  10o000          1100xxx0100
7000  *     rt -----
7001  *          rs -----
7002  *                       shift -----
7003  */
7004 std::string NMD::DSRL(uint64 instruction)
7005 {
7006     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7007     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7008     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
7009
7010     std::string rt = GPR(copy(rt_value));
7011     std::string rs = GPR(copy(rs_value));
7012     std::string shift = IMMEDIATE(copy(shift_value));
7013
7014     return img::format("DSRL %s, %s, %s", rt, rs, shift);
7015 }
7016
7017
7018 /*
7019  * DSRL[32] -
7020  *
7021  *   3         2         1
7022  *  10987654321098765432109876543210
7023  *  10o000          1100xxx0010
7024  *     rt -----
7025  *          rs -----
7026  *                       shift -----
7027  */
7028 std::string NMD::DSRL32(uint64 instruction)
7029 {
7030     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7031     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7032     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
7033
7034     std::string rt = GPR(copy(rt_value));
7035     std::string rs = GPR(copy(rs_value));
7036     std::string shift = IMMEDIATE(copy(shift_value));
7037
7038     return img::format("DSRL32 %s, %s, %s", rt, rs, shift);
7039 }
7040
7041
7042 /*
7043  *
7044  *
7045  *   3         2         1
7046  *  10987654321098765432109876543210
7047  *  001000               x1110000101
7048  *     rt -----
7049  *          rs -----
7050  *               rd -----
7051  */
7052 std::string NMD::DSRLV(uint64 instruction)
7053 {
7054     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7055     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7056     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7057
7058     std::string rd = GPR(copy(rd_value));
7059     std::string rs = GPR(copy(rs_value));
7060     std::string rt = GPR(copy(rt_value));
7061
7062     return img::format("DSRLV %s, %s, %s", rd, rs, rt);
7063 }
7064
7065
7066 /*
7067  *
7068  *
7069  *   3         2         1
7070  *  10987654321098765432109876543210
7071  *  001000               x1110000101
7072  *     rt -----
7073  *          rs -----
7074  *               rd -----
7075  */
7076 std::string NMD::DSUB(uint64 instruction)
7077 {
7078     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7079     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7080     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7081
7082     std::string rd = GPR(copy(rd_value));
7083     std::string rs = GPR(copy(rs_value));
7084     std::string rt = GPR(copy(rt_value));
7085
7086     return img::format("DSUB %s, %s, %s", rd, rs, rt);
7087 }
7088
7089
7090 /*
7091  *
7092  *
7093  *   3         2         1
7094  *  10987654321098765432109876543210
7095  *  001000               x1110000101
7096  *     rt -----
7097  *          rs -----
7098  *               rd -----
7099  */
7100 std::string NMD::DSUBU(uint64 instruction)
7101 {
7102     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7103     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7104     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7105
7106     std::string rd = GPR(copy(rd_value));
7107     std::string rs = GPR(copy(rs_value));
7108     std::string rt = GPR(copy(rt_value));
7109
7110     return img::format("DSUBU %s, %s, %s", rd, rs, rt);
7111 }
7112
7113
7114 /*
7115  *
7116  *
7117  *   3         2         1
7118  *  10987654321098765432109876543210
7119  *  001000               x1110000101
7120  *     rt -----
7121  *          rs -----
7122  *               rd -----
7123  */
7124 std::string NMD::DVPE(uint64 instruction)
7125 {
7126     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7127
7128     std::string rt = GPR(copy(rt_value));
7129
7130     return img::format("DVPE %s", rt);
7131 }
7132
7133
7134 /*
7135  *
7136  *
7137  *   3         2         1
7138  *  10987654321098765432109876543210
7139  *  001000               x1110000101
7140  *     rt -----
7141  *          rs -----
7142  *               rd -----
7143  */
7144 std::string NMD::DVP(uint64 instruction)
7145 {
7146     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7147
7148     std::string rt = GPR(copy(rt_value));
7149
7150     return img::format("DVP %s", rt);
7151 }
7152
7153
7154 /*
7155  *
7156  *
7157  *   3         2         1
7158  *  10987654321098765432109876543210
7159  *  001000               x1110000101
7160  *     rt -----
7161  *          rs -----
7162  *               rd -----
7163  */
7164 std::string NMD::EHB(uint64 instruction)
7165 {
7166     (void)instruction;
7167
7168     return "EHB ";
7169 }
7170
7171
7172 /*
7173  *
7174  *
7175  *   3         2         1
7176  *  10987654321098765432109876543210
7177  *  001000               x1110000101
7178  *     rt -----
7179  *          rs -----
7180  *               rd -----
7181  */
7182 std::string NMD::EI(uint64 instruction)
7183 {
7184     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7185
7186     std::string rt = GPR(copy(rt_value));
7187
7188     return img::format("EI %s", rt);
7189 }
7190
7191
7192 /*
7193  *
7194  *
7195  *   3         2         1
7196  *  10987654321098765432109876543210
7197  *  001000               x1110000101
7198  *     rt -----
7199  *          rs -----
7200  *               rd -----
7201  */
7202 std::string NMD::EMT(uint64 instruction)
7203 {
7204     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7205
7206     std::string rt = GPR(copy(rt_value));
7207
7208     return img::format("EMT %s", rt);
7209 }
7210
7211
7212 /*
7213  *
7214  *
7215  *   3         2         1
7216  *  10987654321098765432109876543210
7217  *  001000               x1110000101
7218  *     rt -----
7219  *          rs -----
7220  *               rd -----
7221  */
7222 std::string NMD::ERET(uint64 instruction)
7223 {
7224     (void)instruction;
7225
7226     return "ERET ";
7227 }
7228
7229
7230 /*
7231  *
7232  *
7233  *   3         2         1
7234  *  10987654321098765432109876543210
7235  *  001000               x1110000101
7236  *     rt -----
7237  *          rs -----
7238  *               rd -----
7239  */
7240 std::string NMD::ERETNC(uint64 instruction)
7241 {
7242     (void)instruction;
7243
7244     return "ERETNC ";
7245 }
7246
7247
7248 /*
7249  *
7250  *
7251  *   3         2         1
7252  *  10987654321098765432109876543210
7253  *  001000               x1110000101
7254  *     rt -----
7255  *          rs -----
7256  *               rd -----
7257  */
7258 std::string NMD::EVP(uint64 instruction)
7259 {
7260     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7261
7262     std::string rt = GPR(copy(rt_value));
7263
7264     return img::format("EVP %s", rt);
7265 }
7266
7267
7268 /*
7269  *
7270  *
7271  *   3         2         1
7272  *  10987654321098765432109876543210
7273  *  001000               x1110000101
7274  *     rt -----
7275  *          rs -----
7276  *               rd -----
7277  */
7278 std::string NMD::EVPE(uint64 instruction)
7279 {
7280     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7281
7282     std::string rt = GPR(copy(rt_value));
7283
7284     return img::format("EVPE %s", rt);
7285 }
7286
7287
7288 /*
7289  *
7290  *
7291  *   3         2         1
7292  *  10987654321098765432109876543210
7293  *  001000               x1110000101
7294  *     rt -----
7295  *          rs -----
7296  *               rd -----
7297  */
7298 std::string NMD::EXT(uint64 instruction)
7299 {
7300     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7301     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7302     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7303     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7304
7305     std::string rt = GPR(copy(rt_value));
7306     std::string rs = GPR(copy(rs_value));
7307     std::string lsb = IMMEDIATE(copy(lsb_value));
7308     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
7309
7310     return img::format("EXT %s, %s, %s, %s", rt, rs, lsb, msbd);
7311 }
7312
7313
7314 /*
7315  *
7316  *
7317  *   3         2         1
7318  *  10987654321098765432109876543210
7319  *  001000               x1110000101
7320  *     rt -----
7321  *          rs -----
7322  *               rd -----
7323  */
7324 std::string NMD::EXTD(uint64 instruction)
7325 {
7326     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7327     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7328     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7329     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7330
7331     std::string rd = GPR(copy(rd_value));
7332     std::string rs = GPR(copy(rs_value));
7333     std::string rt = GPR(copy(rt_value));
7334     std::string shift = IMMEDIATE(copy(shift_value));
7335
7336     return img::format("EXTD %s, %s, %s, %s", rd, rs, rt, shift);
7337 }
7338
7339
7340 /*
7341  *
7342  *
7343  *   3         2         1
7344  *  10987654321098765432109876543210
7345  *  001000               x1110000101
7346  *     rt -----
7347  *          rs -----
7348  *               rd -----
7349  */
7350 std::string NMD::EXTD32(uint64 instruction)
7351 {
7352     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7353     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7354     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7355     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7356
7357     std::string rd = GPR(copy(rd_value));
7358     std::string rs = GPR(copy(rs_value));
7359     std::string rt = GPR(copy(rt_value));
7360     std::string shift = IMMEDIATE(copy(shift_value));
7361
7362     return img::format("EXTD32 %s, %s, %s, %s", rd, rs, rt, shift);
7363 }
7364
7365
7366 /*
7367  *
7368  *
7369  *   3         2         1
7370  *  10987654321098765432109876543210
7371  *  001000               x1110000101
7372  *     rt -----
7373  *          rs -----
7374  *               rd -----
7375  */
7376 std::string NMD::EXTPDP(uint64 instruction)
7377 {
7378     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7379     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7380     uint64 ac_value = extract_ac_15_14(instruction);
7381
7382     std::string rt = GPR(copy(rt_value));
7383     std::string ac = AC(copy(ac_value));
7384     std::string size = IMMEDIATE(copy(size_value));
7385
7386     return img::format("EXTPDP %s, %s, %s", rt, ac, size);
7387 }
7388
7389
7390 /*
7391  *
7392  *
7393  *   3         2         1
7394  *  10987654321098765432109876543210
7395  *  001000               x1110000101
7396  *     rt -----
7397  *          rs -----
7398  *               rd -----
7399  */
7400 std::string NMD::EXTPDPV(uint64 instruction)
7401 {
7402     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7403     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7404     uint64 ac_value = extract_ac_15_14(instruction);
7405
7406     std::string rt = GPR(copy(rt_value));
7407     std::string ac = AC(copy(ac_value));
7408     std::string rs = GPR(copy(rs_value));
7409
7410     return img::format("EXTPDPV %s, %s, %s", rt, ac, rs);
7411 }
7412
7413
7414 /*
7415  *
7416  *
7417  *   3         2         1
7418  *  10987654321098765432109876543210
7419  *  001000               x1110000101
7420  *     rt -----
7421  *          rs -----
7422  *               rd -----
7423  */
7424 std::string NMD::EXTP(uint64 instruction)
7425 {
7426     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7427     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7428     uint64 ac_value = extract_ac_15_14(instruction);
7429
7430     std::string rt = GPR(copy(rt_value));
7431     std::string ac = AC(copy(ac_value));
7432     std::string size = IMMEDIATE(copy(size_value));
7433
7434     return img::format("EXTP %s, %s, %s", rt, ac, size);
7435 }
7436
7437
7438 /*
7439  *
7440  *
7441  *   3         2         1
7442  *  10987654321098765432109876543210
7443  *  001000               x1110000101
7444  *     rt -----
7445  *          rs -----
7446  *               rd -----
7447  */
7448 std::string NMD::EXTPV(uint64 instruction)
7449 {
7450     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7451     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7452     uint64 ac_value = extract_ac_15_14(instruction);
7453
7454     std::string rt = GPR(copy(rt_value));
7455     std::string ac = AC(copy(ac_value));
7456     std::string rs = GPR(copy(rs_value));
7457
7458     return img::format("EXTPV %s, %s, %s", rt, ac, rs);
7459 }
7460
7461
7462 /*
7463  * [DSP] EXTR_RS.W rt, ac, shift - Extract word value from accumulator to GPR
7464  *   with right shift
7465  *
7466  *   3         2         1
7467  *  10987654321098765432109876543210
7468  *  001000            10111001111111
7469  *     rt -----
7470  *       shift -----
7471  *               ac --
7472  */
7473 std::string NMD::EXTR_RS_W(uint64 instruction)
7474 {
7475     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7476     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7477     uint64 ac_value = extract_ac_15_14(instruction);
7478
7479     std::string rt = GPR(copy(rt_value));
7480     std::string ac = AC(copy(ac_value));
7481     std::string shift = IMMEDIATE(copy(shift_value));
7482
7483     return img::format("EXTR_RS.W %s, %s, %s", rt, ac, shift);
7484 }
7485
7486
7487 /*
7488  * [DSP] EXTR_R.W rt, ac, shift - Extract word value from accumulator to GPR
7489  *   with right shift
7490  *
7491  *   3         2         1
7492  *  10987654321098765432109876543210
7493  *  001000            01111001111111
7494  *     rt -----
7495  *       shift -----
7496  *               ac --
7497  */
7498 std::string NMD::EXTR_R_W(uint64 instruction)
7499 {
7500     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7501     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7502     uint64 ac_value = extract_ac_15_14(instruction);
7503
7504     std::string rt = GPR(copy(rt_value));
7505     std::string ac = AC(copy(ac_value));
7506     std::string shift = IMMEDIATE(copy(shift_value));
7507
7508     return img::format("EXTR_R.W %s, %s, %s", rt, ac, shift);
7509 }
7510
7511
7512 /*
7513  * [DSP] EXTR_S.H rt, ac, shift - Extract halfword value from accumulator
7514  *   to GPR with right shift and saturate
7515  *
7516  *   3         2         1
7517  *  10987654321098765432109876543210
7518  *  001000            11111001111111
7519  *     rt -----
7520  *       shift -----
7521  *               ac --
7522  */
7523 std::string NMD::EXTR_S_H(uint64 instruction)
7524 {
7525     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7526     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7527     uint64 ac_value = extract_ac_15_14(instruction);
7528
7529     std::string rt = GPR(copy(rt_value));
7530     std::string ac = AC(copy(ac_value));
7531     std::string shift = IMMEDIATE(copy(shift_value));
7532
7533     return img::format("EXTR_S.H %s, %s, %s", rt, ac, shift);
7534 }
7535
7536
7537 /*
7538  * [DSP] EXTR.W rt, ac, shift - Extract word value from accumulator to GPR
7539  *   with right shift
7540  *
7541  *   3         2         1
7542  *  10987654321098765432109876543210
7543  *  001000            00111001111111
7544  *     rt -----
7545  *       shift -----
7546  *               ac --
7547  */
7548 std::string NMD::EXTR_W(uint64 instruction)
7549 {
7550     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7551     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7552     uint64 ac_value = extract_ac_15_14(instruction);
7553
7554     std::string rt = GPR(copy(rt_value));
7555     std::string ac = AC(copy(ac_value));
7556     std::string shift = IMMEDIATE(copy(shift_value));
7557
7558     return img::format("EXTR.W %s, %s, %s", rt, ac, shift);
7559 }
7560
7561
7562 /*
7563  * [DSP] EXTRV_RS.W rt, ac, rs - Extract word value with variable
7564  *   right shift from accumulator to GPR
7565  *
7566  *   3         2         1
7567  *  10987654321098765432109876543210
7568  *  001000            10111010111111
7569  *     rt -----
7570  *          rs -----
7571  *               ac --
7572  */
7573 std::string NMD::EXTRV_RS_W(uint64 instruction)
7574 {
7575     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7576     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7577     uint64 ac_value = extract_ac_15_14(instruction);
7578
7579     std::string rt = GPR(copy(rt_value));
7580     std::string ac = AC(copy(ac_value));
7581     std::string rs = GPR(copy(rs_value));
7582
7583     return img::format("EXTRV_RS.W %s, %s, %s", rt, ac, rs);
7584 }
7585
7586
7587 /*
7588  * [DSP] EXTRV_R.W rt, ac, rs - Extract word value with variable
7589  *   right shift from accumulator to GPR
7590  *
7591  *   3         2         1
7592  *  10987654321098765432109876543210
7593  *  001000            01111010111111
7594  *     rt -----
7595  *          rs -----
7596  *               ac --
7597  */
7598 std::string NMD::EXTRV_R_W(uint64 instruction)
7599 {
7600     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7601     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7602     uint64 ac_value = extract_ac_15_14(instruction);
7603
7604     std::string rt = GPR(copy(rt_value));
7605     std::string ac = AC(copy(ac_value));
7606     std::string rs = GPR(copy(rs_value));
7607
7608     return img::format("EXTRV_R.W %s, %s, %s", rt, ac, rs);
7609 }
7610
7611
7612 /*
7613  * [DSP] EXTRV_S.H rt, ac, rs - Extract halfword value variable from
7614  *   accumulator to GPR with right shift and saturate
7615  *
7616  *   3         2         1
7617  *  10987654321098765432109876543210
7618  *  001000            11111010111111
7619  *     rt -----
7620  *          rs -----
7621  *               ac --
7622  */
7623 std::string NMD::EXTRV_S_H(uint64 instruction)
7624 {
7625     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7626     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7627     uint64 ac_value = extract_ac_15_14(instruction);
7628
7629     std::string rt = GPR(copy(rt_value));
7630     std::string ac = AC(copy(ac_value));
7631     std::string rs = GPR(copy(rs_value));
7632
7633     return img::format("EXTRV_S.H %s, %s, %s", rt, ac, rs);
7634 }
7635
7636
7637 /*
7638  * [DSP] EXTRV.W rt, ac, rs - Extract word value with variable
7639  *   right shift from accumulator to GPR
7640  *
7641  *   3         2         1
7642  *  10987654321098765432109876543210
7643  *  001000            00111010111111
7644  *     rt -----
7645  *          rs -----
7646  *               ac --
7647  */
7648 std::string NMD::EXTRV_W(uint64 instruction)
7649 {
7650     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7651     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7652     uint64 ac_value = extract_ac_15_14(instruction);
7653
7654     std::string rt = GPR(copy(rt_value));
7655     std::string ac = AC(copy(ac_value));
7656     std::string rs = GPR(copy(rs_value));
7657
7658     return img::format("EXTRV.W %s, %s, %s", rt, ac, rs);
7659 }
7660
7661
7662 /*
7663  * EXTW - Extract Word
7664  *
7665  *   3         2         1
7666  *  10987654321098765432109876543210
7667  *  001000                    011111
7668  *     rt -----
7669  *          rs -----
7670  *               rd -----
7671  *                 shift -----
7672  */
7673 std::string NMD::EXTW(uint64 instruction)
7674 {
7675     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7676     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7677     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7678     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7679
7680     std::string rd = GPR(copy(rd_value));
7681     std::string rs = GPR(copy(rs_value));
7682     std::string rt = GPR(copy(rt_value));
7683     std::string shift = IMMEDIATE(copy(shift_value));
7684
7685     return img::format("EXTW %s, %s, %s, %s", rd, rs, rt, shift);
7686 }
7687
7688
7689 /*
7690  *
7691  *
7692  *   3         2         1
7693  *  10987654321098765432109876543210
7694  *  001000               x1110000101
7695  *     rt -----
7696  *          rs -----
7697  *               rd -----
7698  */
7699 std::string NMD::FLOOR_L_D(uint64 instruction)
7700 {
7701     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7702     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7703
7704     std::string ft = FPR(copy(ft_value));
7705     std::string fs = FPR(copy(fs_value));
7706
7707     return img::format("FLOOR.L.D %s, %s", ft, fs);
7708 }
7709
7710
7711 /*
7712  *
7713  *
7714  *   3         2         1
7715  *  10987654321098765432109876543210
7716  *  001000               x1110000101
7717  *     rt -----
7718  *          rs -----
7719  *               rd -----
7720  */
7721 std::string NMD::FLOOR_L_S(uint64 instruction)
7722 {
7723     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7724     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7725
7726     std::string ft = FPR(copy(ft_value));
7727     std::string fs = FPR(copy(fs_value));
7728
7729     return img::format("FLOOR.L.S %s, %s", ft, fs);
7730 }
7731
7732
7733 /*
7734  *
7735  *
7736  *   3         2         1
7737  *  10987654321098765432109876543210
7738  *  001000               x1110000101
7739  *     rt -----
7740  *          rs -----
7741  *               rd -----
7742  */
7743 std::string NMD::FLOOR_W_D(uint64 instruction)
7744 {
7745     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7746     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7747
7748     std::string ft = FPR(copy(ft_value));
7749     std::string fs = FPR(copy(fs_value));
7750
7751     return img::format("FLOOR.W.D %s, %s", ft, fs);
7752 }
7753
7754
7755 /*
7756  *
7757  *
7758  *   3         2         1
7759  *  10987654321098765432109876543210
7760  *  001000               x1110000101
7761  *     rt -----
7762  *          rs -----
7763  *               rd -----
7764  */
7765 std::string NMD::FLOOR_W_S(uint64 instruction)
7766 {
7767     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7768     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7769
7770     std::string ft = FPR(copy(ft_value));
7771     std::string fs = FPR(copy(fs_value));
7772
7773     return img::format("FLOOR.W.S %s, %s", ft, fs);
7774 }
7775
7776
7777 /*
7778  *
7779  *
7780  *   3         2         1
7781  *  10987654321098765432109876543210
7782  *  001000               x1110000101
7783  *     rt -----
7784  *          rs -----
7785  *               rd -----
7786  */
7787 std::string NMD::FORK(uint64 instruction)
7788 {
7789     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7790     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7791     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7792
7793     std::string rd = GPR(copy(rd_value));
7794     std::string rs = GPR(copy(rs_value));
7795     std::string rt = GPR(copy(rt_value));
7796
7797     return img::format("FORK %s, %s, %s", rd, rs, rt);
7798 }
7799
7800
7801 /*
7802  *
7803  *
7804  *   3         2         1
7805  *  10987654321098765432109876543210
7806  *  001000               x1110000101
7807  *     rt -----
7808  *          rs -----
7809  *               rd -----
7810  */
7811 std::string NMD::HYPCALL(uint64 instruction)
7812 {
7813     uint64 code_value = extract_code_17_to_0(instruction);
7814
7815     std::string code = IMMEDIATE(copy(code_value));
7816
7817     return img::format("HYPCALL %s", code);
7818 }
7819
7820
7821 /*
7822  *
7823  *
7824  *   3         2         1
7825  *  10987654321098765432109876543210
7826  *  001000               x1110000101
7827  *     rt -----
7828  *          rs -----
7829  *               rd -----
7830  */
7831 std::string NMD::HYPCALL_16_(uint64 instruction)
7832 {
7833     uint64 code_value = extract_code_1_0(instruction);
7834
7835     std::string code = IMMEDIATE(copy(code_value));
7836
7837     return img::format("HYPCALL %s", code);
7838 }
7839
7840
7841 /*
7842  *
7843  *
7844  *   3         2         1
7845  *  10987654321098765432109876543210
7846  *  001000               x1110000101
7847  *     rt -----
7848  *          rs -----
7849  *               rd -----
7850  */
7851 std::string NMD::INS(uint64 instruction)
7852 {
7853     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7854     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7855     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7856     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7857
7858     std::string rt = GPR(copy(rt_value));
7859     std::string rs = GPR(copy(rs_value));
7860     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
7861     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
7862     /* !!!!!!!!!! - no conversion function */
7863
7864     return img::format("INS %s, %s, %s, %s", rt, rs, pos, size);
7865     /* hand edited */
7866 }
7867
7868
7869 /*
7870  * [DSP] INSV rt, rs - Insert bit field variable
7871  *
7872  *   3         2         1
7873  *  10987654321098765432109876543210
7874  *  001000          0100000100111111
7875  *     rt -----
7876  *          rs -----
7877  */
7878 std::string NMD::INSV(uint64 instruction)
7879 {
7880     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7881     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7882
7883     std::string rt = GPR(copy(rt_value));
7884     std::string rs = GPR(copy(rs_value));
7885
7886     return img::format("INSV %s, %s", rt, rs);
7887 }
7888
7889
7890 /*
7891  *
7892  *
7893  *   3         2         1
7894  *  10987654321098765432109876543210
7895  *  001000               x1110000101
7896  *     rt -----
7897  *          rs -----
7898  *               rd -----
7899  */
7900 std::string NMD::IRET(uint64 instruction)
7901 {
7902     (void)instruction;
7903
7904     return "IRET ";
7905 }
7906
7907
7908 /*
7909  *
7910  *
7911  *   3         2         1
7912  *  10987654321098765432109876543210
7913  *  001000               x1110000101
7914  *     rt -----
7915  *          rs -----
7916  *               rd -----
7917  */
7918 std::string NMD::JALRC_16_(uint64 instruction)
7919 {
7920     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7921
7922     std::string rt = GPR(copy(rt_value));
7923
7924     return img::format("JALRC $%d, %s", 31, rt);
7925 }
7926
7927
7928 /*
7929  *
7930  *
7931  *   3         2         1
7932  *  10987654321098765432109876543210
7933  *  001000               x1110000101
7934  *     rt -----
7935  *          rs -----
7936  *               rd -----
7937  */
7938 std::string NMD::JALRC_32_(uint64 instruction)
7939 {
7940     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7941     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7942
7943     std::string rt = GPR(copy(rt_value));
7944     std::string rs = GPR(copy(rs_value));
7945
7946     return img::format("JALRC %s, %s", rt, rs);
7947 }
7948
7949
7950 /*
7951  *
7952  *
7953  *   3         2         1
7954  *  10987654321098765432109876543210
7955  *  001000               x1110000101
7956  *     rt -----
7957  *          rs -----
7958  *               rd -----
7959  */
7960 std::string NMD::JALRC_HB(uint64 instruction)
7961 {
7962     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7963     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7964
7965     std::string rt = GPR(copy(rt_value));
7966     std::string rs = GPR(copy(rs_value));
7967
7968     return img::format("JALRC.HB %s, %s", rt, rs);
7969 }
7970
7971
7972 /*
7973  *
7974  *
7975  *   3         2         1
7976  *  10987654321098765432109876543210
7977  *  001000               x1110000101
7978  *     rt -----
7979  *          rs -----
7980  *               rd -----
7981  */
7982 std::string NMD::JRC(uint64 instruction)
7983 {
7984     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7985
7986     std::string rt = GPR(copy(rt_value));
7987
7988     return img::format("JRC %s", rt);
7989 }
7990
7991
7992 /*
7993  *
7994  *
7995  *   3         2         1
7996  *  10987654321098765432109876543210
7997  *  001000               x1110000101
7998  *     rt -----
7999  *          rs -----
8000  *               rd -----
8001  */
8002 std::string NMD::LB_16_(uint64 instruction)
8003 {
8004     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8005     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8006     uint64 u_value = extract_u_1_0(instruction);
8007
8008     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8009     std::string u = IMMEDIATE(copy(u_value));
8010     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8011
8012     return img::format("LB %s, %s(%s)", rt3, u, rs3);
8013 }
8014
8015
8016 /*
8017  *
8018  *
8019  *   3         2         1
8020  *  10987654321098765432109876543210
8021  *  001000               x1110000101
8022  *     rt -----
8023  *          rs -----
8024  *               rd -----
8025  */
8026 std::string NMD::LB_GP_(uint64 instruction)
8027 {
8028     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8029     uint64 u_value = extract_u_17_to_0(instruction);
8030
8031     std::string rt = GPR(copy(rt_value));
8032     std::string u = IMMEDIATE(copy(u_value));
8033
8034     return img::format("LB %s, %s($%d)", rt, u, 28);
8035 }
8036
8037
8038 /*
8039  *
8040  *
8041  *   3         2         1
8042  *  10987654321098765432109876543210
8043  *  001000               x1110000101
8044  *     rt -----
8045  *          rs -----
8046  *               rd -----
8047  */
8048 std::string NMD::LB_S9_(uint64 instruction)
8049 {
8050     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8051     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8052     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8053
8054     std::string rt = GPR(copy(rt_value));
8055     std::string s = IMMEDIATE(copy(s_value));
8056     std::string rs = GPR(copy(rs_value));
8057
8058     return img::format("LB %s, %s(%s)", rt, s, rs);
8059 }
8060
8061
8062 /*
8063  *
8064  *
8065  *   3         2         1
8066  *  10987654321098765432109876543210
8067  *  001000               x1110000101
8068  *     rt -----
8069  *          rs -----
8070  *               rd -----
8071  */
8072 std::string NMD::LB_U12_(uint64 instruction)
8073 {
8074     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8075     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8076     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8077
8078     std::string rt = GPR(copy(rt_value));
8079     std::string u = IMMEDIATE(copy(u_value));
8080     std::string rs = GPR(copy(rs_value));
8081
8082     return img::format("LB %s, %s(%s)", rt, u, rs);
8083 }
8084
8085
8086 /*
8087  *
8088  *
8089  *   3         2         1
8090  *  10987654321098765432109876543210
8091  *  001000               x1110000101
8092  *     rt -----
8093  *          rs -----
8094  *               rd -----
8095  */
8096 std::string NMD::LBE(uint64 instruction)
8097 {
8098     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8099     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8100     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8101
8102     std::string rt = GPR(copy(rt_value));
8103     std::string s = IMMEDIATE(copy(s_value));
8104     std::string rs = GPR(copy(rs_value));
8105
8106     return img::format("LBE %s, %s(%s)", rt, s, rs);
8107 }
8108
8109
8110 /*
8111  *
8112  *
8113  *   3         2         1
8114  *  10987654321098765432109876543210
8115  *  001000               x1110000101
8116  *     rt -----
8117  *          rs -----
8118  *               rd -----
8119  */
8120 std::string NMD::LBU_16_(uint64 instruction)
8121 {
8122     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8123     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8124     uint64 u_value = extract_u_1_0(instruction);
8125
8126     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8127     std::string u = IMMEDIATE(copy(u_value));
8128     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8129
8130     return img::format("LBU %s, %s(%s)", rt3, u, rs3);
8131 }
8132
8133
8134 /*
8135  *
8136  *
8137  *   3         2         1
8138  *  10987654321098765432109876543210
8139  *  001000               x1110000101
8140  *     rt -----
8141  *          rs -----
8142  *               rd -----
8143  */
8144 std::string NMD::LBU_GP_(uint64 instruction)
8145 {
8146     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8147     uint64 u_value = extract_u_17_to_0(instruction);
8148
8149     std::string rt = GPR(copy(rt_value));
8150     std::string u = IMMEDIATE(copy(u_value));
8151
8152     return img::format("LBU %s, %s($%d)", rt, u, 28);
8153 }
8154
8155
8156 /*
8157  *
8158  *
8159  *   3         2         1
8160  *  10987654321098765432109876543210
8161  *  001000               x1110000101
8162  *     rt -----
8163  *          rs -----
8164  *               rd -----
8165  */
8166 std::string NMD::LBU_S9_(uint64 instruction)
8167 {
8168     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8169     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8170     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8171
8172     std::string rt = GPR(copy(rt_value));
8173     std::string s = IMMEDIATE(copy(s_value));
8174     std::string rs = GPR(copy(rs_value));
8175
8176     return img::format("LBU %s, %s(%s)", rt, s, rs);
8177 }
8178
8179
8180 /*
8181  *
8182  *
8183  *   3         2         1
8184  *  10987654321098765432109876543210
8185  *  001000               x1110000101
8186  *     rt -----
8187  *          rs -----
8188  *               rd -----
8189  */
8190 std::string NMD::LBU_U12_(uint64 instruction)
8191 {
8192     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8193     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8194     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8195
8196     std::string rt = GPR(copy(rt_value));
8197     std::string u = IMMEDIATE(copy(u_value));
8198     std::string rs = GPR(copy(rs_value));
8199
8200     return img::format("LBU %s, %s(%s)", rt, u, rs);
8201 }
8202
8203
8204 /*
8205  *
8206  *
8207  *   3         2         1
8208  *  10987654321098765432109876543210
8209  *  001000               x1110000101
8210  *     rt -----
8211  *          rs -----
8212  *               rd -----
8213  */
8214 std::string NMD::LBUE(uint64 instruction)
8215 {
8216     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8217     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8218     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8219
8220     std::string rt = GPR(copy(rt_value));
8221     std::string s = IMMEDIATE(copy(s_value));
8222     std::string rs = GPR(copy(rs_value));
8223
8224     return img::format("LBUE %s, %s(%s)", rt, s, rs);
8225 }
8226
8227
8228 /*
8229  *
8230  *
8231  *   3         2         1
8232  *  10987654321098765432109876543210
8233  *  001000               x1110000101
8234  *     rt -----
8235  *          rs -----
8236  *               rd -----
8237  */
8238 std::string NMD::LBUX(uint64 instruction)
8239 {
8240     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8241     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8242     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8243
8244     std::string rd = GPR(copy(rd_value));
8245     std::string rs = GPR(copy(rs_value));
8246     std::string rt = GPR(copy(rt_value));
8247
8248     return img::format("LBUX %s, %s(%s)", rd, rs, rt);
8249 }
8250
8251
8252 /*
8253  *
8254  *
8255  *   3         2         1
8256  *  10987654321098765432109876543210
8257  *  001000               x1110000101
8258  *     rt -----
8259  *          rs -----
8260  *               rd -----
8261  */
8262 std::string NMD::LBX(uint64 instruction)
8263 {
8264     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8265     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8266     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8267
8268     std::string rd = GPR(copy(rd_value));
8269     std::string rs = GPR(copy(rs_value));
8270     std::string rt = GPR(copy(rt_value));
8271
8272     return img::format("LBX %s, %s(%s)", rd, rs, rt);
8273 }
8274
8275
8276 /*
8277  *
8278  *
8279  *   3         2         1
8280  *  10987654321098765432109876543210
8281  *  001000               x1110000101
8282  *     rt -----
8283  *          rs -----
8284  *               rd -----
8285  */
8286 std::string NMD::LD_GP_(uint64 instruction)
8287 {
8288     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8289     uint64 u_value = extract_u_20_to_3__s3(instruction);
8290
8291     std::string rt = GPR(copy(rt_value));
8292     std::string u = IMMEDIATE(copy(u_value));
8293
8294     return img::format("LD %s, %s($%d)", rt, u, 28);
8295 }
8296
8297
8298 /*
8299  *
8300  *
8301  *   3         2         1
8302  *  10987654321098765432109876543210
8303  *  001000               x1110000101
8304  *     rt -----
8305  *          rs -----
8306  *               rd -----
8307  */
8308 std::string NMD::LD_S9_(uint64 instruction)
8309 {
8310     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8311     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8312     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8313
8314     std::string rt = GPR(copy(rt_value));
8315     std::string s = IMMEDIATE(copy(s_value));
8316     std::string rs = GPR(copy(rs_value));
8317
8318     return img::format("LD %s, %s(%s)", rt, s, rs);
8319 }
8320
8321
8322 /*
8323  *
8324  *
8325  *   3         2         1
8326  *  10987654321098765432109876543210
8327  *  001000               x1110000101
8328  *     rt -----
8329  *          rs -----
8330  *               rd -----
8331  */
8332 std::string NMD::LD_U12_(uint64 instruction)
8333 {
8334     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8335     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8336     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8337
8338     std::string rt = GPR(copy(rt_value));
8339     std::string u = IMMEDIATE(copy(u_value));
8340     std::string rs = GPR(copy(rs_value));
8341
8342     return img::format("LD %s, %s(%s)", rt, u, rs);
8343 }
8344
8345
8346 /*
8347  *
8348  *
8349  *   3         2         1
8350  *  10987654321098765432109876543210
8351  *  001000               x1110000101
8352  *     rt -----
8353  *          rs -----
8354  *               rd -----
8355  */
8356 std::string NMD::LDC1_GP_(uint64 instruction)
8357 {
8358     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8359     uint64 u_value = extract_u_17_to_2__s2(instruction);
8360
8361     std::string ft = FPR(copy(ft_value));
8362     std::string u = IMMEDIATE(copy(u_value));
8363
8364     return img::format("LDC1 %s, %s($%d)", ft, u, 28);
8365 }
8366
8367
8368 /*
8369  *
8370  *
8371  *   3         2         1
8372  *  10987654321098765432109876543210
8373  *  001000               x1110000101
8374  *     rt -----
8375  *          rs -----
8376  *               rd -----
8377  */
8378 std::string NMD::LDC1_S9_(uint64 instruction)
8379 {
8380     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8381     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8382     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8383
8384     std::string ft = FPR(copy(ft_value));
8385     std::string s = IMMEDIATE(copy(s_value));
8386     std::string rs = GPR(copy(rs_value));
8387
8388     return img::format("LDC1 %s, %s(%s)", ft, s, rs);
8389 }
8390
8391
8392 /*
8393  *
8394  *
8395  *   3         2         1
8396  *  10987654321098765432109876543210
8397  *  001000               x1110000101
8398  *     rt -----
8399  *          rs -----
8400  *               rd -----
8401  */
8402 std::string NMD::LDC1_U12_(uint64 instruction)
8403 {
8404     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8405     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8406     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8407
8408     std::string ft = FPR(copy(ft_value));
8409     std::string u = IMMEDIATE(copy(u_value));
8410     std::string rs = GPR(copy(rs_value));
8411
8412     return img::format("LDC1 %s, %s(%s)", ft, u, rs);
8413 }
8414
8415
8416 /*
8417  *
8418  *
8419  *   3         2         1
8420  *  10987654321098765432109876543210
8421  *  001000               x1110000101
8422  *     rt -----
8423  *          rs -----
8424  *               rd -----
8425  */
8426 std::string NMD::LDC1XS(uint64 instruction)
8427 {
8428     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8429     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8430     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8431
8432     std::string ft = FPR(copy(ft_value));
8433     std::string rs = GPR(copy(rs_value));
8434     std::string rt = GPR(copy(rt_value));
8435
8436     return img::format("LDC1XS %s, %s(%s)", ft, rs, rt);
8437 }
8438
8439
8440 /*
8441  *
8442  *
8443  *   3         2         1
8444  *  10987654321098765432109876543210
8445  *  001000               x1110000101
8446  *     rt -----
8447  *          rs -----
8448  *               rd -----
8449  */
8450 std::string NMD::LDC1X(uint64 instruction)
8451 {
8452     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8453     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8454     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8455
8456     std::string ft = FPR(copy(ft_value));
8457     std::string rs = GPR(copy(rs_value));
8458     std::string rt = GPR(copy(rt_value));
8459
8460     return img::format("LDC1X %s, %s(%s)", ft, rs, rt);
8461 }
8462
8463
8464 /*
8465  *
8466  *
8467  *   3         2         1
8468  *  10987654321098765432109876543210
8469  *  001000               x1110000101
8470  *     rt -----
8471  *          rs -----
8472  *               rd -----
8473  */
8474 std::string NMD::LDC2(uint64 instruction)
8475 {
8476     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
8477     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8478     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8479
8480     std::string ct = CPR(copy(ct_value));
8481     std::string s = IMMEDIATE(copy(s_value));
8482     std::string rs = GPR(copy(rs_value));
8483
8484     return img::format("LDC2 %s, %s(%s)", ct, s, rs);
8485 }
8486
8487
8488 /*
8489  *
8490  *
8491  *   3         2         1
8492  *  10987654321098765432109876543210
8493  *  001000               x1110000101
8494  *     rt -----
8495  *          rs -----
8496  *               rd -----
8497  */
8498 std::string NMD::LDM(uint64 instruction)
8499 {
8500     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8501     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8502     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8503     uint64 count3_value = extract_count3_14_13_12(instruction);
8504
8505     std::string rt = GPR(copy(rt_value));
8506     std::string s = IMMEDIATE(copy(s_value));
8507     std::string rs = GPR(copy(rs_value));
8508     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
8509
8510     return img::format("LDM %s, %s(%s), %s", rt, s, rs, count3);
8511 }
8512
8513
8514 /*
8515  *
8516  *
8517  *   3         2         1
8518  *  10987654321098765432109876543210
8519  *  001000               x1110000101
8520  *     rt -----
8521  *          rs -----
8522  *               rd -----
8523  */
8524 std::string NMD::LDPC_48_(uint64 instruction)
8525 {
8526     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8527     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8528
8529     std::string rt = GPR(copy(rt_value));
8530     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
8531
8532     return img::format("LDPC %s, %s", rt, s);
8533 }
8534
8535
8536 /*
8537  *
8538  *
8539  *   3         2         1
8540  *  10987654321098765432109876543210
8541  *  001000               x1110000101
8542  *     rt -----
8543  *          rs -----
8544  *               rd -----
8545  */
8546 std::string NMD::LDX(uint64 instruction)
8547 {
8548     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8549     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8550     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8551
8552     std::string rd = GPR(copy(rd_value));
8553     std::string rs = GPR(copy(rs_value));
8554     std::string rt = GPR(copy(rt_value));
8555
8556     return img::format("LDX %s, %s(%s)", rd, rs, rt);
8557 }
8558
8559
8560 /*
8561  *
8562  *
8563  *   3         2         1
8564  *  10987654321098765432109876543210
8565  *  001000               x1110000101
8566  *     rt -----
8567  *          rs -----
8568  *               rd -----
8569  */
8570 std::string NMD::LDXS(uint64 instruction)
8571 {
8572     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8573     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8574     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8575
8576     std::string rd = GPR(copy(rd_value));
8577     std::string rs = GPR(copy(rs_value));
8578     std::string rt = GPR(copy(rt_value));
8579
8580     return img::format("LDXS %s, %s(%s)", rd, rs, rt);
8581 }
8582
8583
8584 /*
8585  *
8586  *
8587  *   3         2         1
8588  *  10987654321098765432109876543210
8589  *  001000               x1110000101
8590  *     rt -----
8591  *          rs -----
8592  *               rd -----
8593  */
8594 std::string NMD::LH_16_(uint64 instruction)
8595 {
8596     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8597     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8598     uint64 u_value = extract_u_2_1__s1(instruction);
8599
8600     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8601     std::string u = IMMEDIATE(copy(u_value));
8602     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8603
8604     return img::format("LH %s, %s(%s)", rt3, u, rs3);
8605 }
8606
8607
8608 /*
8609  *
8610  *
8611  *   3         2         1
8612  *  10987654321098765432109876543210
8613  *  001000               x1110000101
8614  *     rt -----
8615  *          rs -----
8616  *               rd -----
8617  */
8618 std::string NMD::LH_GP_(uint64 instruction)
8619 {
8620     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8621     uint64 u_value = extract_u_17_to_1__s1(instruction);
8622
8623     std::string rt = GPR(copy(rt_value));
8624     std::string u = IMMEDIATE(copy(u_value));
8625
8626     return img::format("LH %s, %s($%d)", rt, u, 28);
8627 }
8628
8629
8630 /*
8631  *
8632  *
8633  *   3         2         1
8634  *  10987654321098765432109876543210
8635  *  001000               x1110000101
8636  *     rt -----
8637  *          rs -----
8638  *               rd -----
8639  */
8640 std::string NMD::LH_S9_(uint64 instruction)
8641 {
8642     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8643     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8644     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8645
8646     std::string rt = GPR(copy(rt_value));
8647     std::string s = IMMEDIATE(copy(s_value));
8648     std::string rs = GPR(copy(rs_value));
8649
8650     return img::format("LH %s, %s(%s)", rt, s, rs);
8651 }
8652
8653
8654 /*
8655  *
8656  *
8657  *   3         2         1
8658  *  10987654321098765432109876543210
8659  *  001000               x1110000101
8660  *     rt -----
8661  *          rs -----
8662  *               rd -----
8663  */
8664 std::string NMD::LH_U12_(uint64 instruction)
8665 {
8666     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8667     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8668     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8669
8670     std::string rt = GPR(copy(rt_value));
8671     std::string u = IMMEDIATE(copy(u_value));
8672     std::string rs = GPR(copy(rs_value));
8673
8674     return img::format("LH %s, %s(%s)", rt, u, rs);
8675 }
8676
8677
8678 /*
8679  *
8680  *
8681  *   3         2         1
8682  *  10987654321098765432109876543210
8683  *  001000               x1110000101
8684  *     rt -----
8685  *          rs -----
8686  *               rd -----
8687  */
8688 std::string NMD::LHE(uint64 instruction)
8689 {
8690     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8691     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8692     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8693
8694     std::string rt = GPR(copy(rt_value));
8695     std::string s = IMMEDIATE(copy(s_value));
8696     std::string rs = GPR(copy(rs_value));
8697
8698     return img::format("LHE %s, %s(%s)", rt, s, rs);
8699 }
8700
8701
8702 /*
8703  *
8704  *
8705  *   3         2         1
8706  *  10987654321098765432109876543210
8707  *  001000               x1110000101
8708  *     rt -----
8709  *          rs -----
8710  *               rd -----
8711  */
8712 std::string NMD::LHU_16_(uint64 instruction)
8713 {
8714     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8715     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8716     uint64 u_value = extract_u_2_1__s1(instruction);
8717
8718     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8719     std::string u = IMMEDIATE(copy(u_value));
8720     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8721
8722     return img::format("LHU %s, %s(%s)", rt3, u, rs3);
8723 }
8724
8725
8726 /*
8727  *
8728  *
8729  *   3         2         1
8730  *  10987654321098765432109876543210
8731  *  001000               x1110000101
8732  *     rt -----
8733  *          rs -----
8734  *               rd -----
8735  */
8736 std::string NMD::LHU_GP_(uint64 instruction)
8737 {
8738     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8739     uint64 u_value = extract_u_17_to_1__s1(instruction);
8740
8741     std::string rt = GPR(copy(rt_value));
8742     std::string u = IMMEDIATE(copy(u_value));
8743
8744     return img::format("LHU %s, %s($%d)", rt, u, 28);
8745 }
8746
8747
8748 /*
8749  *
8750  *
8751  *   3         2         1
8752  *  10987654321098765432109876543210
8753  *  001000               x1110000101
8754  *     rt -----
8755  *          rs -----
8756  *               rd -----
8757  */
8758 std::string NMD::LHU_S9_(uint64 instruction)
8759 {
8760     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8761     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8762     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8763
8764     std::string rt = GPR(copy(rt_value));
8765     std::string s = IMMEDIATE(copy(s_value));
8766     std::string rs = GPR(copy(rs_value));
8767
8768     return img::format("LHU %s, %s(%s)", rt, s, rs);
8769 }
8770
8771
8772 /*
8773  *
8774  *
8775  *   3         2         1
8776  *  10987654321098765432109876543210
8777  *  001000               x1110000101
8778  *     rt -----
8779  *          rs -----
8780  *               rd -----
8781  */
8782 std::string NMD::LHU_U12_(uint64 instruction)
8783 {
8784     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8785     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8786     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8787
8788     std::string rt = GPR(copy(rt_value));
8789     std::string u = IMMEDIATE(copy(u_value));
8790     std::string rs = GPR(copy(rs_value));
8791
8792     return img::format("LHU %s, %s(%s)", rt, u, rs);
8793 }
8794
8795
8796 /*
8797  *
8798  *
8799  *   3         2         1
8800  *  10987654321098765432109876543210
8801  *  001000               x1110000101
8802  *     rt -----
8803  *          rs -----
8804  *               rd -----
8805  */
8806 std::string NMD::LHUE(uint64 instruction)
8807 {
8808     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8809     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8810     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8811
8812     std::string rt = GPR(copy(rt_value));
8813     std::string s = IMMEDIATE(copy(s_value));
8814     std::string rs = GPR(copy(rs_value));
8815
8816     return img::format("LHUE %s, %s(%s)", rt, s, rs);
8817 }
8818
8819
8820 /*
8821  *
8822  *
8823  *   3         2         1
8824  *  10987654321098765432109876543210
8825  *  001000               x1110000101
8826  *     rt -----
8827  *          rs -----
8828  *               rd -----
8829  */
8830 std::string NMD::LHUX(uint64 instruction)
8831 {
8832     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8833     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8834     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8835
8836     std::string rd = GPR(copy(rd_value));
8837     std::string rs = GPR(copy(rs_value));
8838     std::string rt = GPR(copy(rt_value));
8839
8840     return img::format("LHUX %s, %s(%s)", rd, rs, rt);
8841 }
8842
8843
8844 /*
8845  *
8846  *
8847  *   3         2         1
8848  *  10987654321098765432109876543210
8849  *  001000               x1110000101
8850  *     rt -----
8851  *          rs -----
8852  *               rd -----
8853  */
8854 std::string NMD::LHUXS(uint64 instruction)
8855 {
8856     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8857     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8858     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8859
8860     std::string rd = GPR(copy(rd_value));
8861     std::string rs = GPR(copy(rs_value));
8862     std::string rt = GPR(copy(rt_value));
8863
8864     return img::format("LHUXS %s, %s(%s)", rd, rs, rt);
8865 }
8866
8867
8868 /*
8869  *
8870  *
8871  *   3         2         1
8872  *  10987654321098765432109876543210
8873  *  001000               x1110000101
8874  *     rt -----
8875  *          rs -----
8876  *               rd -----
8877  */
8878 std::string NMD::LHXS(uint64 instruction)
8879 {
8880     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8881     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8882     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8883
8884     std::string rd = GPR(copy(rd_value));
8885     std::string rs = GPR(copy(rs_value));
8886     std::string rt = GPR(copy(rt_value));
8887
8888     return img::format("LHXS %s, %s(%s)", rd, rs, rt);
8889 }
8890
8891
8892 /*
8893  *
8894  *
8895  *   3         2         1
8896  *  10987654321098765432109876543210
8897  *  001000               x1110000101
8898  *     rt -----
8899  *          rs -----
8900  *               rd -----
8901  */
8902 std::string NMD::LHX(uint64 instruction)
8903 {
8904     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8905     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8906     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8907
8908     std::string rd = GPR(copy(rd_value));
8909     std::string rs = GPR(copy(rs_value));
8910     std::string rt = GPR(copy(rt_value));
8911
8912     return img::format("LHX %s, %s(%s)", rd, rs, rt);
8913 }
8914
8915
8916 /*
8917  *
8918  *
8919  *   3         2         1
8920  *  10987654321098765432109876543210
8921  *  001000               x1110000101
8922  *     rt -----
8923  *          rs -----
8924  *               rd -----
8925  */
8926 std::string NMD::LI_16_(uint64 instruction)
8927 {
8928     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8929     uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction);
8930
8931     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8932     std::string eu = IMMEDIATE(encode_eu_from_s_li16(eu_value));
8933
8934     return img::format("LI %s, %s", rt3, eu);
8935 }
8936
8937
8938 /*
8939  *
8940  *
8941  *   3         2         1
8942  *  10987654321098765432109876543210
8943  *  001000               x1110000101
8944  *     rt -----
8945  *          rs -----
8946  *               rd -----
8947  */
8948 std::string NMD::LI_48_(uint64 instruction)
8949 {
8950     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8951     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8952
8953     std::string rt = GPR(copy(rt_value));
8954     std::string s = IMMEDIATE(copy(s_value));
8955
8956     return img::format("LI %s, %s", rt, s);
8957 }
8958
8959
8960 /*
8961  *
8962  *
8963  *   3         2         1
8964  *  10987654321098765432109876543210
8965  *  001000               x1110000101
8966  *     rt -----
8967  *          rs -----
8968  *               rd -----
8969  */
8970 std::string NMD::LL(uint64 instruction)
8971 {
8972     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8973     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8974     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
8975
8976     std::string rt = GPR(copy(rt_value));
8977     std::string s = IMMEDIATE(copy(s_value));
8978     std::string rs = GPR(copy(rs_value));
8979
8980     return img::format("LL %s, %s(%s)", rt, s, rs);
8981 }
8982
8983
8984 /*
8985  *
8986  *
8987  *   3         2         1
8988  *  10987654321098765432109876543210
8989  *  001000               x1110000101
8990  *     rt -----
8991  *          rs -----
8992  *               rd -----
8993  */
8994 std::string NMD::LLD(uint64 instruction)
8995 {
8996     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8997     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8998     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
8999
9000     std::string rt = GPR(copy(rt_value));
9001     std::string s = IMMEDIATE(copy(s_value));
9002     std::string rs = GPR(copy(rs_value));
9003
9004     return img::format("LLD %s, %s(%s)", rt, s, rs);
9005 }
9006
9007
9008 /*
9009  *
9010  *
9011  *   3         2         1
9012  *  10987654321098765432109876543210
9013  *  001000               x1110000101
9014  *     rt -----
9015  *          rs -----
9016  *               rd -----
9017  */
9018 std::string NMD::LLDP(uint64 instruction)
9019 {
9020     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9021     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9022     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9023
9024     std::string rt = GPR(copy(rt_value));
9025     std::string ru = GPR(copy(ru_value));
9026     std::string rs = GPR(copy(rs_value));
9027
9028     return img::format("LLDP %s, %s, (%s)", rt, ru, rs);
9029 }
9030
9031
9032 /*
9033  *
9034  *
9035  *   3         2         1
9036  *  10987654321098765432109876543210
9037  *  001000               x1110000101
9038  *     rt -----
9039  *          rs -----
9040  *               rd -----
9041  */
9042 std::string NMD::LLE(uint64 instruction)
9043 {
9044     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9045     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9046     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
9047
9048     std::string rt = GPR(copy(rt_value));
9049     std::string s = IMMEDIATE(copy(s_value));
9050     std::string rs = GPR(copy(rs_value));
9051
9052     return img::format("LLE %s, %s(%s)", rt, s, rs);
9053 }
9054
9055
9056 /*
9057  *
9058  *
9059  *   3         2         1
9060  *  10987654321098765432109876543210
9061  *  001000               x1110000101
9062  *     rt -----
9063  *          rs -----
9064  *               rd -----
9065  */
9066 std::string NMD::LLWP(uint64 instruction)
9067 {
9068     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9069     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9070     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9071
9072     std::string rt = GPR(copy(rt_value));
9073     std::string ru = GPR(copy(ru_value));
9074     std::string rs = GPR(copy(rs_value));
9075
9076     return img::format("LLWP %s, %s, (%s)", rt, ru, rs);
9077 }
9078
9079
9080 /*
9081  *
9082  *
9083  *   3         2         1
9084  *  10987654321098765432109876543210
9085  *  001000               x1110000101
9086  *     rt -----
9087  *          rs -----
9088  *               rd -----
9089  */
9090 std::string NMD::LLWPE(uint64 instruction)
9091 {
9092     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9093     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9094     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9095
9096     std::string rt = GPR(copy(rt_value));
9097     std::string ru = GPR(copy(ru_value));
9098     std::string rs = GPR(copy(rs_value));
9099
9100     return img::format("LLWPE %s, %s, (%s)", rt, ru, rs);
9101 }
9102
9103
9104 /*
9105  *
9106  *
9107  *   3         2         1
9108  *  10987654321098765432109876543210
9109  *  001000               x1110000101
9110  *     rt -----
9111  *          rs -----
9112  *               rd -----
9113  */
9114 std::string NMD::LSA(uint64 instruction)
9115 {
9116     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9117     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9118     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9119     uint64 u2_value = extract_u2_10_9(instruction);
9120
9121     std::string rd = GPR(copy(rd_value));
9122     std::string rs = GPR(copy(rs_value));
9123     std::string rt = GPR(copy(rt_value));
9124     std::string u2 = IMMEDIATE(copy(u2_value));
9125
9126     return img::format("LSA %s, %s, %s, %s", rd, rs, rt, u2);
9127 }
9128
9129
9130 /*
9131  *
9132  *
9133  *   3         2         1
9134  *  10987654321098765432109876543210
9135  *  001000               x1110000101
9136  *     rt -----
9137  *          rs -----
9138  *               rd -----
9139  */
9140 std::string NMD::LUI(uint64 instruction)
9141 {
9142     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9143     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
9144
9145     std::string rt = GPR(copy(rt_value));
9146     std::string s = IMMEDIATE(copy(s_value));
9147
9148     return img::format("LUI %s, %%hi(%s)", rt, s);
9149 }
9150
9151
9152 /*
9153  *
9154  *
9155  *   3         2         1
9156  *  10987654321098765432109876543210
9157  *  001000               x1110000101
9158  *     rt -----
9159  *          rs -----
9160  *               rd -----
9161  */
9162 std::string NMD::LW_16_(uint64 instruction)
9163 {
9164     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9165     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9166     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
9167
9168     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
9169     std::string u = IMMEDIATE(copy(u_value));
9170     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
9171
9172     return img::format("LW %s, %s(%s)", rt3, u, rs3);
9173 }
9174
9175
9176 /*
9177  *
9178  *
9179  *   3         2         1
9180  *  10987654321098765432109876543210
9181  *  001000               x1110000101
9182  *     rt -----
9183  *          rs -----
9184  *               rd -----
9185  */
9186 std::string NMD::LW_4X4_(uint64 instruction)
9187 {
9188     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
9189     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
9190     uint64 u_value = extract_u_3_8__s2(instruction);
9191
9192     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
9193     std::string u = IMMEDIATE(copy(u_value));
9194     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
9195
9196     return img::format("LW %s, %s(%s)", rt4, u, rs4);
9197 }
9198
9199
9200 /*
9201  *
9202  *
9203  *   3         2         1
9204  *  10987654321098765432109876543210
9205  *  001000               x1110000101
9206  *     rt -----
9207  *          rs -----
9208  *               rd -----
9209  */
9210 std::string NMD::LW_GP_(uint64 instruction)
9211 {
9212     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9213     uint64 u_value = extract_u_20_to_2__s2(instruction);
9214
9215     std::string rt = GPR(copy(rt_value));
9216     std::string u = IMMEDIATE(copy(u_value));
9217
9218     return img::format("LW %s, %s($%d)", rt, u, 28);
9219 }
9220
9221
9222 /*
9223  *
9224  *
9225  *   3         2         1
9226  *  10987654321098765432109876543210
9227  *  001000               x1110000101
9228  *     rt -----
9229  *          rs -----
9230  *               rd -----
9231  */
9232 std::string NMD::LW_GP16_(uint64 instruction)
9233 {
9234     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9235     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
9236
9237     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
9238     std::string u = IMMEDIATE(copy(u_value));
9239
9240     return img::format("LW %s, %s($%d)", rt3, u, 28);
9241 }
9242
9243
9244 /*
9245  *
9246  *
9247  *   3         2         1
9248  *  10987654321098765432109876543210
9249  *  001000               x1110000101
9250  *     rt -----
9251  *          rs -----
9252  *               rd -----
9253  */
9254 std::string NMD::LW_S9_(uint64 instruction)
9255 {
9256     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9257     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9258     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9259
9260     std::string rt = GPR(copy(rt_value));
9261     std::string s = IMMEDIATE(copy(s_value));
9262     std::string rs = GPR(copy(rs_value));
9263
9264     return img::format("LW %s, %s(%s)", rt, s, rs);
9265 }
9266
9267
9268 /*
9269  *
9270  *
9271  *   3         2         1
9272  *  10987654321098765432109876543210
9273  *  001000               x1110000101
9274  *     rt -----
9275  *          rs -----
9276  *               rd -----
9277  */
9278 std::string NMD::LW_SP_(uint64 instruction)
9279 {
9280     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
9281     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
9282
9283     std::string rt = GPR(copy(rt_value));
9284     std::string u = IMMEDIATE(copy(u_value));
9285
9286     return img::format("LW %s, %s($%d)", rt, u, 29);
9287 }
9288
9289
9290 /*
9291  *
9292  *
9293  *   3         2         1
9294  *  10987654321098765432109876543210
9295  *  001000               x1110000101
9296  *     rt -----
9297  *          rs -----
9298  *               rd -----
9299  */
9300 std::string NMD::LW_U12_(uint64 instruction)
9301 {
9302     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9303     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9304     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9305
9306     std::string rt = GPR(copy(rt_value));
9307     std::string u = IMMEDIATE(copy(u_value));
9308     std::string rs = GPR(copy(rs_value));
9309
9310     return img::format("LW %s, %s(%s)", rt, u, rs);
9311 }
9312
9313
9314 /*
9315  *
9316  *
9317  *   3         2         1
9318  *  10987654321098765432109876543210
9319  *  001000               x1110000101
9320  *     rt -----
9321  *          rs -----
9322  *               rd -----
9323  */
9324 std::string NMD::LWC1_GP_(uint64 instruction)
9325 {
9326     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9327     uint64 u_value = extract_u_17_to_2__s2(instruction);
9328
9329     std::string ft = FPR(copy(ft_value));
9330     std::string u = IMMEDIATE(copy(u_value));
9331
9332     return img::format("LWC1 %s, %s($%d)", ft, u, 28);
9333 }
9334
9335
9336 /*
9337  *
9338  *
9339  *   3         2         1
9340  *  10987654321098765432109876543210
9341  *  001000               x1110000101
9342  *     rt -----
9343  *          rs -----
9344  *               rd -----
9345  */
9346 std::string NMD::LWC1_S9_(uint64 instruction)
9347 {
9348     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9349     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9350     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9351
9352     std::string ft = FPR(copy(ft_value));
9353     std::string s = IMMEDIATE(copy(s_value));
9354     std::string rs = GPR(copy(rs_value));
9355
9356     return img::format("LWC1 %s, %s(%s)", ft, s, rs);
9357 }
9358
9359
9360 /*
9361  *
9362  *
9363  *   3         2         1
9364  *  10987654321098765432109876543210
9365  *  001000               x1110000101
9366  *     rt -----
9367  *          rs -----
9368  *               rd -----
9369  */
9370 std::string NMD::LWC1_U12_(uint64 instruction)
9371 {
9372     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9373     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9374     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9375
9376     std::string ft = FPR(copy(ft_value));
9377     std::string u = IMMEDIATE(copy(u_value));
9378     std::string rs = GPR(copy(rs_value));
9379
9380     return img::format("LWC1 %s, %s(%s)", ft, u, rs);
9381 }
9382
9383
9384 /*
9385  *
9386  *
9387  *   3         2         1
9388  *  10987654321098765432109876543210
9389  *  001000               x1110000101
9390  *     rt -----
9391  *          rs -----
9392  *               rd -----
9393  */
9394 std::string NMD::LWC1X(uint64 instruction)
9395 {
9396     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9397     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9398     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9399
9400     std::string ft = FPR(copy(ft_value));
9401     std::string rs = GPR(copy(rs_value));
9402     std::string rt = GPR(copy(rt_value));
9403
9404     return img::format("LWC1X %s, %s(%s)", ft, rs, rt);
9405 }
9406
9407
9408 /*
9409  *
9410  *
9411  *   3         2         1
9412  *  10987654321098765432109876543210
9413  *  001000               x1110000101
9414  *     rt -----
9415  *          rs -----
9416  *               rd -----
9417  */
9418 std::string NMD::LWC1XS(uint64 instruction)
9419 {
9420     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9421     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9422     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9423
9424     std::string ft = FPR(copy(ft_value));
9425     std::string rs = GPR(copy(rs_value));
9426     std::string rt = GPR(copy(rt_value));
9427
9428     return img::format("LWC1XS %s, %s(%s)", ft, rs, rt);
9429 }
9430
9431
9432 /*
9433  *
9434  *
9435  *   3         2         1
9436  *  10987654321098765432109876543210
9437  *  001000               x1110000101
9438  *     rt -----
9439  *          rs -----
9440  *               rd -----
9441  */
9442 std::string NMD::LWC2(uint64 instruction)
9443 {
9444     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
9445     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9446     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9447
9448     std::string ct = CPR(copy(ct_value));
9449     std::string s = IMMEDIATE(copy(s_value));
9450     std::string rs = GPR(copy(rs_value));
9451
9452     return img::format("LWC2 %s, %s(%s)", ct, s, rs);
9453 }
9454
9455
9456 /*
9457  *
9458  *
9459  *   3         2         1
9460  *  10987654321098765432109876543210
9461  *  001000               x1110000101
9462  *     rt -----
9463  *          rs -----
9464  *               rd -----
9465  */
9466 std::string NMD::LWE(uint64 instruction)
9467 {
9468     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9469     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9470     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9471
9472     std::string rt = GPR(copy(rt_value));
9473     std::string s = IMMEDIATE(copy(s_value));
9474     std::string rs = GPR(copy(rs_value));
9475
9476     return img::format("LWE %s, %s(%s)", rt, s, rs);
9477 }
9478
9479
9480 /*
9481  *
9482  *
9483  *   3         2         1
9484  *  10987654321098765432109876543210
9485  *  001000               x1110000101
9486  *     rt -----
9487  *          rs -----
9488  *               rd -----
9489  */
9490 std::string NMD::LWM(uint64 instruction)
9491 {
9492     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9493     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9494     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9495     uint64 count3_value = extract_count3_14_13_12(instruction);
9496
9497     std::string rt = GPR(copy(rt_value));
9498     std::string s = IMMEDIATE(copy(s_value));
9499     std::string rs = GPR(copy(rs_value));
9500     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
9501
9502     return img::format("LWM %s, %s(%s), %s", rt, s, rs, count3);
9503 }
9504
9505
9506 /*
9507  *
9508  *
9509  *   3         2         1
9510  *  10987654321098765432109876543210
9511  *  001000               x1110000101
9512  *     rt -----
9513  *          rs -----
9514  *               rd -----
9515  */
9516 std::string NMD::LWPC_48_(uint64 instruction)
9517 {
9518     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
9519     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
9520
9521     std::string rt = GPR(copy(rt_value));
9522     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
9523
9524     return img::format("LWPC %s, %s", rt, s);
9525 }
9526
9527
9528 /*
9529  *
9530  *
9531  *   3         2         1
9532  *  10987654321098765432109876543210
9533  *  001000               x1110000101
9534  *     rt -----
9535  *          rs -----
9536  *               rd -----
9537  */
9538 std::string NMD::LWU_GP_(uint64 instruction)
9539 {
9540     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9541     uint64 u_value = extract_u_17_to_2__s2(instruction);
9542
9543     std::string rt = GPR(copy(rt_value));
9544     std::string u = IMMEDIATE(copy(u_value));
9545
9546     return img::format("LWU %s, %s($%d)", rt, u, 28);
9547 }
9548
9549
9550 /*
9551  *
9552  *
9553  *   3         2         1
9554  *  10987654321098765432109876543210
9555  *  001000               x1110000101
9556  *     rt -----
9557  *          rs -----
9558  *               rd -----
9559  */
9560 std::string NMD::LWU_S9_(uint64 instruction)
9561 {
9562     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9563     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9564     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9565
9566     std::string rt = GPR(copy(rt_value));
9567     std::string s = IMMEDIATE(copy(s_value));
9568     std::string rs = GPR(copy(rs_value));
9569
9570     return img::format("LWU %s, %s(%s)", rt, s, rs);
9571 }
9572
9573
9574 /*
9575  *
9576  *
9577  *   3         2         1
9578  *  10987654321098765432109876543210
9579  *  001000               x1110000101
9580  *     rt -----
9581  *          rs -----
9582  *               rd -----
9583  */
9584 std::string NMD::LWU_U12_(uint64 instruction)
9585 {
9586     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9587     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9588     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9589
9590     std::string rt = GPR(copy(rt_value));
9591     std::string u = IMMEDIATE(copy(u_value));
9592     std::string rs = GPR(copy(rs_value));
9593
9594     return img::format("LWU %s, %s(%s)", rt, u, rs);
9595 }
9596
9597
9598 /*
9599  *
9600  *
9601  *   3         2         1
9602  *  10987654321098765432109876543210
9603  *  001000               x1110000101
9604  *     rt -----
9605  *          rs -----
9606  *               rd -----
9607  */
9608 std::string NMD::LWUX(uint64 instruction)
9609 {
9610     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9611     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9612     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9613
9614     std::string rd = GPR(copy(rd_value));
9615     std::string rs = GPR(copy(rs_value));
9616     std::string rt = GPR(copy(rt_value));
9617
9618     return img::format("LWUX %s, %s(%s)", rd, rs, rt);
9619 }
9620
9621
9622 /*
9623  *
9624  *
9625  *   3         2         1
9626  *  10987654321098765432109876543210
9627  *  001000               x1110000101
9628  *     rt -----
9629  *          rs -----
9630  *               rd -----
9631  */
9632 std::string NMD::LWUXS(uint64 instruction)
9633 {
9634     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9635     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9636     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9637
9638     std::string rd = GPR(copy(rd_value));
9639     std::string rs = GPR(copy(rs_value));
9640     std::string rt = GPR(copy(rt_value));
9641
9642     return img::format("LWUXS %s, %s(%s)", rd, rs, rt);
9643 }
9644
9645
9646 /*
9647  *
9648  *
9649  *   3         2         1
9650  *  10987654321098765432109876543210
9651  *  001000               x1110000101
9652  *     rt -----
9653  *          rs -----
9654  *               rd -----
9655  */
9656 std::string NMD::LWX(uint64 instruction)
9657 {
9658     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9659     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9660     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9661
9662     std::string rd = GPR(copy(rd_value));
9663     std::string rs = GPR(copy(rs_value));
9664     std::string rt = GPR(copy(rt_value));
9665
9666     return img::format("LWX %s, %s(%s)", rd, rs, rt);
9667 }
9668
9669
9670 /*
9671  *
9672  *
9673  *   3         2         1
9674  *  10987654321098765432109876543210
9675  *  001000               x1110000101
9676  *     rt -----
9677  *          rs -----
9678  *               rd -----
9679  */
9680 std::string NMD::LWXS_16_(uint64 instruction)
9681 {
9682     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9683     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9684     uint64 rd3_value = extract_rd3_3_2_1(instruction);
9685
9686     std::string rd3 = GPR(decode_gpr_gpr3(rd3_value));
9687     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
9688     std::string rt3 = IMMEDIATE(decode_gpr_gpr3(rt3_value));
9689
9690     return img::format("LWXS %s, %s(%s)", rd3, rs3, rt3);
9691 }
9692
9693
9694 /*
9695  *
9696  *
9697  *   3         2         1
9698  *  10987654321098765432109876543210
9699  *  001000               x1110000101
9700  *     rt -----
9701  *          rs -----
9702  *               rd -----
9703  */
9704 std::string NMD::LWXS_32_(uint64 instruction)
9705 {
9706     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9707     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9708     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9709
9710     std::string rd = GPR(copy(rd_value));
9711     std::string rs = GPR(copy(rs_value));
9712     std::string rt = GPR(copy(rt_value));
9713
9714     return img::format("LWXS %s, %s(%s)", rd, rs, rt);
9715 }
9716
9717
9718 /*
9719  * [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
9720  *         accumulator
9721  *
9722  *   3         2         1
9723  *  10987654321098765432109876543210
9724  *  001000               x1110000101
9725  *     rt -----
9726  *          rs -----
9727  *               rd -----
9728  */
9729 std::string NMD::MADD_DSP_(uint64 instruction)
9730 {
9731     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9732     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9733     uint64 ac_value = extract_ac_15_14(instruction);
9734
9735     std::string ac = AC(copy(ac_value));
9736     std::string rs = GPR(copy(rs_value));
9737     std::string rt = GPR(copy(rt_value));
9738
9739     return img::format("MADD %s, %s, %s", ac, rs, rt);
9740 }
9741
9742
9743 /*
9744  *
9745  *
9746  *   3         2         1
9747  *  10987654321098765432109876543210
9748  *  001000               x1110000101
9749  *     rt -----
9750  *          rs -----
9751  *               rd -----
9752  */
9753 std::string NMD::MADDF_D(uint64 instruction)
9754 {
9755     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9756     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9757     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9758
9759     std::string fd = FPR(copy(fd_value));
9760     std::string fs = FPR(copy(fs_value));
9761     std::string ft = FPR(copy(ft_value));
9762
9763     return img::format("MADDF.D %s, %s, %s", fd, fs, ft);
9764 }
9765
9766
9767 /*
9768  *
9769  *
9770  *   3         2         1
9771  *  10987654321098765432109876543210
9772  *  001000               x1110000101
9773  *     rt -----
9774  *          rs -----
9775  *               rd -----
9776  */
9777 std::string NMD::MADDF_S(uint64 instruction)
9778 {
9779     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9780     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9781     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9782
9783     std::string fd = FPR(copy(fd_value));
9784     std::string fs = FPR(copy(fs_value));
9785     std::string ft = FPR(copy(ft_value));
9786
9787     return img::format("MADDF.S %s, %s, %s", fd, fs, ft);
9788 }
9789
9790
9791 /*
9792  * [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
9793  *         specified accumulator
9794  *
9795  *   3         2         1
9796  *  10987654321098765432109876543210
9797  *  001000               x1110000101
9798  *     rt -----
9799  *          rs -----
9800  *               rd -----
9801  */
9802 std::string NMD::MADDU_DSP_(uint64 instruction)
9803 {
9804     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9805     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9806     uint64 ac_value = extract_ac_15_14(instruction);
9807
9808     std::string ac = AC(copy(ac_value));
9809     std::string rs = GPR(copy(rs_value));
9810     std::string rt = GPR(copy(rt_value));
9811
9812     return img::format("MADDU %s, %s, %s", ac, rs, rt);
9813 }
9814
9815
9816 /*
9817  * [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
9818  *         fractional halfword elements with accumulation
9819  *
9820  *   3         2         1
9821  *  10987654321098765432109876543210
9822  *  001000               x1110000101
9823  *     rt -----
9824  *          rs -----
9825  *               rd -----
9826  */
9827 std::string NMD::MAQ_S_W_PHL(uint64 instruction)
9828 {
9829     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9830     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9831     uint64 ac_value = extract_ac_15_14(instruction);
9832
9833     std::string ac = AC(copy(ac_value));
9834     std::string rs = GPR(copy(rs_value));
9835     std::string rt = GPR(copy(rt_value));
9836
9837     return img::format("MAQ_S.W.PHL %s, %s, %s", ac, rs, rt);
9838 }
9839
9840
9841 /*
9842  * [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
9843  *         fractional halfword elements with accumulation
9844  *
9845  *   3         2         1
9846  *  10987654321098765432109876543210
9847  *  001000               x1110000101
9848  *     rt -----
9849  *          rs -----
9850  *               rd -----
9851  */
9852 std::string NMD::MAQ_S_W_PHR(uint64 instruction)
9853 {
9854     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9855     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9856     uint64 ac_value = extract_ac_15_14(instruction);
9857
9858     std::string ac = AC(copy(ac_value));
9859     std::string rs = GPR(copy(rs_value));
9860     std::string rt = GPR(copy(rt_value));
9861
9862     return img::format("MAQ_S.W.PHR %s, %s, %s", ac, rs, rt);
9863 }
9864
9865
9866 /*
9867  * [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
9868  *         fractional halfword elements with saturating accumulation
9869  *
9870  *   3         2         1
9871  *  10987654321098765432109876543210
9872  *  001000               x1110000101
9873  *     rt -----
9874  *          rs -----
9875  *               rd -----
9876  */
9877 std::string NMD::MAQ_SA_W_PHL(uint64 instruction)
9878 {
9879     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9880     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9881     uint64 ac_value = extract_ac_15_14(instruction);
9882
9883     std::string ac = AC(copy(ac_value));
9884     std::string rs = GPR(copy(rs_value));
9885     std::string rt = GPR(copy(rt_value));
9886
9887     return img::format("MAQ_SA.W.PHL %s, %s, %s", ac, rs, rt);
9888 }
9889
9890
9891 /*
9892  * [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
9893  *         fractional halfword elements with saturating accumulation
9894  *
9895  *   3         2         1
9896  *  10987654321098765432109876543210
9897  *  001000               x1110000101
9898  *     rt -----
9899  *          rs -----
9900  *               rd -----
9901  */
9902 std::string NMD::MAQ_SA_W_PHR(uint64 instruction)
9903 {
9904     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9905     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9906     uint64 ac_value = extract_ac_15_14(instruction);
9907
9908     std::string ac = AC(copy(ac_value));
9909     std::string rs = GPR(copy(rs_value));
9910     std::string rt = GPR(copy(rt_value));
9911
9912     return img::format("MAQ_SA.W.PHR %s, %s, %s", ac, rs, rt);
9913 }
9914
9915
9916 /*
9917  *
9918  *
9919  *   3         2         1
9920  *  10987654321098765432109876543210
9921  *  001000               x1110000101
9922  *     rt -----
9923  *          rs -----
9924  *               rd -----
9925  */
9926 std::string NMD::MAX_D(uint64 instruction)
9927 {
9928     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9929     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9930     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9931
9932     std::string fd = FPR(copy(fd_value));
9933     std::string fs = FPR(copy(fs_value));
9934     std::string ft = FPR(copy(ft_value));
9935
9936     return img::format("MAX.D %s, %s, %s", fd, fs, ft);
9937 }
9938
9939
9940 /*
9941  *
9942  *
9943  *   3         2         1
9944  *  10987654321098765432109876543210
9945  *  001000               x1110000101
9946  *     rt -----
9947  *          rs -----
9948  *               rd -----
9949  */
9950 std::string NMD::MAX_S(uint64 instruction)
9951 {
9952     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9953     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9954     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9955
9956     std::string fd = FPR(copy(fd_value));
9957     std::string fs = FPR(copy(fs_value));
9958     std::string ft = FPR(copy(ft_value));
9959
9960     return img::format("MAX.S %s, %s, %s", fd, fs, ft);
9961 }
9962
9963
9964 /*
9965  *
9966  *
9967  *   3         2         1
9968  *  10987654321098765432109876543210
9969  *  001000               x1110000101
9970  *     rt -----
9971  *          rs -----
9972  *               rd -----
9973  */
9974 std::string NMD::MAXA_D(uint64 instruction)
9975 {
9976     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9977     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9978     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9979
9980     std::string fd = FPR(copy(fd_value));
9981     std::string fs = FPR(copy(fs_value));
9982     std::string ft = FPR(copy(ft_value));
9983
9984     return img::format("MAXA.D %s, %s, %s", fd, fs, ft);
9985 }
9986
9987
9988 /*
9989  *
9990  *
9991  *   3         2         1
9992  *  10987654321098765432109876543210
9993  *  001000               x1110000101
9994  *     rt -----
9995  *          rs -----
9996  *               rd -----
9997  */
9998 std::string NMD::MAXA_S(uint64 instruction)
9999 {
10000     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10001     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10002     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10003
10004     std::string fd = FPR(copy(fd_value));
10005     std::string fs = FPR(copy(fs_value));
10006     std::string ft = FPR(copy(ft_value));
10007
10008     return img::format("MAXA.S %s, %s, %s", fd, fs, ft);
10009 }
10010
10011
10012 /*
10013  *
10014  *
10015  *   3         2         1
10016  *  10987654321098765432109876543210
10017  *  001000               x1110000101
10018  *     rt -----
10019  *          rs -----
10020  *               rd -----
10021  */
10022 std::string NMD::MFC0(uint64 instruction)
10023 {
10024     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10025     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10026     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10027
10028     std::string rt = GPR(copy(rt_value));
10029     std::string c0s = CPR(copy(c0s_value));
10030     std::string sel = IMMEDIATE(copy(sel_value));
10031
10032     return img::format("MFC0 %s, %s, %s", rt, c0s, sel);
10033 }
10034
10035
10036 /*
10037  *
10038  *
10039  *   3         2         1
10040  *  10987654321098765432109876543210
10041  *  001000               x1110000101
10042  *     rt -----
10043  *          rs -----
10044  *               rd -----
10045  */
10046 std::string NMD::MFC1(uint64 instruction)
10047 {
10048     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10049     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10050
10051     std::string rt = GPR(copy(rt_value));
10052     std::string fs = FPR(copy(fs_value));
10053
10054     return img::format("MFC1 %s, %s", rt, fs);
10055 }
10056
10057
10058 /*
10059  *
10060  *
10061  *   3         2         1
10062  *  10987654321098765432109876543210
10063  *  001000               x1110000101
10064  *     rt -----
10065  *          rs -----
10066  *               rd -----
10067  */
10068 std::string NMD::MFC2(uint64 instruction)
10069 {
10070     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10071     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10072
10073     std::string rt = GPR(copy(rt_value));
10074     std::string cs = CPR(copy(cs_value));
10075
10076     return img::format("MFC2 %s, %s", rt, cs);
10077 }
10078
10079
10080 /*
10081  *
10082  *
10083  *   3         2         1
10084  *  10987654321098765432109876543210
10085  *  001000               x1110000101
10086  *     rt -----
10087  *          rs -----
10088  *               rd -----
10089  */
10090 std::string NMD::MFGC0(uint64 instruction)
10091 {
10092     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10093     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10094     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10095
10096     std::string rt = GPR(copy(rt_value));
10097     std::string c0s = CPR(copy(c0s_value));
10098     std::string sel = IMMEDIATE(copy(sel_value));
10099
10100     return img::format("MFGC0 %s, %s, %s", rt, c0s, sel);
10101 }
10102
10103
10104 /*
10105  *
10106  *
10107  *   3         2         1
10108  *  10987654321098765432109876543210
10109  *  001000               x1110000101
10110  *     rt -----
10111  *          rs -----
10112  *               rd -----
10113  */
10114 std::string NMD::MFHC0(uint64 instruction)
10115 {
10116     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10117     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10118     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10119
10120     std::string rt = GPR(copy(rt_value));
10121     std::string c0s = CPR(copy(c0s_value));
10122     std::string sel = IMMEDIATE(copy(sel_value));
10123
10124     return img::format("MFHC0 %s, %s, %s", rt, c0s, sel);
10125 }
10126
10127
10128 /*
10129  *
10130  *
10131  *   3         2         1
10132  *  10987654321098765432109876543210
10133  *  001000               x1110000101
10134  *     rt -----
10135  *          rs -----
10136  *               rd -----
10137  */
10138 std::string NMD::MFHC1(uint64 instruction)
10139 {
10140     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10141     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10142
10143     std::string rt = GPR(copy(rt_value));
10144     std::string fs = FPR(copy(fs_value));
10145
10146     return img::format("MFHC1 %s, %s", rt, fs);
10147 }
10148
10149
10150 /*
10151  *
10152  *
10153  *   3         2         1
10154  *  10987654321098765432109876543210
10155  *  001000               x1110000101
10156  *     rt -----
10157  *          rs -----
10158  *               rd -----
10159  */
10160 std::string NMD::MFHC2(uint64 instruction)
10161 {
10162     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10163     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10164
10165     std::string rt = GPR(copy(rt_value));
10166     std::string cs = CPR(copy(cs_value));
10167
10168     return img::format("MFHC2 %s, %s", rt, cs);
10169 }
10170
10171
10172 /*
10173  *
10174  *
10175  *   3         2         1
10176  *  10987654321098765432109876543210
10177  *  001000               x1110000101
10178  *     rt -----
10179  *          rs -----
10180  *               rd -----
10181  */
10182 std::string NMD::MFHGC0(uint64 instruction)
10183 {
10184     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10185     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10186     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10187
10188     std::string rt = GPR(copy(rt_value));
10189     std::string c0s = CPR(copy(c0s_value));
10190     std::string sel = IMMEDIATE(copy(sel_value));
10191
10192     return img::format("MFHGC0 %s, %s, %s", rt, c0s, sel);
10193 }
10194
10195
10196 /*
10197  * [DSP] MFHI rs, ac - Move from HI register
10198  *
10199  *   3         2         1
10200  *  10987654321098765432109876543210
10201  *  001000     xxxxx  00000001111111
10202  *     rt -----
10203  *               ac --
10204  */
10205 std::string NMD::MFHI_DSP_(uint64 instruction)
10206 {
10207     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10208     uint64 ac_value = extract_ac_15_14(instruction);
10209
10210     std::string rt = GPR(copy(rt_value));
10211     std::string ac = AC(copy(ac_value));
10212
10213     return img::format("MFHI %s, %s", rt, ac);
10214 }
10215
10216
10217 /*
10218  *
10219  *
10220  *   3         2         1
10221  *  10987654321098765432109876543210
10222  *  001000               x1110000101
10223  *     rt -----
10224  *          rs -----
10225  *               rd -----
10226  */
10227 std::string NMD::MFHTR(uint64 instruction)
10228 {
10229     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10230     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10231     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10232     uint64 u_value = extract_u_10(instruction);
10233
10234     std::string rt = GPR(copy(rt_value));
10235     std::string c0s = IMMEDIATE(copy(c0s_value));
10236     std::string u = IMMEDIATE(copy(u_value));
10237     std::string sel = IMMEDIATE(copy(sel_value));
10238
10239     return img::format("MFHTR %s, %s, %s, %s", rt, c0s, u, sel);
10240 }
10241
10242
10243 /*
10244  * [DSP] MFLO rs, ac - Move from HI register
10245  *
10246  *   3         2         1
10247  *  10987654321098765432109876543210
10248  *  001000     xxxxx  01000001111111
10249  *     rt -----
10250  *               ac --
10251  */
10252 std::string NMD::MFLO_DSP_(uint64 instruction)
10253 {
10254     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10255     uint64 ac_value = extract_ac_15_14(instruction);
10256
10257     std::string rt = GPR(copy(rt_value));
10258     std::string ac = AC(copy(ac_value));
10259
10260     return img::format("MFLO %s, %s", rt, ac);
10261 }
10262
10263
10264 /*
10265  *
10266  *
10267  *   3         2         1
10268  *  10987654321098765432109876543210
10269  *  001000               x1110000101
10270  *     rt -----
10271  *          rs -----
10272  *               rd -----
10273  */
10274 std::string NMD::MFTR(uint64 instruction)
10275 {
10276     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10277     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10278     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10279     uint64 u_value = extract_u_10(instruction);
10280
10281     std::string rt = GPR(copy(rt_value));
10282     std::string c0s = IMMEDIATE(copy(c0s_value));
10283     std::string u = IMMEDIATE(copy(u_value));
10284     std::string sel = IMMEDIATE(copy(sel_value));
10285
10286     return img::format("MFTR %s, %s, %s, %s", rt, c0s, u, sel);
10287 }
10288
10289
10290 /*
10291  *
10292  *
10293  *   3         2         1
10294  *  10987654321098765432109876543210
10295  *  001000               x1110000101
10296  *     rt -----
10297  *          rs -----
10298  *               rd -----
10299  */
10300 std::string NMD::MIN_D(uint64 instruction)
10301 {
10302     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10303     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10304     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10305
10306     std::string fd = FPR(copy(fd_value));
10307     std::string fs = FPR(copy(fs_value));
10308     std::string ft = FPR(copy(ft_value));
10309
10310     return img::format("MIN.D %s, %s, %s", fd, fs, ft);
10311 }
10312
10313
10314 /*
10315  *
10316  *
10317  *   3         2         1
10318  *  10987654321098765432109876543210
10319  *  001000               x1110000101
10320  *     rt -----
10321  *          rs -----
10322  *               rd -----
10323  */
10324 std::string NMD::MIN_S(uint64 instruction)
10325 {
10326     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10327     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10328     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10329
10330     std::string fd = FPR(copy(fd_value));
10331     std::string fs = FPR(copy(fs_value));
10332     std::string ft = FPR(copy(ft_value));
10333
10334     return img::format("MIN.S %s, %s, %s", fd, fs, ft);
10335 }
10336
10337
10338 /*
10339  *
10340  *
10341  *   3         2         1
10342  *  10987654321098765432109876543210
10343  *  001000               x1110000101
10344  *     rt -----
10345  *          rs -----
10346  *               rd -----
10347  */
10348 std::string NMD::MINA_D(uint64 instruction)
10349 {
10350     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10351     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10352     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10353
10354     std::string fd = FPR(copy(fd_value));
10355     std::string fs = FPR(copy(fs_value));
10356     std::string ft = FPR(copy(ft_value));
10357
10358     return img::format("MINA.D %s, %s, %s", fd, fs, ft);
10359 }
10360
10361
10362 /*
10363  *
10364  *
10365  *   3         2         1
10366  *  10987654321098765432109876543210
10367  *  001000               x1110000101
10368  *     rt -----
10369  *          rs -----
10370  *               rd -----
10371  */
10372 std::string NMD::MINA_S(uint64 instruction)
10373 {
10374     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10375     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10376     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10377
10378     std::string fd = FPR(copy(fd_value));
10379     std::string fs = FPR(copy(fs_value));
10380     std::string ft = FPR(copy(ft_value));
10381
10382     return img::format("MINA.S %s, %s, %s", fd, fs, ft);
10383 }
10384
10385
10386 /*
10387  *
10388  *
10389  *   3         2         1
10390  *  10987654321098765432109876543210
10391  *  001000               x1110000101
10392  *     rt -----
10393  *          rs -----
10394  *               rd -----
10395  */
10396 std::string NMD::MOD(uint64 instruction)
10397 {
10398     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10399     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10400     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10401
10402     std::string rd = GPR(copy(rd_value));
10403     std::string rs = GPR(copy(rs_value));
10404     std::string rt = GPR(copy(rt_value));
10405
10406     return img::format("MOD %s, %s, %s", rd, rs, rt);
10407 }
10408
10409
10410 /*
10411  * [DSP] MODSUB rd, rs, rt - Modular subtraction on an index value
10412  *
10413  *   3         2         1
10414  *  10987654321098765432109876543210
10415  *  001000               x1110000101
10416  *     rt -----
10417  *          rs -----
10418  *               rd -----
10419  */
10420 std::string NMD::MODSUB(uint64 instruction)
10421 {
10422     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10423     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10424     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10425
10426     std::string rd = GPR(copy(rd_value));
10427     std::string rs = GPR(copy(rs_value));
10428     std::string rt = GPR(copy(rt_value));
10429
10430     return img::format("MODSUB %s, %s, %s", rd, rs, rt);
10431 }
10432
10433
10434 /*
10435  *
10436  *
10437  *   3         2         1
10438  *  10987654321098765432109876543210
10439  *  001000               x1010010101
10440  *     rt -----
10441  *          rs -----
10442  *               rd -----
10443  */
10444 std::string NMD::MODU(uint64 instruction)
10445 {
10446     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10447     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10448     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10449
10450     std::string rd = GPR(copy(rd_value));
10451     std::string rs = GPR(copy(rs_value));
10452     std::string rt = GPR(copy(rt_value));
10453
10454     return img::format("MODU %s, %s, %s", rd, rs, rt);
10455 }
10456
10457
10458 /*
10459  *
10460  *
10461  *   3         2         1
10462  *  10987654321098765432109876543210
10463  *  001000               x1110000101
10464  *     rt -----
10465  *          rs -----
10466  *               rd -----
10467  */
10468 std::string NMD::MOV_D(uint64 instruction)
10469 {
10470     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10471     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10472
10473     std::string ft = FPR(copy(ft_value));
10474     std::string fs = FPR(copy(fs_value));
10475
10476     return img::format("MOV.D %s, %s", ft, fs);
10477 }
10478
10479
10480 /*
10481  *
10482  *
10483  *   3         2         1
10484  *  10987654321098765432109876543210
10485  *  001000               x1110000101
10486  *     rt -----
10487  *          rs -----
10488  *               rd -----
10489  */
10490 std::string NMD::MOV_S(uint64 instruction)
10491 {
10492     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10493     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10494
10495     std::string ft = FPR(copy(ft_value));
10496     std::string fs = FPR(copy(fs_value));
10497
10498     return img::format("MOV.S %s, %s", ft, fs);
10499 }
10500
10501
10502 /*
10503  *
10504  *
10505  *   3         2         1
10506  *  10987654321098765432109876543210
10507  *  001000               x1110000101
10508  *     rt -----
10509  *          rs -----
10510  *               rd -----
10511  */
10512 std::string NMD::MOVE_BALC(uint64 instruction)
10513 {
10514     uint64 rtz4_value = extract_rtz4_27_26_25_23_22_21(instruction);
10515     uint64 rd1_value = extract_rdl_25_24(instruction);
10516     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
10517
10518     std::string rd1 = GPR(decode_gpr_gpr1(rd1_value));
10519     std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value));
10520     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
10521
10522     return img::format("MOVE.BALC %s, %s, %s", rd1, rtz4, s);
10523 }
10524
10525
10526 /*
10527  *
10528  *
10529  *   3         2         1
10530  *  10987654321098765432109876543210
10531  *  001000               x1110000101
10532  *     rt -----
10533  *          rs -----
10534  *               rd -----
10535  */
10536 std::string NMD::MOVEP(uint64 instruction)
10537 {
10538     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
10539     uint64 rd2_value = extract_rd2_3_8(instruction);
10540     uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction);
10541
10542     std::string rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value));
10543     std::string re2 = GPR(decode_gpr_gpr2_reg2(rd2_value));
10544     /* !!!!!!!!!! - no conversion function */
10545     std::string rsz4 = GPR(decode_gpr_gpr4_zero(rsz4_value));
10546     std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value));
10547
10548     return img::format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4);
10549     /* hand edited */
10550 }
10551
10552
10553 /*
10554  *
10555  *
10556  *   3         2         1
10557  *  10987654321098765432109876543210
10558  *  001000               x1110000101
10559  *     rt -----
10560  *          rs -----
10561  *               rd -----
10562  */
10563 std::string NMD::MOVEP_REV_(uint64 instruction)
10564 {
10565     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
10566     uint64 rd2_value = extract_rd2_3_8(instruction);
10567     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
10568
10569     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
10570     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
10571     std::string rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value));
10572     std::string rs2 = GPR(decode_gpr_gpr2_reg2(rd2_value));
10573     /* !!!!!!!!!! - no conversion function */
10574
10575     return img::format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2);
10576     /* hand edited */
10577 }
10578
10579
10580 /*
10581  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10582  *
10583  *   3         2         1
10584  *  10987654321098765432109876543210
10585  *  001000               00010001101
10586  *     rt -----
10587  *          rs -----
10588  *               rd -----
10589  */
10590 std::string NMD::MOVE(uint64 instruction)
10591 {
10592     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
10593     uint64 rs_value = extract_rs_4_3_2_1_0(instruction);
10594
10595     std::string rt = GPR(copy(rt_value));
10596     std::string rs = GPR(copy(rs_value));
10597
10598     return img::format("MOVE %s, %s", rt, rs);
10599 }
10600
10601
10602 /*
10603  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10604  *
10605  *   3         2         1
10606  *  10987654321098765432109876543210
10607  *  001000               00010001101
10608  *     rt -----
10609  *          rs -----
10610  *               rd -----
10611  */
10612 std::string NMD::MOVN(uint64 instruction)
10613 {
10614     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10615     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10616     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10617
10618     std::string rd = GPR(copy(rd_value));
10619     std::string rs = GPR(copy(rs_value));
10620     std::string rt = GPR(copy(rt_value));
10621
10622     return img::format("MOVN %s, %s, %s", rd, rs, rt);
10623 }
10624
10625
10626 /*
10627  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10628  *
10629  *   3         2         1
10630  *  10987654321098765432109876543210
10631  *  001000               00010001101
10632  *     rt -----
10633  *          rs -----
10634  *               rd -----
10635  */
10636 std::string NMD::MOVZ(uint64 instruction)
10637 {
10638     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10639     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10640     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10641
10642     std::string rd = GPR(copy(rd_value));
10643     std::string rs = GPR(copy(rs_value));
10644     std::string rt = GPR(copy(rt_value));
10645
10646     return img::format("MOVZ %s, %s, %s", rd, rs, rt);
10647 }
10648
10649
10650 /*
10651  * [DSP] MSUB ac, rs, rt - Multiply word and subtract from accumulator
10652  *
10653  *   3         2         1
10654  *  10987654321098765432109876543210
10655  *  001000            10101010111111
10656  *     rt -----
10657  *          rs -----
10658  *               ac --
10659  */
10660 std::string NMD::MSUB_DSP_(uint64 instruction)
10661 {
10662     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10663     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10664     uint64 ac_value = extract_ac_15_14(instruction);
10665
10666     std::string ac = AC(copy(ac_value));
10667     std::string rs = GPR(copy(rs_value));
10668     std::string rt = GPR(copy(rt_value));
10669
10670     return img::format("MSUB %s, %s, %s", ac, rs, rt);
10671 }
10672
10673
10674 /*
10675  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10676  *
10677  *   3         2         1
10678  *  10987654321098765432109876543210
10679  *  001000               00010001101
10680  *     rt -----
10681  *          rs -----
10682  *               rd -----
10683  */
10684 std::string NMD::MSUBF_D(uint64 instruction)
10685 {
10686     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10687     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10688     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10689
10690     std::string fd = FPR(copy(fd_value));
10691     std::string fs = FPR(copy(fs_value));
10692     std::string ft = FPR(copy(ft_value));
10693
10694     return img::format("MSUBF.D %s, %s, %s", fd, fs, ft);
10695 }
10696
10697
10698 /*
10699  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10700  *
10701  *   3         2         1
10702  *  10987654321098765432109876543210
10703  *  001000               00010001101
10704  *     rt -----
10705  *          rs -----
10706  *               rd -----
10707  */
10708 std::string NMD::MSUBF_S(uint64 instruction)
10709 {
10710     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10711     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10712     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10713
10714     std::string fd = FPR(copy(fd_value));
10715     std::string fs = FPR(copy(fs_value));
10716     std::string ft = FPR(copy(ft_value));
10717
10718     return img::format("MSUBF.S %s, %s, %s", fd, fs, ft);
10719 }
10720
10721
10722 /*
10723  * [DSP] MSUBU ac, rs, rt - Multiply word and add to accumulator
10724  *
10725  *   3         2         1
10726  *  10987654321098765432109876543210
10727  *  001000            11101010111111
10728  *     rt -----
10729  *          rs -----
10730  *               ac --
10731  */
10732 std::string NMD::MSUBU_DSP_(uint64 instruction)
10733 {
10734     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10735     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10736     uint64 ac_value = extract_ac_15_14(instruction);
10737
10738     std::string ac = AC(copy(ac_value));
10739     std::string rs = GPR(copy(rs_value));
10740     std::string rt = GPR(copy(rt_value));
10741
10742     return img::format("MSUBU %s, %s, %s", ac, rs, rt);
10743 }
10744
10745
10746 /*
10747  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10748  *
10749  *   3         2         1
10750  *  10987654321098765432109876543210
10751  *  001000               00010001101
10752  *     rt -----
10753  *          rs -----
10754  *               rd -----
10755  */
10756 std::string NMD::MTC0(uint64 instruction)
10757 {
10758     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10759     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10760     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10761
10762     std::string rt = GPR(copy(rt_value));
10763     std::string c0s = CPR(copy(c0s_value));
10764     std::string sel = IMMEDIATE(copy(sel_value));
10765
10766     return img::format("MTC0 %s, %s, %s", rt, c0s, sel);
10767 }
10768
10769
10770 /*
10771  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10772  *
10773  *   3         2         1
10774  *  10987654321098765432109876543210
10775  *  001000               00010001101
10776  *     rt -----
10777  *          rs -----
10778  *               rd -----
10779  */
10780 std::string NMD::MTC1(uint64 instruction)
10781 {
10782     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10783     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10784
10785     std::string rt = GPR(copy(rt_value));
10786     std::string fs = FPR(copy(fs_value));
10787
10788     return img::format("MTC1 %s, %s", rt, fs);
10789 }
10790
10791
10792 /*
10793  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10794  *
10795  *   3         2         1
10796  *  10987654321098765432109876543210
10797  *  001000               00010001101
10798  *     rt -----
10799  *          rs -----
10800  *               rd -----
10801  */
10802 std::string NMD::MTC2(uint64 instruction)
10803 {
10804     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10805     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10806
10807     std::string rt = GPR(copy(rt_value));
10808     std::string cs = CPR(copy(cs_value));
10809
10810     return img::format("MTC2 %s, %s", rt, cs);
10811 }
10812
10813
10814 /*
10815  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10816  *
10817  *   3         2         1
10818  *  10987654321098765432109876543210
10819  *  001000               00010001101
10820  *     rt -----
10821  *          rs -----
10822  *               rd -----
10823  */
10824 std::string NMD::MTGC0(uint64 instruction)
10825 {
10826     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10827     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10828     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10829
10830     std::string rt = GPR(copy(rt_value));
10831     std::string c0s = CPR(copy(c0s_value));
10832     std::string sel = IMMEDIATE(copy(sel_value));
10833
10834     return img::format("MTGC0 %s, %s, %s", rt, c0s, sel);
10835 }
10836
10837
10838 /*
10839  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10840  *
10841  *   3         2         1
10842  *  10987654321098765432109876543210
10843  *  001000               00010001101
10844  *     rt -----
10845  *          rs -----
10846  *               rd -----
10847  */
10848 std::string NMD::MTHC0(uint64 instruction)
10849 {
10850     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10851     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10852     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10853
10854     std::string rt = GPR(copy(rt_value));
10855     std::string c0s = CPR(copy(c0s_value));
10856     std::string sel = IMMEDIATE(copy(sel_value));
10857
10858     return img::format("MTHC0 %s, %s, %s", rt, c0s, sel);
10859 }
10860
10861
10862 /*
10863  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10864  *
10865  *   3         2         1
10866  *  10987654321098765432109876543210
10867  *  001000               00010001101
10868  *     rt -----
10869  *          rs -----
10870  *               rd -----
10871  */
10872 std::string NMD::MTHC1(uint64 instruction)
10873 {
10874     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10875     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10876
10877     std::string rt = GPR(copy(rt_value));
10878     std::string fs = FPR(copy(fs_value));
10879
10880     return img::format("MTHC1 %s, %s", rt, fs);
10881 }
10882
10883
10884 /*
10885  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10886  *
10887  *   3         2         1
10888  *  10987654321098765432109876543210
10889  *  001000               00010001101
10890  *     rt -----
10891  *          rs -----
10892  *               rd -----
10893  */
10894 std::string NMD::MTHC2(uint64 instruction)
10895 {
10896     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10897     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10898
10899     std::string rt = GPR(copy(rt_value));
10900     std::string cs = CPR(copy(cs_value));
10901
10902     return img::format("MTHC2 %s, %s", rt, cs);
10903 }
10904
10905
10906 /*
10907  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10908  *
10909  *   3         2         1
10910  *  10987654321098765432109876543210
10911  *  001000               00010001101
10912  *     rt -----
10913  *          rs -----
10914  *               rd -----
10915  */
10916 std::string NMD::MTHGC0(uint64 instruction)
10917 {
10918     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10919     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10920     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10921
10922     std::string rt = GPR(copy(rt_value));
10923     std::string c0s = CPR(copy(c0s_value));
10924     std::string sel = IMMEDIATE(copy(sel_value));
10925
10926     return img::format("MTHGC0 %s, %s, %s", rt, c0s, sel);
10927 }
10928
10929
10930 /*
10931  * [DSP] MTHI rs, ac - Move to HI register
10932  *
10933  *   3         2         1
10934  *  10987654321098765432109876543210
10935  *  001000xxxxx       10000001111111
10936  *          rs -----
10937  *               ac --
10938  */
10939 std::string NMD::MTHI_DSP_(uint64 instruction)
10940 {
10941     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10942     uint64 ac_value = extract_ac_15_14(instruction);
10943
10944     std::string rs = GPR(copy(rs_value));
10945     std::string ac = AC(copy(ac_value));
10946
10947     return img::format("MTHI %s, %s", rs, ac);
10948 }
10949
10950
10951 /*
10952  * [DSP] MTHLIP rs, ac - Copy LO to HI and a GPR to LO and increment pos by 32
10953  *
10954  *   3         2         1
10955  *  10987654321098765432109876543210
10956  *  001000xxxxx       00001001111111
10957  *          rs -----
10958  *               ac --
10959  */
10960 std::string NMD::MTHLIP(uint64 instruction)
10961 {
10962     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10963     uint64 ac_value = extract_ac_15_14(instruction);
10964
10965     std::string rs = GPR(copy(rs_value));
10966     std::string ac = AC(copy(ac_value));
10967
10968     return img::format("MTHLIP %s, %s", rs, ac);
10969 }
10970
10971
10972 /*
10973  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10974  *
10975  *   3         2         1
10976  *  10987654321098765432109876543210
10977  *  001000               00010001101
10978  *     rt -----
10979  *          rs -----
10980  *               rd -----
10981  */
10982 std::string NMD::MTHTR(uint64 instruction)
10983 {
10984     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10985     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10986     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10987     uint64 u_value = extract_u_10(instruction);
10988
10989     std::string rt = GPR(copy(rt_value));
10990     std::string c0s = IMMEDIATE(copy(c0s_value));
10991     std::string u = IMMEDIATE(copy(u_value));
10992     std::string sel = IMMEDIATE(copy(sel_value));
10993
10994     return img::format("MTHTR %s, %s, %s, %s", rt, c0s, u, sel);
10995 }
10996
10997
10998 /*
10999  * [DSP] MTLO rs, ac - Move to LO register
11000  *
11001  *   3         2         1
11002  *  10987654321098765432109876543210
11003  *  001000xxxxx       11000001111111
11004  *          rs -----
11005  *               ac --
11006  */
11007 std::string NMD::MTLO_DSP_(uint64 instruction)
11008 {
11009     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11010     uint64 ac_value = extract_ac_15_14(instruction);
11011
11012     std::string rs = GPR(copy(rs_value));
11013     std::string ac = AC(copy(ac_value));
11014
11015     return img::format("MTLO %s, %s", rs, ac);
11016 }
11017
11018
11019 /*
11020  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11021  *
11022  *   3         2         1
11023  *  10987654321098765432109876543210
11024  *  001000               00010001101
11025  *     rt -----
11026  *          rs -----
11027  *               rd -----
11028  */
11029 std::string NMD::MTTR(uint64 instruction)
11030 {
11031     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11032     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
11033     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
11034     uint64 u_value = extract_u_10(instruction);
11035
11036     std::string rt = GPR(copy(rt_value));
11037     std::string c0s = IMMEDIATE(copy(c0s_value));
11038     std::string u = IMMEDIATE(copy(u_value));
11039     std::string sel = IMMEDIATE(copy(sel_value));
11040
11041     return img::format("MTTR %s, %s, %s, %s", rt, c0s, u, sel);
11042 }
11043
11044
11045 /*
11046  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11047  *
11048  *   3         2         1
11049  *  10987654321098765432109876543210
11050  *  001000               00010001101
11051  *     rt -----
11052  *          rs -----
11053  *               rd -----
11054  */
11055 std::string NMD::MUH(uint64 instruction)
11056 {
11057     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11058     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11059     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11060
11061     std::string rd = GPR(copy(rd_value));
11062     std::string rs = GPR(copy(rs_value));
11063     std::string rt = GPR(copy(rt_value));
11064
11065     return img::format("MUH %s, %s, %s", rd, rs, rt);
11066 }
11067
11068
11069 /*
11070  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11071  *
11072  *   3         2         1
11073  *  10987654321098765432109876543210
11074  *  001000               00010001101
11075  *     rt -----
11076  *          rs -----
11077  *               rd -----
11078  */
11079 std::string NMD::MUHU(uint64 instruction)
11080 {
11081     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11082     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11083     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11084
11085     std::string rd = GPR(copy(rd_value));
11086     std::string rs = GPR(copy(rs_value));
11087     std::string rt = GPR(copy(rt_value));
11088
11089     return img::format("MUHU %s, %s, %s", rd, rs, rt);
11090 }
11091
11092
11093 /*
11094  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11095  *
11096  *   3         2         1
11097  *  10987654321098765432109876543210
11098  *  001000               00010001101
11099  *     rt -----
11100  *          rs -----
11101  *               rd -----
11102  */
11103 std::string NMD::MUL_32_(uint64 instruction)
11104 {
11105     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11106     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11107     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11108
11109     std::string rd = GPR(copy(rd_value));
11110     std::string rs = GPR(copy(rs_value));
11111     std::string rt = GPR(copy(rt_value));
11112
11113     return img::format("MUL %s, %s, %s", rd, rs, rt);
11114 }
11115
11116
11117 /*
11118  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11119  *
11120  *   3         2         1
11121  *  10987654321098765432109876543210
11122  *  001000               00010001101
11123  *     rt -----
11124  *          rs -----
11125  *               rd -----
11126  */
11127 std::string NMD::MUL_4X4_(uint64 instruction)
11128 {
11129     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
11130     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
11131
11132     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
11133     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
11134
11135     return img::format("MUL %s, %s", rs4, rt4);
11136 }
11137
11138
11139 /*
11140  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11141  *
11142  *   3         2         1
11143  *  10987654321098765432109876543210
11144  *  001000               00010001101
11145  *     rt -----
11146  *          rs -----
11147  *               rd -----
11148  */
11149 std::string NMD::MUL_D(uint64 instruction)
11150 {
11151     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11152     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11153     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
11154
11155     std::string fd = FPR(copy(fd_value));
11156     std::string fs = FPR(copy(fs_value));
11157     std::string ft = FPR(copy(ft_value));
11158
11159     return img::format("MUL.D %s, %s, %s", fd, fs, ft);
11160 }
11161
11162
11163 /*
11164  * [DSP] MUL.PH rd, rs, rt - Multiply vector integer half words to same size
11165  *   products
11166  *
11167  *   3         2         1
11168  *  10987654321098765432109876543210
11169  *  001000               00000101101
11170  *     rt -----
11171  *          rs -----
11172  *               rd -----
11173  */
11174 std::string NMD::MUL_PH(uint64 instruction)
11175 {
11176     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11177     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11178     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11179
11180     std::string rd = GPR(copy(rd_value));
11181     std::string rs = GPR(copy(rs_value));
11182     std::string rt = GPR(copy(rt_value));
11183
11184     return img::format("MUL.PH %s, %s, %s", rd, rs, rt);
11185 }
11186
11187
11188 /*
11189  * [DSP] MUL_S.PH rd, rs, rt - Multiply vector integer half words to same size
11190  *   products (saturated)
11191  *
11192  *   3         2         1
11193  *  10987654321098765432109876543210
11194  *  001000               10000101101
11195  *     rt -----
11196  *          rs -----
11197  *               rd -----
11198  */
11199 std::string NMD::MUL_S_PH(uint64 instruction)
11200 {
11201     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11202     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11203     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11204
11205     std::string rd = GPR(copy(rd_value));
11206     std::string rs = GPR(copy(rs_value));
11207     std::string rt = GPR(copy(rt_value));
11208
11209     return img::format("MUL_S.PH %s, %s, %s", rd, rs, rt);
11210 }
11211
11212
11213 /*
11214  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11215  *
11216  *   3         2         1
11217  *  10987654321098765432109876543210
11218  *  001000               00010001101
11219  *     rt -----
11220  *          rs -----
11221  *               rd -----
11222  */
11223 std::string NMD::MUL_S(uint64 instruction)
11224 {
11225     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11226     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11227     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
11228
11229     std::string fd = FPR(copy(fd_value));
11230     std::string fs = FPR(copy(fs_value));
11231     std::string ft = FPR(copy(ft_value));
11232
11233     return img::format("MUL.S %s, %s, %s", fd, fs, ft);
11234 }
11235
11236
11237 /*
11238  * [DSP] MULEQ_S.W.PHL rd, rs, rt - Multiply vector fractional left halfwords
11239  *   to expanded width products
11240  *
11241  *   3         2         1
11242  *  10987654321098765432109876543210
11243  *  001000               x0000100101
11244  *     rt -----
11245  *          rs -----
11246  *               rd -----
11247  */
11248 std::string NMD::MULEQ_S_W_PHL(uint64 instruction)
11249 {
11250     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11251     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11252     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11253
11254     std::string rd = GPR(copy(rd_value));
11255     std::string rs = GPR(copy(rs_value));
11256     std::string rt = GPR(copy(rt_value));
11257
11258     return img::format("MULEQ_S.W.PHL %s, %s, %s", rd, rs, rt);
11259 }
11260
11261
11262 /*
11263  * [DSP] MULEQ_S.W.PHR rd, rs, rt - Multiply vector fractional right halfwords
11264  *   to expanded width products
11265  *
11266  *   3         2         1
11267  *  10987654321098765432109876543210
11268  *  001000               x0001100101
11269  *     rt -----
11270  *          rs -----
11271  *               rd -----
11272  */
11273 std::string NMD::MULEQ_S_W_PHR(uint64 instruction)
11274 {
11275     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11276     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11277     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11278
11279     std::string rd = GPR(copy(rd_value));
11280     std::string rs = GPR(copy(rs_value));
11281     std::string rt = GPR(copy(rt_value));
11282
11283     return img::format("MULEQ_S.W.PHR %s, %s, %s", rd, rs, rt);
11284 }
11285
11286
11287 /*
11288  * [DSP] MULEU_S.PH.QBL rd, rs, rt - Multiply vector fractional left bytes
11289  *   by halfwords to halfword products
11290  *
11291  *   3         2         1
11292  *  10987654321098765432109876543210
11293  *  001000               x0010010101
11294  *     rt -----
11295  *          rs -----
11296  *               rd -----
11297  */
11298 std::string NMD::MULEU_S_PH_QBL(uint64 instruction)
11299 {
11300     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11301     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11302     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11303
11304     std::string rd = GPR(copy(rd_value));
11305     std::string rs = GPR(copy(rs_value));
11306     std::string rt = GPR(copy(rt_value));
11307
11308     return img::format("MULEU_S.PH.QBL %s, %s, %s", rd, rs, rt);
11309 }
11310
11311
11312 /*
11313  * [DSP] MULEU_S.PH.QBR rd, rs, rt - Multiply vector fractional right bytes
11314  *   by halfwords to halfword products
11315  *
11316  *   3         2         1
11317  *  10987654321098765432109876543210
11318  *  001000               x0011010101
11319  *     rt -----
11320  *          rs -----
11321  *               rd -----
11322  */
11323 std::string NMD::MULEU_S_PH_QBR(uint64 instruction)
11324 {
11325     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11326     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11327     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11328
11329     std::string rd = GPR(copy(rd_value));
11330     std::string rs = GPR(copy(rs_value));
11331     std::string rt = GPR(copy(rt_value));
11332
11333     return img::format("MULEU_S.PH.QBR %s, %s, %s", rd, rs, rt);
11334 }
11335
11336
11337 /*
11338  * [DSP] MULQ_RS.PH rd, rs, rt - Multiply vector fractional halfwords
11339  *   to fractional halfword products
11340  *
11341  *   3         2         1
11342  *  10987654321098765432109876543210
11343  *  001000               x0100010101
11344  *     rt -----
11345  *          rs -----
11346  *               rd -----
11347  */
11348 std::string NMD::MULQ_RS_PH(uint64 instruction)
11349 {
11350     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11351     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11352     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11353
11354     std::string rd = GPR(copy(rd_value));
11355     std::string rs = GPR(copy(rs_value));
11356     std::string rt = GPR(copy(rt_value));
11357
11358     return img::format("MULQ_RS.PH %s, %s, %s", rd, rs, rt);
11359 }
11360
11361
11362 /*
11363  * [DSP] MULQ_RS.W rd, rs, rt - Multiply fractional words to same size
11364  *   product with saturation and rounding
11365  *
11366  *   3         2         1
11367  *  10987654321098765432109876543210
11368  *  001000               x0110010101
11369  *     rt -----
11370  *          rs -----
11371  *               rd -----
11372  */
11373 std::string NMD::MULQ_RS_W(uint64 instruction)
11374 {
11375     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11376     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11377     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11378
11379     std::string rd = GPR(copy(rd_value));
11380     std::string rs = GPR(copy(rs_value));
11381     std::string rt = GPR(copy(rt_value));
11382
11383     return img::format("MULQ_RS.W %s, %s, %s", rd, rs, rt);
11384 }
11385
11386
11387 /*
11388  * [DSP] MULQ_S.PH rd, rs, rt - Multiply fractional halfwords to same size
11389  *   products
11390  *
11391  *   3         2         1
11392  *  10987654321098765432109876543210
11393  *  001000               x0101010101
11394  *     rt -----
11395  *          rs -----
11396  *               rd -----
11397  */
11398 std::string NMD::MULQ_S_PH(uint64 instruction)
11399 {
11400     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11401     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11402     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11403
11404     std::string rd = GPR(copy(rd_value));
11405     std::string rs = GPR(copy(rs_value));
11406     std::string rt = GPR(copy(rt_value));
11407
11408     return img::format("MULQ_S.PH %s, %s, %s", rd, rs, rt);
11409 }
11410
11411
11412 /*
11413  * [DSP] MULQ_S.W rd, rs, rt - Multiply fractional words to same size product
11414  *   with saturation
11415  *
11416  *   3         2         1
11417  *  10987654321098765432109876543210
11418  *  001000               x0111010101
11419  *     rt -----
11420  *          rs -----
11421  *               rd -----
11422  */
11423 std::string NMD::MULQ_S_W(uint64 instruction)
11424 {
11425     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11426     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11427     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11428
11429     std::string rd = GPR(copy(rd_value));
11430     std::string rs = GPR(copy(rs_value));
11431     std::string rt = GPR(copy(rt_value));
11432
11433     return img::format("MULQ_S.W %s, %s, %s", rd, rs, rt);
11434 }
11435
11436
11437 /*
11438  * [DSP] MULSA.W.PH ac, rs, rt - Multiply and subtract vector integer halfword
11439  *   elements and accumulate
11440  *
11441  *   3         2         1
11442  *  10987654321098765432109876543210
11443  *  001000            10110010111111
11444  *     rt -----
11445  *          rs -----
11446  *               ac --
11447  */
11448 std::string NMD::MULSA_W_PH(uint64 instruction)
11449 {
11450     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11451     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11452     uint64 ac_value = extract_ac_15_14(instruction);
11453
11454     std::string ac = AC(copy(ac_value));
11455     std::string rs = GPR(copy(rs_value));
11456     std::string rt = GPR(copy(rt_value));
11457
11458     return img::format("MULSA.W.PH %s, %s, %s", ac, rs, rt);
11459 }
11460
11461
11462 /*
11463  * [DSP] MULSAQ_S.W.PH ac, rs, rt - Multiply and subtract vector fractional
11464  *   halfwords and accumulate
11465  *
11466  *   3         2         1
11467  *  10987654321098765432109876543210
11468  *  001000            11110010111111
11469  *     rt -----
11470  *          rs -----
11471  *               ac --
11472  */
11473 std::string NMD::MULSAQ_S_W_PH(uint64 instruction)
11474 {
11475     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11476     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11477     uint64 ac_value = extract_ac_15_14(instruction);
11478
11479     std::string ac = AC(copy(ac_value));
11480     std::string rs = GPR(copy(rs_value));
11481     std::string rt = GPR(copy(rt_value));
11482
11483     return img::format("MULSAQ_S.W.PH %s, %s, %s", ac, rs, rt);
11484 }
11485
11486
11487 /*
11488  * [DSP] MULT ac, rs, rt - Multiply word
11489  *
11490  *   3         2         1
11491  *  10987654321098765432109876543210
11492  *  001000            00110010111111
11493  *     rt -----
11494  *          rs -----
11495  *               ac --
11496  */
11497 std::string NMD::MULT_DSP_(uint64 instruction)
11498 {
11499     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11500     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11501     uint64 ac_value = extract_ac_15_14(instruction);
11502
11503     std::string ac = AC(copy(ac_value));
11504     std::string rs = GPR(copy(rs_value));
11505     std::string rt = GPR(copy(rt_value));
11506
11507     return img::format("MULT %s, %s, %s", ac, rs, rt);
11508 }
11509
11510
11511 /*
11512  * [DSP] MULTU ac, rs, rt - Multiply unsigned word
11513  *
11514  *   3         2         1
11515  *  10987654321098765432109876543210
11516  *  001000            01110010111111
11517  *     rt -----
11518  *          rs -----
11519  *               ac --
11520  */
11521 std::string NMD::MULTU_DSP_(uint64 instruction)
11522 {
11523     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11524     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11525     uint64 ac_value = extract_ac_15_14(instruction);
11526
11527     std::string ac = AC(copy(ac_value));
11528     std::string rs = GPR(copy(rs_value));
11529     std::string rt = GPR(copy(rt_value));
11530
11531     return img::format("MULTU %s, %s, %s", ac, rs, rt);
11532 }
11533
11534
11535 /*
11536  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11537  *
11538  *   3         2         1
11539  *  10987654321098765432109876543210
11540  *  001000               00010001101
11541  *     rt -----
11542  *          rs -----
11543  *               rd -----
11544  */
11545 std::string NMD::MULU(uint64 instruction)
11546 {
11547     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11548     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11549     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11550
11551     std::string rd = GPR(copy(rd_value));
11552     std::string rs = GPR(copy(rs_value));
11553     std::string rt = GPR(copy(rt_value));
11554
11555     return img::format("MULU %s, %s, %s", rd, rs, rt);
11556 }
11557
11558
11559 /*
11560  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11561  *
11562  *   3         2         1
11563  *  10987654321098765432109876543210
11564  *  001000               00010001101
11565  *     rt -----
11566  *          rs -----
11567  *               rd -----
11568  */
11569 std::string NMD::NEG_D(uint64 instruction)
11570 {
11571     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11572     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11573
11574     std::string ft = FPR(copy(ft_value));
11575     std::string fs = FPR(copy(fs_value));
11576
11577     return img::format("NEG.D %s, %s", ft, fs);
11578 }
11579
11580
11581 /*
11582  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11583  *
11584  *   3         2         1
11585  *  10987654321098765432109876543210
11586  *  001000               00010001101
11587  *     rt -----
11588  *          rs -----
11589  *               rd -----
11590  */
11591 std::string NMD::NEG_S(uint64 instruction)
11592 {
11593     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11594     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11595
11596     std::string ft = FPR(copy(ft_value));
11597     std::string fs = FPR(copy(fs_value));
11598
11599     return img::format("NEG.S %s, %s", ft, fs);
11600 }
11601
11602
11603 /*
11604  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11605  *
11606  *   3         2         1
11607  *  10987654321098765432109876543210
11608  *  001000               00010001101
11609  *     rt -----
11610  *          rs -----
11611  *               rd -----
11612  */
11613 std::string NMD::NOP_16_(uint64 instruction)
11614 {
11615     (void)instruction;
11616
11617     return "NOP ";
11618 }
11619
11620
11621 /*
11622  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11623  *
11624  *   3         2         1
11625  *  10987654321098765432109876543210
11626  *  001000               00010001101
11627  *     rt -----
11628  *          rs -----
11629  *               rd -----
11630  */
11631 std::string NMD::NOP_32_(uint64 instruction)
11632 {
11633     (void)instruction;
11634
11635     return "NOP ";
11636 }
11637
11638
11639 /*
11640  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11641  *
11642  *   3         2         1
11643  *  10987654321098765432109876543210
11644  *  001000               00010001101
11645  *     rt -----
11646  *          rs -----
11647  *               rd -----
11648  */
11649 std::string NMD::NOR(uint64 instruction)
11650 {
11651     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11652     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11653     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11654
11655     std::string rd = GPR(copy(rd_value));
11656     std::string rs = GPR(copy(rs_value));
11657     std::string rt = GPR(copy(rt_value));
11658
11659     return img::format("NOR %s, %s, %s", rd, rs, rt);
11660 }
11661
11662
11663 /*
11664  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11665  *
11666  *   3         2         1
11667  *  10987654321098765432109876543210
11668  *  001000               00010001101
11669  *     rt -----
11670  *          rs -----
11671  *               rd -----
11672  */
11673 std::string NMD::NOT_16_(uint64 instruction)
11674 {
11675     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11676     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11677
11678     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
11679     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
11680
11681     return img::format("NOT %s, %s", rt3, rs3);
11682 }
11683
11684
11685 /*
11686  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11687  *
11688  *   3         2         1
11689  *  10987654321098765432109876543210
11690  *  001000               00010001101
11691  *     rt -----
11692  *          rs -----
11693  *               rd -----
11694  */
11695 std::string NMD::OR_16_(uint64 instruction)
11696 {
11697     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11698     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11699
11700     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
11701     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
11702
11703     return img::format("OR %s, %s", rs3, rt3);
11704 }
11705
11706
11707 /*
11708  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11709  *
11710  *   3         2         1
11711  *  10987654321098765432109876543210
11712  *  001000               00010001101
11713  *     rt -----
11714  *          rs -----
11715  *               rd -----
11716  */
11717 std::string NMD::OR_32_(uint64 instruction)
11718 {
11719     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11720     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11721     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11722
11723     std::string rd = GPR(copy(rd_value));
11724     std::string rs = GPR(copy(rs_value));
11725     std::string rt = GPR(copy(rt_value));
11726
11727     return img::format("OR %s, %s, %s", rd, rs, rt);
11728 }
11729
11730
11731 /*
11732  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11733  *
11734  *   3         2         1
11735  *  10987654321098765432109876543210
11736  *  001000               00010001101
11737  *     rt -----
11738  *          rs -----
11739  *               rd -----
11740  */
11741 std::string NMD::ORI(uint64 instruction)
11742 {
11743     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11744     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11745     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
11746
11747     std::string rt = GPR(copy(rt_value));
11748     std::string rs = GPR(copy(rs_value));
11749     std::string u = IMMEDIATE(copy(u_value));
11750
11751     return img::format("ORI %s, %s, %s", rt, rs, u);
11752 }
11753
11754
11755 /*
11756  * [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
11757  *         source register and left halfword from another source register
11758  *
11759  *   3         2         1
11760  *  10987654321098765432109876543210
11761  *  001000               00010001101
11762  *     rt -----
11763  *          rs -----
11764  *               rd -----
11765  */
11766 std::string NMD::PACKRL_PH(uint64 instruction)
11767 {
11768     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11769     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11770     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11771
11772     std::string rd = GPR(copy(rd_value));
11773     std::string rs = GPR(copy(rs_value));
11774     std::string rt = GPR(copy(rt_value));
11775
11776     return img::format("PACKRL.PH %s, %s, %s", rd, rs, rt);
11777 }
11778
11779
11780 /*
11781  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11782  *
11783  *   3         2         1
11784  *  10987654321098765432109876543210
11785  *  001000               00010001101
11786  *     rt -----
11787  *          rs -----
11788  *               rd -----
11789  */
11790 std::string NMD::PAUSE(uint64 instruction)
11791 {
11792     (void)instruction;
11793
11794     return "PAUSE ";
11795 }
11796
11797
11798 /*
11799  * [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
11800  *         code bits
11801  *
11802  *   3         2         1
11803  *  10987654321098765432109876543210
11804  *  001000               00010001101
11805  *     rt -----
11806  *          rs -----
11807  *               rd -----
11808  */
11809 std::string NMD::PICK_PH(uint64 instruction)
11810 {
11811     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11812     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11813     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11814
11815     std::string rd = GPR(copy(rd_value));
11816     std::string rs = GPR(copy(rs_value));
11817     std::string rt = GPR(copy(rt_value));
11818
11819     return img::format("PICK.PH %s, %s, %s", rd, rs, rt);
11820 }
11821
11822
11823 /*
11824  * [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
11825  *         code bits
11826  *
11827  *   3         2         1
11828  *  10987654321098765432109876543210
11829  *  001000               00010001101
11830  *     rt -----
11831  *          rs -----
11832  *               rd -----
11833  */
11834 std::string NMD::PICK_QB(uint64 instruction)
11835 {
11836     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11837     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11838     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11839
11840     std::string rd = GPR(copy(rd_value));
11841     std::string rs = GPR(copy(rs_value));
11842     std::string rt = GPR(copy(rt_value));
11843
11844     return img::format("PICK.QB %s, %s, %s", rd, rs, rt);
11845 }
11846
11847
11848 /*
11849  * [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
11850  *         of a paired halfword
11851  *
11852  *   3         2         1
11853  *  10987654321098765432109876543210
11854  *  001000               00010001101
11855  *     rt -----
11856  *          rs -----
11857  *               rd -----
11858  */
11859 std::string NMD::PRECEQ_W_PHL(uint64 instruction)
11860 {
11861     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11862     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11863
11864     std::string rt = GPR(copy(rt_value));
11865     std::string rs = GPR(copy(rs_value));
11866
11867     return img::format("PRECEQ.W.PHL %s, %s", rt, rs);
11868 }
11869
11870
11871 /*
11872  * [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
11873  *         of a paired halfword
11874  *
11875  *   3         2         1
11876  *  10987654321098765432109876543210
11877  *  001000               00010001101
11878  *     rt -----
11879  *          rs -----
11880  *               rd -----
11881  */
11882 std::string NMD::PRECEQ_W_PHR(uint64 instruction)
11883 {
11884     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11885     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11886
11887     std::string rt = GPR(copy(rt_value));
11888     std::string rs = GPR(copy(rs_value));
11889
11890     return img::format("PRECEQ.W.PHR %s, %s", rt, rs);
11891 }
11892
11893
11894 /*
11895  * [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
11896  *         left-alternate elements of a quad byte vector
11897  *
11898  *   3         2         1
11899  *  10987654321098765432109876543210
11900  *  001000               00010001101
11901  *     rt -----
11902  *          rs -----
11903  *               rd -----
11904  */
11905 std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)
11906 {
11907     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11908     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11909
11910     std::string rt = GPR(copy(rt_value));
11911     std::string rs = GPR(copy(rs_value));
11912
11913     return img::format("PRECEQU.PH.QBLA %s, %s", rt, rs);
11914 }
11915
11916
11917 /*
11918  * [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
11919  *         elements of a quad byte vector
11920  *
11921  *   3         2         1
11922  *  10987654321098765432109876543210
11923  *  001000               00010001101
11924  *     rt -----
11925  *          rs -----
11926  *               rd -----
11927  */
11928 std::string NMD::PRECEQU_PH_QBL(uint64 instruction)
11929 {
11930     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11931     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11932
11933     std::string rt = GPR(copy(rt_value));
11934     std::string rs = GPR(copy(rs_value));
11935
11936     return img::format("PRECEQU.PH.QBL %s, %s", rt, rs);
11937 }
11938
11939
11940 /*
11941  * [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
11942  *         right-alternate elements of a quad byte vector
11943  *
11944  *   3         2         1
11945  *  10987654321098765432109876543210
11946  *  001000               00010001101
11947  *     rt -----
11948  *          rs -----
11949  *               rd -----
11950  */
11951 std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)
11952 {
11953     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11954     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11955
11956     std::string rt = GPR(copy(rt_value));
11957     std::string rs = GPR(copy(rs_value));
11958
11959     return img::format("PRECEQU.PH.QBRA %s, %s", rt, rs);
11960 }
11961
11962
11963 /*
11964  * [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
11965  *         elements of a quad byte vector
11966  *
11967  *   3         2         1
11968  *  10987654321098765432109876543210
11969  *  001000               00010001101
11970  *     rt -----
11971  *          rs -----
11972  *               rd -----
11973  */
11974 std::string NMD::PRECEQU_PH_QBR(uint64 instruction)
11975 {
11976     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11977     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11978
11979     std::string rt = GPR(copy(rt_value));
11980     std::string rs = GPR(copy(rs_value));
11981
11982     return img::format("PRECEQU.PH.QBR %s, %s", rt, rs);
11983 }
11984
11985
11986 /*
11987  * [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
11988  *         left-alternate elements of a quad byte vector to four unsigned
11989  *         halfwords
11990  *
11991  *   3         2         1
11992  *  10987654321098765432109876543210
11993  *  001000               00010001101
11994  *     rt -----
11995  *          rs -----
11996  *               rd -----
11997  */
11998 std::string NMD::PRECEU_PH_QBLA(uint64 instruction)
11999 {
12000     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12001     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12002
12003     std::string rt = GPR(copy(rt_value));
12004     std::string rs = GPR(copy(rs_value));
12005
12006     return img::format("PRECEU.PH.QBLA %s, %s", rt, rs);
12007 }
12008
12009
12010 /*
12011  * [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
12012  *         elements of a quad byte vector to form unsigned halfwords
12013  *
12014  *   3         2         1
12015  *  10987654321098765432109876543210
12016  *  001000               00010001101
12017  *     rt -----
12018  *          rs -----
12019  *               rd -----
12020  */
12021 std::string NMD::PRECEU_PH_QBL(uint64 instruction)
12022 {
12023     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12024     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12025
12026     std::string rt = GPR(copy(rt_value));
12027     std::string rs = GPR(copy(rs_value));
12028
12029     return img::format("PRECEU.PH.QBL %s, %s", rt, rs);
12030 }
12031
12032
12033 /*
12034  * [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
12035  *         right-alternate elements of a quad byte vector to form four
12036  *         unsigned halfwords
12037  *
12038  *   3         2         1
12039  *  10987654321098765432109876543210
12040  *  001000               00010001101
12041  *     rt -----
12042  *          rs -----
12043  *               rd -----
12044  */
12045 std::string NMD::PRECEU_PH_QBRA(uint64 instruction)
12046 {
12047     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12048     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12049
12050     std::string rt = GPR(copy(rt_value));
12051     std::string rs = GPR(copy(rs_value));
12052
12053     return img::format("PRECEU.PH.QBRA %s, %s", rt, rs);
12054 }
12055
12056
12057 /*
12058  * [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
12059  *         elements of a quad byte vector to form unsigned halfwords
12060  *
12061  *   3         2         1
12062  *  10987654321098765432109876543210
12063  *  001000               00010001101
12064  *     rt -----
12065  *          rs -----
12066  *               rd -----
12067  */
12068 std::string NMD::PRECEU_PH_QBR(uint64 instruction)
12069 {
12070     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12071     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12072
12073     std::string rt = GPR(copy(rt_value));
12074     std::string rs = GPR(copy(rs_value));
12075
12076     return img::format("PRECEU.PH.QBR %s, %s", rt, rs);
12077 }
12078
12079
12080 /*
12081  * [DSP] PRECR.QB.PH rd, rs, rt - Reduce the precision of four integer
12082  *   halfwords to four bytes
12083  *
12084  *   3         2         1
12085  *  10987654321098765432109876543210
12086  *  001000               x0001101101
12087  *     rt -----
12088  *          rs -----
12089  *               rd -----
12090  */
12091 std::string NMD::PRECR_QB_PH(uint64 instruction)
12092 {
12093     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12094     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12095     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12096
12097     std::string rd = GPR(copy(rd_value));
12098     std::string rs = GPR(copy(rs_value));
12099     std::string rt = GPR(copy(rt_value));
12100
12101     return img::format("PRECR.QB.PH %s, %s, %s", rd, rs, rt);
12102 }
12103
12104
12105 /*
12106  * [DSP] PRECR_SRA.PH.W rt, rs, sa - Reduce the precision of two integer
12107  *   words to halfwords after a right shift
12108  *
12109  *   3         2         1
12110  *  10987654321098765432109876543210
12111  *  001000               x1110000101
12112  *     rt -----
12113  *          rs -----
12114  *               rd -----
12115  */
12116 std::string NMD::PRECR_SRA_PH_W(uint64 instruction)
12117 {
12118     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12119     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12120     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12121
12122     std::string rt = GPR(copy(rt_value));
12123     std::string rs = GPR(copy(rs_value));
12124     std::string sa = IMMEDIATE(copy(sa_value));
12125
12126     return img::format("PRECR_SRA.PH.W %s, %s, %s", rt, rs, sa);
12127 }
12128
12129
12130 /*
12131  * [DSP] PRECR_SRA_R.PH.W rt, rs, sa - Reduce the precision of two integer
12132  *   words to halfwords after a right shift with rounding
12133  *
12134  *   3         2         1
12135  *  10987654321098765432109876543210
12136  *  001000               x1110000101
12137  *     rt -----
12138  *          rs -----
12139  *               rd -----
12140  */
12141 std::string NMD::PRECR_SRA_R_PH_W(uint64 instruction)
12142 {
12143     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12144     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12145     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12146
12147     std::string rt = GPR(copy(rt_value));
12148     std::string rs = GPR(copy(rs_value));
12149     std::string sa = IMMEDIATE(copy(sa_value));
12150
12151     return img::format("PRECR_SRA_R.PH.W %s, %s, %s", rt, rs, sa);
12152 }
12153
12154
12155 /*
12156  * [DSP] PRECRQ.PH.W rd, rs, rt - Reduce the precision of fractional
12157  *   words to fractional halfwords
12158  *
12159  *   3         2         1
12160  *  10987654321098765432109876543210
12161  *  001000               x1110000101
12162  *     rt -----
12163  *          rs -----
12164  *               rd -----
12165  */
12166 std::string NMD::PRECRQ_PH_W(uint64 instruction)
12167 {
12168     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12169     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12170     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12171
12172     std::string rd = GPR(copy(rd_value));
12173     std::string rs = GPR(copy(rs_value));
12174     std::string rt = GPR(copy(rt_value));
12175
12176     return img::format("PRECRQ.PH.W %s, %s, %s", rd, rs, rt);
12177 }
12178
12179
12180 /*
12181  * [DSP] PRECRQ.QB.PH rd, rs, rt - Reduce the precision of four fractional
12182  *   halfwords to four bytes
12183  *
12184  *   3         2         1
12185  *  10987654321098765432109876543210
12186  *  001000               x0010101101
12187  *     rt -----
12188  *          rs -----
12189  *               rd -----
12190  */
12191 std::string NMD::PRECRQ_QB_PH(uint64 instruction)
12192 {
12193     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12194     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12195     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12196
12197     std::string rd = GPR(copy(rd_value));
12198     std::string rs = GPR(copy(rs_value));
12199     std::string rt = GPR(copy(rt_value));
12200
12201     return img::format("PRECRQ.QB.PH %s, %s, %s", rd, rs, rt);
12202 }
12203
12204
12205 /*
12206  * [DSP] PRECRQ_RS.PH.W rd, rs, rt - Reduce the precision of fractional
12207  *   words to halfwords with rounding and saturation
12208  *
12209  *   3         2         1
12210  *  10987654321098765432109876543210
12211  *  001000               x1110000101
12212  *     rt -----
12213  *          rs -----
12214  *               rd -----
12215  */
12216 std::string NMD::PRECRQ_RS_PH_W(uint64 instruction)
12217 {
12218     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12219     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12220     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12221
12222     std::string rd = GPR(copy(rd_value));
12223     std::string rs = GPR(copy(rs_value));
12224     std::string rt = GPR(copy(rt_value));
12225
12226     return img::format("PRECRQ_RS.PH.W %s, %s, %s", rd, rs, rt);
12227 }
12228
12229
12230 /*
12231  * [DSP] PRECRQU_S.QB.PH rd, rs, rt - Reduce the precision of fractional
12232  *   halfwords to unsigned bytes with saturation
12233  *
12234  *   3         2         1
12235  *  10987654321098765432109876543210
12236  *  001000               x1110000101
12237  *     rt -----
12238  *          rs -----
12239  *               rd -----
12240  */
12241 std::string NMD::PRECRQU_S_QB_PH(uint64 instruction)
12242 {
12243     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12244     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12245     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12246
12247     std::string rd = GPR(copy(rd_value));
12248     std::string rs = GPR(copy(rs_value));
12249     std::string rt = GPR(copy(rt_value));
12250
12251     return img::format("PRECRQU_S.QB.PH %s, %s, %s", rd, rs, rt);
12252 }
12253
12254
12255 /*
12256  *
12257  *
12258  *   3         2         1
12259  *  10987654321098765432109876543210
12260  *  001000               x1110000101
12261  *     rt -----
12262  *          rs -----
12263  *               rd -----
12264  */
12265 std::string NMD::PREF_S9_(uint64 instruction)
12266 {
12267     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12268     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12269     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12270
12271     std::string hint = IMMEDIATE(copy(hint_value));
12272     std::string s = IMMEDIATE(copy(s_value));
12273     std::string rs = GPR(copy(rs_value));
12274
12275     return img::format("PREF %s, %s(%s)", hint, s, rs);
12276 }
12277
12278
12279 /*
12280  *
12281  *
12282  *   3         2         1
12283  *  10987654321098765432109876543210
12284  *  001000               x1110000101
12285  *     rt -----
12286  *          rs -----
12287  *               rd -----
12288  */
12289 std::string NMD::PREF_U12_(uint64 instruction)
12290 {
12291     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12292     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12293     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12294
12295     std::string hint = IMMEDIATE(copy(hint_value));
12296     std::string u = IMMEDIATE(copy(u_value));
12297     std::string rs = GPR(copy(rs_value));
12298
12299     return img::format("PREF %s, %s(%s)", hint, u, rs);
12300 }
12301
12302
12303 /*
12304  *
12305  *
12306  *   3         2         1
12307  *  10987654321098765432109876543210
12308  *  001000               x1110000101
12309  *     rt -----
12310  *          rs -----
12311  *               rd -----
12312  */
12313 std::string NMD::PREFE(uint64 instruction)
12314 {
12315     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12316     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12317     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12318
12319     std::string hint = IMMEDIATE(copy(hint_value));
12320     std::string s = IMMEDIATE(copy(s_value));
12321     std::string rs = GPR(copy(rs_value));
12322
12323     return img::format("PREFE %s, %s(%s)", hint, s, rs);
12324 }
12325
12326
12327 /*
12328  * [DSP] PREPEND rt, rs, sa - Right shift and prepend bits to the MSB
12329  *
12330  *   3         2         1
12331  *  10987654321098765432109876543210
12332  *  001000               x1110000101
12333  *     rt -----
12334  *          rs -----
12335  *               rd -----
12336  */
12337 std::string NMD::PREPEND(uint64 instruction)
12338 {
12339     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12340     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12341     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12342
12343     std::string rt = GPR(copy(rt_value));
12344     std::string rs = GPR(copy(rs_value));
12345     std::string sa = IMMEDIATE(copy(sa_value));
12346
12347     return img::format("PREPEND %s, %s, %s", rt, rs, sa);
12348 }
12349
12350
12351 /*
12352  * [DSP] RADDU.W.QB rt, rs - Unsigned reduction add of vector quad bytes
12353  *
12354  *   3         2         1
12355  *  10987654321098765432109876543210
12356  *  001000          1111000100111111
12357  *     rt -----
12358  *          rs -----
12359  */
12360 std::string NMD::RADDU_W_QB(uint64 instruction)
12361 {
12362     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12363     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12364
12365     std::string rt = GPR(copy(rt_value));
12366     std::string rs = GPR(copy(rs_value));
12367
12368     return img::format("RADDU.W.QB %s, %s", rt, rs);
12369 }
12370
12371
12372 /*
12373  * [DSP] RDDSP rt, mask - Read DSPControl register fields to a GPR
12374  *
12375  *   3         2         1
12376  *  10987654321098765432109876543210
12377  *  001000            00011001111111
12378  *     rt -----
12379  *        mask -------
12380  */
12381 std::string NMD::RDDSP(uint64 instruction)
12382 {
12383     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12384     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
12385
12386     std::string rt = GPR(copy(rt_value));
12387     std::string mask = IMMEDIATE(copy(mask_value));
12388
12389     return img::format("RDDSP %s, %s", rt, mask);
12390 }
12391
12392
12393 /*
12394  *
12395  *
12396  *   3         2         1
12397  *  10987654321098765432109876543210
12398  *  001000               x1110000101
12399  *     rt -----
12400  *          rs -----
12401  *               rd -----
12402  */
12403 std::string NMD::RDHWR(uint64 instruction)
12404 {
12405     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12406     uint64 hs_value = extract_hs_20_19_18_17_16(instruction);
12407     uint64 sel_value = extract_sel_13_12_11(instruction);
12408
12409     std::string rt = GPR(copy(rt_value));
12410     std::string hs = CPR(copy(hs_value));
12411     std::string sel = IMMEDIATE(copy(sel_value));
12412
12413     return img::format("RDHWR %s, %s, %s", rt, hs, sel);
12414 }
12415
12416
12417 /*
12418  *
12419  *
12420  *   3         2         1
12421  *  10987654321098765432109876543210
12422  *  001000               x1110000101
12423  *     rt -----
12424  *          rs -----
12425  *               rd -----
12426  */
12427 std::string NMD::RDPGPR(uint64 instruction)
12428 {
12429     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12430     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12431
12432     std::string rt = GPR(copy(rt_value));
12433     std::string rs = GPR(copy(rs_value));
12434
12435     return img::format("RDPGPR %s, %s", rt, rs);
12436 }
12437
12438
12439 /*
12440  *
12441  *
12442  *   3         2         1
12443  *  10987654321098765432109876543210
12444  *  001000               x1110000101
12445  *     rt -----
12446  *          rs -----
12447  *               rd -----
12448  */
12449 std::string NMD::RECIP_D(uint64 instruction)
12450 {
12451     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12452     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12453
12454     std::string ft = FPR(copy(ft_value));
12455     std::string fs = FPR(copy(fs_value));
12456
12457     return img::format("RECIP.D %s, %s", ft, fs);
12458 }
12459
12460
12461 /*
12462  *
12463  *
12464  *   3         2         1
12465  *  10987654321098765432109876543210
12466  *  001000               x1110000101
12467  *     rt -----
12468  *          rs -----
12469  *               rd -----
12470  */
12471 std::string NMD::RECIP_S(uint64 instruction)
12472 {
12473     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12474     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12475
12476     std::string ft = FPR(copy(ft_value));
12477     std::string fs = FPR(copy(fs_value));
12478
12479     return img::format("RECIP.S %s, %s", ft, fs);
12480 }
12481
12482
12483 /*
12484  * [DSP] REPL.PH rd, s - Replicate immediate integer into all vector element
12485  *   positions
12486  *
12487  *   3         2         1
12488  *  10987654321098765432109876543210
12489  *  001000               x0000111101
12490  *     rt -----
12491  *           s ----------
12492  */
12493 std::string NMD::REPL_PH(uint64 instruction)
12494 {
12495     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12496     int64 s_value = extract_s__se9_20_19_18_17_16_15_14_13_12_11(instruction);
12497
12498     std::string rt = GPR(copy(rt_value));
12499     std::string s = IMMEDIATE(copy(s_value));
12500
12501     return img::format("REPL.PH %s, %s", rt, s);
12502 }
12503
12504
12505 /*
12506  * [DSP] REPL.QB rd, u - Replicate immediate integer into all vector element
12507  *   positions
12508  *
12509  *   3         2         1
12510  *  10987654321098765432109876543210
12511  *  001000             x010111111111
12512  *     rt -----
12513  *           u --------
12514  */
12515 std::string NMD::REPL_QB(uint64 instruction)
12516 {
12517     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12518     uint64 u_value = extract_u_20_19_18_17_16_15_14_13(instruction);
12519
12520     std::string rt = GPR(copy(rt_value));
12521     std::string u = IMMEDIATE(copy(u_value));
12522
12523     return img::format("REPL.QB %s, %s", rt, u);
12524 }
12525
12526
12527 /*
12528  * [DSP] REPLV.PH rt, rs - Replicate a halfword into all vector element
12529  *   positions
12530  *
12531  *   3         2         1
12532  *  10987654321098765432109876543210
12533  *  001000          0000001100111111
12534  *     rt -----
12535  *          rs -----
12536  */
12537 std::string NMD::REPLV_PH(uint64 instruction)
12538 {
12539     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12540     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12541
12542     std::string rt = GPR(copy(rt_value));
12543     std::string rs = GPR(copy(rs_value));
12544
12545     return img::format("REPLV.PH %s, %s", rt, rs);
12546 }
12547
12548
12549 /*
12550  * [DSP] REPLV.QB rt, rs - Replicate byte into all vector element positions
12551  *
12552  *   3         2         1
12553  *  10987654321098765432109876543210
12554  *  001000          0001001100111111
12555  *     rt -----
12556  *          rs -----
12557  */
12558 std::string NMD::REPLV_QB(uint64 instruction)
12559 {
12560     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12561     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12562
12563     std::string rt = GPR(copy(rt_value));
12564     std::string rs = GPR(copy(rs_value));
12565
12566     return img::format("REPLV.QB %s, %s", rt, rs);
12567 }
12568
12569
12570 /*
12571  *
12572  *
12573  *   3         2         1
12574  *  10987654321098765432109876543210
12575  *  001000               x1110000101
12576  *     rt -----
12577  *          rs -----
12578  *               rd -----
12579  */
12580 std::string NMD::RESTORE_32_(uint64 instruction)
12581 {
12582     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12583     uint64 count_value = extract_count_19_18_17_16(instruction);
12584     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12585     uint64 gp_value = extract_gp_2(instruction);
12586
12587     std::string u = IMMEDIATE(copy(u_value));
12588     return img::format("RESTORE %s%s", u,
12589                save_restore_list(rt_value, count_value, gp_value));
12590 }
12591
12592
12593 /*
12594  *
12595  *
12596  *   3         2         1
12597  *  10987654321098765432109876543210
12598  *  001000               x1110000101
12599  *     rt -----
12600  *          rs -----
12601  *               rd -----
12602  */
12603 std::string NMD::RESTORE_JRC_16_(uint64 instruction)
12604 {
12605     uint64 rt1_value = extract_rtl_11(instruction);
12606     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12607     uint64 count_value = extract_count_3_2_1_0(instruction);
12608
12609     std::string u = IMMEDIATE(copy(u_value));
12610     return img::format("RESTORE.JRC %s%s", u,
12611         save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));
12612 }
12613
12614
12615 /*
12616  *
12617  *
12618  *   3         2         1
12619  *  10987654321098765432109876543210
12620  *  001000               x1110000101
12621  *     rt -----
12622  *          rs -----
12623  *               rd -----
12624  */
12625 std::string NMD::RESTORE_JRC_32_(uint64 instruction)
12626 {
12627     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12628     uint64 count_value = extract_count_19_18_17_16(instruction);
12629     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12630     uint64 gp_value = extract_gp_2(instruction);
12631
12632     std::string u = IMMEDIATE(copy(u_value));
12633     return img::format("RESTORE.JRC %s%s", u,
12634                save_restore_list(rt_value, count_value, gp_value));
12635 }
12636
12637
12638 /*
12639  *
12640  *
12641  *   3         2         1
12642  *  10987654321098765432109876543210
12643  *  001000               x1110000101
12644  *     rt -----
12645  *          rs -----
12646  *               rd -----
12647  */
12648 std::string NMD::RESTOREF(uint64 instruction)
12649 {
12650     uint64 count_value = extract_count_19_18_17_16(instruction);
12651     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12652
12653     std::string u = IMMEDIATE(copy(u_value));
12654     std::string count = IMMEDIATE(copy(count_value));
12655
12656     return img::format("RESTOREF %s, %s", u, count);
12657 }
12658
12659
12660 /*
12661  *
12662  *
12663  *   3         2         1
12664  *  10987654321098765432109876543210
12665  *  001000               x1110000101
12666  *     rt -----
12667  *          rs -----
12668  *               rd -----
12669  */
12670 std::string NMD::RINT_D(uint64 instruction)
12671 {
12672     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12673     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12674
12675     std::string ft = FPR(copy(ft_value));
12676     std::string fs = FPR(copy(fs_value));
12677
12678     return img::format("RINT.D %s, %s", ft, fs);
12679 }
12680
12681
12682 /*
12683  *
12684  *
12685  *   3         2         1
12686  *  10987654321098765432109876543210
12687  *  001000               x1110000101
12688  *     rt -----
12689  *          rs -----
12690  *               rd -----
12691  */
12692 std::string NMD::RINT_S(uint64 instruction)
12693 {
12694     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12695     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12696
12697     std::string ft = FPR(copy(ft_value));
12698     std::string fs = FPR(copy(fs_value));
12699
12700     return img::format("RINT.S %s, %s", ft, fs);
12701 }
12702
12703
12704 /*
12705  *
12706  *
12707  *   3         2         1
12708  *  10987654321098765432109876543210
12709  *  001000               x1110000101
12710  *     rt -----
12711  *          rs -----
12712  *               rd -----
12713  */
12714 std::string NMD::ROTR(uint64 instruction)
12715 {
12716     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12717     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12718     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12719
12720     std::string rt = GPR(copy(rt_value));
12721     std::string rs = GPR(copy(rs_value));
12722     std::string shift = IMMEDIATE(copy(shift_value));
12723
12724     return img::format("ROTR %s, %s, %s", rt, rs, shift);
12725 }
12726
12727
12728 /*
12729  *
12730  *
12731  *   3         2         1
12732  *  10987654321098765432109876543210
12733  *  001000               x1110000101
12734  *     rt -----
12735  *          rs -----
12736  *               rd -----
12737  */
12738 std::string NMD::ROTRV(uint64 instruction)
12739 {
12740     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12741     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12742     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12743
12744     std::string rd = GPR(copy(rd_value));
12745     std::string rs = GPR(copy(rs_value));
12746     std::string rt = GPR(copy(rt_value));
12747
12748     return img::format("ROTRV %s, %s, %s", rd, rs, rt);
12749 }
12750
12751
12752 /*
12753  *
12754  *
12755  *   3         2         1
12756  *  10987654321098765432109876543210
12757  *  001000               x1110000101
12758  *     rt -----
12759  *          rs -----
12760  *               rd -----
12761  */
12762 std::string NMD::ROTX(uint64 instruction)
12763 {
12764     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12765     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12766     uint64 shiftx_value = extract_shiftx_10_9_8_7__s1(instruction);
12767     uint64 stripe_value = extract_stripe_6(instruction);
12768     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12769
12770     std::string rt = GPR(copy(rt_value));
12771     std::string rs = GPR(copy(rs_value));
12772     std::string shift = IMMEDIATE(copy(shift_value));
12773     std::string shiftx = IMMEDIATE(copy(shiftx_value));
12774     std::string stripe = IMMEDIATE(copy(stripe_value));
12775
12776     return img::format("ROTX %s, %s, %s, %s, %s",
12777                        rt, rs, shift, shiftx, stripe);
12778 }
12779
12780
12781 /*
12782  *
12783  *
12784  *   3         2         1
12785  *  10987654321098765432109876543210
12786  *  001000               x1110000101
12787  *     rt -----
12788  *          rs -----
12789  *               rd -----
12790  */
12791 std::string NMD::ROUND_L_D(uint64 instruction)
12792 {
12793     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12794     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12795
12796     std::string ft = FPR(copy(ft_value));
12797     std::string fs = FPR(copy(fs_value));
12798
12799     return img::format("ROUND.L.D %s, %s", ft, fs);
12800 }
12801
12802
12803 /*
12804  *
12805  *
12806  *   3         2         1
12807  *  10987654321098765432109876543210
12808  *  001000               x1110000101
12809  *     rt -----
12810  *          rs -----
12811  *               rd -----
12812  */
12813 std::string NMD::ROUND_L_S(uint64 instruction)
12814 {
12815     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12816     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12817
12818     std::string ft = FPR(copy(ft_value));
12819     std::string fs = FPR(copy(fs_value));
12820
12821     return img::format("ROUND.L.S %s, %s", ft, fs);
12822 }
12823
12824
12825 /*
12826  *
12827  *
12828  *   3         2         1
12829  *  10987654321098765432109876543210
12830  *  001000               x1110000101
12831  *     rt -----
12832  *          rs -----
12833  *               rd -----
12834  */
12835 std::string NMD::ROUND_W_D(uint64 instruction)
12836 {
12837     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12838     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12839
12840     std::string ft = FPR(copy(ft_value));
12841     std::string fs = FPR(copy(fs_value));
12842
12843     return img::format("ROUND.W.D %s, %s", ft, fs);
12844 }
12845
12846
12847 /*
12848  *
12849  *
12850  *   3         2         1
12851  *  10987654321098765432109876543210
12852  *  001000               x1110000101
12853  *     rt -----
12854  *          rs -----
12855  *               rd -----
12856  */
12857 std::string NMD::ROUND_W_S(uint64 instruction)
12858 {
12859     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12860     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12861
12862     std::string ft = FPR(copy(ft_value));
12863     std::string fs = FPR(copy(fs_value));
12864
12865     return img::format("ROUND.W.S %s, %s", ft, fs);
12866 }
12867
12868
12869 /*
12870  *
12871  *
12872  *   3         2         1
12873  *  10987654321098765432109876543210
12874  *  001000               x1110000101
12875  *     rt -----
12876  *          rs -----
12877  *               rd -----
12878  */
12879 std::string NMD::RSQRT_D(uint64 instruction)
12880 {
12881     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12882     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12883
12884     std::string ft = FPR(copy(ft_value));
12885     std::string fs = FPR(copy(fs_value));
12886
12887     return img::format("RSQRT.D %s, %s", ft, fs);
12888 }
12889
12890
12891 /*
12892  *
12893  *
12894  *   3         2         1
12895  *  10987654321098765432109876543210
12896  *  001000               x1110000101
12897  *     rt -----
12898  *          rs -----
12899  *               rd -----
12900  */
12901 std::string NMD::RSQRT_S(uint64 instruction)
12902 {
12903     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12904     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12905
12906     std::string ft = FPR(copy(ft_value));
12907     std::string fs = FPR(copy(fs_value));
12908
12909     return img::format("RSQRT.S %s, %s", ft, fs);
12910 }
12911
12912
12913 /*
12914  *
12915  *
12916  *   3         2         1
12917  *  10987654321098765432109876543210
12918  *  001000               01001001101
12919  *     rt -----
12920  *          rs -----
12921  *               rd -----
12922  */
12923 std::string NMD::SAVE_16_(uint64 instruction)
12924 {
12925     uint64 rt1_value = extract_rtl_11(instruction);
12926     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12927     uint64 count_value = extract_count_3_2_1_0(instruction);
12928
12929     std::string u = IMMEDIATE(copy(u_value));
12930     return img::format("SAVE %s%s", u,
12931         save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));
12932 }
12933
12934
12935 /*
12936  *
12937  *
12938  *   3         2         1
12939  *  10987654321098765432109876543210
12940  *  001000               01001001101
12941  *     rt -----
12942  *          rs -----
12943  *               rd -----
12944  */
12945 std::string NMD::SAVE_32_(uint64 instruction)
12946 {
12947     uint64 count_value = extract_count_19_18_17_16(instruction);
12948     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12949     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12950     uint64 gp_value = extract_gp_2(instruction);
12951
12952     std::string u = IMMEDIATE(copy(u_value));
12953     return img::format("SAVE %s%s", u,
12954                save_restore_list(rt_value, count_value, gp_value));
12955 }
12956
12957
12958 /*
12959  *
12960  *
12961  *   3         2         1
12962  *  10987654321098765432109876543210
12963  *  001000               01001001101
12964  *     rt -----
12965  *          rs -----
12966  *               rd -----
12967  */
12968 std::string NMD::SAVEF(uint64 instruction)
12969 {
12970     uint64 count_value = extract_count_19_18_17_16(instruction);
12971     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12972
12973     std::string u = IMMEDIATE(copy(u_value));
12974     std::string count = IMMEDIATE(copy(count_value));
12975
12976     return img::format("SAVEF %s, %s", u, count);
12977 }
12978
12979
12980 /*
12981  *
12982  *
12983  *   3         2         1
12984  *  10987654321098765432109876543210
12985  *  001000               01001001101
12986  *     rt -----
12987  *          rs -----
12988  *               rd -----
12989  */
12990 std::string NMD::SB_16_(uint64 instruction)
12991 {
12992     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
12993     uint64 rs3_value = extract_rs3_6_5_4(instruction);
12994     uint64 u_value = extract_u_1_0(instruction);
12995
12996     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
12997     std::string u = IMMEDIATE(copy(u_value));
12998     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
12999
13000     return img::format("SB %s, %s(%s)", rtz3, u, rs3);
13001 }
13002
13003
13004 /*
13005  *
13006  *
13007  *   3         2         1
13008  *  10987654321098765432109876543210
13009  *  001000               01001001101
13010  *     rt -----
13011  *          rs -----
13012  *               rd -----
13013  */
13014 std::string NMD::SB_GP_(uint64 instruction)
13015 {
13016     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13017     uint64 u_value = extract_u_17_to_0(instruction);
13018
13019     std::string rt = GPR(copy(rt_value));
13020     std::string u = IMMEDIATE(copy(u_value));
13021
13022     return img::format("SB %s, %s($%d)", rt, u, 28);
13023 }
13024
13025
13026 /*
13027  *
13028  *
13029  *   3         2         1
13030  *  10987654321098765432109876543210
13031  *  001000               01001001101
13032  *     rt -----
13033  *          rs -----
13034  *               rd -----
13035  */
13036 std::string NMD::SB_S9_(uint64 instruction)
13037 {
13038     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13039     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13040     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13041
13042     std::string rt = GPR(copy(rt_value));
13043     std::string s = IMMEDIATE(copy(s_value));
13044     std::string rs = GPR(copy(rs_value));
13045
13046     return img::format("SB %s, %s(%s)", rt, s, rs);
13047 }
13048
13049
13050 /*
13051  *
13052  *
13053  *   3         2         1
13054  *  10987654321098765432109876543210
13055  *  001000               01001001101
13056  *     rt -----
13057  *          rs -----
13058  *               rd -----
13059  */
13060 std::string NMD::SB_U12_(uint64 instruction)
13061 {
13062     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13063     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13064     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13065
13066     std::string rt = GPR(copy(rt_value));
13067     std::string u = IMMEDIATE(copy(u_value));
13068     std::string rs = GPR(copy(rs_value));
13069
13070     return img::format("SB %s, %s(%s)", rt, u, rs);
13071 }
13072
13073
13074 /*
13075  *
13076  *
13077  *   3         2         1
13078  *  10987654321098765432109876543210
13079  *  001000               01001001101
13080  *     rt -----
13081  *          rs -----
13082  *               rd -----
13083  */
13084 std::string NMD::SBE(uint64 instruction)
13085 {
13086     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13087     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13088     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13089
13090     std::string rt = GPR(copy(rt_value));
13091     std::string s = IMMEDIATE(copy(s_value));
13092     std::string rs = GPR(copy(rs_value));
13093
13094     return img::format("SBE %s, %s(%s)", rt, s, rs);
13095 }
13096
13097
13098 /*
13099  *
13100  *
13101  *   3         2         1
13102  *  10987654321098765432109876543210
13103  *  001000               01001001101
13104  *     rt -----
13105  *          rs -----
13106  *               rd -----
13107  */
13108 std::string NMD::SBX(uint64 instruction)
13109 {
13110     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13111     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13112     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13113
13114     std::string rd = GPR(copy(rd_value));
13115     std::string rs = GPR(copy(rs_value));
13116     std::string rt = GPR(copy(rt_value));
13117
13118     return img::format("SBX %s, %s(%s)", rd, rs, rt);
13119 }
13120
13121
13122 /*
13123  *
13124  *
13125  *   3         2         1
13126  *  10987654321098765432109876543210
13127  *  001000               01001001101
13128  *     rt -----
13129  *          rs -----
13130  *               rd -----
13131  */
13132 std::string NMD::SC(uint64 instruction)
13133 {
13134     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13135     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13136     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
13137
13138     std::string rt = GPR(copy(rt_value));
13139     std::string s = IMMEDIATE(copy(s_value));
13140     std::string rs = GPR(copy(rs_value));
13141
13142     return img::format("SC %s, %s(%s)", rt, s, rs);
13143 }
13144
13145
13146 /*
13147  *
13148  *
13149  *   3         2         1
13150  *  10987654321098765432109876543210
13151  *  001000               01001001101
13152  *     rt -----
13153  *          rs -----
13154  *               rd -----
13155  */
13156 std::string NMD::SCD(uint64 instruction)
13157 {
13158     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13159     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13160     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
13161
13162     std::string rt = GPR(copy(rt_value));
13163     std::string s = IMMEDIATE(copy(s_value));
13164     std::string rs = GPR(copy(rs_value));
13165
13166     return img::format("SCD %s, %s(%s)", rt, s, rs);
13167 }
13168
13169
13170 /*
13171  *
13172  *
13173  *   3         2         1
13174  *  10987654321098765432109876543210
13175  *  001000               01001001101
13176  *     rt -----
13177  *          rs -----
13178  *               rd -----
13179  */
13180 std::string NMD::SCDP(uint64 instruction)
13181 {
13182     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13183     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13184     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13185
13186     std::string rt = GPR(copy(rt_value));
13187     std::string ru = GPR(copy(ru_value));
13188     std::string rs = GPR(copy(rs_value));
13189
13190     return img::format("SCDP %s, %s, (%s)", rt, ru, rs);
13191 }
13192
13193
13194 /*
13195  *
13196  *
13197  *   3         2         1
13198  *  10987654321098765432109876543210
13199  *  001000               01001001101
13200  *     rt -----
13201  *          rs -----
13202  *               rd -----
13203  */
13204 std::string NMD::SCE(uint64 instruction)
13205 {
13206     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13207     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13208     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
13209
13210     std::string rt = GPR(copy(rt_value));
13211     std::string s = IMMEDIATE(copy(s_value));
13212     std::string rs = GPR(copy(rs_value));
13213
13214     return img::format("SCE %s, %s(%s)", rt, s, rs);
13215 }
13216
13217
13218 /*
13219  *
13220  *
13221  *   3         2         1
13222  *  10987654321098765432109876543210
13223  *  001000               01001001101
13224  *     rt -----
13225  *          rs -----
13226  *               rd -----
13227  */
13228 std::string NMD::SCWP(uint64 instruction)
13229 {
13230     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13231     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13232     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13233
13234     std::string rt = GPR(copy(rt_value));
13235     std::string ru = GPR(copy(ru_value));
13236     std::string rs = GPR(copy(rs_value));
13237
13238     return img::format("SCWP %s, %s, (%s)", rt, ru, rs);
13239 }
13240
13241
13242 /*
13243  *
13244  *
13245  *   3         2         1
13246  *  10987654321098765432109876543210
13247  *  001000               01001001101
13248  *     rt -----
13249  *          rs -----
13250  *               rd -----
13251  */
13252 std::string NMD::SCWPE(uint64 instruction)
13253 {
13254     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13255     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13256     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13257
13258     std::string rt = GPR(copy(rt_value));
13259     std::string ru = GPR(copy(ru_value));
13260     std::string rs = GPR(copy(rs_value));
13261
13262     return img::format("SCWPE %s, %s, (%s)", rt, ru, rs);
13263 }
13264
13265
13266 /*
13267  *
13268  *
13269  *   3         2         1
13270  *  10987654321098765432109876543210
13271  *  001000               01001001101
13272  *     rt -----
13273  *          rs -----
13274  *               rd -----
13275  */
13276 std::string NMD::SD_GP_(uint64 instruction)
13277 {
13278     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13279     uint64 u_value = extract_u_20_to_3__s3(instruction);
13280
13281     std::string rt = GPR(copy(rt_value));
13282     std::string u = IMMEDIATE(copy(u_value));
13283
13284     return img::format("SD %s, %s($%d)", rt, u, 28);
13285 }
13286
13287
13288 /*
13289  *
13290  *
13291  *   3         2         1
13292  *  10987654321098765432109876543210
13293  *  001000               01001001101
13294  *     rt -----
13295  *          rs -----
13296  *               rd -----
13297  */
13298 std::string NMD::SD_S9_(uint64 instruction)
13299 {
13300     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13301     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13302     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13303
13304     std::string rt = GPR(copy(rt_value));
13305     std::string s = IMMEDIATE(copy(s_value));
13306     std::string rs = GPR(copy(rs_value));
13307
13308     return img::format("SD %s, %s(%s)", rt, s, rs);
13309 }
13310
13311
13312 /*
13313  *
13314  *
13315  *   3         2         1
13316  *  10987654321098765432109876543210
13317  *  001000               01001001101
13318  *     rt -----
13319  *          rs -----
13320  *               rd -----
13321  */
13322 std::string NMD::SD_U12_(uint64 instruction)
13323 {
13324     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13325     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13326     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13327
13328     std::string rt = GPR(copy(rt_value));
13329     std::string u = IMMEDIATE(copy(u_value));
13330     std::string rs = GPR(copy(rs_value));
13331
13332     return img::format("SD %s, %s(%s)", rt, u, rs);
13333 }
13334
13335
13336 /*
13337  *
13338  *
13339  *   3         2         1
13340  *  10987654321098765432109876543210
13341  *  001000               01001001101
13342  *     rt -----
13343  *          rs -----
13344  *               rd -----
13345  */
13346 std::string NMD::SDBBP_16_(uint64 instruction)
13347 {
13348     uint64 code_value = extract_code_2_1_0(instruction);
13349
13350     std::string code = IMMEDIATE(copy(code_value));
13351
13352     return img::format("SDBBP %s", code);
13353 }
13354
13355
13356 /*
13357  *
13358  *
13359  *   3         2         1
13360  *  10987654321098765432109876543210
13361  *  001000               01001001101
13362  *     rt -----
13363  *          rs -----
13364  *               rd -----
13365  */
13366 std::string NMD::SDBBP_32_(uint64 instruction)
13367 {
13368     uint64 code_value = extract_code_18_to_0(instruction);
13369
13370     std::string code = IMMEDIATE(copy(code_value));
13371
13372     return img::format("SDBBP %s", code);
13373 }
13374
13375
13376 /*
13377  *
13378  *
13379  *   3         2         1
13380  *  10987654321098765432109876543210
13381  *  001000               01001001101
13382  *     rt -----
13383  *          rs -----
13384  *               rd -----
13385  */
13386 std::string NMD::SDC1_GP_(uint64 instruction)
13387 {
13388     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13389     uint64 u_value = extract_u_17_to_2__s2(instruction);
13390
13391     std::string ft = FPR(copy(ft_value));
13392     std::string u = IMMEDIATE(copy(u_value));
13393
13394     return img::format("SDC1 %s, %s($%d)", ft, u, 28);
13395 }
13396
13397
13398 /*
13399  *
13400  *
13401  *   3         2         1
13402  *  10987654321098765432109876543210
13403  *  001000               01001001101
13404  *     rt -----
13405  *          rs -----
13406  *               rd -----
13407  */
13408 std::string NMD::SDC1_S9_(uint64 instruction)
13409 {
13410     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13411     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13412     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13413
13414     std::string ft = FPR(copy(ft_value));
13415     std::string s = IMMEDIATE(copy(s_value));
13416     std::string rs = GPR(copy(rs_value));
13417
13418     return img::format("SDC1 %s, %s(%s)", ft, s, rs);
13419 }
13420
13421
13422 /*
13423  *
13424  *
13425  *   3         2         1
13426  *  10987654321098765432109876543210
13427  *  001000               01001001101
13428  *     rt -----
13429  *          rs -----
13430  *               rd -----
13431  */
13432 std::string NMD::SDC1_U12_(uint64 instruction)
13433 {
13434     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13435     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13436     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13437
13438     std::string ft = FPR(copy(ft_value));
13439     std::string u = IMMEDIATE(copy(u_value));
13440     std::string rs = GPR(copy(rs_value));
13441
13442     return img::format("SDC1 %s, %s(%s)", ft, u, rs);
13443 }
13444
13445
13446 /*
13447  *
13448  *
13449  *   3         2         1
13450  *  10987654321098765432109876543210
13451  *  001000               01001001101
13452  *     rt -----
13453  *          rs -----
13454  *               rd -----
13455  */
13456 std::string NMD::SDC1X(uint64 instruction)
13457 {
13458     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13459     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13460     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13461
13462     std::string ft = FPR(copy(ft_value));
13463     std::string rs = GPR(copy(rs_value));
13464     std::string rt = GPR(copy(rt_value));
13465
13466     return img::format("SDC1X %s, %s(%s)", ft, rs, rt);
13467 }
13468
13469
13470 /*
13471  *
13472  *
13473  *   3         2         1
13474  *  10987654321098765432109876543210
13475  *  001000               01001001101
13476  *     rt -----
13477  *          rs -----
13478  *               rd -----
13479  */
13480 std::string NMD::SDC1XS(uint64 instruction)
13481 {
13482     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13483     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13484     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13485
13486     std::string ft = FPR(copy(ft_value));
13487     std::string rs = GPR(copy(rs_value));
13488     std::string rt = GPR(copy(rt_value));
13489
13490     return img::format("SDC1XS %s, %s(%s)", ft, rs, rt);
13491 }
13492
13493
13494 /*
13495  *
13496  *
13497  *   3         2         1
13498  *  10987654321098765432109876543210
13499  *  001000               01001001101
13500  *     rt -----
13501  *          rs -----
13502  *               rd -----
13503  */
13504 std::string NMD::SDC2(uint64 instruction)
13505 {
13506     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
13507     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13508     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13509
13510     std::string cs = CPR(copy(cs_value));
13511     std::string s = IMMEDIATE(copy(s_value));
13512     std::string rs = GPR(copy(rs_value));
13513
13514     return img::format("SDC2 %s, %s(%s)", cs, s, rs);
13515 }
13516
13517
13518 /*
13519  *
13520  *
13521  *   3         2         1
13522  *  10987654321098765432109876543210
13523  *  001000               01001001101
13524  *     rt -----
13525  *          rs -----
13526  *               rd -----
13527  */
13528 std::string NMD::SDM(uint64 instruction)
13529 {
13530     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13531     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13532     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13533     uint64 count3_value = extract_count3_14_13_12(instruction);
13534
13535     std::string rt = GPR(copy(rt_value));
13536     std::string s = IMMEDIATE(copy(s_value));
13537     std::string rs = GPR(copy(rs_value));
13538     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
13539
13540     return img::format("SDM %s, %s(%s), %s", rt, s, rs, count3);
13541 }
13542
13543
13544 /*
13545  *
13546  *
13547  *   3         2         1
13548  *  10987654321098765432109876543210
13549  *  001000               01001001101
13550  *     rt -----
13551  *          rs -----
13552  *               rd -----
13553  */
13554 std::string NMD::SDPC_48_(uint64 instruction)
13555 {
13556     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
13557     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
13558
13559     std::string rt = GPR(copy(rt_value));
13560     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
13561
13562     return img::format("SDPC %s, %s", rt, s);
13563 }
13564
13565
13566 /*
13567  *
13568  *
13569  *   3         2         1
13570  *  10987654321098765432109876543210
13571  *  001000               01001001101
13572  *     rt -----
13573  *          rs -----
13574  *               rd -----
13575  */
13576 std::string NMD::SDXS(uint64 instruction)
13577 {
13578     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13579     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13580     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13581
13582     std::string rd = GPR(copy(rd_value));
13583     std::string rs = GPR(copy(rs_value));
13584     std::string rt = GPR(copy(rt_value));
13585
13586     return img::format("SDXS %s, %s(%s)", rd, rs, rt);
13587 }
13588
13589
13590 /*
13591  *
13592  *
13593  *   3         2         1
13594  *  10987654321098765432109876543210
13595  *  001000               01001001101
13596  *     rt -----
13597  *          rs -----
13598  *               rd -----
13599  */
13600 std::string NMD::SDX(uint64 instruction)
13601 {
13602     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13603     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13604     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13605
13606     std::string rd = GPR(copy(rd_value));
13607     std::string rs = GPR(copy(rs_value));
13608     std::string rt = GPR(copy(rt_value));
13609
13610     return img::format("SDX %s, %s(%s)", rd, rs, rt);
13611 }
13612
13613
13614 /*
13615  *
13616  *
13617  *   3         2         1
13618  *  10987654321098765432109876543210
13619  *  001000               01001001101
13620  *     rt -----
13621  *          rs -----
13622  *               rd -----
13623  */
13624 std::string NMD::SEB(uint64 instruction)
13625 {
13626     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13627     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13628
13629     std::string rt = GPR(copy(rt_value));
13630     std::string rs = GPR(copy(rs_value));
13631
13632     return img::format("SEB %s, %s", rt, rs);
13633 }
13634
13635
13636 /*
13637  *
13638  *
13639  *   3         2         1
13640  *  10987654321098765432109876543210
13641  *  001000               01001001101
13642  *     rt -----
13643  *          rs -----
13644  *               rd -----
13645  */
13646 std::string NMD::SEH(uint64 instruction)
13647 {
13648     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13649     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13650
13651     std::string rt = GPR(copy(rt_value));
13652     std::string rs = GPR(copy(rs_value));
13653
13654     return img::format("SEH %s, %s", rt, rs);
13655 }
13656
13657
13658 /*
13659  *
13660  *
13661  *   3         2         1
13662  *  10987654321098765432109876543210
13663  *  001000               01001001101
13664  *     rt -----
13665  *          rs -----
13666  *               rd -----
13667  */
13668 std::string NMD::SEL_D(uint64 instruction)
13669 {
13670     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13671     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13672     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13673
13674     std::string fd = FPR(copy(fd_value));
13675     std::string fs = FPR(copy(fs_value));
13676     std::string ft = FPR(copy(ft_value));
13677
13678     return img::format("SEL.D %s, %s, %s", fd, fs, ft);
13679 }
13680
13681
13682 /*
13683  *
13684  *
13685  *   3         2         1
13686  *  10987654321098765432109876543210
13687  *  001000               01001001101
13688  *     rt -----
13689  *          rs -----
13690  *               rd -----
13691  */
13692 std::string NMD::SEL_S(uint64 instruction)
13693 {
13694     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13695     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13696     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13697
13698     std::string fd = FPR(copy(fd_value));
13699     std::string fs = FPR(copy(fs_value));
13700     std::string ft = FPR(copy(ft_value));
13701
13702     return img::format("SEL.S %s, %s, %s", fd, fs, ft);
13703 }
13704
13705
13706 /*
13707  *
13708  *
13709  *   3         2         1
13710  *  10987654321098765432109876543210
13711  *  001000               01001001101
13712  *     rt -----
13713  *          rs -----
13714  *               rd -----
13715  */
13716 std::string NMD::SELEQZ_D(uint64 instruction)
13717 {
13718     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13719     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13720     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13721
13722     std::string fd = FPR(copy(fd_value));
13723     std::string fs = FPR(copy(fs_value));
13724     std::string ft = FPR(copy(ft_value));
13725
13726     return img::format("SELEQZ.D %s, %s, %s", fd, fs, ft);
13727 }
13728
13729
13730 /*
13731  *
13732  *
13733  *   3         2         1
13734  *  10987654321098765432109876543210
13735  *  001000               01001001101
13736  *     rt -----
13737  *          rs -----
13738  *               rd -----
13739  */
13740 std::string NMD::SELEQZ_S(uint64 instruction)
13741 {
13742     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13743     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13744     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13745
13746     std::string fd = FPR(copy(fd_value));
13747     std::string fs = FPR(copy(fs_value));
13748     std::string ft = FPR(copy(ft_value));
13749
13750     return img::format("SELEQZ.S %s, %s, %s", fd, fs, ft);
13751 }
13752
13753
13754 /*
13755  *
13756  *
13757  *   3         2         1
13758  *  10987654321098765432109876543210
13759  *  001000               01001001101
13760  *     rt -----
13761  *          rs -----
13762  *               rd -----
13763  */
13764 std::string NMD::SELNEZ_D(uint64 instruction)
13765 {
13766     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13767     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13768     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13769
13770     std::string fd = FPR(copy(fd_value));
13771     std::string fs = FPR(copy(fs_value));
13772     std::string ft = FPR(copy(ft_value));
13773
13774     return img::format("SELNEZ.D %s, %s, %s", fd, fs, ft);
13775 }
13776
13777
13778 /*
13779  *
13780  *
13781  *   3         2         1
13782  *  10987654321098765432109876543210
13783  *  001000               01001001101
13784  *     rt -----
13785  *          rs -----
13786  *               rd -----
13787  */
13788 std::string NMD::SELNEZ_S(uint64 instruction)
13789 {
13790     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13791     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13792     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13793
13794     std::string fd = FPR(copy(fd_value));
13795     std::string fs = FPR(copy(fs_value));
13796     std::string ft = FPR(copy(ft_value));
13797
13798     return img::format("SELNEZ.S %s, %s, %s", fd, fs, ft);
13799 }
13800
13801
13802 /*
13803  *
13804  *
13805  *   3         2         1
13806  *  10987654321098765432109876543210
13807  *  001000               01001001101
13808  *     rt -----
13809  *          rs -----
13810  *               rd -----
13811  */
13812 std::string NMD::SEQI(uint64 instruction)
13813 {
13814     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13815     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13816     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13817
13818     std::string rt = GPR(copy(rt_value));
13819     std::string rs = GPR(copy(rs_value));
13820     std::string u = IMMEDIATE(copy(u_value));
13821
13822     return img::format("SEQI %s, %s, %s", rt, rs, u);
13823 }
13824
13825
13826 /*
13827  *
13828  *
13829  *   3         2         1
13830  *  10987654321098765432109876543210
13831  *  001000               01001001101
13832  *     rt -----
13833  *          rs -----
13834  *               rd -----
13835  */
13836 std::string NMD::SH_16_(uint64 instruction)
13837 {
13838     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
13839     uint64 rs3_value = extract_rs3_6_5_4(instruction);
13840     uint64 u_value = extract_u_2_1__s1(instruction);
13841
13842     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
13843     std::string u = IMMEDIATE(copy(u_value));
13844     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
13845
13846     return img::format("SH %s, %s(%s)", rtz3, u, rs3);
13847 }
13848
13849
13850 /*
13851  *
13852  *
13853  *   3         2         1
13854  *  10987654321098765432109876543210
13855  *  001000               01001001101
13856  *     rt -----
13857  *          rs -----
13858  *               rd -----
13859  */
13860 std::string NMD::SH_GP_(uint64 instruction)
13861 {
13862     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13863     uint64 u_value = extract_u_17_to_1__s1(instruction);
13864
13865     std::string rt = GPR(copy(rt_value));
13866     std::string u = IMMEDIATE(copy(u_value));
13867
13868     return img::format("SH %s, %s($%d)", rt, u, 28);
13869 }
13870
13871
13872 /*
13873  *
13874  *
13875  *   3         2         1
13876  *  10987654321098765432109876543210
13877  *  001000               01001001101
13878  *     rt -----
13879  *          rs -----
13880  *               rd -----
13881  */
13882 std::string NMD::SH_S9_(uint64 instruction)
13883 {
13884     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13885     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13886     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13887
13888     std::string rt = GPR(copy(rt_value));
13889     std::string s = IMMEDIATE(copy(s_value));
13890     std::string rs = GPR(copy(rs_value));
13891
13892     return img::format("SH %s, %s(%s)", rt, s, rs);
13893 }
13894
13895
13896 /*
13897  *
13898  *
13899  *   3         2         1
13900  *  10987654321098765432109876543210
13901  *  001000               01001001101
13902  *     rt -----
13903  *          rs -----
13904  *               rd -----
13905  */
13906 std::string NMD::SH_U12_(uint64 instruction)
13907 {
13908     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13909     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13910     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13911
13912     std::string rt = GPR(copy(rt_value));
13913     std::string u = IMMEDIATE(copy(u_value));
13914     std::string rs = GPR(copy(rs_value));
13915
13916     return img::format("SH %s, %s(%s)", rt, u, rs);
13917 }
13918
13919
13920 /*
13921  *
13922  *
13923  *   3         2         1
13924  *  10987654321098765432109876543210
13925  *  001000               01001001101
13926  *     rt -----
13927  *          rs -----
13928  *               rd -----
13929  */
13930 std::string NMD::SHE(uint64 instruction)
13931 {
13932     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13933     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13934     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13935
13936     std::string rt = GPR(copy(rt_value));
13937     std::string s = IMMEDIATE(copy(s_value));
13938     std::string rs = GPR(copy(rs_value));
13939
13940     return img::format("SHE %s, %s(%s)", rt, s, rs);
13941 }
13942
13943
13944 /*
13945  * [DSP] SHILO ac, shift - Shift an accumulator value leaving the result in
13946  *   the same accumulator
13947  *
13948  *   3         2         1
13949  *  10987654321098765432109876543210
13950  *  001000xxxx        xxxx0000011101
13951  *      shift ------
13952  *               ac --
13953  */
13954 std::string NMD::SHILO(uint64 instruction)
13955 {
13956     int64 shift_value = extract_shift__se5_21_20_19_18_17_16(instruction);
13957     uint64 ac_value = extract_ac_15_14(instruction);
13958
13959     std::string shift = IMMEDIATE(copy(shift_value));
13960     std::string ac = AC(copy(ac_value));
13961
13962     return img::format("SHILO %s, %s", ac, shift);
13963 }
13964
13965
13966 /*
13967  * [DSP] SHILOV ac, rs - Variable shift of accumulator value leaving the result
13968  *   in the same accumulator
13969  *
13970  *   3         2         1
13971  *  10987654321098765432109876543210
13972  *  001000xxxxx       01001001111111
13973  *          rs -----
13974  *               ac --
13975  */
13976 std::string NMD::SHILOV(uint64 instruction)
13977 {
13978     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13979     uint64 ac_value = extract_ac_15_14(instruction);
13980
13981     std::string rs = GPR(copy(rs_value));
13982     std::string ac = AC(copy(ac_value));
13983
13984     return img::format("SHILOV %s, %s", ac, rs);
13985 }
13986
13987
13988 /*
13989  * [DSP] SHLL.PH rt, rs, sa - Shift left logical vector pair halfwords
13990  *
13991  *   3         2         1
13992  *  10987654321098765432109876543210
13993  *  001000              001110110101
13994  *     rt -----
13995  *          rs -----
13996  *               sa ----
13997  */
13998 std::string NMD::SHLL_PH(uint64 instruction)
13999 {
14000     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14001     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14002     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14003
14004     std::string rt = GPR(copy(rt_value));
14005     std::string rs = GPR(copy(rs_value));
14006     std::string sa = IMMEDIATE(copy(sa_value));
14007
14008     return img::format("SHLL.PH %s, %s, %s", rt, rs, sa);
14009 }
14010
14011
14012 /*
14013  * [DSP] SHLL.QB rt, rs, sa - Shift left logical vector quad bytes
14014  *
14015  *   3         2         1
14016  *  10987654321098765432109876543210
14017  *  001000             0100001111111
14018  *     rt -----
14019  *          rs -----
14020  *               sa ---
14021  */
14022 std::string NMD::SHLL_QB(uint64 instruction)
14023 {
14024     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14025     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14026     uint64 sa_value = extract_sa_15_14_13(instruction);
14027
14028     std::string rt = GPR(copy(rt_value));
14029     std::string rs = GPR(copy(rs_value));
14030     std::string sa = IMMEDIATE(copy(sa_value));
14031
14032     return img::format("SHLL.QB %s, %s, %s", rt, rs, sa);
14033 }
14034
14035
14036 /*
14037  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical vector pair halfwords
14038  *   with saturation
14039  *
14040  *   3         2         1
14041  *  10987654321098765432109876543210
14042  *  001000              001110110101
14043  *     rt -----
14044  *          rs -----
14045  *               sa ----
14046  */
14047 std::string NMD::SHLL_S_PH(uint64 instruction)
14048 {
14049     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14050     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14051     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14052
14053     std::string rt = GPR(copy(rt_value));
14054     std::string rs = GPR(copy(rs_value));
14055     std::string sa = IMMEDIATE(copy(sa_value));
14056
14057     return img::format("SHLL_S.PH %s, %s, %s", rt, rs, sa);
14058 }
14059
14060
14061 /*
14062  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical word with saturation
14063  *
14064  *   3         2         1
14065  *  10987654321098765432109876543210
14066  *  001000               x1111110101
14067  *     rt -----
14068  *          rs -----
14069  *               sa -----
14070  */
14071 std::string NMD::SHLL_S_W(uint64 instruction)
14072 {
14073     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14074     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14075     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
14076
14077     std::string rt = GPR(copy(rt_value));
14078     std::string rs = GPR(copy(rs_value));
14079     std::string sa = IMMEDIATE(copy(sa_value));
14080
14081     return img::format("SHLL_S.W %s, %s, %s", rt, rs, sa);
14082 }
14083
14084
14085 /*
14086  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
14087  *   halfwords
14088  *
14089  *   3         2         1
14090  *  10987654321098765432109876543210
14091  *  001000               01110001101
14092  *     rt -----
14093  *          rs -----
14094  *               rd -----
14095  */
14096 std::string NMD::SHLLV_PH(uint64 instruction)
14097 {
14098     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14099     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14100     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14101
14102     std::string rd = GPR(copy(rd_value));
14103     std::string rt = GPR(copy(rt_value));
14104     std::string rs = GPR(copy(rs_value));
14105
14106     return img::format("SHLLV.PH %s, %s, %s", rd, rt, rs);
14107 }
14108
14109
14110 /*
14111  * [DSP] SHLLV_S.QB rd, rt, rs - Shift left logical variable vector quad bytes
14112  *
14113  *   3         2         1
14114  *  10987654321098765432109876543210
14115  *  001000               x1110010101
14116  *     rt -----
14117  *          rs -----
14118  *               rd -----
14119  */
14120 std::string NMD::SHLLV_QB(uint64 instruction)
14121 {
14122     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14123     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14124     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14125
14126     std::string rd = GPR(copy(rd_value));
14127     std::string rt = GPR(copy(rt_value));
14128     std::string rs = GPR(copy(rs_value));
14129
14130     return img::format("SHLLV.QB %s, %s, %s", rd, rt, rs);
14131 }
14132
14133
14134 /*
14135  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
14136  *   halfwords with saturation
14137  *
14138  *   3         2         1
14139  *  10987654321098765432109876543210
14140  *  001000               11110001101
14141  *     rt -----
14142  *          rs -----
14143  *               rd -----
14144  */
14145 std::string NMD::SHLLV_S_PH(uint64 instruction)
14146 {
14147     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14148     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14149     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14150
14151     std::string rd = GPR(copy(rd_value));
14152     std::string rt = GPR(copy(rt_value));
14153     std::string rs = GPR(copy(rs_value));
14154
14155     return img::format("SHLLV_S.PH %s, %s, %s", rd, rt, rs);
14156 }
14157
14158
14159 /*
14160  * [DSP] SHLLV_S.W rd, rt, rs - Shift left logical variable vector word
14161  *
14162  *   3         2         1
14163  *  10987654321098765432109876543210
14164  *  001000               x1111010101
14165  *     rt -----
14166  *          rs -----
14167  *               rd -----
14168  */
14169 std::string NMD::SHLLV_S_W(uint64 instruction)
14170 {
14171     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14172     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14173     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14174
14175     std::string rd = GPR(copy(rd_value));
14176     std::string rt = GPR(copy(rt_value));
14177     std::string rs = GPR(copy(rs_value));
14178
14179     return img::format("SHLLV_S.W %s, %s, %s", rd, rt, rs);
14180 }
14181
14182
14183 /*
14184  *
14185  *
14186  *   3         2         1
14187  *  10987654321098765432109876543210
14188  *  001000               01001001101
14189  *     rt -----
14190  *          rs -----
14191  *               rd -----
14192  */
14193 std::string NMD::SHRA_PH(uint64 instruction)
14194 {
14195     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14196     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14197     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14198
14199     std::string rt = GPR(copy(rt_value));
14200     std::string rs = GPR(copy(rs_value));
14201     std::string sa = IMMEDIATE(copy(sa_value));
14202
14203     return img::format("SHRA.PH %s, %s, %s", rt, rs, sa);
14204 }
14205
14206
14207 /*
14208  *
14209  *
14210  *   3         2         1
14211  *  10987654321098765432109876543210
14212  *  001000               01001001101
14213  *     rt -----
14214  *          rs -----
14215  *               rd -----
14216  */
14217 std::string NMD::SHRA_QB(uint64 instruction)
14218 {
14219     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14220     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14221     uint64 sa_value = extract_sa_15_14_13(instruction);
14222
14223     std::string rt = GPR(copy(rt_value));
14224     std::string rs = GPR(copy(rs_value));
14225     std::string sa = IMMEDIATE(copy(sa_value));
14226
14227     return img::format("SHRA.QB %s, %s, %s", rt, rs, sa);
14228 }
14229
14230
14231 /*
14232  *
14233  *
14234  *   3         2         1
14235  *  10987654321098765432109876543210
14236  *  001000               01001001101
14237  *     rt -----
14238  *          rs -----
14239  *               rd -----
14240  */
14241 std::string NMD::SHRA_R_PH(uint64 instruction)
14242 {
14243     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14244     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14245     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14246
14247     std::string rt = GPR(copy(rt_value));
14248     std::string rs = GPR(copy(rs_value));
14249     std::string sa = IMMEDIATE(copy(sa_value));
14250
14251     return img::format("SHRA_R.PH %s, %s, %s", rt, rs, sa);
14252 }
14253
14254
14255 /*
14256  *
14257  *
14258  *   3         2         1
14259  *  10987654321098765432109876543210
14260  *  001000               01001001101
14261  *     rt -----
14262  *          rs -----
14263  *               rd -----
14264  */
14265 std::string NMD::SHRA_R_QB(uint64 instruction)
14266 {
14267     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14268     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14269     uint64 sa_value = extract_sa_15_14_13(instruction);
14270
14271     std::string rt = GPR(copy(rt_value));
14272     std::string rs = GPR(copy(rs_value));
14273     std::string sa = IMMEDIATE(copy(sa_value));
14274
14275     return img::format("SHRA_R.QB %s, %s, %s", rt, rs, sa);
14276 }
14277
14278
14279 /*
14280  *
14281  *
14282  *   3         2         1
14283  *  10987654321098765432109876543210
14284  *  001000               01001001101
14285  *     rt -----
14286  *          rs -----
14287  *               rd -----
14288  */
14289 std::string NMD::SHRA_R_W(uint64 instruction)
14290 {
14291     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14292     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14293     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
14294
14295     std::string rt = GPR(copy(rt_value));
14296     std::string rs = GPR(copy(rs_value));
14297     std::string sa = IMMEDIATE(copy(sa_value));
14298
14299     return img::format("SHRA_R.W %s, %s, %s", rt, rs, sa);
14300 }
14301
14302
14303 /*
14304  *
14305  *
14306  *   3         2         1
14307  *  10987654321098765432109876543210
14308  *  001000               01001001101
14309  *     rt -----
14310  *          rs -----
14311  *               rd -----
14312  */
14313 std::string NMD::SHRAV_PH(uint64 instruction)
14314 {
14315     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14316     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14317     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14318
14319     std::string rd = GPR(copy(rd_value));
14320     std::string rt = GPR(copy(rt_value));
14321     std::string rs = GPR(copy(rs_value));
14322
14323     return img::format("SHRAV.PH %s, %s, %s", rd, rt, rs);
14324 }
14325
14326
14327 /*
14328  *
14329  *
14330  *   3         2         1
14331  *  10987654321098765432109876543210
14332  *  001000               01001001101
14333  *     rt -----
14334  *          rs -----
14335  *               rd -----
14336  */
14337 std::string NMD::SHRAV_QB(uint64 instruction)
14338 {
14339     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14340     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14341     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14342
14343     std::string rd = GPR(copy(rd_value));
14344     std::string rt = GPR(copy(rt_value));
14345     std::string rs = GPR(copy(rs_value));
14346
14347     return img::format("SHRAV.QB %s, %s, %s", rd, rt, rs);
14348 }
14349
14350
14351 /*
14352  *
14353  *
14354  *   3         2         1
14355  *  10987654321098765432109876543210
14356  *  001000               01001001101
14357  *     rt -----
14358  *          rs -----
14359  *               rd -----
14360  */
14361 std::string NMD::SHRAV_R_PH(uint64 instruction)
14362 {
14363     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14364     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14365     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14366
14367     std::string rd = GPR(copy(rd_value));
14368     std::string rt = GPR(copy(rt_value));
14369     std::string rs = GPR(copy(rs_value));
14370
14371     return img::format("SHRAV_R.PH %s, %s, %s", rd, rt, rs);
14372 }
14373
14374
14375 /*
14376  *
14377  *
14378  *   3         2         1
14379  *  10987654321098765432109876543210
14380  *  001000               01001001101
14381  *     rt -----
14382  *          rs -----
14383  *               rd -----
14384  */
14385 std::string NMD::SHRAV_R_QB(uint64 instruction)
14386 {
14387     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14388     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14389     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14390
14391     std::string rd = GPR(copy(rd_value));
14392     std::string rt = GPR(copy(rt_value));
14393     std::string rs = GPR(copy(rs_value));
14394
14395     return img::format("SHRAV_R.QB %s, %s, %s", rd, rt, rs);
14396 }
14397
14398
14399 /*
14400  *
14401  *
14402  *   3         2         1
14403  *  10987654321098765432109876543210
14404  *  001000               01001001101
14405  *     rt -----
14406  *          rs -----
14407  *               rd -----
14408  */
14409 std::string NMD::SHRAV_R_W(uint64 instruction)
14410 {
14411     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14412     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14413     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14414
14415     std::string rd = GPR(copy(rd_value));
14416     std::string rt = GPR(copy(rt_value));
14417     std::string rs = GPR(copy(rs_value));
14418
14419     return img::format("SHRAV_R.W %s, %s, %s", rd, rt, rs);
14420 }
14421
14422
14423 /*
14424  * [DSP] SHRL.PH rt, rs, sa - Shift right logical two halfwords
14425  *
14426  *   3         2         1
14427  *  10987654321098765432109876543210
14428  *  001000              001111111111
14429  *     rt -----
14430  *          rs -----
14431  *               sa ----
14432  */
14433 std::string NMD::SHRL_PH(uint64 instruction)
14434 {
14435     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14436     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14437     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14438
14439     std::string rt = GPR(copy(rt_value));
14440     std::string rs = GPR(copy(rs_value));
14441     std::string sa = IMMEDIATE(copy(sa_value));
14442
14443     return img::format("SHRL.PH %s, %s, %s", rt, rs, sa);
14444 }
14445
14446
14447 /*
14448  * [DSP] SHRL.QB rt, rs, sa - Shift right logical vector quad bytes
14449  *
14450  *   3         2         1
14451  *  10987654321098765432109876543210
14452  *  001000             1100001111111
14453  *     rt -----
14454  *          rs -----
14455  *               sa ---
14456  */
14457 std::string NMD::SHRL_QB(uint64 instruction)
14458 {
14459     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14460     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14461     uint64 sa_value = extract_sa_15_14_13(instruction);
14462
14463     std::string rt = GPR(copy(rt_value));
14464     std::string rs = GPR(copy(rs_value));
14465     std::string sa = IMMEDIATE(copy(sa_value));
14466
14467     return img::format("SHRL.QB %s, %s, %s", rt, rs, sa);
14468 }
14469
14470
14471 /*
14472  * [DSP] SHLLV.PH rd, rt, rs - Shift right logical variable vector pair of
14473  *   halfwords
14474  *
14475  *   3         2         1
14476  *  10987654321098765432109876543210
14477  *  001000               x1100010101
14478  *     rt -----
14479  *          rs -----
14480  *               rd -----
14481  */
14482 std::string NMD::SHRLV_PH(uint64 instruction)
14483 {
14484     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14485     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14486     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14487
14488     std::string rd = GPR(copy(rd_value));
14489     std::string rt = GPR(copy(rt_value));
14490     std::string rs = GPR(copy(rs_value));
14491
14492     return img::format("SHRLV.PH %s, %s, %s", rd, rt, rs);
14493 }
14494
14495
14496 /*
14497  * [DSP] SHLLV.QB rd, rt, rs - Shift right logical variable vector quad bytes
14498  *
14499  *   3         2         1
14500  *  10987654321098765432109876543210
14501  *  001000               x1101010101
14502  *     rt -----
14503  *          rs -----
14504  *               rd -----
14505  */
14506 std::string NMD::SHRLV_QB(uint64 instruction)
14507 {
14508     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14509     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14510     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14511
14512     std::string rd = GPR(copy(rd_value));
14513     std::string rt = GPR(copy(rt_value));
14514     std::string rs = GPR(copy(rs_value));
14515
14516     return img::format("SHRLV.QB %s, %s, %s", rd, rt, rs);
14517 }
14518
14519
14520 /*
14521  *
14522  *
14523  *   3         2         1
14524  *  10987654321098765432109876543210
14525  *  001000               01001001101
14526  *     rt -----
14527  *          rs -----
14528  *               rd -----
14529  */
14530 std::string NMD::SHX(uint64 instruction)
14531 {
14532     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14533     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14534     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14535
14536     std::string rd = GPR(copy(rd_value));
14537     std::string rs = GPR(copy(rs_value));
14538     std::string rt = GPR(copy(rt_value));
14539
14540     return img::format("SHX %s, %s(%s)", rd, rs, rt);
14541 }
14542
14543
14544 /*
14545  *
14546  *
14547  *   3         2         1
14548  *  10987654321098765432109876543210
14549  *  001000               01001001101
14550  *     rt -----
14551  *          rs -----
14552  *               rd -----
14553  */
14554 std::string NMD::SHXS(uint64 instruction)
14555 {
14556     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14557     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14558     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14559
14560     std::string rd = GPR(copy(rd_value));
14561     std::string rs = GPR(copy(rs_value));
14562     std::string rt = GPR(copy(rt_value));
14563
14564     return img::format("SHXS %s, %s(%s)", rd, rs, rt);
14565 }
14566
14567
14568 /*
14569  *
14570  *
14571  *   3         2         1
14572  *  10987654321098765432109876543210
14573  *  001000               01001001101
14574  *     rt -----
14575  *          rs -----
14576  *               rd -----
14577  */
14578 std::string NMD::SIGRIE(uint64 instruction)
14579 {
14580     uint64 code_value = extract_code_18_to_0(instruction);
14581
14582     std::string code = IMMEDIATE(copy(code_value));
14583
14584     return img::format("SIGRIE %s", code);
14585 }
14586
14587
14588 /*
14589  *
14590  *
14591  *   3         2         1
14592  *  10987654321098765432109876543210
14593  *  001000               01001001101
14594  *     rt -----
14595  *          rs -----
14596  *               rd -----
14597  */
14598 std::string NMD::SLL_16_(uint64 instruction)
14599 {
14600     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14601     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14602     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14603
14604     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
14605     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
14606     std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));
14607
14608     return img::format("SLL %s, %s, %s", rt3, rs3, shift3);
14609 }
14610
14611
14612 /*
14613  *
14614  *
14615  *   3         2         1
14616  *  10987654321098765432109876543210
14617  *  001000               01001001101
14618  *     rt -----
14619  *          rs -----
14620  *               rd -----
14621  */
14622 std::string NMD::SLL_32_(uint64 instruction)
14623 {
14624     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14625     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14626     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14627
14628     std::string rt = GPR(copy(rt_value));
14629     std::string rs = GPR(copy(rs_value));
14630     std::string shift = IMMEDIATE(copy(shift_value));
14631
14632     return img::format("SLL %s, %s, %s", rt, rs, shift);
14633 }
14634
14635
14636 /*
14637  *
14638  *
14639  *   3         2         1
14640  *  10987654321098765432109876543210
14641  *  001000               01001001101
14642  *     rt -----
14643  *          rs -----
14644  *               rd -----
14645  */
14646 std::string NMD::SLLV(uint64 instruction)
14647 {
14648     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14649     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14650     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14651
14652     std::string rd = GPR(copy(rd_value));
14653     std::string rs = GPR(copy(rs_value));
14654     std::string rt = GPR(copy(rt_value));
14655
14656     return img::format("SLLV %s, %s, %s", rd, rs, rt);
14657 }
14658
14659
14660 /*
14661  *
14662  *
14663  *   3         2         1
14664  *  10987654321098765432109876543210
14665  *  001000               01001001101
14666  *     rt -----
14667  *          rs -----
14668  *               rd -----
14669  */
14670 std::string NMD::SLT(uint64 instruction)
14671 {
14672     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14673     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14674     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14675
14676     std::string rd = GPR(copy(rd_value));
14677     std::string rs = GPR(copy(rs_value));
14678     std::string rt = GPR(copy(rt_value));
14679
14680     return img::format("SLT %s, %s, %s", rd, rs, rt);
14681 }
14682
14683
14684 /*
14685  *
14686  *
14687  *   3         2         1
14688  *  10987654321098765432109876543210
14689  *  001000               01001001101
14690  *     rt -----
14691  *          rs -----
14692  *               rd -----
14693  */
14694 std::string NMD::SLTI(uint64 instruction)
14695 {
14696     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14697     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14698     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14699
14700     std::string rt = GPR(copy(rt_value));
14701     std::string rs = GPR(copy(rs_value));
14702     std::string u = IMMEDIATE(copy(u_value));
14703
14704     return img::format("SLTI %s, %s, %s", rt, rs, u);
14705 }
14706
14707
14708 /*
14709  *
14710  *
14711  *   3         2         1
14712  *  10987654321098765432109876543210
14713  *  001000               01001001101
14714  *     rt -----
14715  *          rs -----
14716  *               rd -----
14717  */
14718 std::string NMD::SLTIU(uint64 instruction)
14719 {
14720     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14721     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14722     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14723
14724     std::string rt = GPR(copy(rt_value));
14725     std::string rs = GPR(copy(rs_value));
14726     std::string u = IMMEDIATE(copy(u_value));
14727
14728     return img::format("SLTIU %s, %s, %s", rt, rs, u);
14729 }
14730
14731
14732 /*
14733  *
14734  *
14735  *   3         2         1
14736  *  10987654321098765432109876543210
14737  *  001000               01001001101
14738  *     rt -----
14739  *          rs -----
14740  *               rd -----
14741  */
14742 std::string NMD::SLTU(uint64 instruction)
14743 {
14744     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14745     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14746     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14747
14748     std::string rd = GPR(copy(rd_value));
14749     std::string rs = GPR(copy(rs_value));
14750     std::string rt = GPR(copy(rt_value));
14751
14752     return img::format("SLTU %s, %s, %s", rd, rs, rt);
14753 }
14754
14755
14756 /*
14757  *
14758  *
14759  *   3         2         1
14760  *  10987654321098765432109876543210
14761  *  001000               01001001101
14762  *     rt -----
14763  *          rs -----
14764  *               rd -----
14765  */
14766 std::string NMD::SOV(uint64 instruction)
14767 {
14768     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14769     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14770     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14771
14772     std::string rd = GPR(copy(rd_value));
14773     std::string rs = GPR(copy(rs_value));
14774     std::string rt = GPR(copy(rt_value));
14775
14776     return img::format("SOV %s, %s, %s", rd, rs, rt);
14777 }
14778
14779
14780 /*
14781  *
14782  *
14783  *   3         2         1
14784  *  10987654321098765432109876543210
14785  *  001000               01001001101
14786  *     rt -----
14787  *          rs -----
14788  *               rd -----
14789  */
14790 std::string NMD::SPECIAL2(uint64 instruction)
14791 {
14792     uint64 op_value = extract_op_25_to_3(instruction);
14793
14794     std::string op = IMMEDIATE(copy(op_value));
14795
14796     return img::format("SPECIAL2 %s", op);
14797 }
14798
14799
14800 /*
14801  *
14802  *
14803  *   3         2         1
14804  *  10987654321098765432109876543210
14805  *  001000               01001001101
14806  *     rt -----
14807  *          rs -----
14808  *               rd -----
14809  */
14810 std::string NMD::SQRT_D(uint64 instruction)
14811 {
14812     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14813     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14814
14815     std::string ft = FPR(copy(ft_value));
14816     std::string fs = FPR(copy(fs_value));
14817
14818     return img::format("SQRT.D %s, %s", ft, fs);
14819 }
14820
14821
14822 /*
14823  *
14824  *
14825  *   3         2         1
14826  *  10987654321098765432109876543210
14827  *  001000               01001001101
14828  *     rt -----
14829  *          rs -----
14830  *               rd -----
14831  */
14832 std::string NMD::SQRT_S(uint64 instruction)
14833 {
14834     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14835     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14836
14837     std::string ft = FPR(copy(ft_value));
14838     std::string fs = FPR(copy(fs_value));
14839
14840     return img::format("SQRT.S %s, %s", ft, fs);
14841 }
14842
14843
14844 /*
14845  * SRA rd, rt, sa - Shift Word Right Arithmetic
14846  *
14847  *   3         2         1
14848  *  10987654321098765432109876543210
14849  *  00000000000               000011
14850  *          rt -----
14851  *               rd -----
14852  *                    sa -----
14853  */
14854 std::string NMD::SRA(uint64 instruction)
14855 {
14856     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14857     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14858     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14859
14860     std::string rt = GPR(copy(rt_value));
14861     std::string rs = GPR(copy(rs_value));
14862     std::string shift = IMMEDIATE(copy(shift_value));
14863
14864     return img::format("SRA %s, %s, %s", rt, rs, shift);
14865 }
14866
14867
14868 /*
14869  * SRAV rd, rt, rs - Shift Word Right Arithmetic Variable
14870  *
14871  *   3         2         1
14872  *  10987654321098765432109876543210
14873  *  001000               00000000111
14874  *     rs -----
14875  *          rt -----
14876  *               rd -----
14877  */
14878 std::string NMD::SRAV(uint64 instruction)
14879 {
14880     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14881     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14882     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14883
14884     std::string rd = GPR(copy(rd_value));
14885     std::string rs = GPR(copy(rs_value));
14886     std::string rt = GPR(copy(rt_value));
14887
14888     return img::format("SRAV %s, %s, %s", rd, rs, rt);
14889 }
14890
14891
14892 /*
14893  *
14894  *
14895  *   3         2         1
14896  *  10987654321098765432109876543210
14897  *  001000               00000000111
14898  *     rs -----
14899  *          rt -----
14900  *               rd -----
14901  */
14902 std::string NMD::SRL_16_(uint64 instruction)
14903 {
14904     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14905     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14906     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14907
14908     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
14909     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
14910     std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));
14911
14912     return img::format("SRL %s, %s, %s", rt3, rs3, shift3);
14913 }
14914
14915
14916 /*
14917  *
14918  *
14919  *   3         2         1
14920  *  10987654321098765432109876543210
14921  *  001000               01001001101
14922  *     rt -----
14923  *          rs -----
14924  *               rd -----
14925  */
14926 std::string NMD::SRL_32_(uint64 instruction)
14927 {
14928     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14929     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14930     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14931
14932     std::string rt = GPR(copy(rt_value));
14933     std::string rs = GPR(copy(rs_value));
14934     std::string shift = IMMEDIATE(copy(shift_value));
14935
14936     return img::format("SRL %s, %s, %s", rt, rs, shift);
14937 }
14938
14939
14940 /*
14941  *
14942  *
14943  *   3         2         1
14944  *  10987654321098765432109876543210
14945  *  001000               01001001101
14946  *     rt -----
14947  *          rs -----
14948  *               rd -----
14949  */
14950 std::string NMD::SRLV(uint64 instruction)
14951 {
14952     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14953     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14954     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14955
14956     std::string rd = GPR(copy(rd_value));
14957     std::string rs = GPR(copy(rs_value));
14958     std::string rt = GPR(copy(rt_value));
14959
14960     return img::format("SRLV %s, %s, %s", rd, rs, rt);
14961 }
14962
14963
14964 /*
14965  *
14966  *
14967  *   3         2         1
14968  *  10987654321098765432109876543210
14969  *  001000               01001001101
14970  *     rt -----
14971  *          rs -----
14972  *               rd -----
14973  */
14974 std::string NMD::SUB(uint64 instruction)
14975 {
14976     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14977     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14978     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14979
14980     std::string rd = GPR(copy(rd_value));
14981     std::string rs = GPR(copy(rs_value));
14982     std::string rt = GPR(copy(rt_value));
14983
14984     return img::format("SUB %s, %s, %s", rd, rs, rt);
14985 }
14986
14987
14988 /*
14989  *
14990  *
14991  *   3         2         1
14992  *  10987654321098765432109876543210
14993  *  001000               01001001101
14994  *     rt -----
14995  *          rs -----
14996  *               rd -----
14997  */
14998 std::string NMD::SUB_D(uint64 instruction)
14999 {
15000     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15001     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15002     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
15003
15004     std::string fd = FPR(copy(fd_value));
15005     std::string fs = FPR(copy(fs_value));
15006     std::string ft = FPR(copy(ft_value));
15007
15008     return img::format("SUB.D %s, %s, %s", fd, fs, ft);
15009 }
15010
15011
15012 /*
15013  *
15014  *
15015  *   3         2         1
15016  *  10987654321098765432109876543210
15017  *  001000               01001001101
15018  *     rt -----
15019  *          rs -----
15020  *               rd -----
15021  */
15022 std::string NMD::SUB_S(uint64 instruction)
15023 {
15024     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15025     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15026     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
15027
15028     std::string fd = FPR(copy(fd_value));
15029     std::string fs = FPR(copy(fs_value));
15030     std::string ft = FPR(copy(ft_value));
15031
15032     return img::format("SUB.S %s, %s, %s", fd, fs, ft);
15033 }
15034
15035
15036 /*
15037  *
15038  *
15039  *   3         2         1
15040  *  10987654321098765432109876543210
15041  *  001000               01001001101
15042  *     rt -----
15043  *          rs -----
15044  *               rd -----
15045  */
15046 std::string NMD::SUBQ_PH(uint64 instruction)
15047 {
15048     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15049     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15050     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15051
15052     std::string rd = GPR(copy(rd_value));
15053     std::string rs = GPR(copy(rs_value));
15054     std::string rt = GPR(copy(rt_value));
15055
15056     return img::format("SUBQ.PH %s, %s, %s", rd, rs, rt);
15057 }
15058
15059
15060 /*
15061  * [DSP] SUBQ.S.PH rd, rt, rs - Subtract fractional halfword vectors and shift
15062  *   right to halve results
15063  *
15064  *   3         2         1
15065  *  10987654321098765432109876543210
15066  *  001000               01001001101
15067  *     rt -----
15068  *          rs -----
15069  *               rd -----
15070  */
15071 std::string NMD::SUBQ_S_PH(uint64 instruction)
15072 {
15073     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15074     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15075     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15076
15077     std::string rd = GPR(copy(rd_value));
15078     std::string rs = GPR(copy(rs_value));
15079     std::string rt = GPR(copy(rt_value));
15080
15081     return img::format("SUBQ_S.PH %s, %s, %s", rd, rs, rt);
15082 }
15083
15084
15085 /*
15086  * [DSP] SUBQ.S.W rd, rt, rs - Subtract fractional halfword vectors and shift
15087  *   right to halve results
15088  *
15089  *   3         2         1
15090  *  10987654321098765432109876543210
15091  *  001000               01001001101
15092  *     rt -----
15093  *          rs -----
15094  *               rd -----
15095  */
15096 std::string NMD::SUBQ_S_W(uint64 instruction)
15097 {
15098     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15099     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15100     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15101
15102     std::string rd = GPR(copy(rd_value));
15103     std::string rs = GPR(copy(rs_value));
15104     std::string rt = GPR(copy(rt_value));
15105
15106     return img::format("SUBQ_S.W %s, %s, %s", rd, rs, rt);
15107 }
15108
15109
15110 /*
15111  * [DSP] SUBQH.PH rd, rt, rs - Subtract fractional halfword vectors and shift
15112  *   right to halve results
15113  *
15114  *   3         2         1
15115  *  10987654321098765432109876543210
15116  *  001000               01001001101
15117  *     rt -----
15118  *          rs -----
15119  *               rd -----
15120  */
15121 std::string NMD::SUBQH_PH(uint64 instruction)
15122 {
15123     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15124     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15125     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15126
15127     std::string rd = GPR(copy(rd_value));
15128     std::string rs = GPR(copy(rs_value));
15129     std::string rt = GPR(copy(rt_value));
15130
15131     return img::format("SUBQH.PH %s, %s, %s", rd, rs, rt);
15132 }
15133
15134
15135 /*
15136  * [DSP] SUBQH_R.PH rd, rt, rs - Subtract fractional halfword vectors and shift
15137  *   right to halve results
15138  *
15139  *   3         2         1
15140  *  10987654321098765432109876543210
15141  *  001000               01001001101
15142  *     rt -----
15143  *          rs -----
15144  *               rd -----
15145  */
15146 std::string NMD::SUBQH_R_PH(uint64 instruction)
15147 {
15148     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15149     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15150     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15151
15152     std::string rd = GPR(copy(rd_value));
15153     std::string rs = GPR(copy(rs_value));
15154     std::string rt = GPR(copy(rt_value));
15155
15156     return img::format("SUBQH_R.PH %s, %s, %s", rd, rs, rt);
15157 }
15158
15159
15160 /*
15161  * [DSP] SUBQH_R.W rd, rt, rs - Subtract fractional halfword vectors and shift
15162  *   right to halve results with rounding
15163  *
15164  *   3         2         1
15165  *  10987654321098765432109876543210
15166  *  001000               11001001101
15167  *     rt -----
15168  *          rs -----
15169  *               rd -----
15170  */
15171 std::string NMD::SUBQH_R_W(uint64 instruction)
15172 {
15173     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15174     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15175     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15176
15177     std::string rd = GPR(copy(rd_value));
15178     std::string rs = GPR(copy(rs_value));
15179     std::string rt = GPR(copy(rt_value));
15180
15181     return img::format("SUBQH_R.W %s, %s, %s", rd, rs, rt);
15182 }
15183
15184
15185 /*
15186  * [DSP] SUBQH.W rd, rs, rt - Subtract fractional words and shift right to
15187  *   halve results
15188  *
15189  *   3         2         1
15190  *  10987654321098765432109876543210
15191  *  001000               01010001101
15192  *     rt -----
15193  *          rs -----
15194  *               rd -----
15195  */
15196 std::string NMD::SUBQH_W(uint64 instruction)
15197 {
15198     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15199     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15200     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15201
15202     std::string rd = GPR(copy(rd_value));
15203     std::string rs = GPR(copy(rs_value));
15204     std::string rt = GPR(copy(rt_value));
15205
15206     return img::format("SUBQH.W %s, %s, %s", rd, rs, rt);
15207 }
15208
15209
15210 /*
15211  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15212  *
15213  *   3         2         1
15214  *  10987654321098765432109876543210
15215  *  001000               00010001101
15216  *     rt -----
15217  *          rs -----
15218  *               rd -----
15219  */
15220 std::string NMD::SUBU_16_(uint64 instruction)
15221 {
15222     uint64 rt3_value = extract_rt3_9_8_7(instruction);
15223     uint64 rs3_value = extract_rs3_6_5_4(instruction);
15224     uint64 rd3_value = extract_rd3_3_2_1(instruction);
15225
15226     std::string rd3 = GPR(decode_gpr_gpr3(rd3_value));
15227     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
15228     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
15229
15230     return img::format("SUBU %s, %s, %s", rd3, rs3, rt3);
15231 }
15232
15233
15234 /*
15235  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15236  *
15237  *   3         2         1
15238  *  10987654321098765432109876543210
15239  *  001000               00010001101
15240  *     rt -----
15241  *          rs -----
15242  *               rd -----
15243  */
15244 std::string NMD::SUBU_32_(uint64 instruction)
15245 {
15246     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15247     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15248     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15249
15250     std::string rd = GPR(copy(rd_value));
15251     std::string rs = GPR(copy(rs_value));
15252     std::string rt = GPR(copy(rt_value));
15253
15254     return img::format("SUBU %s, %s, %s", rd, rs, rt);
15255 }
15256
15257
15258 /*
15259  * [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
15260  *
15261  *   3         2         1
15262  *  10987654321098765432109876543210
15263  *  001000               01100001101
15264  *     rt -----
15265  *          rs -----
15266  *               rd -----
15267  */
15268 std::string NMD::SUBU_PH(uint64 instruction)
15269 {
15270     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15271     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15272     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15273
15274     std::string rd = GPR(copy(rd_value));
15275     std::string rs = GPR(copy(rs_value));
15276     std::string rt = GPR(copy(rt_value));
15277
15278     return img::format("SUBU.PH %s, %s, %s", rd, rs, rt);
15279 }
15280
15281
15282 /*
15283  * [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
15284  *
15285  *   3         2         1
15286  *  10987654321098765432109876543210
15287  *  001000               01011001101
15288  *     rt -----
15289  *          rs -----
15290  *               rd -----
15291  */
15292 std::string NMD::SUBU_QB(uint64 instruction)
15293 {
15294     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15295     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15296     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15297
15298     std::string rd = GPR(copy(rd_value));
15299     std::string rs = GPR(copy(rs_value));
15300     std::string rt = GPR(copy(rt_value));
15301
15302     return img::format("SUBU.QB %s, %s, %s", rd, rs, rt);
15303 }
15304
15305
15306 /*
15307  * [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
15308  *   8-bit saturation
15309  *
15310  *   3         2         1
15311  *  10987654321098765432109876543210
15312  *  001000               11100001101
15313  *     rt -----
15314  *          rs -----
15315  *               rd -----
15316  */
15317 std::string NMD::SUBU_S_PH(uint64 instruction)
15318 {
15319     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15320     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15321     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15322
15323     std::string rd = GPR(copy(rd_value));
15324     std::string rs = GPR(copy(rs_value));
15325     std::string rt = GPR(copy(rt_value));
15326
15327     return img::format("SUBU_S.PH %s, %s, %s", rd, rs, rt);
15328 }
15329
15330
15331 /*
15332  * [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
15333  *   8-bit saturation
15334  *
15335  *   3         2         1
15336  *  10987654321098765432109876543210
15337  *  001000               11011001101
15338  *     rt -----
15339  *          rs -----
15340  *               rd -----
15341  */
15342 std::string NMD::SUBU_S_QB(uint64 instruction)
15343 {
15344     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15345     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15346     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15347
15348     std::string rd = GPR(copy(rd_value));
15349     std::string rs = GPR(copy(rs_value));
15350     std::string rt = GPR(copy(rt_value));
15351
15352     return img::format("SUBU_S.QB %s, %s, %s", rd, rs, rt);
15353 }
15354
15355
15356 /*
15357  * [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
15358  *   to halve results
15359  *
15360  *   3         2         1
15361  *  10987654321098765432109876543210
15362  *  001000               01101001101
15363  *     rt -----
15364  *          rs -----
15365  *               rd -----
15366  */
15367 std::string NMD::SUBUH_QB(uint64 instruction)
15368 {
15369     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15370     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15371     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15372
15373     std::string rd = GPR(copy(rd_value));
15374     std::string rs = GPR(copy(rs_value));
15375     std::string rt = GPR(copy(rt_value));
15376
15377     return img::format("SUBUH.QB %s, %s, %s", rd, rs, rt);
15378 }
15379
15380
15381 /*
15382  * [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
15383  *   to halve results with rounding
15384  *
15385  *   3         2         1
15386  *  10987654321098765432109876543210
15387  *  001000               11101001101
15388  *     rt -----
15389  *          rs -----
15390  *               rd -----
15391  */
15392 std::string NMD::SUBUH_R_QB(uint64 instruction)
15393 {
15394     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15395     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15396     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15397
15398     std::string rd = GPR(copy(rd_value));
15399     std::string rs = GPR(copy(rs_value));
15400     std::string rt = GPR(copy(rt_value));
15401
15402     return img::format("SUBUH_R.QB %s, %s, %s", rd, rs, rt);
15403 }
15404
15405
15406 /*
15407  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15408  *
15409  *   3         2         1
15410  *  10987654321098765432109876543210
15411  *  001000               00010001101
15412  *     rt -----
15413  *          rs -----
15414  *               rd -----
15415  */
15416 std::string NMD::SW_16_(uint64 instruction)
15417 {
15418     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
15419     uint64 rs3_value = extract_rs3_6_5_4(instruction);
15420     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
15421
15422     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
15423     std::string u = IMMEDIATE(copy(u_value));
15424     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
15425
15426     return img::format("SW %s, %s(%s)", rtz3, u, rs3);
15427 }
15428
15429
15430 /*
15431  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15432  *
15433  *   3         2         1
15434  *  10987654321098765432109876543210
15435  *  001000               00010001101
15436  *     rt -----
15437  *          rs -----
15438  *               rd -----
15439  */
15440 std::string NMD::SW_4X4_(uint64 instruction)
15441 {
15442     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
15443     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
15444     uint64 u_value = extract_u_3_8__s2(instruction);
15445
15446     std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value));
15447     std::string u = IMMEDIATE(copy(u_value));
15448     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
15449
15450     return img::format("SW %s, %s(%s)", rtz4, u, rs4);
15451 }
15452
15453
15454 /*
15455  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15456  *
15457  *   3         2         1
15458  *  10987654321098765432109876543210
15459  *  001000               00010001101
15460  *     rt -----
15461  *          rs -----
15462  *               rd -----
15463  */
15464 std::string NMD::SW_GP16_(uint64 instruction)
15465 {
15466     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
15467     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
15468
15469     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
15470     std::string u = IMMEDIATE(copy(u_value));
15471
15472     return img::format("SW %s, %s($%d)", rtz3, u, 28);
15473 }
15474
15475
15476 /*
15477  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15478  *
15479  *   3         2         1
15480  *  10987654321098765432109876543210
15481  *  001000               00010001101
15482  *     rt -----
15483  *          rs -----
15484  *               rd -----
15485  */
15486 std::string NMD::SW_GP_(uint64 instruction)
15487 {
15488     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15489     uint64 u_value = extract_u_20_to_2__s2(instruction);
15490
15491     std::string rt = GPR(copy(rt_value));
15492     std::string u = IMMEDIATE(copy(u_value));
15493
15494     return img::format("SW %s, %s($%d)", rt, u, 28);
15495 }
15496
15497
15498 /*
15499  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15500  *
15501  *   3         2         1
15502  *  10987654321098765432109876543210
15503  *  001000               00010001101
15504  *     rt -----
15505  *          rs -----
15506  *               rd -----
15507  */
15508 std::string NMD::SW_S9_(uint64 instruction)
15509 {
15510     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15511     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15512     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15513
15514     std::string rt = GPR(copy(rt_value));
15515     std::string s = IMMEDIATE(copy(s_value));
15516     std::string rs = GPR(copy(rs_value));
15517
15518     return img::format("SW %s, %s(%s)", rt, s, rs);
15519 }
15520
15521
15522 /*
15523  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15524  *
15525  *   3         2         1
15526  *  10987654321098765432109876543210
15527  *  001000               00010001101
15528  *     rt -----
15529  *          rs -----
15530  *               rd -----
15531  */
15532 std::string NMD::SW_SP_(uint64 instruction)
15533 {
15534     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
15535     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
15536
15537     std::string rt = GPR(copy(rt_value));
15538     std::string u = IMMEDIATE(copy(u_value));
15539
15540     return img::format("SW %s, %s($%d)", rt, u, 29);
15541 }
15542
15543
15544 /*
15545  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15546  *
15547  *   3         2         1
15548  *  10987654321098765432109876543210
15549  *  001000               00010001101
15550  *     rt -----
15551  *          rs -----
15552  *               rd -----
15553  */
15554 std::string NMD::SW_U12_(uint64 instruction)
15555 {
15556     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15557     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15558     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15559
15560     std::string rt = GPR(copy(rt_value));
15561     std::string u = IMMEDIATE(copy(u_value));
15562     std::string rs = GPR(copy(rs_value));
15563
15564     return img::format("SW %s, %s(%s)", rt, u, rs);
15565 }
15566
15567
15568 /*
15569  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15570  *
15571  *   3         2         1
15572  *  10987654321098765432109876543210
15573  *  001000               00010001101
15574  *     rt -----
15575  *          rs -----
15576  *               rd -----
15577  */
15578 std::string NMD::SWC1_GP_(uint64 instruction)
15579 {
15580     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15581     uint64 u_value = extract_u_17_to_2__s2(instruction);
15582
15583     std::string ft = FPR(copy(ft_value));
15584     std::string u = IMMEDIATE(copy(u_value));
15585
15586     return img::format("SWC1 %s, %s($%d)", ft, u, 28);
15587 }
15588
15589
15590 /*
15591  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15592  *
15593  *   3         2         1
15594  *  10987654321098765432109876543210
15595  *  001000               00010001101
15596  *     rt -----
15597  *          rs -----
15598  *               rd -----
15599  */
15600 std::string NMD::SWC1_S9_(uint64 instruction)
15601 {
15602     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15603     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15604     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15605
15606     std::string ft = FPR(copy(ft_value));
15607     std::string s = IMMEDIATE(copy(s_value));
15608     std::string rs = GPR(copy(rs_value));
15609
15610     return img::format("SWC1 %s, %s(%s)", ft, s, rs);
15611 }
15612
15613
15614 /*
15615  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15616  *
15617  *   3         2         1
15618  *  10987654321098765432109876543210
15619  *  001000               00010001101
15620  *     rt -----
15621  *          rs -----
15622  *               rd -----
15623  */
15624 std::string NMD::SWC1_U12_(uint64 instruction)
15625 {
15626     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15627     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15628     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15629
15630     std::string ft = FPR(copy(ft_value));
15631     std::string u = IMMEDIATE(copy(u_value));
15632     std::string rs = GPR(copy(rs_value));
15633
15634     return img::format("SWC1 %s, %s(%s)", ft, u, rs);
15635 }
15636
15637
15638 /*
15639  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15640  *
15641  *   3         2         1
15642  *  10987654321098765432109876543210
15643  *  001000               00010001101
15644  *     rt -----
15645  *          rs -----
15646  *               rd -----
15647  */
15648 std::string NMD::SWC1X(uint64 instruction)
15649 {
15650     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15651     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15652     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15653
15654     std::string ft = FPR(copy(ft_value));
15655     std::string rs = GPR(copy(rs_value));
15656     std::string rt = GPR(copy(rt_value));
15657
15658     return img::format("SWC1X %s, %s(%s)", ft, rs, rt);
15659 }
15660
15661
15662 /*
15663  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15664  *
15665  *   3         2         1
15666  *  10987654321098765432109876543210
15667  *  001000               00010001101
15668  *     rt -----
15669  *          rs -----
15670  *               rd -----
15671  */
15672 std::string NMD::SWC1XS(uint64 instruction)
15673 {
15674     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15675     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15676     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15677
15678     std::string ft = FPR(copy(ft_value));
15679     std::string rs = GPR(copy(rs_value));
15680     std::string rt = GPR(copy(rt_value));
15681
15682     return img::format("SWC1XS %s, %s(%s)", ft, rs, rt);
15683 }
15684
15685
15686 /*
15687  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15688  *
15689  *   3         2         1
15690  *  10987654321098765432109876543210
15691  *  001000               00010001101
15692  *     rt -----
15693  *          rs -----
15694  *               rd -----
15695  */
15696 std::string NMD::SWC2(uint64 instruction)
15697 {
15698     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
15699     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15700     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15701
15702     std::string cs = CPR(copy(cs_value));
15703     std::string s = IMMEDIATE(copy(s_value));
15704     std::string rs = GPR(copy(rs_value));
15705
15706     return img::format("SWC2 %s, %s(%s)", cs, s, rs);
15707 }
15708
15709
15710 /*
15711  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15712  *
15713  *   3         2         1
15714  *  10987654321098765432109876543210
15715  *  001000               00010001101
15716  *     rt -----
15717  *          rs -----
15718  *               rd -----
15719  */
15720 std::string NMD::SWE(uint64 instruction)
15721 {
15722     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15723     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15724     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15725
15726     std::string rt = GPR(copy(rt_value));
15727     std::string s = IMMEDIATE(copy(s_value));
15728     std::string rs = GPR(copy(rs_value));
15729
15730     return img::format("SWE %s, %s(%s)", rt, s, rs);
15731 }
15732
15733
15734 /*
15735  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15736  *
15737  *   3         2         1
15738  *  10987654321098765432109876543210
15739  *  001000               00010001101
15740  *     rt -----
15741  *          rs -----
15742  *               rd -----
15743  */
15744 std::string NMD::SWM(uint64 instruction)
15745 {
15746     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15747     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15748     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15749     uint64 count3_value = extract_count3_14_13_12(instruction);
15750
15751     std::string rt = GPR(copy(rt_value));
15752     std::string s = IMMEDIATE(copy(s_value));
15753     std::string rs = GPR(copy(rs_value));
15754     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
15755
15756     return img::format("SWM %s, %s(%s), %s", rt, s, rs, count3);
15757 }
15758
15759
15760 /*
15761  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15762  *
15763  *   3         2         1
15764  *  10987654321098765432109876543210
15765  *  001000               00010001101
15766  *     rt -----
15767  *          rs -----
15768  *               rd -----
15769  */
15770 std::string NMD::SWPC_48_(uint64 instruction)
15771 {
15772     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
15773     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
15774
15775     std::string rt = GPR(copy(rt_value));
15776     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
15777
15778     return img::format("SWPC %s, %s", rt, s);
15779 }
15780
15781
15782 /*
15783  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15784  *
15785  *   3         2         1
15786  *  10987654321098765432109876543210
15787  *  001000               00010001101
15788  *     rt -----
15789  *          rs -----
15790  *               rd -----
15791  */
15792 std::string NMD::SWX(uint64 instruction)
15793 {
15794     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15795     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15796     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15797
15798     std::string rd = GPR(copy(rd_value));
15799     std::string rs = GPR(copy(rs_value));
15800     std::string rt = GPR(copy(rt_value));
15801
15802     return img::format("SWX %s, %s(%s)", rd, rs, rt);
15803 }
15804
15805
15806 /*
15807  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15808  *
15809  *   3         2         1
15810  *  10987654321098765432109876543210
15811  *  001000               00010001101
15812  *     rt -----
15813  *          rs -----
15814  *               rd -----
15815  */
15816 std::string NMD::SWXS(uint64 instruction)
15817 {
15818     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15819     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15820     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15821
15822     std::string rd = GPR(copy(rd_value));
15823     std::string rs = GPR(copy(rs_value));
15824     std::string rt = GPR(copy(rt_value));
15825
15826     return img::format("SWXS %s, %s(%s)", rd, rs, rt);
15827 }
15828
15829
15830 /*
15831  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15832  *
15833  *   3         2         1
15834  *  10987654321098765432109876543210
15835  *  001000               00010001101
15836  *     rt -----
15837  *          rs -----
15838  *               rd -----
15839  */
15840 std::string NMD::SYNC(uint64 instruction)
15841 {
15842     uint64 stype_value = extract_stype_20_19_18_17_16(instruction);
15843
15844     std::string stype = IMMEDIATE(copy(stype_value));
15845
15846     return img::format("SYNC %s", stype);
15847 }
15848
15849
15850 /*
15851  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15852  *
15853  *   3         2         1
15854  *  10987654321098765432109876543210
15855  *  001000               00010001101
15856  *     rt -----
15857  *          rs -----
15858  *               rd -----
15859  */
15860 std::string NMD::SYNCI(uint64 instruction)
15861 {
15862     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15863     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15864
15865     std::string s = IMMEDIATE(copy(s_value));
15866     std::string rs = GPR(copy(rs_value));
15867
15868     return img::format("SYNCI %s(%s)", s, rs);
15869 }
15870
15871
15872 /*
15873  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15874  *
15875  *   3         2         1
15876  *  10987654321098765432109876543210
15877  *  001000               00010001101
15878  *     rt -----
15879  *          rs -----
15880  *               rd -----
15881  */
15882 std::string NMD::SYNCIE(uint64 instruction)
15883 {
15884     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15885     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15886
15887     std::string s = IMMEDIATE(copy(s_value));
15888     std::string rs = GPR(copy(rs_value));
15889
15890     return img::format("SYNCIE %s(%s)", s, rs);
15891 }
15892
15893
15894 /*
15895  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15896  *
15897  *   3         2         1
15898  *  10987654321098765432109876543210
15899  *  001000               00010001101
15900  *     rt -----
15901  *          rs -----
15902  *               rd -----
15903  */
15904 std::string NMD::SYSCALL_16_(uint64 instruction)
15905 {
15906     uint64 code_value = extract_code_1_0(instruction);
15907
15908     std::string code = IMMEDIATE(copy(code_value));
15909
15910     return img::format("SYSCALL %s", code);
15911 }
15912
15913
15914 /*
15915  * SYSCALL code - System Call. Cause a System Call Exception
15916  *
15917  *   3         2         1
15918  *  10987654321098765432109876543210
15919  *  00000000000010
15920  *           code ------------------
15921  */
15922 std::string NMD::SYSCALL_32_(uint64 instruction)
15923 {
15924     uint64 code_value = extract_code_17_to_0(instruction);
15925
15926     std::string code = IMMEDIATE(copy(code_value));
15927
15928     return img::format("SYSCALL %s", code);
15929 }
15930
15931
15932 /*
15933  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15934  *
15935  *   3         2         1
15936  *  10987654321098765432109876543210
15937  *  001000               00010001101
15938  *     rt -----
15939  *          rs -----
15940  *               rd -----
15941  */
15942 std::string NMD::TEQ(uint64 instruction)
15943 {
15944     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15945     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15946
15947     std::string rs = GPR(copy(rs_value));
15948     std::string rt = GPR(copy(rt_value));
15949
15950     return img::format("TEQ %s, %s", rs, rt);
15951 }
15952
15953
15954 /*
15955  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15956  *
15957  *   3         2         1
15958  *  10987654321098765432109876543210
15959  *  001000               00010001101
15960  *     rt -----
15961  *          rs -----
15962  *               rd -----
15963  */
15964 std::string NMD::TLBGINV(uint64 instruction)
15965 {
15966     (void)instruction;
15967
15968     return "TLBGINV ";
15969 }
15970
15971
15972 /*
15973  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15974  *
15975  *   3         2         1
15976  *  10987654321098765432109876543210
15977  *  001000               00010001101
15978  *     rt -----
15979  *          rs -----
15980  *               rd -----
15981  */
15982 std::string NMD::TLBGINVF(uint64 instruction)
15983 {
15984     (void)instruction;
15985
15986     return "TLBGINVF ";
15987 }
15988
15989
15990 /*
15991  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15992  *
15993  *   3         2         1
15994  *  10987654321098765432109876543210
15995  *  001000               00010001101
15996  *     rt -----
15997  *          rs -----
15998  *               rd -----
15999  */
16000 std::string NMD::TLBGP(uint64 instruction)
16001 {
16002     (void)instruction;
16003
16004     return "TLBGP ";
16005 }
16006
16007
16008 /*
16009  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16010  *
16011  *   3         2         1
16012  *  10987654321098765432109876543210
16013  *  001000               00010001101
16014  *     rt -----
16015  *          rs -----
16016  *               rd -----
16017  */
16018 std::string NMD::TLBGR(uint64 instruction)
16019 {
16020     (void)instruction;
16021
16022     return "TLBGR ";
16023 }
16024
16025
16026 /*
16027  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16028  *
16029  *   3         2         1
16030  *  10987654321098765432109876543210
16031  *  001000               00010001101
16032  *     rt -----
16033  *          rs -----
16034  *               rd -----
16035  */
16036 std::string NMD::TLBGWI(uint64 instruction)
16037 {
16038     (void)instruction;
16039
16040     return "TLBGWI ";
16041 }
16042
16043
16044 /*
16045  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16046  *
16047  *   3         2         1
16048  *  10987654321098765432109876543210
16049  *  001000               00010001101
16050  *     rt -----
16051  *          rs -----
16052  *               rd -----
16053  */
16054 std::string NMD::TLBGWR(uint64 instruction)
16055 {
16056     (void)instruction;
16057
16058     return "TLBGWR ";
16059 }
16060
16061
16062 /*
16063  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16064  *
16065  *   3         2         1
16066  *  10987654321098765432109876543210
16067  *  001000               00010001101
16068  *     rt -----
16069  *          rs -----
16070  *               rd -----
16071  */
16072 std::string NMD::TLBINV(uint64 instruction)
16073 {
16074     (void)instruction;
16075
16076     return "TLBINV ";
16077 }
16078
16079
16080 /*
16081  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16082  *
16083  *   3         2         1
16084  *  10987654321098765432109876543210
16085  *  001000               00010001101
16086  *     rt -----
16087  *          rs -----
16088  *               rd -----
16089  */
16090 std::string NMD::TLBINVF(uint64 instruction)
16091 {
16092     (void)instruction;
16093
16094     return "TLBINVF ";
16095 }
16096
16097
16098 /*
16099  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16100  *
16101  *   3         2         1
16102  *  10987654321098765432109876543210
16103  *  001000               00010001101
16104  *     rt -----
16105  *          rs -----
16106  *               rd -----
16107  */
16108 std::string NMD::TLBP(uint64 instruction)
16109 {
16110     (void)instruction;
16111
16112     return "TLBP ";
16113 }
16114
16115
16116 /*
16117  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16118  *
16119  *   3         2         1
16120  *  10987654321098765432109876543210
16121  *  001000               00010001101
16122  *     rt -----
16123  *          rs -----
16124  *               rd -----
16125  */
16126 std::string NMD::TLBR(uint64 instruction)
16127 {
16128     (void)instruction;
16129
16130     return "TLBR ";
16131 }
16132
16133
16134 /*
16135  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16136  *
16137  *   3         2         1
16138  *  10987654321098765432109876543210
16139  *  001000               00010001101
16140  *     rt -----
16141  *          rs -----
16142  *               rd -----
16143  */
16144 std::string NMD::TLBWI(uint64 instruction)
16145 {
16146     (void)instruction;
16147
16148     return "TLBWI ";
16149 }
16150
16151
16152 /*
16153  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16154  *
16155  *   3         2         1
16156  *  10987654321098765432109876543210
16157  *  001000               00010001101
16158  *     rt -----
16159  *          rs -----
16160  *               rd -----
16161  */
16162 std::string NMD::TLBWR(uint64 instruction)
16163 {
16164     (void)instruction;
16165
16166     return "TLBWR ";
16167 }
16168
16169
16170 /*
16171  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16172  *
16173  *   3         2         1
16174  *  10987654321098765432109876543210
16175  *  001000               00010001101
16176  *     rt -----
16177  *          rs -----
16178  *               rd -----
16179  */
16180 std::string NMD::TNE(uint64 instruction)
16181 {
16182     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16183     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16184
16185     std::string rs = GPR(copy(rs_value));
16186     std::string rt = GPR(copy(rt_value));
16187
16188     return img::format("TNE %s, %s", rs, rt);
16189 }
16190
16191
16192 /*
16193  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16194  *
16195  *   3         2         1
16196  *  10987654321098765432109876543210
16197  *  001000               00010001101
16198  *     rt -----
16199  *          rs -----
16200  *               rd -----
16201  */
16202 std::string NMD::TRUNC_L_D(uint64 instruction)
16203 {
16204     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16205     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16206
16207     std::string ft = FPR(copy(ft_value));
16208     std::string fs = FPR(copy(fs_value));
16209
16210     return img::format("TRUNC.L.D %s, %s", ft, fs);
16211 }
16212
16213
16214 /*
16215  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16216  *
16217  *   3         2         1
16218  *  10987654321098765432109876543210
16219  *  001000               00010001101
16220  *     rt -----
16221  *          rs -----
16222  *               rd -----
16223  */
16224 std::string NMD::TRUNC_L_S(uint64 instruction)
16225 {
16226     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16227     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16228
16229     std::string ft = FPR(copy(ft_value));
16230     std::string fs = FPR(copy(fs_value));
16231
16232     return img::format("TRUNC.L.S %s, %s", ft, fs);
16233 }
16234
16235
16236 /*
16237  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16238  *
16239  *   3         2         1
16240  *  10987654321098765432109876543210
16241  *  001000               00010001101
16242  *     rt -----
16243  *          rs -----
16244  *               rd -----
16245  */
16246 std::string NMD::TRUNC_W_D(uint64 instruction)
16247 {
16248     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16249     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16250
16251     std::string ft = FPR(copy(ft_value));
16252     std::string fs = FPR(copy(fs_value));
16253
16254     return img::format("TRUNC.W.D %s, %s", ft, fs);
16255 }
16256
16257
16258 /*
16259  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16260  *
16261  *   3         2         1
16262  *  10987654321098765432109876543210
16263  *  001000               00010001101
16264  *     rt -----
16265  *          rs -----
16266  *               rd -----
16267  */
16268 std::string NMD::TRUNC_W_S(uint64 instruction)
16269 {
16270     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16271     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16272
16273     std::string ft = FPR(copy(ft_value));
16274     std::string fs = FPR(copy(fs_value));
16275
16276     return img::format("TRUNC.W.S %s, %s", ft, fs);
16277 }
16278
16279
16280 /*
16281  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16282  *
16283  *   3         2         1
16284  *  10987654321098765432109876543210
16285  *  001000               00010001101
16286  *     rt -----
16287  *          rs -----
16288  *               rd -----
16289  */
16290 std::string NMD::UALDM(uint64 instruction)
16291 {
16292     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16293     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16294     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16295     uint64 count3_value = extract_count3_14_13_12(instruction);
16296
16297     std::string rt = GPR(copy(rt_value));
16298     std::string s = IMMEDIATE(copy(s_value));
16299     std::string rs = GPR(copy(rs_value));
16300     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16301
16302     return img::format("UALDM %s, %s(%s), %s", rt, s, rs, count3);
16303 }
16304
16305
16306 /*
16307  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16308  *
16309  *   3         2         1
16310  *  10987654321098765432109876543210
16311  *  001000               00010001101
16312  *     rt -----
16313  *          rs -----
16314  *               rd -----
16315  */
16316 std::string NMD::UALH(uint64 instruction)
16317 {
16318     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16319     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16320     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16321
16322     std::string rt = GPR(copy(rt_value));
16323     std::string s = IMMEDIATE(copy(s_value));
16324     std::string rs = GPR(copy(rs_value));
16325
16326     return img::format("UALH %s, %s(%s)", rt, s, rs);
16327 }
16328
16329
16330 /*
16331  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16332  *
16333  *   3         2         1
16334  *  10987654321098765432109876543210
16335  *  001000               00010001101
16336  *     rt -----
16337  *          rs -----
16338  *               rd -----
16339  */
16340 std::string NMD::UALWM(uint64 instruction)
16341 {
16342     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16343     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16344     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16345     uint64 count3_value = extract_count3_14_13_12(instruction);
16346
16347     std::string rt = GPR(copy(rt_value));
16348     std::string s = IMMEDIATE(copy(s_value));
16349     std::string rs = GPR(copy(rs_value));
16350     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16351
16352     return img::format("UALWM %s, %s(%s), %s", rt, s, rs, count3);
16353 }
16354
16355
16356 /*
16357  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16358  *
16359  *   3         2         1
16360  *  10987654321098765432109876543210
16361  *  001000               00010001101
16362  *     rt -----
16363  *          rs -----
16364  *               rd -----
16365  */
16366 std::string NMD::UASDM(uint64 instruction)
16367 {
16368     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16369     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16370     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16371     uint64 count3_value = extract_count3_14_13_12(instruction);
16372
16373     std::string rt = GPR(copy(rt_value));
16374     std::string s = IMMEDIATE(copy(s_value));
16375     std::string rs = GPR(copy(rs_value));
16376     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16377
16378     return img::format("UASDM %s, %s(%s), %s", rt, s, rs, count3);
16379 }
16380
16381
16382 /*
16383  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16384  *
16385  *   3         2         1
16386  *  10987654321098765432109876543210
16387  *  001000               00010001101
16388  *     rt -----
16389  *          rs -----
16390  *               rd -----
16391  */
16392 std::string NMD::UASH(uint64 instruction)
16393 {
16394     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16395     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16396     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16397
16398     std::string rt = GPR(copy(rt_value));
16399     std::string s = IMMEDIATE(copy(s_value));
16400     std::string rs = GPR(copy(rs_value));
16401
16402     return img::format("UASH %s, %s(%s)", rt, s, rs);
16403 }
16404
16405
16406 /*
16407  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16408  *
16409  *   3         2         1
16410  *  10987654321098765432109876543210
16411  *  001000               00010001101
16412  *     rt -----
16413  *          rs -----
16414  *               rd -----
16415  */
16416 std::string NMD::UASWM(uint64 instruction)
16417 {
16418     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16419     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16420     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16421     uint64 count3_value = extract_count3_14_13_12(instruction);
16422
16423     std::string rt = GPR(copy(rt_value));
16424     std::string s = IMMEDIATE(copy(s_value));
16425     std::string rs = GPR(copy(rs_value));
16426     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16427
16428     return img::format("UASWM %s, %s(%s), %s", rt, s, rs, count3);
16429 }
16430
16431
16432 /*
16433  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16434  *
16435  *   3         2         1
16436  *  10987654321098765432109876543210
16437  *  001000               00010001101
16438  *     rt -----
16439  *          rs -----
16440  *               rd -----
16441  */
16442 std::string NMD::UDI(uint64 instruction)
16443 {
16444     uint64 op_value = extract_op_25_to_3(instruction);
16445
16446     std::string op = IMMEDIATE(copy(op_value));
16447
16448     return img::format("UDI %s", op);
16449 }
16450
16451
16452 /*
16453  * WAIT code - Enter Wait State
16454  *
16455  *   3         2         1
16456  *  10987654321098765432109876543210
16457  *  001000          1100001101111111
16458  *   code ----------
16459  */
16460 std::string NMD::WAIT(uint64 instruction)
16461 {
16462     uint64 code_value = extract_code_25_24_23_22_21_20_19_18_17_16(instruction);
16463
16464     std::string code = IMMEDIATE(copy(code_value));
16465
16466     return img::format("WAIT %s", code);
16467 }
16468
16469
16470 /*
16471  * [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
16472  *         register
16473  *
16474  *   3         2         1
16475  *  10987654321098765432109876543210
16476  *  001000            01011001111111
16477  *     rt -----
16478  *        mask -------
16479  */
16480 std::string NMD::WRDSP(uint64 instruction)
16481 {
16482     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16483     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
16484
16485     std::string rt = GPR(copy(rt_value));
16486     std::string mask = IMMEDIATE(copy(mask_value));
16487
16488     return img::format("WRDSP %s, %s", rt, mask);
16489 }
16490
16491
16492 /*
16493  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16494  *
16495  *   3         2         1
16496  *  10987654321098765432109876543210
16497  *  001000               00010001101
16498  *     rt -----
16499  *          rs -----
16500  *               rd -----
16501  */
16502 std::string NMD::WRPGPR(uint64 instruction)
16503 {
16504     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16505     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16506
16507     std::string rt = GPR(copy(rt_value));
16508     std::string rs = GPR(copy(rs_value));
16509
16510     return img::format("WRPGPR %s, %s", rt, rs);
16511 }
16512
16513
16514 /*
16515  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16516  *
16517  *   3         2         1
16518  *  10987654321098765432109876543210
16519  *  001000               00010001101
16520  *     rt -----
16521  *          rs -----
16522  *               rd -----
16523  */
16524 std::string NMD::XOR_16_(uint64 instruction)
16525 {
16526     uint64 rt3_value = extract_rt3_9_8_7(instruction);
16527     uint64 rs3_value = extract_rs3_6_5_4(instruction);
16528
16529     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
16530     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
16531
16532     return img::format("XOR %s, %s", rs3, rt3);
16533 }
16534
16535
16536 /*
16537  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16538  *
16539  *   3         2         1
16540  *  10987654321098765432109876543210
16541  *  001000               00010001101
16542  *     rt -----
16543  *          rs -----
16544  *               rd -----
16545  */
16546 std::string NMD::XOR_32_(uint64 instruction)
16547 {
16548     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16549     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16550     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
16551
16552     std::string rd = GPR(copy(rd_value));
16553     std::string rs = GPR(copy(rs_value));
16554     std::string rt = GPR(copy(rt_value));
16555
16556     return img::format("XOR %s, %s, %s", rd, rs, rt);
16557 }
16558
16559
16560 /*
16561  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16562  *
16563  *   3         2         1
16564  *  10987654321098765432109876543210
16565  *  001000               00010001101
16566  *     rt -----
16567  *          rs -----
16568  *               rd -----
16569  */
16570 std::string NMD::XORI(uint64 instruction)
16571 {
16572     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16573     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16574     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
16575
16576     std::string rt = GPR(copy(rt_value));
16577     std::string rs = GPR(copy(rs_value));
16578     std::string u = IMMEDIATE(copy(u_value));
16579
16580     return img::format("XORI %s, %s, %s", rt, rs, u);
16581 }
16582
16583
16584 /*
16585  * YIELD rt, rs -
16586  *
16587  *   3         2         1
16588  *  10987654321098765432109876543210
16589  *  001000               00010001101
16590  *     rt -----
16591  *          rs -----
16592  */
16593 std::string NMD::YIELD(uint64 instruction)
16594 {
16595     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16596     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16597
16598     std::string rt = GPR(copy(rt_value));
16599     std::string rs = GPR(copy(rs_value));
16600
16601     return img::format("YIELD %s, %s", rt, rs);
16602 }
16603
16604
16605
16606 /*
16607  *                nanoMIPS instruction pool organization
16608  *                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16609  *
16610  *
16611  *                 ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL
16612  *                 │
16613  *                 │                                      ┌─ P.TRAP
16614  *                 │                                      │
16615  *                 │                      ┌─ _POOL32A0_0 ─┼─ P.CMOVE
16616  *                 │                      │               │
16617  *                 │                      │               └─ P.SLTU
16618  *                 │        ┌─ _POOL32A0 ─┤
16619  *                 │        │             │
16620  *                 │        │             │
16621  *                 │        │             └─ _POOL32A0_1 ─── CRC32
16622  *                 │        │
16623  *                 ├─ P32A ─┤
16624  *                 │        │                           ┌─ PP.LSX
16625  *                 │        │             ┌─ P.LSX ─────┤
16626  *                 │        │             │             └─ PP.LSXS
16627  *                 │        └─ _POOL32A7 ─┤
16628  *                 │                      │             ┌─ POOL32Axf_4
16629  *                 │                      └─ POOL32Axf ─┤
16630  *                 │                                    └─ POOL32Axf_5
16631  *                 │
16632  *                 ├─ PBAL
16633  *                 │
16634  *                 ├─ P.GP.W   ┌─ PP.LSX
16635  *         ┌─ P32 ─┤           │
16636  *         │       ├─ P.GP.BH ─┴─ PP.LSXS
16637  *         │       │
16638  *         │       ├─ P.J ─────── PP.BALRSC
16639  *         │       │
16640  *         │       ├─ P48I
16641  *         │       │           ┌─ P.SR
16642  *         │       │           │
16643  *         │       │           ├─ P.SHIFT
16644  *         │       │           │
16645  *         │       ├─ P.U12 ───┼─ P.ROTX
16646  *         │       │           │
16647  *         │       │           ├─ P.INS
16648  *         │       │           │
16649  *         │       │           └─ P.EXT
16650  *         │       │
16651  *         │       ├─ P.LS.U12 ── P.PREF.U12
16652  *         │       │
16653  *         │       ├─ P.BR1 ───── P.BR3A
16654  *         │       │
16655  *         │       │           ┌─ P.LS.S0 ─── P16.SYSCALL
16656  *         │       │           │
16657  *         │       │           │           ┌─ P.LL
16658  *         │       │           ├─ P.LS.S1 ─┤
16659  *         │       │           │           └─ P.SC
16660  *         │       │           │
16661  *         │       │           │           ┌─ P.PREFE
16662  *  MAJOR ─┤       ├─ P.LS.S9 ─┤           │
16663  *         │       │           ├─ P.LS.E0 ─┼─ P.LLE
16664  *         │       │           │           │
16665  *         │       │           │           └─ P.SCE
16666  *         │       │           │
16667  *         │       │           ├─ P.LS.WM
16668  *         │       │           │
16669  *         │       │           └─ P.LS.UAWM
16670  *         │       │
16671  *         │       │
16672  *         │       ├─ P.BR2
16673  *         │       │
16674  *         │       ├─ P.BRI
16675  *         │       │
16676  *         │       └─ P.LUI
16677  *         │
16678  *         │
16679  *         │       ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL
16680  *         │       │
16681  *         │       ├─ P16.SR
16682  *         │       │
16683  *         │       ├─ P16.SHIFT
16684  *         │       │
16685  *         │       ├─ P16.4x4
16686  *         │       │
16687  *         │       ├─ P16C ────── POOL16C_0 ── POOL16C_00
16688  *         │       │
16689  *         └─ P16 ─┼─ P16.LB
16690  *                 │
16691  *                 ├─ P16.A1
16692  *                 │
16693  *                 ├─ P16.LH
16694  *                 │
16695  *                 ├─ P16.A2 ──── P.ADDIU[RS5]
16696  *                 │
16697  *                 ├─ P16.ADDU
16698  *                 │
16699  *                 └─ P16.BR ──┬─ P16.JRC
16700  *                             │
16701  *                             └─ P16.BR1
16702  *
16703  *
16704  *  (FP, DPS, and some minor instruction pools are omitted from the diagram)
16705  *
16706  */
16707
16708 NMD::Pool NMD::P_SYSCALL[2] = {
16709     { instruction         , 0                   , 0   , 32,
16710        0xfffc0000, 0x00080000, &NMD::SYSCALL_32_      , 0,
16711        0x0                 },        /* SYSCALL[32] */
16712     { instruction         , 0                   , 0   , 32,
16713        0xfffc0000, 0x000c0000, &NMD::HYPCALL          , 0,
16714        CP0_ | VZ_          },        /* HYPCALL */
16715 };
16716
16717
16718 NMD::Pool NMD::P_RI[4] = {
16719     { instruction         , 0                   , 0   , 32,
16720        0xfff80000, 0x00000000, &NMD::SIGRIE           , 0,
16721        0x0                 },        /* SIGRIE */
16722     { pool                , P_SYSCALL           , 2   , 32,
16723        0xfff80000, 0x00080000, 0                      , 0,
16724        0x0                 },        /* P.SYSCALL */
16725     { instruction         , 0                   , 0   , 32,
16726        0xfff80000, 0x00100000, &NMD::BREAK_32_        , 0,
16727        0x0                 },        /* BREAK[32] */
16728     { instruction         , 0                   , 0   , 32,
16729        0xfff80000, 0x00180000, &NMD::SDBBP_32_        , 0,
16730        EJTAG_              },        /* SDBBP[32] */
16731 };
16732
16733
16734 NMD::Pool NMD::P_ADDIU[2] = {
16735     { pool                , P_RI                , 4   , 32,
16736        0xffe00000, 0x00000000, 0                      , 0,
16737        0x0                 },        /* P.RI */
16738     { instruction         , 0                   , 0   , 32,
16739        0xfc000000, 0x00000000, &NMD::ADDIU_32_        , &NMD::ADDIU_32__cond   ,
16740        0x0                 },        /* ADDIU[32] */
16741 };
16742
16743
16744 NMD::Pool NMD::P_TRAP[2] = {
16745     { instruction         , 0                   , 0   , 32,
16746        0xfc0007ff, 0x20000000, &NMD::TEQ              , 0,
16747        XMMS_               },        /* TEQ */
16748     { instruction         , 0                   , 0   , 32,
16749        0xfc0007ff, 0x20000400, &NMD::TNE              , 0,
16750        XMMS_               },        /* TNE */
16751 };
16752
16753
16754 NMD::Pool NMD::P_CMOVE[2] = {
16755     { instruction         , 0                   , 0   , 32,
16756        0xfc0007ff, 0x20000210, &NMD::MOVZ             , 0,
16757        0x0                 },        /* MOVZ */
16758     { instruction         , 0                   , 0   , 32,
16759        0xfc0007ff, 0x20000610, &NMD::MOVN             , 0,
16760        0x0                 },        /* MOVN */
16761 };
16762
16763
16764 NMD::Pool NMD::P_D_MT_VPE[2] = {
16765     { instruction         , 0                   , 0   , 32,
16766        0xfc1f3fff, 0x20010ab0, &NMD::DMT              , 0,
16767        MT_                 },        /* DMT */
16768     { instruction         , 0                   , 0   , 32,
16769        0xfc1f3fff, 0x20000ab0, &NMD::DVPE             , 0,
16770        MT_                 },        /* DVPE */
16771 };
16772
16773
16774 NMD::Pool NMD::P_E_MT_VPE[2] = {
16775     { instruction         , 0                   , 0   , 32,
16776        0xfc1f3fff, 0x20010eb0, &NMD::EMT              , 0,
16777        MT_                 },        /* EMT */
16778     { instruction         , 0                   , 0   , 32,
16779        0xfc1f3fff, 0x20000eb0, &NMD::EVPE             , 0,
16780        MT_                 },        /* EVPE */
16781 };
16782
16783
16784 NMD::Pool NMD::_P_MT_VPE[2] = {
16785     { pool                , P_D_MT_VPE          , 2   , 32,
16786        0xfc003fff, 0x20000ab0, 0                      , 0,
16787        0x0                 },        /* P.D_MT_VPE */
16788     { pool                , P_E_MT_VPE          , 2   , 32,
16789        0xfc003fff, 0x20000eb0, 0                      , 0,
16790        0x0                 },        /* P.E_MT_VPE */
16791 };
16792
16793
16794 NMD::Pool NMD::P_MT_VPE[8] = {
16795     { reserved_block      , 0                   , 0   , 32,
16796        0xfc003bff, 0x200002b0, 0                      , 0,
16797        0x0                 },        /* P.MT_VPE~*(0) */
16798     { pool                , _P_MT_VPE           , 2   , 32,
16799        0xfc003bff, 0x20000ab0, 0                      , 0,
16800        0x0                 },        /* _P.MT_VPE */
16801     { reserved_block      , 0                   , 0   , 32,
16802        0xfc003bff, 0x200012b0, 0                      , 0,
16803        0x0                 },        /* P.MT_VPE~*(2) */
16804     { reserved_block      , 0                   , 0   , 32,
16805        0xfc003bff, 0x20001ab0, 0                      , 0,
16806        0x0                 },        /* P.MT_VPE~*(3) */
16807     { reserved_block      , 0                   , 0   , 32,
16808        0xfc003bff, 0x200022b0, 0                      , 0,
16809        0x0                 },        /* P.MT_VPE~*(4) */
16810     { reserved_block      , 0                   , 0   , 32,
16811        0xfc003bff, 0x20002ab0, 0                      , 0,
16812        0x0                 },        /* P.MT_VPE~*(5) */
16813     { reserved_block      , 0                   , 0   , 32,
16814        0xfc003bff, 0x200032b0, 0                      , 0,
16815        0x0                 },        /* P.MT_VPE~*(6) */
16816     { reserved_block      , 0                   , 0   , 32,
16817        0xfc003bff, 0x20003ab0, 0                      , 0,
16818        0x0                 },        /* P.MT_VPE~*(7) */
16819 };
16820
16821
16822 NMD::Pool NMD::P_DVP[2] = {
16823     { instruction         , 0                   , 0   , 32,
16824        0xfc00ffff, 0x20000390, &NMD::DVP              , 0,
16825        0x0                 },        /* DVP */
16826     { instruction         , 0                   , 0   , 32,
16827        0xfc00ffff, 0x20000790, &NMD::EVP              , 0,
16828        0x0                 },        /* EVP */
16829 };
16830
16831
16832 NMD::Pool NMD::P_SLTU[2] = {
16833     { pool                , P_DVP               , 2   , 32,
16834        0xfc00fbff, 0x20000390, 0                      , 0,
16835        0x0                 },        /* P.DVP */
16836     { instruction         , 0                   , 0   , 32,
16837        0xfc0003ff, 0x20000390, &NMD::SLTU             , &NMD::SLTU_cond        ,
16838        0x0                 },        /* SLTU */
16839 };
16840
16841
16842 NMD::Pool NMD::_POOL32A0[128] = {
16843     { pool                , P_TRAP              , 2   , 32,
16844        0xfc0003ff, 0x20000000, 0                      , 0,
16845        0x0                 },        /* P.TRAP */
16846     { instruction         , 0                   , 0   , 32,
16847        0xfc0003ff, 0x20000008, &NMD::SEB              , 0,
16848        XMMS_               },        /* SEB */
16849     { instruction         , 0                   , 0   , 32,
16850        0xfc0003ff, 0x20000010, &NMD::SLLV             , 0,
16851        0x0                 },        /* SLLV */
16852     { instruction         , 0                   , 0   , 32,
16853        0xfc0003ff, 0x20000018, &NMD::MUL_32_          , 0,
16854        0x0                 },        /* MUL[32] */
16855     { reserved_block      , 0                   , 0   , 32,
16856        0xfc0003ff, 0x20000020, 0                      , 0,
16857        0x0                 },        /* _POOL32A0~*(4) */
16858     { reserved_block      , 0                   , 0   , 32,
16859        0xfc0003ff, 0x20000028, 0                      , 0,
16860        0x0                 },        /* _POOL32A0~*(5) */
16861     { instruction         , 0                   , 0   , 32,
16862        0xfc0003ff, 0x20000030, &NMD::MFC0             , 0,
16863        0x0                 },        /* MFC0 */
16864     { instruction         , 0                   , 0   , 32,
16865        0xfc0003ff, 0x20000038, &NMD::MFHC0            , 0,
16866        CP0_ | MVH_         },        /* MFHC0 */
16867     { reserved_block      , 0                   , 0   , 32,
16868        0xfc0003ff, 0x20000040, 0                      , 0,
16869        0x0                 },        /* _POOL32A0~*(8) */
16870     { instruction         , 0                   , 0   , 32,
16871        0xfc0003ff, 0x20000048, &NMD::SEH              , 0,
16872        0x0                 },        /* SEH */
16873     { instruction         , 0                   , 0   , 32,
16874        0xfc0003ff, 0x20000050, &NMD::SRLV             , 0,
16875        0x0                 },        /* SRLV */
16876     { instruction         , 0                   , 0   , 32,
16877        0xfc0003ff, 0x20000058, &NMD::MUH              , 0,
16878        0x0                 },        /* MUH */
16879     { reserved_block      , 0                   , 0   , 32,
16880        0xfc0003ff, 0x20000060, 0                      , 0,
16881        0x0                 },        /* _POOL32A0~*(12) */
16882     { reserved_block      , 0                   , 0   , 32,
16883        0xfc0003ff, 0x20000068, 0                      , 0,
16884        0x0                 },        /* _POOL32A0~*(13) */
16885     { instruction         , 0                   , 0   , 32,
16886        0xfc0003ff, 0x20000070, &NMD::MTC0             , 0,
16887        CP0_                },        /* MTC0 */
16888     { instruction         , 0                   , 0   , 32,
16889        0xfc0003ff, 0x20000078, &NMD::MTHC0            , 0,
16890        CP0_ | MVH_         },        /* MTHC0 */
16891     { reserved_block      , 0                   , 0   , 32,
16892        0xfc0003ff, 0x20000080, 0                      , 0,
16893        0x0                 },        /* _POOL32A0~*(16) */
16894     { reserved_block      , 0                   , 0   , 32,
16895        0xfc0003ff, 0x20000088, 0                      , 0,
16896        0x0                 },        /* _POOL32A0~*(17) */
16897     { instruction         , 0                   , 0   , 32,
16898        0xfc0003ff, 0x20000090, &NMD::SRAV             , 0,
16899        0x0                 },        /* SRAV */
16900     { instruction         , 0                   , 0   , 32,
16901        0xfc0003ff, 0x20000098, &NMD::MULU             , 0,
16902        0x0                 },        /* MULU */
16903     { reserved_block      , 0                   , 0   , 32,
16904        0xfc0003ff, 0x200000a0, 0                      , 0,
16905        0x0                 },        /* _POOL32A0~*(20) */
16906     { reserved_block      , 0                   , 0   , 32,
16907        0xfc0003ff, 0x200000a8, 0                      , 0,
16908        0x0                 },        /* _POOL32A0~*(21) */
16909     { instruction         , 0                   , 0   , 32,
16910        0xfc0003ff, 0x200000b0, &NMD::MFGC0            , 0,
16911        CP0_ | VZ_          },        /* MFGC0 */
16912     { instruction         , 0                   , 0   , 32,
16913        0xfc0003ff, 0x200000b8, &NMD::MFHGC0           , 0,
16914        CP0_ | VZ_ | MVH_   },        /* MFHGC0 */
16915     { reserved_block      , 0                   , 0   , 32,
16916        0xfc0003ff, 0x200000c0, 0                      , 0,
16917        0x0                 },        /* _POOL32A0~*(24) */
16918     { reserved_block      , 0                   , 0   , 32,
16919        0xfc0003ff, 0x200000c8, 0                      , 0,
16920        0x0                 },        /* _POOL32A0~*(25) */
16921     { instruction         , 0                   , 0   , 32,
16922        0xfc0003ff, 0x200000d0, &NMD::ROTRV            , 0,
16923        0x0                 },        /* ROTRV */
16924     { instruction         , 0                   , 0   , 32,
16925        0xfc0003ff, 0x200000d8, &NMD::MUHU             , 0,
16926        0x0                 },        /* MUHU */
16927     { reserved_block      , 0                   , 0   , 32,
16928        0xfc0003ff, 0x200000e0, 0                      , 0,
16929        0x0                 },        /* _POOL32A0~*(28) */
16930     { reserved_block      , 0                   , 0   , 32,
16931        0xfc0003ff, 0x200000e8, 0                      , 0,
16932        0x0                 },        /* _POOL32A0~*(29) */
16933     { instruction         , 0                   , 0   , 32,
16934        0xfc0003ff, 0x200000f0, &NMD::MTGC0            , 0,
16935        CP0_ | VZ_          },        /* MTGC0 */
16936     { instruction         , 0                   , 0   , 32,
16937        0xfc0003ff, 0x200000f8, &NMD::MTHGC0           , 0,
16938        CP0_ | VZ_ | MVH_   },        /* MTHGC0 */
16939     { reserved_block      , 0                   , 0   , 32,
16940        0xfc0003ff, 0x20000100, 0                      , 0,
16941        0x0                 },        /* _POOL32A0~*(32) */
16942     { reserved_block      , 0                   , 0   , 32,
16943        0xfc0003ff, 0x20000108, 0                      , 0,
16944        0x0                 },        /* _POOL32A0~*(33) */
16945     { instruction         , 0                   , 0   , 32,
16946        0xfc0003ff, 0x20000110, &NMD::ADD              , 0,
16947        XMMS_               },        /* ADD */
16948     { instruction         , 0                   , 0   , 32,
16949        0xfc0003ff, 0x20000118, &NMD::DIV              , 0,
16950        0x0                 },        /* DIV */
16951     { reserved_block      , 0                   , 0   , 32,
16952        0xfc0003ff, 0x20000120, 0                      , 0,
16953        0x0                 },        /* _POOL32A0~*(36) */
16954     { reserved_block      , 0                   , 0   , 32,
16955        0xfc0003ff, 0x20000128, 0                      , 0,
16956        0x0                 },        /* _POOL32A0~*(37) */
16957     { instruction         , 0                   , 0   , 32,
16958        0xfc0003ff, 0x20000130, &NMD::DMFC0            , 0,
16959        CP0_ | MIPS64_      },        /* DMFC0 */
16960     { reserved_block      , 0                   , 0   , 32,
16961        0xfc0003ff, 0x20000138, 0                      , 0,
16962        0x0                 },        /* _POOL32A0~*(39) */
16963     { reserved_block      , 0                   , 0   , 32,
16964        0xfc0003ff, 0x20000140, 0                      , 0,
16965        0x0                 },        /* _POOL32A0~*(40) */
16966     { reserved_block      , 0                   , 0   , 32,
16967        0xfc0003ff, 0x20000148, 0                      , 0,
16968        0x0                 },        /* _POOL32A0~*(41) */
16969     { instruction         , 0                   , 0   , 32,
16970        0xfc0003ff, 0x20000150, &NMD::ADDU_32_         , 0,
16971        0x0                 },        /* ADDU[32] */
16972     { instruction         , 0                   , 0   , 32,
16973        0xfc0003ff, 0x20000158, &NMD::MOD              , 0,
16974        0x0                 },        /* MOD */
16975     { reserved_block      , 0                   , 0   , 32,
16976        0xfc0003ff, 0x20000160, 0                      , 0,
16977        0x0                 },        /* _POOL32A0~*(44) */
16978     { reserved_block      , 0                   , 0   , 32,
16979        0xfc0003ff, 0x20000168, 0                      , 0,
16980        0x0                 },        /* _POOL32A0~*(45) */
16981     { instruction         , 0                   , 0   , 32,
16982        0xfc0003ff, 0x20000170, &NMD::DMTC0            , 0,
16983        CP0_ | MIPS64_      },        /* DMTC0 */
16984     { reserved_block      , 0                   , 0   , 32,
16985        0xfc0003ff, 0x20000178, 0                      , 0,
16986        0x0                 },        /* _POOL32A0~*(47) */
16987     { reserved_block      , 0                   , 0   , 32,
16988        0xfc0003ff, 0x20000180, 0                      , 0,
16989        0x0                 },        /* _POOL32A0~*(48) */
16990     { reserved_block      , 0                   , 0   , 32,
16991        0xfc0003ff, 0x20000188, 0                      , 0,
16992        0x0                 },        /* _POOL32A0~*(49) */
16993     { instruction         , 0                   , 0   , 32,
16994        0xfc0003ff, 0x20000190, &NMD::SUB              , 0,
16995        XMMS_               },        /* SUB */
16996     { instruction         , 0                   , 0   , 32,
16997        0xfc0003ff, 0x20000198, &NMD::DIVU             , 0,
16998        0x0                 },        /* DIVU */
16999     { reserved_block      , 0                   , 0   , 32,
17000        0xfc0003ff, 0x200001a0, 0                      , 0,
17001        0x0                 },        /* _POOL32A0~*(52) */
17002     { reserved_block      , 0                   , 0   , 32,
17003        0xfc0003ff, 0x200001a8, 0                      , 0,
17004        0x0                 },        /* _POOL32A0~*(53) */
17005     { instruction         , 0                   , 0   , 32,
17006        0xfc0003ff, 0x200001b0, &NMD::DMFGC0           , 0,
17007        CP0_ | MIPS64_ | VZ_},        /* DMFGC0 */
17008     { reserved_block      , 0                   , 0   , 32,
17009        0xfc0003ff, 0x200001b8, 0                      , 0,
17010        0x0                 },        /* _POOL32A0~*(55) */
17011     { instruction         , 0                   , 0   , 32,
17012        0xfc0003ff, 0x200001c0, &NMD::RDHWR            , 0,
17013        XMMS_               },        /* RDHWR */
17014     { reserved_block      , 0                   , 0   , 32,
17015        0xfc0003ff, 0x200001c8, 0                      , 0,
17016        0x0                 },        /* _POOL32A0~*(57) */
17017     { instruction         , 0                   , 0   , 32,
17018        0xfc0003ff, 0x200001d0, &NMD::SUBU_32_         , 0,
17019        0x0                 },        /* SUBU[32] */
17020     { instruction         , 0                   , 0   , 32,
17021        0xfc0003ff, 0x200001d8, &NMD::MODU             , 0,
17022        0x0                 },        /* MODU */
17023     { reserved_block      , 0                   , 0   , 32,
17024        0xfc0003ff, 0x200001e0, 0                      , 0,
17025        0x0                 },        /* _POOL32A0~*(60) */
17026     { reserved_block      , 0                   , 0   , 32,
17027        0xfc0003ff, 0x200001e8, 0                      , 0,
17028        0x0                 },        /* _POOL32A0~*(61) */
17029     { instruction         , 0                   , 0   , 32,
17030        0xfc0003ff, 0x200001f0, &NMD::DMTGC0           , 0,
17031        CP0_ | MIPS64_ | VZ_},        /* DMTGC0 */
17032     { reserved_block      , 0                   , 0   , 32,
17033        0xfc0003ff, 0x200001f8, 0                      , 0,
17034        0x0                 },        /* _POOL32A0~*(63) */
17035     { reserved_block      , 0                   , 0   , 32,
17036        0xfc0003ff, 0x20000200, 0                      , 0,
17037        0x0                 },        /* _POOL32A0~*(64) */
17038     { reserved_block      , 0                   , 0   , 32,
17039        0xfc0003ff, 0x20000208, 0                      , 0,
17040        0x0                 },        /* _POOL32A0~*(65) */
17041     { pool                , P_CMOVE             , 2   , 32,
17042        0xfc0003ff, 0x20000210, 0                      , 0,
17043        0x0                 },        /* P.CMOVE */
17044     { reserved_block      , 0                   , 0   , 32,
17045        0xfc0003ff, 0x20000218, 0                      , 0,
17046        0x0                 },        /* _POOL32A0~*(67) */
17047     { reserved_block      , 0                   , 0   , 32,
17048        0xfc0003ff, 0x20000220, 0                      , 0,
17049        0x0                 },        /* _POOL32A0~*(68) */
17050     { instruction         , 0                   , 0   , 32,
17051        0xfc0003ff, 0x20000228, &NMD::FORK             , 0,
17052        MT_                 },        /* FORK */
17053     { instruction         , 0                   , 0   , 32,
17054        0xfc0003ff, 0x20000230, &NMD::MFTR             , 0,
17055        MT_                 },        /* MFTR */
17056     { instruction         , 0                   , 0   , 32,
17057        0xfc0003ff, 0x20000238, &NMD::MFHTR            , 0,
17058        MT_                 },        /* MFHTR */
17059     { reserved_block      , 0                   , 0   , 32,
17060        0xfc0003ff, 0x20000240, 0                      , 0,
17061        0x0                 },        /* _POOL32A0~*(72) */
17062     { reserved_block      , 0                   , 0   , 32,
17063        0xfc0003ff, 0x20000248, 0                      , 0,
17064        0x0                 },        /* _POOL32A0~*(73) */
17065     { instruction         , 0                   , 0   , 32,
17066        0xfc0003ff, 0x20000250, &NMD::AND_32_          , 0,
17067        0x0                 },        /* AND[32] */
17068     { reserved_block      , 0                   , 0   , 32,
17069        0xfc0003ff, 0x20000258, 0                      , 0,
17070        0x0                 },        /* _POOL32A0~*(75) */
17071     { reserved_block      , 0                   , 0   , 32,
17072        0xfc0003ff, 0x20000260, 0                      , 0,
17073        0x0                 },        /* _POOL32A0~*(76) */
17074     { instruction         , 0                   , 0   , 32,
17075        0xfc0003ff, 0x20000268, &NMD::YIELD            , 0,
17076        MT_                 },        /* YIELD */
17077     { instruction         , 0                   , 0   , 32,
17078        0xfc0003ff, 0x20000270, &NMD::MTTR             , 0,
17079        MT_                 },        /* MTTR */
17080     { instruction         , 0                   , 0   , 32,
17081        0xfc0003ff, 0x20000278, &NMD::MTHTR            , 0,
17082        MT_                 },        /* MTHTR */
17083     { reserved_block      , 0                   , 0   , 32,
17084        0xfc0003ff, 0x20000280, 0                      , 0,
17085        0x0                 },        /* _POOL32A0~*(80) */
17086     { reserved_block      , 0                   , 0   , 32,
17087        0xfc0003ff, 0x20000288, 0                      , 0,
17088        0x0                 },        /* _POOL32A0~*(81) */
17089     { instruction         , 0                   , 0   , 32,
17090        0xfc0003ff, 0x20000290, &NMD::OR_32_           , 0,
17091        0x0                 },        /* OR[32] */
17092     { reserved_block      , 0                   , 0   , 32,
17093        0xfc0003ff, 0x20000298, 0                      , 0,
17094        0x0                 },        /* _POOL32A0~*(83) */
17095     { reserved_block      , 0                   , 0   , 32,
17096        0xfc0003ff, 0x200002a0, 0                      , 0,
17097        0x0                 },        /* _POOL32A0~*(84) */
17098     { reserved_block      , 0                   , 0   , 32,
17099        0xfc0003ff, 0x200002a8, 0                      , 0,
17100        0x0                 },        /* _POOL32A0~*(85) */
17101     { pool                , P_MT_VPE            , 8   , 32,
17102        0xfc0003ff, 0x200002b0, 0                      , 0,
17103        0x0                 },        /* P.MT_VPE */
17104     { reserved_block      , 0                   , 0   , 32,
17105        0xfc0003ff, 0x200002b8, 0                      , 0,
17106        0x0                 },        /* _POOL32A0~*(87) */
17107     { reserved_block      , 0                   , 0   , 32,
17108        0xfc0003ff, 0x200002c0, 0                      , 0,
17109        0x0                 },        /* _POOL32A0~*(88) */
17110     { reserved_block      , 0                   , 0   , 32,
17111        0xfc0003ff, 0x200002c8, 0                      , 0,
17112        0x0                 },        /* _POOL32A0~*(89) */
17113     { instruction         , 0                   , 0   , 32,
17114        0xfc0003ff, 0x200002d0, &NMD::NOR              , 0,
17115        0x0                 },        /* NOR */
17116     { reserved_block      , 0                   , 0   , 32,
17117        0xfc0003ff, 0x200002d8, 0                      , 0,
17118        0x0                 },        /* _POOL32A0~*(91) */
17119     { reserved_block      , 0                   , 0   , 32,
17120        0xfc0003ff, 0x200002e0, 0                      , 0,
17121        0x0                 },        /* _POOL32A0~*(92) */
17122     { reserved_block      , 0                   , 0   , 32,
17123        0xfc0003ff, 0x200002e8, 0                      , 0,
17124        0x0                 },        /* _POOL32A0~*(93) */
17125     { reserved_block      , 0                   , 0   , 32,
17126        0xfc0003ff, 0x200002f0, 0                      , 0,
17127        0x0                 },        /* _POOL32A0~*(94) */
17128     { reserved_block      , 0                   , 0   , 32,
17129        0xfc0003ff, 0x200002f8, 0                      , 0,
17130        0x0                 },        /* _POOL32A0~*(95) */
17131     { reserved_block      , 0                   , 0   , 32,
17132        0xfc0003ff, 0x20000300, 0                      , 0,
17133        0x0                 },        /* _POOL32A0~*(96) */
17134     { reserved_block      , 0                   , 0   , 32,
17135        0xfc0003ff, 0x20000308, 0                      , 0,
17136        0x0                 },        /* _POOL32A0~*(97) */
17137     { instruction         , 0                   , 0   , 32,
17138        0xfc0003ff, 0x20000310, &NMD::XOR_32_          , 0,
17139        0x0                 },        /* XOR[32] */
17140     { reserved_block      , 0                   , 0   , 32,
17141        0xfc0003ff, 0x20000318, 0                      , 0,
17142        0x0                 },        /* _POOL32A0~*(99) */
17143     { reserved_block      , 0                   , 0   , 32,
17144        0xfc0003ff, 0x20000320, 0                      , 0,
17145        0x0                 },        /* _POOL32A0~*(100) */
17146     { reserved_block      , 0                   , 0   , 32,
17147        0xfc0003ff, 0x20000328, 0                      , 0,
17148        0x0                 },        /* _POOL32A0~*(101) */
17149     { reserved_block      , 0                   , 0   , 32,
17150        0xfc0003ff, 0x20000330, 0                      , 0,
17151        0x0                 },        /* _POOL32A0~*(102) */
17152     { reserved_block      , 0                   , 0   , 32,
17153        0xfc0003ff, 0x20000338, 0                      , 0,
17154        0x0                 },        /* _POOL32A0~*(103) */
17155     { reserved_block      , 0                   , 0   , 32,
17156        0xfc0003ff, 0x20000340, 0                      , 0,
17157        0x0                 },        /* _POOL32A0~*(104) */
17158     { reserved_block      , 0                   , 0   , 32,
17159        0xfc0003ff, 0x20000348, 0                      , 0,
17160        0x0                 },        /* _POOL32A0~*(105) */
17161     { instruction         , 0                   , 0   , 32,
17162        0xfc0003ff, 0x20000350, &NMD::SLT              , 0,
17163        0x0                 },        /* SLT */
17164     { reserved_block      , 0                   , 0   , 32,
17165        0xfc0003ff, 0x20000358, 0                      , 0,
17166        0x0                 },        /* _POOL32A0~*(107) */
17167     { reserved_block      , 0                   , 0   , 32,
17168        0xfc0003ff, 0x20000360, 0                      , 0,
17169        0x0                 },        /* _POOL32A0~*(108) */
17170     { reserved_block      , 0                   , 0   , 32,
17171        0xfc0003ff, 0x20000368, 0                      , 0,
17172        0x0                 },        /* _POOL32A0~*(109) */
17173     { reserved_block      , 0                   , 0   , 32,
17174        0xfc0003ff, 0x20000370, 0                      , 0,
17175        0x0                 },        /* _POOL32A0~*(110) */
17176     { reserved_block      , 0                   , 0   , 32,
17177        0xfc0003ff, 0x20000378, 0                      , 0,
17178        0x0                 },        /* _POOL32A0~*(111) */
17179     { reserved_block      , 0                   , 0   , 32,
17180        0xfc0003ff, 0x20000380, 0                      , 0,
17181        0x0                 },        /* _POOL32A0~*(112) */
17182     { reserved_block      , 0                   , 0   , 32,
17183        0xfc0003ff, 0x20000388, 0                      , 0,
17184        0x0                 },        /* _POOL32A0~*(113) */
17185     { pool                , P_SLTU              , 2   , 32,
17186        0xfc0003ff, 0x20000390, 0                      , 0,
17187        0x0                 },        /* P.SLTU */
17188     { reserved_block      , 0                   , 0   , 32,
17189        0xfc0003ff, 0x20000398, 0                      , 0,
17190        0x0                 },        /* _POOL32A0~*(115) */
17191     { reserved_block      , 0                   , 0   , 32,
17192        0xfc0003ff, 0x200003a0, 0                      , 0,
17193        0x0                 },        /* _POOL32A0~*(116) */
17194     { reserved_block      , 0                   , 0   , 32,
17195        0xfc0003ff, 0x200003a8, 0                      , 0,
17196        0x0                 },        /* _POOL32A0~*(117) */
17197     { reserved_block      , 0                   , 0   , 32,
17198        0xfc0003ff, 0x200003b0, 0                      , 0,
17199        0x0                 },        /* _POOL32A0~*(118) */
17200     { reserved_block      , 0                   , 0   , 32,
17201        0xfc0003ff, 0x200003b8, 0                      , 0,
17202        0x0                 },        /* _POOL32A0~*(119) */
17203     { reserved_block      , 0                   , 0   , 32,
17204        0xfc0003ff, 0x200003c0, 0                      , 0,
17205        0x0                 },        /* _POOL32A0~*(120) */
17206     { reserved_block      , 0                   , 0   , 32,
17207        0xfc0003ff, 0x200003c8, 0                      , 0,
17208        0x0                 },        /* _POOL32A0~*(121) */
17209     { instruction         , 0                   , 0   , 32,
17210        0xfc0003ff, 0x200003d0, &NMD::SOV              , 0,
17211        0x0                 },        /* SOV */
17212     { reserved_block      , 0                   , 0   , 32,
17213        0xfc0003ff, 0x200003d8, 0                      , 0,
17214        0x0                 },        /* _POOL32A0~*(123) */
17215     { reserved_block      , 0                   , 0   , 32,
17216        0xfc0003ff, 0x200003e0, 0                      , 0,
17217        0x0                 },        /* _POOL32A0~*(124) */
17218     { reserved_block      , 0                   , 0   , 32,
17219        0xfc0003ff, 0x200003e8, 0                      , 0,
17220        0x0                 },        /* _POOL32A0~*(125) */
17221     { reserved_block      , 0                   , 0   , 32,
17222        0xfc0003ff, 0x200003f0, 0                      , 0,
17223        0x0                 },        /* _POOL32A0~*(126) */
17224     { reserved_block      , 0                   , 0   , 32,
17225        0xfc0003ff, 0x200003f8, 0                      , 0,
17226        0x0                 },        /* _POOL32A0~*(127) */
17227 };
17228
17229
17230 NMD::Pool NMD::ADDQ__S__PH[2] = {
17231     { instruction         , 0                   , 0   , 32,
17232        0xfc0007ff, 0x2000000d, &NMD::ADDQ_PH          , 0,
17233        DSP_                },        /* ADDQ.PH */
17234     { instruction         , 0                   , 0   , 32,
17235        0xfc0007ff, 0x2000040d, &NMD::ADDQ_S_PH        , 0,
17236        DSP_                },        /* ADDQ_S.PH */
17237 };
17238
17239
17240 NMD::Pool NMD::MUL__S__PH[2] = {
17241     { instruction         , 0                   , 0   , 32,
17242        0xfc0007ff, 0x2000002d, &NMD::MUL_PH           , 0,
17243        DSP_                },        /* MUL.PH */
17244     { instruction         , 0                   , 0   , 32,
17245        0xfc0007ff, 0x2000042d, &NMD::MUL_S_PH         , 0,
17246        DSP_                },        /* MUL_S.PH */
17247 };
17248
17249
17250 NMD::Pool NMD::ADDQH__R__PH[2] = {
17251     { instruction         , 0                   , 0   , 32,
17252        0xfc0007ff, 0x2000004d, &NMD::ADDQH_PH         , 0,
17253        DSP_                },        /* ADDQH.PH */
17254     { instruction         , 0                   , 0   , 32,
17255        0xfc0007ff, 0x2000044d, &NMD::ADDQH_R_PH       , 0,
17256        DSP_                },        /* ADDQH_R.PH */
17257 };
17258
17259
17260 NMD::Pool NMD::ADDQH__R__W[2] = {
17261     { instruction         , 0                   , 0   , 32,
17262        0xfc0007ff, 0x2000008d, &NMD::ADDQH_W          , 0,
17263        DSP_                },        /* ADDQH.W */
17264     { instruction         , 0                   , 0   , 32,
17265        0xfc0007ff, 0x2000048d, &NMD::ADDQH_R_W        , 0,
17266        DSP_                },        /* ADDQH_R.W */
17267 };
17268
17269
17270 NMD::Pool NMD::ADDU__S__QB[2] = {
17271     { instruction         , 0                   , 0   , 32,
17272        0xfc0007ff, 0x200000cd, &NMD::ADDU_QB          , 0,
17273        DSP_                },        /* ADDU.QB */
17274     { instruction         , 0                   , 0   , 32,
17275        0xfc0007ff, 0x200004cd, &NMD::ADDU_S_QB        , 0,
17276        DSP_                },        /* ADDU_S.QB */
17277 };
17278
17279
17280 NMD::Pool NMD::ADDU__S__PH[2] = {
17281     { instruction         , 0                   , 0   , 32,
17282        0xfc0007ff, 0x2000010d, &NMD::ADDU_PH          , 0,
17283        DSP_                },        /* ADDU.PH */
17284     { instruction         , 0                   , 0   , 32,
17285        0xfc0007ff, 0x2000050d, &NMD::ADDU_S_PH        , 0,
17286        DSP_                },        /* ADDU_S.PH */
17287 };
17288
17289
17290 NMD::Pool NMD::ADDUH__R__QB[2] = {
17291     { instruction         , 0                   , 0   , 32,
17292        0xfc0007ff, 0x2000014d, &NMD::ADDUH_QB         , 0,
17293        DSP_                },        /* ADDUH.QB */
17294     { instruction         , 0                   , 0   , 32,
17295        0xfc0007ff, 0x2000054d, &NMD::ADDUH_R_QB       , 0,
17296        DSP_                },        /* ADDUH_R.QB */
17297 };
17298
17299
17300 NMD::Pool NMD::SHRAV__R__PH[2] = {
17301     { instruction         , 0                   , 0   , 32,
17302        0xfc0007ff, 0x2000018d, &NMD::SHRAV_PH         , 0,
17303        DSP_                },        /* SHRAV.PH */
17304     { instruction         , 0                   , 0   , 32,
17305        0xfc0007ff, 0x2000058d, &NMD::SHRAV_R_PH       , 0,
17306        DSP_                },        /* SHRAV_R.PH */
17307 };
17308
17309
17310 NMD::Pool NMD::SHRAV__R__QB[2] = {
17311     { instruction         , 0                   , 0   , 32,
17312        0xfc0007ff, 0x200001cd, &NMD::SHRAV_QB         , 0,
17313        DSP_                },        /* SHRAV.QB */
17314     { instruction         , 0                   , 0   , 32,
17315        0xfc0007ff, 0x200005cd, &NMD::SHRAV_R_QB       , 0,
17316        DSP_                },        /* SHRAV_R.QB */
17317 };
17318
17319
17320 NMD::Pool NMD::SUBQ__S__PH[2] = {
17321     { instruction         , 0                   , 0   , 32,
17322        0xfc0007ff, 0x2000020d, &NMD::SUBQ_PH          , 0,
17323        DSP_                },        /* SUBQ.PH */
17324     { instruction         , 0                   , 0   , 32,
17325        0xfc0007ff, 0x2000060d, &NMD::SUBQ_S_PH        , 0,
17326        DSP_                },        /* SUBQ_S.PH */
17327 };
17328
17329
17330 NMD::Pool NMD::SUBQH__R__PH[2] = {
17331     { instruction         , 0                   , 0   , 32,
17332        0xfc0007ff, 0x2000024d, &NMD::SUBQH_PH         , 0,
17333        DSP_                },        /* SUBQH.PH */
17334     { instruction         , 0                   , 0   , 32,
17335        0xfc0007ff, 0x2000064d, &NMD::SUBQH_R_PH       , 0,
17336        DSP_                },        /* SUBQH_R.PH */
17337 };
17338
17339
17340 NMD::Pool NMD::SUBQH__R__W[2] = {
17341     { instruction         , 0                   , 0   , 32,
17342        0xfc0007ff, 0x2000028d, &NMD::SUBQH_W          , 0,
17343        DSP_                },        /* SUBQH.W */
17344     { instruction         , 0                   , 0   , 32,
17345        0xfc0007ff, 0x2000068d, &NMD::SUBQH_R_W        , 0,
17346        DSP_                },        /* SUBQH_R.W */
17347 };
17348
17349
17350 NMD::Pool NMD::SUBU__S__QB[2] = {
17351     { instruction         , 0                   , 0   , 32,
17352        0xfc0007ff, 0x200002cd, &NMD::SUBU_QB          , 0,
17353        DSP_                },        /* SUBU.QB */
17354     { instruction         , 0                   , 0   , 32,
17355        0xfc0007ff, 0x200006cd, &NMD::SUBU_S_QB        , 0,
17356        DSP_                },        /* SUBU_S.QB */
17357 };
17358
17359
17360 NMD::Pool NMD::SUBU__S__PH[2] = {
17361     { instruction         , 0                   , 0   , 32,
17362        0xfc0007ff, 0x2000030d, &NMD::SUBU_PH          , 0,
17363        DSP_                },        /* SUBU.PH */
17364     { instruction         , 0                   , 0   , 32,
17365        0xfc0007ff, 0x2000070d, &NMD::SUBU_S_PH        , 0,
17366        DSP_                },        /* SUBU_S.PH */
17367 };
17368
17369
17370 NMD::Pool NMD::SHRA__R__PH[2] = {
17371     { instruction         , 0                   , 0   , 32,
17372        0xfc0007ff, 0x20000335, &NMD::SHRA_PH          , 0,
17373        DSP_                },        /* SHRA.PH */
17374     { instruction         , 0                   , 0   , 32,
17375        0xfc0007ff, 0x20000735, &NMD::SHRA_R_PH        , 0,
17376        DSP_                },        /* SHRA_R.PH */
17377 };
17378
17379
17380 NMD::Pool NMD::SUBUH__R__QB[2] = {
17381     { instruction         , 0                   , 0   , 32,
17382        0xfc0007ff, 0x2000034d, &NMD::SUBUH_QB         , 0,
17383        DSP_                },        /* SUBUH.QB */
17384     { instruction         , 0                   , 0   , 32,
17385        0xfc0007ff, 0x2000074d, &NMD::SUBUH_R_QB       , 0,
17386        DSP_                },        /* SUBUH_R.QB */
17387 };
17388
17389
17390 NMD::Pool NMD::SHLLV__S__PH[2] = {
17391     { instruction         , 0                   , 0   , 32,
17392        0xfc0007ff, 0x2000038d, &NMD::SHLLV_PH         , 0,
17393        DSP_                },        /* SHLLV.PH */
17394     { instruction         , 0                   , 0   , 32,
17395        0xfc0007ff, 0x2000078d, &NMD::SHLLV_S_PH       , 0,
17396        DSP_                },        /* SHLLV_S.PH */
17397 };
17398
17399
17400 NMD::Pool NMD::SHLL__S__PH[4] = {
17401     { instruction         , 0                   , 0   , 32,
17402        0xfc000fff, 0x200003b5, &NMD::SHLL_PH          , 0,
17403        DSP_                },        /* SHLL.PH */
17404     { reserved_block      , 0                   , 0   , 32,
17405        0xfc000fff, 0x200007b5, 0                      , 0,
17406        0x0                 },        /* SHLL[_S].PH~*(1) */
17407     { instruction         , 0                   , 0   , 32,
17408        0xfc000fff, 0x20000bb5, &NMD::SHLL_S_PH        , 0,
17409        DSP_                },        /* SHLL_S.PH */
17410     { reserved_block      , 0                   , 0   , 32,
17411        0xfc000fff, 0x20000fb5, 0                      , 0,
17412        0x0                 },        /* SHLL[_S].PH~*(3) */
17413 };
17414
17415
17416 NMD::Pool NMD::PRECR_SRA__R__PH_W[2] = {
17417     { instruction         , 0                   , 0   , 32,
17418        0xfc0007ff, 0x200003cd, &NMD::PRECR_SRA_PH_W   , 0,
17419        DSP_                },        /* PRECR_SRA.PH.W */
17420     { instruction         , 0                   , 0   , 32,
17421        0xfc0007ff, 0x200007cd, &NMD::PRECR_SRA_R_PH_W , 0,
17422        DSP_                },        /* PRECR_SRA_R.PH.W */
17423 };
17424
17425
17426 NMD::Pool NMD::_POOL32A5[128] = {
17427     { instruction         , 0                   , 0   , 32,
17428        0xfc0003ff, 0x20000005, &NMD::CMP_EQ_PH        , 0,
17429        DSP_                },        /* CMP.EQ.PH */
17430     { pool                , ADDQ__S__PH         , 2   , 32,
17431        0xfc0003ff, 0x2000000d, 0                      , 0,
17432        0x0                 },        /* ADDQ[_S].PH */
17433     { reserved_block      , 0                   , 0   , 32,
17434        0xfc0003ff, 0x20000015, 0                      , 0,
17435        0x0                 },        /* _POOL32A5~*(2) */
17436     { instruction         , 0                   , 0   , 32,
17437        0xfc0003ff, 0x2000001d, &NMD::SHILO            , 0,
17438        DSP_                },        /* SHILO */
17439     { instruction         , 0                   , 0   , 32,
17440        0xfc0003ff, 0x20000025, &NMD::MULEQ_S_W_PHL    , 0,
17441        DSP_                },        /* MULEQ_S.W.PHL */
17442     { pool                , MUL__S__PH          , 2   , 32,
17443        0xfc0003ff, 0x2000002d, 0                      , 0,
17444        0x0                 },        /* MUL[_S].PH */
17445     { reserved_block      , 0                   , 0   , 32,
17446        0xfc0003ff, 0x20000035, 0                      , 0,
17447        0x0                 },        /* _POOL32A5~*(6) */
17448     { instruction         , 0                   , 0   , 32,
17449        0xfc0003ff, 0x2000003d, &NMD::REPL_PH          , 0,
17450        DSP_                },        /* REPL.PH */
17451     { instruction         , 0                   , 0   , 32,
17452        0xfc0003ff, 0x20000045, &NMD::CMP_LT_PH        , 0,
17453        DSP_                },        /* CMP.LT.PH */
17454     { pool                , ADDQH__R__PH        , 2   , 32,
17455        0xfc0003ff, 0x2000004d, 0                      , 0,
17456        0x0                 },        /* ADDQH[_R].PH */
17457     { reserved_block      , 0                   , 0   , 32,
17458        0xfc0003ff, 0x20000055, 0                      , 0,
17459        0x0                 },        /* _POOL32A5~*(10) */
17460     { reserved_block      , 0                   , 0   , 32,
17461        0xfc0003ff, 0x2000005d, 0                      , 0,
17462        0x0                 },        /* _POOL32A5~*(11) */
17463     { instruction         , 0                   , 0   , 32,
17464        0xfc0003ff, 0x20000065, &NMD::MULEQ_S_W_PHR    , 0,
17465        DSP_                },        /* MULEQ_S.W.PHR */
17466     { instruction         , 0                   , 0   , 32,
17467        0xfc0003ff, 0x2000006d, &NMD::PRECR_QB_PH      , 0,
17468        DSP_                },        /* PRECR.QB.PH */
17469     { reserved_block      , 0                   , 0   , 32,
17470        0xfc0003ff, 0x20000075, 0                      , 0,
17471        0x0                 },        /* _POOL32A5~*(14) */
17472     { reserved_block      , 0                   , 0   , 32,
17473        0xfc0003ff, 0x2000007d, 0                      , 0,
17474        0x0                 },        /* _POOL32A5~*(15) */
17475     { instruction         , 0                   , 0   , 32,
17476        0xfc0003ff, 0x20000085, &NMD::CMP_LE_PH        , 0,
17477        DSP_                },        /* CMP.LE.PH */
17478     { pool                , ADDQH__R__W         , 2   , 32,
17479        0xfc0003ff, 0x2000008d, 0                      , 0,
17480        0x0                 },        /* ADDQH[_R].W */
17481     { instruction         , 0                   , 0   , 32,
17482        0xfc0003ff, 0x20000095, &NMD::MULEU_S_PH_QBL   , 0,
17483        DSP_                },        /* MULEU_S.PH.QBL */
17484     { reserved_block      , 0                   , 0   , 32,
17485        0xfc0003ff, 0x2000009d, 0                      , 0,
17486        0x0                 },        /* _POOL32A5~*(19) */
17487     { reserved_block      , 0                   , 0   , 32,
17488        0xfc0003ff, 0x200000a5, 0                      , 0,
17489        0x0                 },        /* _POOL32A5~*(20) */
17490     { instruction         , 0                   , 0   , 32,
17491        0xfc0003ff, 0x200000ad, &NMD::PRECRQ_QB_PH     , 0,
17492        DSP_                },        /* PRECRQ.QB.PH */
17493     { reserved_block      , 0                   , 0   , 32,
17494        0xfc0003ff, 0x200000b5, 0                      , 0,
17495        0x0                 },        /* _POOL32A5~*(22) */
17496     { reserved_block      , 0                   , 0   , 32,
17497        0xfc0003ff, 0x200000bd, 0                      , 0,
17498        0x0                 },        /* _POOL32A5~*(23) */
17499     { instruction         , 0                   , 0   , 32,
17500        0xfc0003ff, 0x200000c5, &NMD::CMPGU_EQ_QB      , 0,
17501        DSP_                },        /* CMPGU.EQ.QB */
17502     { pool                , ADDU__S__QB         , 2   , 32,
17503        0xfc0003ff, 0x200000cd, 0                      , 0,
17504        0x0                 },        /* ADDU[_S].QB */
17505     { instruction         , 0                   , 0   , 32,
17506        0xfc0003ff, 0x200000d5, &NMD::MULEU_S_PH_QBR   , 0,
17507        DSP_                },        /* MULEU_S.PH.QBR */
17508     { reserved_block      , 0                   , 0   , 32,
17509        0xfc0003ff, 0x200000dd, 0                      , 0,
17510        0x0                 },        /* _POOL32A5~*(27) */
17511     { reserved_block      , 0                   , 0   , 32,
17512        0xfc0003ff, 0x200000e5, 0                      , 0,
17513        0x0                 },        /* _POOL32A5~*(28) */
17514     { instruction         , 0                   , 0   , 32,
17515        0xfc0003ff, 0x200000ed, &NMD::PRECRQ_PH_W      , 0,
17516        DSP_                },        /* PRECRQ.PH.W */
17517     { reserved_block      , 0                   , 0   , 32,
17518        0xfc0003ff, 0x200000f5, 0                      , 0,
17519        0x0                 },        /* _POOL32A5~*(30) */
17520     { reserved_block      , 0                   , 0   , 32,
17521        0xfc0003ff, 0x200000fd, 0                      , 0,
17522        0x0                 },        /* _POOL32A5~*(31) */
17523     { instruction         , 0                   , 0   , 32,
17524        0xfc0003ff, 0x20000105, &NMD::CMPGU_LT_QB      , 0,
17525        DSP_                },        /* CMPGU.LT.QB */
17526     { pool                , ADDU__S__PH         , 2   , 32,
17527        0xfc0003ff, 0x2000010d, 0                      , 0,
17528        0x0                 },        /* ADDU[_S].PH */
17529     { instruction         , 0                   , 0   , 32,
17530        0xfc0003ff, 0x20000115, &NMD::MULQ_RS_PH       , 0,
17531        DSP_                },        /* MULQ_RS.PH */
17532     { reserved_block      , 0                   , 0   , 32,
17533        0xfc0003ff, 0x2000011d, 0                      , 0,
17534        0x0                 },        /* _POOL32A5~*(35) */
17535     { reserved_block      , 0                   , 0   , 32,
17536        0xfc0003ff, 0x20000125, 0                      , 0,
17537        0x0                 },        /* _POOL32A5~*(36) */
17538     { instruction         , 0                   , 0   , 32,
17539        0xfc0003ff, 0x2000012d, &NMD::PRECRQ_RS_PH_W   , 0,
17540        DSP_                },        /* PRECRQ_RS.PH.W */
17541     { reserved_block      , 0                   , 0   , 32,
17542        0xfc0003ff, 0x20000135, 0                      , 0,
17543        0x0                 },        /* _POOL32A5~*(38) */
17544     { reserved_block      , 0                   , 0   , 32,
17545        0xfc0003ff, 0x2000013d, 0                      , 0,
17546        0x0                 },        /* _POOL32A5~*(39) */
17547     { instruction         , 0                   , 0   , 32,
17548        0xfc0003ff, 0x20000145, &NMD::CMPGU_LE_QB      , 0,
17549        DSP_                },        /* CMPGU.LE.QB */
17550     { pool                , ADDUH__R__QB        , 2   , 32,
17551        0xfc0003ff, 0x2000014d, 0                      , 0,
17552        0x0                 },        /* ADDUH[_R].QB */
17553     { instruction         , 0                   , 0   , 32,
17554        0xfc0003ff, 0x20000155, &NMD::MULQ_S_PH        , 0,
17555        DSP_                },        /* MULQ_S.PH */
17556     { reserved_block      , 0                   , 0   , 32,
17557        0xfc0003ff, 0x2000015d, 0                      , 0,
17558        0x0                 },        /* _POOL32A5~*(43) */
17559     { reserved_block      , 0                   , 0   , 32,
17560        0xfc0003ff, 0x20000165, 0                      , 0,
17561        0x0                 },        /* _POOL32A5~*(44) */
17562     { instruction         , 0                   , 0   , 32,
17563        0xfc0003ff, 0x2000016d, &NMD::PRECRQU_S_QB_PH  , 0,
17564        DSP_                },        /* PRECRQU_S.QB.PH */
17565     { reserved_block      , 0                   , 0   , 32,
17566        0xfc0003ff, 0x20000175, 0                      , 0,
17567        0x0                 },        /* _POOL32A5~*(46) */
17568     { reserved_block      , 0                   , 0   , 32,
17569        0xfc0003ff, 0x2000017d, 0                      , 0,
17570        0x0                 },        /* _POOL32A5~*(47) */
17571     { instruction         , 0                   , 0   , 32,
17572        0xfc0003ff, 0x20000185, &NMD::CMPGDU_EQ_QB     , 0,
17573        DSP_                },        /* CMPGDU.EQ.QB */
17574     { pool                , SHRAV__R__PH        , 2   , 32,
17575        0xfc0003ff, 0x2000018d, 0                      , 0,
17576        0x0                 },        /* SHRAV[_R].PH */
17577     { instruction         , 0                   , 0   , 32,
17578        0xfc0003ff, 0x20000195, &NMD::MULQ_RS_W        , 0,
17579        DSP_                },        /* MULQ_RS.W */
17580     { reserved_block      , 0                   , 0   , 32,
17581        0xfc0003ff, 0x2000019d, 0                      , 0,
17582        0x0                 },        /* _POOL32A5~*(51) */
17583     { reserved_block      , 0                   , 0   , 32,
17584        0xfc0003ff, 0x200001a5, 0                      , 0,
17585        0x0                 },        /* _POOL32A5~*(52) */
17586     { instruction         , 0                   , 0   , 32,
17587        0xfc0003ff, 0x200001ad, &NMD::PACKRL_PH        , 0,
17588        DSP_                },        /* PACKRL.PH */
17589     { reserved_block      , 0                   , 0   , 32,
17590        0xfc0003ff, 0x200001b5, 0                      , 0,
17591        0x0                 },        /* _POOL32A5~*(54) */
17592     { reserved_block      , 0                   , 0   , 32,
17593        0xfc0003ff, 0x200001bd, 0                      , 0,
17594        0x0                 },        /* _POOL32A5~*(55) */
17595     { instruction         , 0                   , 0   , 32,
17596        0xfc0003ff, 0x200001c5, &NMD::CMPGDU_LT_QB     , 0,
17597        DSP_                },        /* CMPGDU.LT.QB */
17598     { pool                , SHRAV__R__QB        , 2   , 32,
17599        0xfc0003ff, 0x200001cd, 0                      , 0,
17600        0x0                 },        /* SHRAV[_R].QB */
17601     { instruction         , 0                   , 0   , 32,
17602        0xfc0003ff, 0x200001d5, &NMD::MULQ_S_W         , 0,
17603        DSP_                },        /* MULQ_S.W */
17604     { reserved_block      , 0                   , 0   , 32,
17605        0xfc0003ff, 0x200001dd, 0                      , 0,
17606        0x0                 },        /* _POOL32A5~*(59) */
17607     { reserved_block      , 0                   , 0   , 32,
17608        0xfc0003ff, 0x200001e5, 0                      , 0,
17609        0x0                 },        /* _POOL32A5~*(60) */
17610     { instruction         , 0                   , 0   , 32,
17611        0xfc0003ff, 0x200001ed, &NMD::PICK_QB          , 0,
17612        DSP_                },        /* PICK.QB */
17613     { reserved_block      , 0                   , 0   , 32,
17614        0xfc0003ff, 0x200001f5, 0                      , 0,
17615        0x0                 },        /* _POOL32A5~*(62) */
17616     { reserved_block      , 0                   , 0   , 32,
17617        0xfc0003ff, 0x200001fd, 0                      , 0,
17618        0x0                 },        /* _POOL32A5~*(63) */
17619     { instruction         , 0                   , 0   , 32,
17620        0xfc0003ff, 0x20000205, &NMD::CMPGDU_LE_QB     , 0,
17621        DSP_                },        /* CMPGDU.LE.QB */
17622     { pool                , SUBQ__S__PH         , 2   , 32,
17623        0xfc0003ff, 0x2000020d, 0                      , 0,
17624        0x0                 },        /* SUBQ[_S].PH */
17625     { instruction         , 0                   , 0   , 32,
17626        0xfc0003ff, 0x20000215, &NMD::APPEND           , 0,
17627        DSP_                },        /* APPEND */
17628     { reserved_block      , 0                   , 0   , 32,
17629        0xfc0003ff, 0x2000021d, 0                      , 0,
17630        0x0                 },        /* _POOL32A5~*(67) */
17631     { reserved_block      , 0                   , 0   , 32,
17632        0xfc0003ff, 0x20000225, 0                      , 0,
17633        0x0                 },        /* _POOL32A5~*(68) */
17634     { instruction         , 0                   , 0   , 32,
17635        0xfc0003ff, 0x2000022d, &NMD::PICK_PH          , 0,
17636        DSP_                },        /* PICK.PH */
17637     { reserved_block      , 0                   , 0   , 32,
17638        0xfc0003ff, 0x20000235, 0                      , 0,
17639        0x0                 },        /* _POOL32A5~*(70) */
17640     { reserved_block      , 0                   , 0   , 32,
17641        0xfc0003ff, 0x2000023d, 0                      , 0,
17642        0x0                 },        /* _POOL32A5~*(71) */
17643     { instruction         , 0                   , 0   , 32,
17644        0xfc0003ff, 0x20000245, &NMD::CMPU_EQ_QB       , 0,
17645        DSP_                },        /* CMPU.EQ.QB */
17646     { pool                , SUBQH__R__PH        , 2   , 32,
17647        0xfc0003ff, 0x2000024d, 0                      , 0,
17648        0x0                 },        /* SUBQH[_R].PH */
17649     { instruction         , 0                   , 0   , 32,
17650        0xfc0003ff, 0x20000255, &NMD::PREPEND          , 0,
17651        DSP_                },        /* PREPEND */
17652     { reserved_block      , 0                   , 0   , 32,
17653        0xfc0003ff, 0x2000025d, 0                      , 0,
17654        0x0                 },        /* _POOL32A5~*(75) */
17655     { reserved_block      , 0                   , 0   , 32,
17656        0xfc0003ff, 0x20000265, 0                      , 0,
17657        0x0                 },        /* _POOL32A5~*(76) */
17658     { reserved_block      , 0                   , 0   , 32,
17659        0xfc0003ff, 0x2000026d, 0                      , 0,
17660        0x0                 },        /* _POOL32A5~*(77) */
17661     { reserved_block      , 0                   , 0   , 32,
17662        0xfc0003ff, 0x20000275, 0                      , 0,
17663        0x0                 },        /* _POOL32A5~*(78) */
17664     { reserved_block      , 0                   , 0   , 32,
17665        0xfc0003ff, 0x2000027d, 0                      , 0,
17666        0x0                 },        /* _POOL32A5~*(79) */
17667     { instruction         , 0                   , 0   , 32,
17668        0xfc0003ff, 0x20000285, &NMD::CMPU_LT_QB       , 0,
17669        DSP_                },        /* CMPU.LT.QB */
17670     { pool                , SUBQH__R__W         , 2   , 32,
17671        0xfc0003ff, 0x2000028d, 0                      , 0,
17672        0x0                 },        /* SUBQH[_R].W */
17673     { instruction         , 0                   , 0   , 32,
17674        0xfc0003ff, 0x20000295, &NMD::MODSUB           , 0,
17675        DSP_                },        /* MODSUB */
17676     { reserved_block      , 0                   , 0   , 32,
17677        0xfc0003ff, 0x2000029d, 0                      , 0,
17678        0x0                 },        /* _POOL32A5~*(83) */
17679     { reserved_block      , 0                   , 0   , 32,
17680        0xfc0003ff, 0x200002a5, 0                      , 0,
17681        0x0                 },        /* _POOL32A5~*(84) */
17682     { reserved_block      , 0                   , 0   , 32,
17683        0xfc0003ff, 0x200002ad, 0                      , 0,
17684        0x0                 },        /* _POOL32A5~*(85) */
17685     { reserved_block      , 0                   , 0   , 32,
17686        0xfc0003ff, 0x200002b5, 0                      , 0,
17687        0x0                 },        /* _POOL32A5~*(86) */
17688     { reserved_block      , 0                   , 0   , 32,
17689        0xfc0003ff, 0x200002bd, 0                      , 0,
17690        0x0                 },        /* _POOL32A5~*(87) */
17691     { instruction         , 0                   , 0   , 32,
17692        0xfc0003ff, 0x200002c5, &NMD::CMPU_LE_QB       , 0,
17693        DSP_                },        /* CMPU.LE.QB */
17694     { pool                , SUBU__S__QB         , 2   , 32,
17695        0xfc0003ff, 0x200002cd, 0                      , 0,
17696        0x0                 },        /* SUBU[_S].QB */
17697     { instruction         , 0                   , 0   , 32,
17698        0xfc0003ff, 0x200002d5, &NMD::SHRAV_R_W        , 0,
17699        DSP_                },        /* SHRAV_R.W */
17700     { reserved_block      , 0                   , 0   , 32,
17701        0xfc0003ff, 0x200002dd, 0                      , 0,
17702        0x0                 },        /* _POOL32A5~*(91) */
17703     { reserved_block      , 0                   , 0   , 32,
17704        0xfc0003ff, 0x200002e5, 0                      , 0,
17705        0x0                 },        /* _POOL32A5~*(92) */
17706     { reserved_block      , 0                   , 0   , 32,
17707        0xfc0003ff, 0x200002ed, 0                      , 0,
17708        0x0                 },        /* _POOL32A5~*(93) */
17709     { instruction         , 0                   , 0   , 32,
17710        0xfc0003ff, 0x200002f5, &NMD::SHRA_R_W         , 0,
17711        DSP_                },        /* SHRA_R.W */
17712     { reserved_block      , 0                   , 0   , 32,
17713        0xfc0003ff, 0x200002fd, 0                      , 0,
17714        0x0                 },        /* _POOL32A5~*(95) */
17715     { instruction         , 0                   , 0   , 32,
17716        0xfc0003ff, 0x20000305, &NMD::ADDQ_S_W         , 0,
17717        DSP_                },        /* ADDQ_S.W */
17718     { pool                , SUBU__S__PH         , 2   , 32,
17719        0xfc0003ff, 0x2000030d, 0                      , 0,
17720        0x0                 },        /* SUBU[_S].PH */
17721     { instruction         , 0                   , 0   , 32,
17722        0xfc0003ff, 0x20000315, &NMD::SHRLV_PH         , 0,
17723        DSP_                },        /* SHRLV.PH */
17724     { reserved_block      , 0                   , 0   , 32,
17725        0xfc0003ff, 0x2000031d, 0                      , 0,
17726        0x0                 },        /* _POOL32A5~*(99) */
17727     { reserved_block      , 0                   , 0   , 32,
17728        0xfc0003ff, 0x20000325, 0                      , 0,
17729        0x0                 },        /* _POOL32A5~*(100) */
17730     { reserved_block      , 0                   , 0   , 32,
17731        0xfc0003ff, 0x2000032d, 0                      , 0,
17732        0x0                 },        /* _POOL32A5~*(101) */
17733     { pool                , SHRA__R__PH         , 2   , 32,
17734        0xfc0003ff, 0x20000335, 0                      , 0,
17735        0x0                 },        /* SHRA[_R].PH */
17736     { reserved_block      , 0                   , 0   , 32,
17737        0xfc0003ff, 0x2000033d, 0                      , 0,
17738        0x0                 },        /* _POOL32A5~*(103) */
17739     { instruction         , 0                   , 0   , 32,
17740        0xfc0003ff, 0x20000345, &NMD::SUBQ_S_W         , 0,
17741        DSP_                },        /* SUBQ_S.W */
17742     { pool                , SUBUH__R__QB        , 2   , 32,
17743        0xfc0003ff, 0x2000034d, 0                      , 0,
17744        0x0                 },        /* SUBUH[_R].QB */
17745     { instruction         , 0                   , 0   , 32,
17746        0xfc0003ff, 0x20000355, &NMD::SHRLV_QB         , 0,
17747        DSP_                },        /* SHRLV.QB */
17748     { reserved_block      , 0                   , 0   , 32,
17749        0xfc0003ff, 0x2000035d, 0                      , 0,
17750        0x0                 },        /* _POOL32A5~*(107) */
17751     { reserved_block      , 0                   , 0   , 32,
17752        0xfc0003ff, 0x20000365, 0                      , 0,
17753        0x0                 },        /* _POOL32A5~*(108) */
17754     { reserved_block      , 0                   , 0   , 32,
17755        0xfc0003ff, 0x2000036d, 0                      , 0,
17756        0x0                 },        /* _POOL32A5~*(109) */
17757     { reserved_block      , 0                   , 0   , 32,
17758        0xfc0003ff, 0x20000375, 0                      , 0,
17759        0x0                 },        /* _POOL32A5~*(110) */
17760     { reserved_block      , 0                   , 0   , 32,
17761        0xfc0003ff, 0x2000037d, 0                      , 0,
17762        0x0                 },        /* _POOL32A5~*(111) */
17763     { instruction         , 0                   , 0   , 32,
17764        0xfc0003ff, 0x20000385, &NMD::ADDSC            , 0,
17765        DSP_                },        /* ADDSC */
17766     { pool                , SHLLV__S__PH        , 2   , 32,
17767        0xfc0003ff, 0x2000038d, 0                      , 0,
17768        0x0                 },        /* SHLLV[_S].PH */
17769     { instruction         , 0                   , 0   , 32,
17770        0xfc0003ff, 0x20000395, &NMD::SHLLV_QB         , 0,
17771        DSP_                },        /* SHLLV.QB */
17772     { reserved_block      , 0                   , 0   , 32,
17773        0xfc0003ff, 0x2000039d, 0                      , 0,
17774        0x0                 },        /* _POOL32A5~*(115) */
17775     { reserved_block      , 0                   , 0   , 32,
17776        0xfc0003ff, 0x200003a5, 0                      , 0,
17777        0x0                 },        /* _POOL32A5~*(116) */
17778     { reserved_block      , 0                   , 0   , 32,
17779        0xfc0003ff, 0x200003ad, 0                      , 0,
17780        0x0                 },        /* _POOL32A5~*(117) */
17781     { pool                , SHLL__S__PH         , 4   , 32,
17782        0xfc0003ff, 0x200003b5, 0                      , 0,
17783        0x0                 },        /* SHLL[_S].PH */
17784     { reserved_block      , 0                   , 0   , 32,
17785        0xfc0003ff, 0x200003bd, 0                      , 0,
17786        0x0                 },        /* _POOL32A5~*(119) */
17787     { instruction         , 0                   , 0   , 32,
17788        0xfc0003ff, 0x200003c5, &NMD::ADDWC            , 0,
17789        DSP_                },        /* ADDWC */
17790     { pool                , PRECR_SRA__R__PH_W  , 2   , 32,
17791        0xfc0003ff, 0x200003cd, 0                      , 0,
17792        0x0                 },        /* PRECR_SRA[_R].PH.W */
17793     { instruction         , 0                   , 0   , 32,
17794        0xfc0003ff, 0x200003d5, &NMD::SHLLV_S_W        , 0,
17795        DSP_                },        /* SHLLV_S.W */
17796     { reserved_block      , 0                   , 0   , 32,
17797        0xfc0003ff, 0x200003dd, 0                      , 0,
17798        0x0                 },        /* _POOL32A5~*(123) */
17799     { reserved_block      , 0                   , 0   , 32,
17800        0xfc0003ff, 0x200003e5, 0                      , 0,
17801        0x0                 },        /* _POOL32A5~*(124) */
17802     { reserved_block      , 0                   , 0   , 32,
17803        0xfc0003ff, 0x200003ed, 0                      , 0,
17804        0x0                 },        /* _POOL32A5~*(125) */
17805     { instruction         , 0                   , 0   , 32,
17806        0xfc0003ff, 0x200003f5, &NMD::SHLL_S_W         , 0,
17807        DSP_                },        /* SHLL_S.W */
17808     { reserved_block      , 0                   , 0   , 32,
17809        0xfc0003ff, 0x200003fd, 0                      , 0,
17810        0x0                 },        /* _POOL32A5~*(127) */
17811 };
17812
17813
17814 NMD::Pool NMD::PP_LSX[16] = {
17815     { instruction         , 0                   , 0   , 32,
17816        0xfc0007ff, 0x20000007, &NMD::LBX              , 0,
17817        0x0                 },        /* LBX */
17818     { instruction         , 0                   , 0   , 32,
17819        0xfc0007ff, 0x20000087, &NMD::SBX              , 0,
17820        XMMS_               },        /* SBX */
17821     { instruction         , 0                   , 0   , 32,
17822        0xfc0007ff, 0x20000107, &NMD::LBUX             , 0,
17823        0x0                 },        /* LBUX */
17824     { reserved_block      , 0                   , 0   , 32,
17825        0xfc0007ff, 0x20000187, 0                      , 0,
17826        0x0                 },        /* PP.LSX~*(3) */
17827     { instruction         , 0                   , 0   , 32,
17828        0xfc0007ff, 0x20000207, &NMD::LHX              , 0,
17829        0x0                 },        /* LHX */
17830     { instruction         , 0                   , 0   , 32,
17831        0xfc0007ff, 0x20000287, &NMD::SHX              , 0,
17832        XMMS_               },        /* SHX */
17833     { instruction         , 0                   , 0   , 32,
17834        0xfc0007ff, 0x20000307, &NMD::LHUX             , 0,
17835        0x0                 },        /* LHUX */
17836     { instruction         , 0                   , 0   , 32,
17837        0xfc0007ff, 0x20000387, &NMD::LWUX             , 0,
17838        MIPS64_             },        /* LWUX */
17839     { instruction         , 0                   , 0   , 32,
17840        0xfc0007ff, 0x20000407, &NMD::LWX              , 0,
17841        0x0                 },        /* LWX */
17842     { instruction         , 0                   , 0   , 32,
17843        0xfc0007ff, 0x20000487, &NMD::SWX              , 0,
17844        XMMS_               },        /* SWX */
17845     { instruction         , 0                   , 0   , 32,
17846        0xfc0007ff, 0x20000507, &NMD::LWC1X            , 0,
17847        CP1_                },        /* LWC1X */
17848     { instruction         , 0                   , 0   , 32,
17849        0xfc0007ff, 0x20000587, &NMD::SWC1X            , 0,
17850        CP1_                },        /* SWC1X */
17851     { instruction         , 0                   , 0   , 32,
17852        0xfc0007ff, 0x20000607, &NMD::LDX              , 0,
17853        MIPS64_             },        /* LDX */
17854     { instruction         , 0                   , 0   , 32,
17855        0xfc0007ff, 0x20000687, &NMD::SDX              , 0,
17856        MIPS64_             },        /* SDX */
17857     { instruction         , 0                   , 0   , 32,
17858        0xfc0007ff, 0x20000707, &NMD::LDC1X            , 0,
17859        CP1_                },        /* LDC1X */
17860     { instruction         , 0                   , 0   , 32,
17861        0xfc0007ff, 0x20000787, &NMD::SDC1X            , 0,
17862        CP1_                },        /* SDC1X */
17863 };
17864
17865
17866 NMD::Pool NMD::PP_LSXS[16] = {
17867     { reserved_block      , 0                   , 0   , 32,
17868        0xfc0007ff, 0x20000047, 0                      , 0,
17869        0x0                 },        /* PP.LSXS~*(0) */
17870     { reserved_block      , 0                   , 0   , 32,
17871        0xfc0007ff, 0x200000c7, 0                      , 0,
17872        0x0                 },        /* PP.LSXS~*(1) */
17873     { reserved_block      , 0                   , 0   , 32,
17874        0xfc0007ff, 0x20000147, 0                      , 0,
17875        0x0                 },        /* PP.LSXS~*(2) */
17876     { reserved_block      , 0                   , 0   , 32,
17877        0xfc0007ff, 0x200001c7, 0                      , 0,
17878        0x0                 },        /* PP.LSXS~*(3) */
17879     { instruction         , 0                   , 0   , 32,
17880        0xfc0007ff, 0x20000247, &NMD::LHXS             , 0,
17881        0x0                 },        /* LHXS */
17882     { instruction         , 0                   , 0   , 32,
17883        0xfc0007ff, 0x200002c7, &NMD::SHXS             , 0,
17884        XMMS_               },        /* SHXS */
17885     { instruction         , 0                   , 0   , 32,
17886        0xfc0007ff, 0x20000347, &NMD::LHUXS            , 0,
17887        0x0                 },        /* LHUXS */
17888     { instruction         , 0                   , 0   , 32,
17889        0xfc0007ff, 0x200003c7, &NMD::LWUXS            , 0,
17890        MIPS64_             },        /* LWUXS */
17891     { instruction         , 0                   , 0   , 32,
17892        0xfc0007ff, 0x20000447, &NMD::LWXS_32_         , 0,
17893        0x0                 },        /* LWXS[32] */
17894     { instruction         , 0                   , 0   , 32,
17895        0xfc0007ff, 0x200004c7, &NMD::SWXS             , 0,
17896        XMMS_               },        /* SWXS */
17897     { instruction         , 0                   , 0   , 32,
17898        0xfc0007ff, 0x20000547, &NMD::LWC1XS           , 0,
17899        CP1_                },        /* LWC1XS */
17900     { instruction         , 0                   , 0   , 32,
17901        0xfc0007ff, 0x200005c7, &NMD::SWC1XS           , 0,
17902        CP1_                },        /* SWC1XS */
17903     { instruction         , 0                   , 0   , 32,
17904        0xfc0007ff, 0x20000647, &NMD::LDXS             , 0,
17905        MIPS64_             },        /* LDXS */
17906     { instruction         , 0                   , 0   , 32,
17907        0xfc0007ff, 0x200006c7, &NMD::SDXS             , 0,
17908        MIPS64_             },        /* SDXS */
17909     { instruction         , 0                   , 0   , 32,
17910        0xfc0007ff, 0x20000747, &NMD::LDC1XS           , 0,
17911        CP1_                },        /* LDC1XS */
17912     { instruction         , 0                   , 0   , 32,
17913        0xfc0007ff, 0x200007c7, &NMD::SDC1XS           , 0,
17914        CP1_                },        /* SDC1XS */
17915 };
17916
17917
17918 NMD::Pool NMD::P_LSX[2] = {
17919     { pool                , PP_LSX              , 16  , 32,
17920        0xfc00007f, 0x20000007, 0                      , 0,
17921        0x0                 },        /* PP.LSX */
17922     { pool                , PP_LSXS             , 16  , 32,
17923        0xfc00007f, 0x20000047, 0                      , 0,
17924        0x0                 },        /* PP.LSXS */
17925 };
17926
17927
17928 NMD::Pool NMD::POOL32Axf_1_0[4] = {
17929     { instruction         , 0                   , 0   , 32,
17930        0xfc003fff, 0x2000007f, &NMD::MFHI_DSP_        , 0,
17931        DSP_                },        /* MFHI[DSP] */
17932     { instruction         , 0                   , 0   , 32,
17933        0xfc003fff, 0x2000107f, &NMD::MFLO_DSP_        , 0,
17934        DSP_                },        /* MFLO[DSP] */
17935     { instruction         , 0                   , 0   , 32,
17936        0xfc003fff, 0x2000207f, &NMD::MTHI_DSP_        , 0,
17937        DSP_                },        /* MTHI[DSP] */
17938     { instruction         , 0                   , 0   , 32,
17939        0xfc003fff, 0x2000307f, &NMD::MTLO_DSP_        , 0,
17940        DSP_                },        /* MTLO[DSP] */
17941 };
17942
17943
17944 NMD::Pool NMD::POOL32Axf_1_1[4] = {
17945     { instruction         , 0                   , 0   , 32,
17946        0xfc003fff, 0x2000027f, &NMD::MTHLIP           , 0,
17947        DSP_                },        /* MTHLIP */
17948     { instruction         , 0                   , 0   , 32,
17949        0xfc003fff, 0x2000127f, &NMD::SHILOV           , 0,
17950        DSP_                },        /* SHILOV */
17951     { reserved_block      , 0                   , 0   , 32,
17952        0xfc003fff, 0x2000227f, 0                      , 0,
17953        0x0                 },        /* POOL32Axf_1_1~*(2) */
17954     { reserved_block      , 0                   , 0   , 32,
17955        0xfc003fff, 0x2000327f, 0                      , 0,
17956        0x0                 },        /* POOL32Axf_1_1~*(3) */
17957 };
17958
17959
17960 NMD::Pool NMD::POOL32Axf_1_3[4] = {
17961     { instruction         , 0                   , 0   , 32,
17962        0xfc003fff, 0x2000067f, &NMD::RDDSP            , 0,
17963        DSP_                },        /* RDDSP */
17964     { instruction         , 0                   , 0   , 32,
17965        0xfc003fff, 0x2000167f, &NMD::WRDSP            , 0,
17966        DSP_                },        /* WRDSP */
17967     { instruction         , 0                   , 0   , 32,
17968        0xfc003fff, 0x2000267f, &NMD::EXTP             , 0,
17969        DSP_                },        /* EXTP */
17970     { instruction         , 0                   , 0   , 32,
17971        0xfc003fff, 0x2000367f, &NMD::EXTPDP           , 0,
17972        DSP_                },        /* EXTPDP */
17973 };
17974
17975
17976 NMD::Pool NMD::POOL32Axf_1_4[2] = {
17977     { instruction         , 0                   , 0   , 32,
17978        0xfc001fff, 0x2000087f, &NMD::SHLL_QB          , 0,
17979        DSP_                },        /* SHLL.QB */
17980     { instruction         , 0                   , 0   , 32,
17981        0xfc001fff, 0x2000187f, &NMD::SHRL_QB          , 0,
17982        DSP_                },        /* SHRL.QB */
17983 };
17984
17985
17986 NMD::Pool NMD::MAQ_S_A__W_PHR[2] = {
17987     { instruction         , 0                   , 0   , 32,
17988        0xfc003fff, 0x20000a7f, &NMD::MAQ_S_W_PHR      , 0,
17989        DSP_                },        /* MAQ_S.W.PHR */
17990     { instruction         , 0                   , 0   , 32,
17991        0xfc003fff, 0x20002a7f, &NMD::MAQ_SA_W_PHR     , 0,
17992        DSP_                },        /* MAQ_SA.W.PHR */
17993 };
17994
17995
17996 NMD::Pool NMD::MAQ_S_A__W_PHL[2] = {
17997     { instruction         , 0                   , 0   , 32,
17998        0xfc003fff, 0x20001a7f, &NMD::MAQ_S_W_PHL      , 0,
17999        DSP_                },        /* MAQ_S.W.PHL */
18000     { instruction         , 0                   , 0   , 32,
18001        0xfc003fff, 0x20003a7f, &NMD::MAQ_SA_W_PHL     , 0,
18002        DSP_                },        /* MAQ_SA.W.PHL */
18003 };
18004
18005
18006 NMD::Pool NMD::POOL32Axf_1_5[2] = {
18007     { pool                , MAQ_S_A__W_PHR      , 2   , 32,
18008        0xfc001fff, 0x20000a7f, 0                      , 0,
18009        0x0                 },        /* MAQ_S[A].W.PHR */
18010     { pool                , MAQ_S_A__W_PHL      , 2   , 32,
18011        0xfc001fff, 0x20001a7f, 0                      , 0,
18012        0x0                 },        /* MAQ_S[A].W.PHL */
18013 };
18014
18015
18016 NMD::Pool NMD::POOL32Axf_1_7[4] = {
18017     { instruction         , 0                   , 0   , 32,
18018        0xfc003fff, 0x20000e7f, &NMD::EXTR_W           , 0,
18019        DSP_                },        /* EXTR.W */
18020     { instruction         , 0                   , 0   , 32,
18021        0xfc003fff, 0x20001e7f, &NMD::EXTR_R_W         , 0,
18022        DSP_                },        /* EXTR_R.W */
18023     { instruction         , 0                   , 0   , 32,
18024        0xfc003fff, 0x20002e7f, &NMD::EXTR_RS_W        , 0,
18025        DSP_                },        /* EXTR_RS.W */
18026     { instruction         , 0                   , 0   , 32,
18027        0xfc003fff, 0x20003e7f, &NMD::EXTR_S_H         , 0,
18028        DSP_                },        /* EXTR_S.H */
18029 };
18030
18031
18032 NMD::Pool NMD::POOL32Axf_1[8] = {
18033     { pool                , POOL32Axf_1_0       , 4   , 32,
18034        0xfc000fff, 0x2000007f, 0                      , 0,
18035        0x0                 },        /* POOL32Axf_1_0 */
18036     { pool                , POOL32Axf_1_1       , 4   , 32,
18037        0xfc000fff, 0x2000027f, 0                      , 0,
18038        0x0                 },        /* POOL32Axf_1_1 */
18039     { reserved_block      , 0                   , 0   , 32,
18040        0xfc000fff, 0x2000047f, 0                      , 0,
18041        0x0                 },        /* POOL32Axf_1~*(2) */
18042     { pool                , POOL32Axf_1_3       , 4   , 32,
18043        0xfc000fff, 0x2000067f, 0                      , 0,
18044        0x0                 },        /* POOL32Axf_1_3 */
18045     { pool                , POOL32Axf_1_4       , 2   , 32,
18046        0xfc000fff, 0x2000087f, 0                      , 0,
18047        0x0                 },        /* POOL32Axf_1_4 */
18048     { pool                , POOL32Axf_1_5       , 2   , 32,
18049        0xfc000fff, 0x20000a7f, 0                      , 0,
18050        0x0                 },        /* POOL32Axf_1_5 */
18051     { reserved_block      , 0                   , 0   , 32,
18052        0xfc000fff, 0x20000c7f, 0                      , 0,
18053        0x0                 },        /* POOL32Axf_1~*(6) */
18054     { pool                , POOL32Axf_1_7       , 4   , 32,
18055        0xfc000fff, 0x20000e7f, 0                      , 0,
18056        0x0                 },        /* POOL32Axf_1_7 */
18057 };
18058
18059
18060 NMD::Pool NMD::POOL32Axf_2_DSP__0_7[8] = {
18061     { instruction         , 0                   , 0   , 32,
18062        0xfc003fff, 0x200000bf, &NMD::DPA_W_PH         , 0,
18063        DSP_                },        /* DPA.W.PH */
18064     { instruction         , 0                   , 0   , 32,
18065        0xfc003fff, 0x200002bf, &NMD::DPAQ_S_W_PH      , 0,
18066        DSP_                },        /* DPAQ_S.W.PH */
18067     { instruction         , 0                   , 0   , 32,
18068        0xfc003fff, 0x200004bf, &NMD::DPS_W_PH         , 0,
18069        DSP_                },        /* DPS.W.PH */
18070     { instruction         , 0                   , 0   , 32,
18071        0xfc003fff, 0x200006bf, &NMD::DPSQ_S_W_PH      , 0,
18072        DSP_                },        /* DPSQ_S.W.PH */
18073     { reserved_block      , 0                   , 0   , 32,
18074        0xfc003fff, 0x200008bf, 0                      , 0,
18075        0x0                 },        /* POOL32Axf_2(DSP)_0_7~*(4) */
18076     { instruction         , 0                   , 0   , 32,
18077        0xfc003fff, 0x20000abf, &NMD::MADD_DSP_        , 0,
18078        DSP_                },        /* MADD[DSP] */
18079     { instruction         , 0                   , 0   , 32,
18080        0xfc003fff, 0x20000cbf, &NMD::MULT_DSP_        , 0,
18081        DSP_                },        /* MULT[DSP] */
18082     { instruction         , 0                   , 0   , 32,
18083        0xfc003fff, 0x20000ebf, &NMD::EXTRV_W          , 0,
18084        DSP_                },        /* EXTRV.W */
18085 };
18086
18087
18088 NMD::Pool NMD::POOL32Axf_2_DSP__8_15[8] = {
18089     { instruction         , 0                   , 0   , 32,
18090        0xfc003fff, 0x200010bf, &NMD::DPAX_W_PH        , 0,
18091        DSP_                },        /* DPAX.W.PH */
18092     { instruction         , 0                   , 0   , 32,
18093        0xfc003fff, 0x200012bf, &NMD::DPAQ_SA_L_W      , 0,
18094        DSP_                },        /* DPAQ_SA.L.W */
18095     { instruction         , 0                   , 0   , 32,
18096        0xfc003fff, 0x200014bf, &NMD::DPSX_W_PH        , 0,
18097        DSP_                },        /* DPSX.W.PH */
18098     { instruction         , 0                   , 0   , 32,
18099        0xfc003fff, 0x200016bf, &NMD::DPSQ_SA_L_W      , 0,
18100        DSP_                },        /* DPSQ_SA.L.W */
18101     { reserved_block      , 0                   , 0   , 32,
18102        0xfc003fff, 0x200018bf, 0                      , 0,
18103        0x0                 },        /* POOL32Axf_2(DSP)_8_15~*(4) */
18104     { instruction         , 0                   , 0   , 32,
18105        0xfc003fff, 0x20001abf, &NMD::MADDU_DSP_       , 0,
18106        DSP_                },        /* MADDU[DSP] */
18107     { instruction         , 0                   , 0   , 32,
18108        0xfc003fff, 0x20001cbf, &NMD::MULTU_DSP_       , 0,
18109        DSP_                },        /* MULTU[DSP] */
18110     { instruction         , 0                   , 0   , 32,
18111        0xfc003fff, 0x20001ebf, &NMD::EXTRV_R_W        , 0,
18112        DSP_                },        /* EXTRV_R.W */
18113 };
18114
18115
18116 NMD::Pool NMD::POOL32Axf_2_DSP__16_23[8] = {
18117     { instruction         , 0                   , 0   , 32,
18118        0xfc003fff, 0x200020bf, &NMD::DPAU_H_QBL       , 0,
18119        DSP_                },        /* DPAU.H.QBL */
18120     { instruction         , 0                   , 0   , 32,
18121        0xfc003fff, 0x200022bf, &NMD::DPAQX_S_W_PH     , 0,
18122        DSP_                },        /* DPAQX_S.W.PH */
18123     { instruction         , 0                   , 0   , 32,
18124        0xfc003fff, 0x200024bf, &NMD::DPSU_H_QBL       , 0,
18125        DSP_                },        /* DPSU.H.QBL */
18126     { instruction         , 0                   , 0   , 32,
18127        0xfc003fff, 0x200026bf, &NMD::DPSQX_S_W_PH     , 0,
18128        DSP_                },        /* DPSQX_S.W.PH */
18129     { instruction         , 0                   , 0   , 32,
18130        0xfc003fff, 0x200028bf, &NMD::EXTPV            , 0,
18131        DSP_                },        /* EXTPV */
18132     { instruction         , 0                   , 0   , 32,
18133        0xfc003fff, 0x20002abf, &NMD::MSUB_DSP_        , 0,
18134        DSP_                },        /* MSUB[DSP] */
18135     { instruction         , 0                   , 0   , 32,
18136        0xfc003fff, 0x20002cbf, &NMD::MULSA_W_PH       , 0,
18137        DSP_                },        /* MULSA.W.PH */
18138     { instruction         , 0                   , 0   , 32,
18139        0xfc003fff, 0x20002ebf, &NMD::EXTRV_RS_W       , 0,
18140        DSP_                },        /* EXTRV_RS.W */
18141 };
18142
18143
18144 NMD::Pool NMD::POOL32Axf_2_DSP__24_31[8] = {
18145     { instruction         , 0                   , 0   , 32,
18146        0xfc003fff, 0x200030bf, &NMD::DPAU_H_QBR       , 0,
18147        DSP_                },        /* DPAU.H.QBR */
18148     { instruction         , 0                   , 0   , 32,
18149        0xfc003fff, 0x200032bf, &NMD::DPAQX_SA_W_PH    , 0,
18150        DSP_                },        /* DPAQX_SA.W.PH */
18151     { instruction         , 0                   , 0   , 32,
18152        0xfc003fff, 0x200034bf, &NMD::DPSU_H_QBR       , 0,
18153        DSP_                },        /* DPSU.H.QBR */
18154     { instruction         , 0                   , 0   , 32,
18155        0xfc003fff, 0x200036bf, &NMD::DPSQX_SA_W_PH    , 0,
18156        DSP_                },        /* DPSQX_SA.W.PH */
18157     { instruction         , 0                   , 0   , 32,
18158        0xfc003fff, 0x200038bf, &NMD::EXTPDPV          , 0,
18159        DSP_                },        /* EXTPDPV */
18160     { instruction         , 0                   , 0   , 32,
18161        0xfc003fff, 0x20003abf, &NMD::MSUBU_DSP_       , 0,
18162        DSP_                },        /* MSUBU[DSP] */
18163     { instruction         , 0                   , 0   , 32,
18164        0xfc003fff, 0x20003cbf, &NMD::MULSAQ_S_W_PH    , 0,
18165        DSP_                },        /* MULSAQ_S.W.PH */
18166     { instruction         , 0                   , 0   , 32,
18167        0xfc003fff, 0x20003ebf, &NMD::EXTRV_S_H        , 0,
18168        DSP_                },        /* EXTRV_S.H */
18169 };
18170
18171
18172 NMD::Pool NMD::POOL32Axf_2[4] = {
18173     { pool                , POOL32Axf_2_DSP__0_7, 8   , 32,
18174        0xfc0031ff, 0x200000bf, 0                      , 0,
18175        0x0                 },        /* POOL32Axf_2(DSP)_0_7 */
18176     { pool                , POOL32Axf_2_DSP__8_15, 8   , 32,
18177        0xfc0031ff, 0x200010bf, 0                      , 0,
18178        0x0                 },        /* POOL32Axf_2(DSP)_8_15 */
18179     { pool                , POOL32Axf_2_DSP__16_23, 8   , 32,
18180        0xfc0031ff, 0x200020bf, 0                      , 0,
18181        0x0                 },        /* POOL32Axf_2(DSP)_16_23 */
18182     { pool                , POOL32Axf_2_DSP__24_31, 8   , 32,
18183        0xfc0031ff, 0x200030bf, 0                      , 0,
18184        0x0                 },        /* POOL32Axf_2(DSP)_24_31 */
18185 };
18186
18187
18188 NMD::Pool NMD::POOL32Axf_4[128] = {
18189     { instruction         , 0                   , 0   , 32,
18190        0xfc00ffff, 0x2000013f, &NMD::ABSQ_S_QB        , 0,
18191        DSP_                },        /* ABSQ_S.QB */
18192     { instruction         , 0                   , 0   , 32,
18193        0xfc00ffff, 0x2000033f, &NMD::REPLV_PH         , 0,
18194        DSP_                },        /* REPLV.PH */
18195     { reserved_block      , 0                   , 0   , 32,
18196        0xfc00ffff, 0x2000053f, 0                      , 0,
18197        0x0                 },        /* POOL32Axf_4~*(2) */
18198     { reserved_block      , 0                   , 0   , 32,
18199        0xfc00ffff, 0x2000073f, 0                      , 0,
18200        0x0                 },        /* POOL32Axf_4~*(3) */
18201     { reserved_block      , 0                   , 0   , 32,
18202        0xfc00ffff, 0x2000093f, 0                      , 0,
18203        0x0                 },        /* POOL32Axf_4~*(4) */
18204     { reserved_block      , 0                   , 0   , 32,
18205        0xfc00ffff, 0x20000b3f, 0                      , 0,
18206        0x0                 },        /* POOL32Axf_4~*(5) */
18207     { reserved_block      , 0                   , 0   , 32,
18208        0xfc00ffff, 0x20000d3f, 0                      , 0,
18209        0x0                 },        /* POOL32Axf_4~*(6) */
18210     { reserved_block      , 0                   , 0   , 32,
18211        0xfc00ffff, 0x20000f3f, 0                      , 0,
18212        0x0                 },        /* POOL32Axf_4~*(7) */
18213     { instruction         , 0                   , 0   , 32,
18214        0xfc00ffff, 0x2000113f, &NMD::ABSQ_S_PH        , 0,
18215        DSP_                },        /* ABSQ_S.PH */
18216     { instruction         , 0                   , 0   , 32,
18217        0xfc00ffff, 0x2000133f, &NMD::REPLV_QB         , 0,
18218        DSP_                },        /* REPLV.QB */
18219     { reserved_block      , 0                   , 0   , 32,
18220        0xfc00ffff, 0x2000153f, 0                      , 0,
18221        0x0                 },        /* POOL32Axf_4~*(10) */
18222     { reserved_block      , 0                   , 0   , 32,
18223        0xfc00ffff, 0x2000173f, 0                      , 0,
18224        0x0                 },        /* POOL32Axf_4~*(11) */
18225     { reserved_block      , 0                   , 0   , 32,
18226        0xfc00ffff, 0x2000193f, 0                      , 0,
18227        0x0                 },        /* POOL32Axf_4~*(12) */
18228     { reserved_block      , 0                   , 0   , 32,
18229        0xfc00ffff, 0x20001b3f, 0                      , 0,
18230        0x0                 },        /* POOL32Axf_4~*(13) */
18231     { reserved_block      , 0                   , 0   , 32,
18232        0xfc00ffff, 0x20001d3f, 0                      , 0,
18233        0x0                 },        /* POOL32Axf_4~*(14) */
18234     { reserved_block      , 0                   , 0   , 32,
18235        0xfc00ffff, 0x20001f3f, 0                      , 0,
18236        0x0                 },        /* POOL32Axf_4~*(15) */
18237     { instruction         , 0                   , 0   , 32,
18238        0xfc00ffff, 0x2000213f, &NMD::ABSQ_S_W         , 0,
18239        DSP_                },        /* ABSQ_S.W */
18240     { reserved_block      , 0                   , 0   , 32,
18241        0xfc00ffff, 0x2000233f, 0                      , 0,
18242        0x0                 },        /* POOL32Axf_4~*(17) */
18243     { reserved_block      , 0                   , 0   , 32,
18244        0xfc00ffff, 0x2000253f, 0                      , 0,
18245        0x0                 },        /* POOL32Axf_4~*(18) */
18246     { reserved_block      , 0                   , 0   , 32,
18247        0xfc00ffff, 0x2000273f, 0                      , 0,
18248        0x0                 },        /* POOL32Axf_4~*(19) */
18249     { reserved_block      , 0                   , 0   , 32,
18250        0xfc00ffff, 0x2000293f, 0                      , 0,
18251        0x0                 },        /* POOL32Axf_4~*(20) */
18252     { reserved_block      , 0                   , 0   , 32,
18253        0xfc00ffff, 0x20002b3f, 0                      , 0,
18254        0x0                 },        /* POOL32Axf_4~*(21) */
18255     { reserved_block      , 0                   , 0   , 32,
18256        0xfc00ffff, 0x20002d3f, 0                      , 0,
18257        0x0                 },        /* POOL32Axf_4~*(22) */
18258     { reserved_block      , 0                   , 0   , 32,
18259        0xfc00ffff, 0x20002f3f, 0                      , 0,
18260        0x0                 },        /* POOL32Axf_4~*(23) */
18261     { reserved_block      , 0                   , 0   , 32,
18262        0xfc00ffff, 0x2000313f, 0                      , 0,
18263        0x0                 },        /* POOL32Axf_4~*(24) */
18264     { reserved_block      , 0                   , 0   , 32,
18265        0xfc00ffff, 0x2000333f, 0                      , 0,
18266        0x0                 },        /* POOL32Axf_4~*(25) */
18267     { reserved_block      , 0                   , 0   , 32,
18268        0xfc00ffff, 0x2000353f, 0                      , 0,
18269        0x0                 },        /* POOL32Axf_4~*(26) */
18270     { reserved_block      , 0                   , 0   , 32,
18271        0xfc00ffff, 0x2000373f, 0                      , 0,
18272        0x0                 },        /* POOL32Axf_4~*(27) */
18273     { reserved_block      , 0                   , 0   , 32,
18274        0xfc00ffff, 0x2000393f, 0                      , 0,
18275        0x0                 },        /* POOL32Axf_4~*(28) */
18276     { reserved_block      , 0                   , 0   , 32,
18277        0xfc00ffff, 0x20003b3f, 0                      , 0,
18278        0x0                 },        /* POOL32Axf_4~*(29) */
18279     { reserved_block      , 0                   , 0   , 32,
18280        0xfc00ffff, 0x20003d3f, 0                      , 0,
18281        0x0                 },        /* POOL32Axf_4~*(30) */
18282     { reserved_block      , 0                   , 0   , 32,
18283        0xfc00ffff, 0x20003f3f, 0                      , 0,
18284        0x0                 },        /* POOL32Axf_4~*(31) */
18285     { instruction         , 0                   , 0   , 32,
18286        0xfc00ffff, 0x2000413f, &NMD::INSV             , 0,
18287        DSP_                },        /* INSV */
18288     { reserved_block      , 0                   , 0   , 32,
18289        0xfc00ffff, 0x2000433f, 0                      , 0,
18290        0x0                 },        /* POOL32Axf_4~*(33) */
18291     { reserved_block      , 0                   , 0   , 32,
18292        0xfc00ffff, 0x2000453f, 0                      , 0,
18293        0x0                 },        /* POOL32Axf_4~*(34) */
18294     { reserved_block      , 0                   , 0   , 32,
18295        0xfc00ffff, 0x2000473f, 0                      , 0,
18296        0x0                 },        /* POOL32Axf_4~*(35) */
18297     { reserved_block      , 0                   , 0   , 32,
18298        0xfc00ffff, 0x2000493f, 0                      , 0,
18299        0x0                 },        /* POOL32Axf_4~*(36) */
18300     { instruction         , 0                   , 0   , 32,
18301        0xfc00ffff, 0x20004b3f, &NMD::CLO              , 0,
18302        XMMS_               },        /* CLO */
18303     { instruction         , 0                   , 0   , 32,
18304        0xfc00ffff, 0x20004d3f, &NMD::MFC2             , 0,
18305        CP2_                },        /* MFC2 */
18306     { reserved_block      , 0                   , 0   , 32,
18307        0xfc00ffff, 0x20004f3f, 0                      , 0,
18308        0x0                 },        /* POOL32Axf_4~*(39) */
18309     { instruction         , 0                   , 0   , 32,
18310        0xfc00ffff, 0x2000513f, &NMD::PRECEQ_W_PHL     , 0,
18311        DSP_                },        /* PRECEQ.W.PHL */
18312     { reserved_block      , 0                   , 0   , 32,
18313        0xfc00ffff, 0x2000533f, 0                      , 0,
18314        0x0                 },        /* POOL32Axf_4~*(41) */
18315     { reserved_block      , 0                   , 0   , 32,
18316        0xfc00ffff, 0x2000553f, 0                      , 0,
18317        0x0                 },        /* POOL32Axf_4~*(42) */
18318     { reserved_block      , 0                   , 0   , 32,
18319        0xfc00ffff, 0x2000573f, 0                      , 0,
18320        0x0                 },        /* POOL32Axf_4~*(43) */
18321     { reserved_block      , 0                   , 0   , 32,
18322        0xfc00ffff, 0x2000593f, 0                      , 0,
18323        0x0                 },        /* POOL32Axf_4~*(44) */
18324     { instruction         , 0                   , 0   , 32,
18325        0xfc00ffff, 0x20005b3f, &NMD::CLZ              , 0,
18326        XMMS_               },        /* CLZ */
18327     { instruction         , 0                   , 0   , 32,
18328        0xfc00ffff, 0x20005d3f, &NMD::MTC2             , 0,
18329        CP2_                },        /* MTC2 */
18330     { reserved_block      , 0                   , 0   , 32,
18331        0xfc00ffff, 0x20005f3f, 0                      , 0,
18332        0x0                 },        /* POOL32Axf_4~*(47) */
18333     { instruction         , 0                   , 0   , 32,
18334        0xfc00ffff, 0x2000613f, &NMD::PRECEQ_W_PHR     , 0,
18335        DSP_                },        /* PRECEQ.W.PHR */
18336     { reserved_block      , 0                   , 0   , 32,
18337        0xfc00ffff, 0x2000633f, 0                      , 0,
18338        0x0                 },        /* POOL32Axf_4~*(49) */
18339     { reserved_block      , 0                   , 0   , 32,
18340        0xfc00ffff, 0x2000653f, 0                      , 0,
18341        0x0                 },        /* POOL32Axf_4~*(50) */
18342     { reserved_block      , 0                   , 0   , 32,
18343        0xfc00ffff, 0x2000673f, 0                      , 0,
18344        0x0                 },        /* POOL32Axf_4~*(51) */
18345     { reserved_block      , 0                   , 0   , 32,
18346        0xfc00ffff, 0x2000693f, 0                      , 0,
18347        0x0                 },        /* POOL32Axf_4~*(52) */
18348     { reserved_block      , 0                   , 0   , 32,
18349        0xfc00ffff, 0x20006b3f, 0                      , 0,
18350        0x0                 },        /* POOL32Axf_4~*(53) */
18351     { instruction         , 0                   , 0   , 32,
18352        0xfc00ffff, 0x20006d3f, &NMD::DMFC2            , 0,
18353        CP2_                },        /* DMFC2 */
18354     { reserved_block      , 0                   , 0   , 32,
18355        0xfc00ffff, 0x20006f3f, 0                      , 0,
18356        0x0                 },        /* POOL32Axf_4~*(55) */
18357     { instruction         , 0                   , 0   , 32,
18358        0xfc00ffff, 0x2000713f, &NMD::PRECEQU_PH_QBL   , 0,
18359        DSP_                },        /* PRECEQU.PH.QBL */
18360     { instruction         , 0                   , 0   , 32,
18361        0xfc00ffff, 0x2000733f, &NMD::PRECEQU_PH_QBLA  , 0,
18362        DSP_                },        /* PRECEQU.PH.QBLA */
18363     { reserved_block      , 0                   , 0   , 32,
18364        0xfc00ffff, 0x2000753f, 0                      , 0,
18365        0x0                 },        /* POOL32Axf_4~*(58) */
18366     { reserved_block      , 0                   , 0   , 32,
18367        0xfc00ffff, 0x2000773f, 0                      , 0,
18368        0x0                 },        /* POOL32Axf_4~*(59) */
18369     { reserved_block      , 0                   , 0   , 32,
18370        0xfc00ffff, 0x2000793f, 0                      , 0,
18371        0x0                 },        /* POOL32Axf_4~*(60) */
18372     { reserved_block      , 0                   , 0   , 32,
18373        0xfc00ffff, 0x20007b3f, 0                      , 0,
18374        0x0                 },        /* POOL32Axf_4~*(61) */
18375     { instruction         , 0                   , 0   , 32,
18376        0xfc00ffff, 0x20007d3f, &NMD::DMTC2            , 0,
18377        CP2_                },        /* DMTC2 */
18378     { reserved_block      , 0                   , 0   , 32,
18379        0xfc00ffff, 0x20007f3f, 0                      , 0,
18380        0x0                 },        /* POOL32Axf_4~*(63) */
18381     { reserved_block      , 0                   , 0   , 32,
18382        0xfc00ffff, 0x2000813f, 0                      , 0,
18383        0x0                 },        /* POOL32Axf_4~*(64) */
18384     { reserved_block      , 0                   , 0   , 32,
18385        0xfc00ffff, 0x2000833f, 0                      , 0,
18386        0x0                 },        /* POOL32Axf_4~*(65) */
18387     { reserved_block      , 0                   , 0   , 32,
18388        0xfc00ffff, 0x2000853f, 0                      , 0,
18389        0x0                 },        /* POOL32Axf_4~*(66) */
18390     { reserved_block      , 0                   , 0   , 32,
18391        0xfc00ffff, 0x2000873f, 0                      , 0,
18392        0x0                 },        /* POOL32Axf_4~*(67) */
18393     { reserved_block      , 0                   , 0   , 32,
18394        0xfc00ffff, 0x2000893f, 0                      , 0,
18395        0x0                 },        /* POOL32Axf_4~*(68) */
18396     { reserved_block      , 0                   , 0   , 32,
18397        0xfc00ffff, 0x20008b3f, 0                      , 0,
18398        0x0                 },        /* POOL32Axf_4~*(69) */
18399     { instruction         , 0                   , 0   , 32,
18400        0xfc00ffff, 0x20008d3f, &NMD::MFHC2            , 0,
18401        CP2_                },        /* MFHC2 */
18402     { reserved_block      , 0                   , 0   , 32,
18403        0xfc00ffff, 0x20008f3f, 0                      , 0,
18404        0x0                 },        /* POOL32Axf_4~*(71) */
18405     { instruction         , 0                   , 0   , 32,
18406        0xfc00ffff, 0x2000913f, &NMD::PRECEQU_PH_QBR   , 0,
18407        DSP_                },        /* PRECEQU.PH.QBR */
18408     { instruction         , 0                   , 0   , 32,
18409        0xfc00ffff, 0x2000933f, &NMD::PRECEQU_PH_QBRA  , 0,
18410        DSP_                },        /* PRECEQU.PH.QBRA */
18411     { reserved_block      , 0                   , 0   , 32,
18412        0xfc00ffff, 0x2000953f, 0                      , 0,
18413        0x0                 },        /* POOL32Axf_4~*(74) */
18414     { reserved_block      , 0                   , 0   , 32,
18415        0xfc00ffff, 0x2000973f, 0                      , 0,
18416        0x0                 },        /* POOL32Axf_4~*(75) */
18417     { reserved_block      , 0                   , 0   , 32,
18418        0xfc00ffff, 0x2000993f, 0                      , 0,
18419        0x0                 },        /* POOL32Axf_4~*(76) */
18420     { reserved_block      , 0                   , 0   , 32,
18421        0xfc00ffff, 0x20009b3f, 0                      , 0,
18422        0x0                 },        /* POOL32Axf_4~*(77) */
18423     { instruction         , 0                   , 0   , 32,
18424        0xfc00ffff, 0x20009d3f, &NMD::MTHC2            , 0,
18425        CP2_                },        /* MTHC2 */
18426     { reserved_block      , 0                   , 0   , 32,
18427        0xfc00ffff, 0x20009f3f, 0                      , 0,
18428        0x0                 },        /* POOL32Axf_4~*(79) */
18429     { reserved_block      , 0                   , 0   , 32,
18430        0xfc00ffff, 0x2000a13f, 0                      , 0,
18431        0x0                 },        /* POOL32Axf_4~*(80) */
18432     { reserved_block      , 0                   , 0   , 32,
18433        0xfc00ffff, 0x2000a33f, 0                      , 0,
18434        0x0                 },        /* POOL32Axf_4~*(81) */
18435     { reserved_block      , 0                   , 0   , 32,
18436        0xfc00ffff, 0x2000a53f, 0                      , 0,
18437        0x0                 },        /* POOL32Axf_4~*(82) */
18438     { reserved_block      , 0                   , 0   , 32,
18439        0xfc00ffff, 0x2000a73f, 0                      , 0,
18440        0x0                 },        /* POOL32Axf_4~*(83) */
18441     { reserved_block      , 0                   , 0   , 32,
18442        0xfc00ffff, 0x2000a93f, 0                      , 0,
18443        0x0                 },        /* POOL32Axf_4~*(84) */
18444     { reserved_block      , 0                   , 0   , 32,
18445        0xfc00ffff, 0x2000ab3f, 0                      , 0,
18446        0x0                 },        /* POOL32Axf_4~*(85) */
18447     { reserved_block      , 0                   , 0   , 32,
18448        0xfc00ffff, 0x2000ad3f, 0                      , 0,
18449        0x0                 },        /* POOL32Axf_4~*(86) */
18450     { reserved_block      , 0                   , 0   , 32,
18451        0xfc00ffff, 0x2000af3f, 0                      , 0,
18452        0x0                 },        /* POOL32Axf_4~*(87) */
18453     { instruction         , 0                   , 0   , 32,
18454        0xfc00ffff, 0x2000b13f, &NMD::PRECEU_PH_QBL    , 0,
18455        DSP_                },        /* PRECEU.PH.QBL */
18456     { instruction         , 0                   , 0   , 32,
18457        0xfc00ffff, 0x2000b33f, &NMD::PRECEU_PH_QBLA   , 0,
18458        DSP_                },        /* PRECEU.PH.QBLA */
18459     { reserved_block      , 0                   , 0   , 32,
18460        0xfc00ffff, 0x2000b53f, 0                      , 0,
18461        0x0                 },        /* POOL32Axf_4~*(90) */
18462     { reserved_block      , 0                   , 0   , 32,
18463        0xfc00ffff, 0x2000b73f, 0                      , 0,
18464        0x0                 },        /* POOL32Axf_4~*(91) */
18465     { reserved_block      , 0                   , 0   , 32,
18466        0xfc00ffff, 0x2000b93f, 0                      , 0,
18467        0x0                 },        /* POOL32Axf_4~*(92) */
18468     { reserved_block      , 0                   , 0   , 32,
18469        0xfc00ffff, 0x2000bb3f, 0                      , 0,
18470        0x0                 },        /* POOL32Axf_4~*(93) */
18471     { reserved_block      , 0                   , 0   , 32,
18472        0xfc00ffff, 0x2000bd3f, 0                      , 0,
18473        0x0                 },        /* POOL32Axf_4~*(94) */
18474     { reserved_block      , 0                   , 0   , 32,
18475        0xfc00ffff, 0x2000bf3f, 0                      , 0,
18476        0x0                 },        /* POOL32Axf_4~*(95) */
18477     { reserved_block      , 0                   , 0   , 32,
18478        0xfc00ffff, 0x2000c13f, 0                      , 0,
18479        0x0                 },        /* POOL32Axf_4~*(96) */
18480     { reserved_block      , 0                   , 0   , 32,
18481        0xfc00ffff, 0x2000c33f, 0                      , 0,
18482        0x0                 },        /* POOL32Axf_4~*(97) */
18483     { reserved_block      , 0                   , 0   , 32,
18484        0xfc00ffff, 0x2000c53f, 0                      , 0,
18485        0x0                 },        /* POOL32Axf_4~*(98) */
18486     { reserved_block      , 0                   , 0   , 32,
18487        0xfc00ffff, 0x2000c73f, 0                      , 0,
18488        0x0                 },        /* POOL32Axf_4~*(99) */
18489     { reserved_block      , 0                   , 0   , 32,
18490        0xfc00ffff, 0x2000c93f, 0                      , 0,
18491        0x0                 },        /* POOL32Axf_4~*(100) */
18492     { reserved_block      , 0                   , 0   , 32,
18493        0xfc00ffff, 0x2000cb3f, 0                      , 0,
18494        0x0                 },        /* POOL32Axf_4~*(101) */
18495     { instruction         , 0                   , 0   , 32,
18496        0xfc00ffff, 0x2000cd3f, &NMD::CFC2             , 0,
18497        CP2_                },        /* CFC2 */
18498     { reserved_block      , 0                   , 0   , 32,
18499        0xfc00ffff, 0x2000cf3f, 0                      , 0,
18500        0x0                 },        /* POOL32Axf_4~*(103) */
18501     { instruction         , 0                   , 0   , 32,
18502        0xfc00ffff, 0x2000d13f, &NMD::PRECEU_PH_QBR    , 0,
18503        DSP_                },        /* PRECEU.PH.QBR */
18504     { instruction         , 0                   , 0   , 32,
18505        0xfc00ffff, 0x2000d33f, &NMD::PRECEU_PH_QBRA   , 0,
18506        DSP_                },        /* PRECEU.PH.QBRA */
18507     { reserved_block      , 0                   , 0   , 32,
18508        0xfc00ffff, 0x2000d53f, 0                      , 0,
18509        0x0                 },        /* POOL32Axf_4~*(106) */
18510     { reserved_block      , 0                   , 0   , 32,
18511        0xfc00ffff, 0x2000d73f, 0                      , 0,
18512        0x0                 },        /* POOL32Axf_4~*(107) */
18513     { reserved_block      , 0                   , 0   , 32,
18514        0xfc00ffff, 0x2000d93f, 0                      , 0,
18515        0x0                 },        /* POOL32Axf_4~*(108) */
18516     { reserved_block      , 0                   , 0   , 32,
18517        0xfc00ffff, 0x2000db3f, 0                      , 0,
18518        0x0                 },        /* POOL32Axf_4~*(109) */
18519     { instruction         , 0                   , 0   , 32,
18520        0xfc00ffff, 0x2000dd3f, &NMD::CTC2             , 0,
18521        CP2_                },        /* CTC2 */
18522     { reserved_block      , 0                   , 0   , 32,
18523        0xfc00ffff, 0x2000df3f, 0                      , 0,
18524        0x0                 },        /* POOL32Axf_4~*(111) */
18525     { reserved_block      , 0                   , 0   , 32,
18526        0xfc00ffff, 0x2000e13f, 0                      , 0,
18527        0x0                 },        /* POOL32Axf_4~*(112) */
18528     { reserved_block      , 0                   , 0   , 32,
18529        0xfc00ffff, 0x2000e33f, 0                      , 0,
18530        0x0                 },        /* POOL32Axf_4~*(113) */
18531     { reserved_block      , 0                   , 0   , 32,
18532        0xfc00ffff, 0x2000e53f, 0                      , 0,
18533        0x0                 },        /* POOL32Axf_4~*(114) */
18534     { reserved_block      , 0                   , 0   , 32,
18535        0xfc00ffff, 0x2000e73f, 0                      , 0,
18536        0x0                 },        /* POOL32Axf_4~*(115) */
18537     { reserved_block      , 0                   , 0   , 32,
18538        0xfc00ffff, 0x2000e93f, 0                      , 0,
18539        0x0                 },        /* POOL32Axf_4~*(116) */
18540     { reserved_block      , 0                   , 0   , 32,
18541        0xfc00ffff, 0x2000eb3f, 0                      , 0,
18542        0x0                 },        /* POOL32Axf_4~*(117) */
18543     { reserved_block      , 0                   , 0   , 32,
18544        0xfc00ffff, 0x2000ed3f, 0                      , 0,
18545        0x0                 },        /* POOL32Axf_4~*(118) */
18546     { reserved_block      , 0                   , 0   , 32,
18547        0xfc00ffff, 0x2000ef3f, 0                      , 0,
18548        0x0                 },        /* POOL32Axf_4~*(119) */
18549     { instruction         , 0                   , 0   , 32,
18550        0xfc00ffff, 0x2000f13f, &NMD::RADDU_W_QB       , 0,
18551        DSP_                },        /* RADDU.W.QB */
18552     { reserved_block      , 0                   , 0   , 32,
18553        0xfc00ffff, 0x2000f33f, 0                      , 0,
18554        0x0                 },        /* POOL32Axf_4~*(121) */
18555     { reserved_block      , 0                   , 0   , 32,
18556        0xfc00ffff, 0x2000f53f, 0                      , 0,
18557        0x0                 },        /* POOL32Axf_4~*(122) */
18558     { reserved_block      , 0                   , 0   , 32,
18559        0xfc00ffff, 0x2000f73f, 0                      , 0,
18560        0x0                 },        /* POOL32Axf_4~*(123) */
18561     { reserved_block      , 0                   , 0   , 32,
18562        0xfc00ffff, 0x2000f93f, 0                      , 0,
18563        0x0                 },        /* POOL32Axf_4~*(124) */
18564     { reserved_block      , 0                   , 0   , 32,
18565        0xfc00ffff, 0x2000fb3f, 0                      , 0,
18566        0x0                 },        /* POOL32Axf_4~*(125) */
18567     { reserved_block      , 0                   , 0   , 32,
18568        0xfc00ffff, 0x2000fd3f, 0                      , 0,
18569        0x0                 },        /* POOL32Axf_4~*(126) */
18570     { reserved_block      , 0                   , 0   , 32,
18571        0xfc00ffff, 0x2000ff3f, 0                      , 0,
18572        0x0                 },        /* POOL32Axf_4~*(127) */
18573 };
18574
18575
18576 NMD::Pool NMD::POOL32Axf_5_group0[32] = {
18577     { instruction         , 0                   , 0   , 32,
18578        0xfc00ffff, 0x2000017f, &NMD::TLBGP            , 0,
18579        CP0_ | VZ_ | TLB_   },        /* TLBGP */
18580     { instruction         , 0                   , 0   , 32,
18581        0xfc00ffff, 0x2000037f, &NMD::TLBP             , 0,
18582        CP0_ | TLB_         },        /* TLBP */
18583     { instruction         , 0                   , 0   , 32,
18584        0xfc00ffff, 0x2000057f, &NMD::TLBGINV          , 0,
18585        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINV */
18586     { instruction         , 0                   , 0   , 32,
18587        0xfc00ffff, 0x2000077f, &NMD::TLBINV           , 0,
18588        CP0_ | TLB_ | TLBINV_},        /* TLBINV */
18589     { reserved_block      , 0                   , 0   , 32,
18590        0xfc00ffff, 0x2000097f, 0                      , 0,
18591        0x0                 },        /* POOL32Axf_5_group0~*(4) */
18592     { reserved_block      , 0                   , 0   , 32,
18593        0xfc00ffff, 0x20000b7f, 0                      , 0,
18594        0x0                 },        /* POOL32Axf_5_group0~*(5) */
18595     { reserved_block      , 0                   , 0   , 32,
18596        0xfc00ffff, 0x20000d7f, 0                      , 0,
18597        0x0                 },        /* POOL32Axf_5_group0~*(6) */
18598     { reserved_block      , 0                   , 0   , 32,
18599        0xfc00ffff, 0x20000f7f, 0                      , 0,
18600        0x0                 },        /* POOL32Axf_5_group0~*(7) */
18601     { instruction         , 0                   , 0   , 32,
18602        0xfc00ffff, 0x2000117f, &NMD::TLBGR            , 0,
18603        CP0_ | VZ_ | TLB_   },        /* TLBGR */
18604     { instruction         , 0                   , 0   , 32,
18605        0xfc00ffff, 0x2000137f, &NMD::TLBR             , 0,
18606        CP0_ | TLB_         },        /* TLBR */
18607     { instruction         , 0                   , 0   , 32,
18608        0xfc00ffff, 0x2000157f, &NMD::TLBGINVF         , 0,
18609        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINVF */
18610     { instruction         , 0                   , 0   , 32,
18611        0xfc00ffff, 0x2000177f, &NMD::TLBINVF          , 0,
18612        CP0_ | TLB_ | TLBINV_},        /* TLBINVF */
18613     { reserved_block      , 0                   , 0   , 32,
18614        0xfc00ffff, 0x2000197f, 0                      , 0,
18615        0x0                 },        /* POOL32Axf_5_group0~*(12) */
18616     { reserved_block      , 0                   , 0   , 32,
18617        0xfc00ffff, 0x20001b7f, 0                      , 0,
18618        0x0                 },        /* POOL32Axf_5_group0~*(13) */
18619     { reserved_block      , 0                   , 0   , 32,
18620        0xfc00ffff, 0x20001d7f, 0                      , 0,
18621        0x0                 },        /* POOL32Axf_5_group0~*(14) */
18622     { reserved_block      , 0                   , 0   , 32,
18623        0xfc00ffff, 0x20001f7f, 0                      , 0,
18624        0x0                 },        /* POOL32Axf_5_group0~*(15) */
18625     { instruction         , 0                   , 0   , 32,
18626        0xfc00ffff, 0x2000217f, &NMD::TLBGWI           , 0,
18627        CP0_ | VZ_ | TLB_   },        /* TLBGWI */
18628     { instruction         , 0                   , 0   , 32,
18629        0xfc00ffff, 0x2000237f, &NMD::TLBWI            , 0,
18630        CP0_ | TLB_         },        /* TLBWI */
18631     { reserved_block      , 0                   , 0   , 32,
18632        0xfc00ffff, 0x2000257f, 0                      , 0,
18633        0x0                 },        /* POOL32Axf_5_group0~*(18) */
18634     { reserved_block      , 0                   , 0   , 32,
18635        0xfc00ffff, 0x2000277f, 0                      , 0,
18636        0x0                 },        /* POOL32Axf_5_group0~*(19) */
18637     { reserved_block      , 0                   , 0   , 32,
18638        0xfc00ffff, 0x2000297f, 0                      , 0,
18639        0x0                 },        /* POOL32Axf_5_group0~*(20) */
18640     { reserved_block      , 0                   , 0   , 32,
18641        0xfc00ffff, 0x20002b7f, 0                      , 0,
18642        0x0                 },        /* POOL32Axf_5_group0~*(21) */
18643     { reserved_block      , 0                   , 0   , 32,
18644        0xfc00ffff, 0x20002d7f, 0                      , 0,
18645        0x0                 },        /* POOL32Axf_5_group0~*(22) */
18646     { reserved_block      , 0                   , 0   , 32,
18647        0xfc00ffff, 0x20002f7f, 0                      , 0,
18648        0x0                 },        /* POOL32Axf_5_group0~*(23) */
18649     { instruction         , 0                   , 0   , 32,
18650        0xfc00ffff, 0x2000317f, &NMD::TLBGWR           , 0,
18651        CP0_ | VZ_ | TLB_   },        /* TLBGWR */
18652     { instruction         , 0                   , 0   , 32,
18653        0xfc00ffff, 0x2000337f, &NMD::TLBWR            , 0,
18654        CP0_ | TLB_         },        /* TLBWR */
18655     { reserved_block      , 0                   , 0   , 32,
18656        0xfc00ffff, 0x2000357f, 0                      , 0,
18657        0x0                 },        /* POOL32Axf_5_group0~*(26) */
18658     { reserved_block      , 0                   , 0   , 32,
18659        0xfc00ffff, 0x2000377f, 0                      , 0,
18660        0x0                 },        /* POOL32Axf_5_group0~*(27) */
18661     { reserved_block      , 0                   , 0   , 32,
18662        0xfc00ffff, 0x2000397f, 0                      , 0,
18663        0x0                 },        /* POOL32Axf_5_group0~*(28) */
18664     { reserved_block      , 0                   , 0   , 32,
18665        0xfc00ffff, 0x20003b7f, 0                      , 0,
18666        0x0                 },        /* POOL32Axf_5_group0~*(29) */
18667     { reserved_block      , 0                   , 0   , 32,
18668        0xfc00ffff, 0x20003d7f, 0                      , 0,
18669        0x0                 },        /* POOL32Axf_5_group0~*(30) */
18670     { reserved_block      , 0                   , 0   , 32,
18671        0xfc00ffff, 0x20003f7f, 0                      , 0,
18672        0x0                 },        /* POOL32Axf_5_group0~*(31) */
18673 };
18674
18675
18676 NMD::Pool NMD::POOL32Axf_5_group1[32] = {
18677     { reserved_block      , 0                   , 0   , 32,
18678        0xfc00ffff, 0x2000417f, 0                      , 0,
18679        0x0                 },        /* POOL32Axf_5_group1~*(0) */
18680     { reserved_block      , 0                   , 0   , 32,
18681        0xfc00ffff, 0x2000437f, 0                      , 0,
18682        0x0                 },        /* POOL32Axf_5_group1~*(1) */
18683     { reserved_block      , 0                   , 0   , 32,
18684        0xfc00ffff, 0x2000457f, 0                      , 0,
18685        0x0                 },        /* POOL32Axf_5_group1~*(2) */
18686     { instruction         , 0                   , 0   , 32,
18687        0xfc00ffff, 0x2000477f, &NMD::DI               , 0,
18688        0x0                 },        /* DI */
18689     { reserved_block      , 0                   , 0   , 32,
18690        0xfc00ffff, 0x2000497f, 0                      , 0,
18691        0x0                 },        /* POOL32Axf_5_group1~*(4) */
18692     { reserved_block      , 0                   , 0   , 32,
18693        0xfc00ffff, 0x20004b7f, 0                      , 0,
18694        0x0                 },        /* POOL32Axf_5_group1~*(5) */
18695     { reserved_block      , 0                   , 0   , 32,
18696        0xfc00ffff, 0x20004d7f, 0                      , 0,
18697        0x0                 },        /* POOL32Axf_5_group1~*(6) */
18698     { reserved_block      , 0                   , 0   , 32,
18699        0xfc00ffff, 0x20004f7f, 0                      , 0,
18700        0x0                 },        /* POOL32Axf_5_group1~*(7) */
18701     { reserved_block      , 0                   , 0   , 32,
18702        0xfc00ffff, 0x2000517f, 0                      , 0,
18703        0x0                 },        /* POOL32Axf_5_group1~*(8) */
18704     { reserved_block      , 0                   , 0   , 32,
18705        0xfc00ffff, 0x2000537f, 0                      , 0,
18706        0x0                 },        /* POOL32Axf_5_group1~*(9) */
18707     { reserved_block      , 0                   , 0   , 32,
18708        0xfc00ffff, 0x2000557f, 0                      , 0,
18709        0x0                 },        /* POOL32Axf_5_group1~*(10) */
18710     { instruction         , 0                   , 0   , 32,
18711        0xfc00ffff, 0x2000577f, &NMD::EI               , 0,
18712        0x0                 },        /* EI */
18713     { reserved_block      , 0                   , 0   , 32,
18714        0xfc00ffff, 0x2000597f, 0                      , 0,
18715        0x0                 },        /* POOL32Axf_5_group1~*(12) */
18716     { reserved_block      , 0                   , 0   , 32,
18717        0xfc00ffff, 0x20005b7f, 0                      , 0,
18718        0x0                 },        /* POOL32Axf_5_group1~*(13) */
18719     { reserved_block      , 0                   , 0   , 32,
18720        0xfc00ffff, 0x20005d7f, 0                      , 0,
18721        0x0                 },        /* POOL32Axf_5_group1~*(14) */
18722     { reserved_block      , 0                   , 0   , 32,
18723        0xfc00ffff, 0x20005f7f, 0                      , 0,
18724        0x0                 },        /* POOL32Axf_5_group1~*(15) */
18725     { reserved_block      , 0                   , 0   , 32,
18726        0xfc00ffff, 0x2000617f, 0                      , 0,
18727        0x0                 },        /* POOL32Axf_5_group1~*(16) */
18728     { reserved_block      , 0                   , 0   , 32,
18729        0xfc00ffff, 0x2000637f, 0                      , 0,
18730        0x0                 },        /* POOL32Axf_5_group1~*(17) */
18731     { reserved_block      , 0                   , 0   , 32,
18732        0xfc00ffff, 0x2000657f, 0                      , 0,
18733        0x0                 },        /* POOL32Axf_5_group1~*(18) */
18734     { reserved_block      , 0                   , 0   , 32,
18735        0xfc00ffff, 0x2000677f, 0                      , 0,
18736        0x0                 },        /* POOL32Axf_5_group1~*(19) */
18737     { reserved_block      , 0                   , 0   , 32,
18738        0xfc00ffff, 0x2000697f, 0                      , 0,
18739        0x0                 },        /* POOL32Axf_5_group1~*(20) */
18740     { reserved_block      , 0                   , 0   , 32,
18741        0xfc00ffff, 0x20006b7f, 0                      , 0,
18742        0x0                 },        /* POOL32Axf_5_group1~*(21) */
18743     { reserved_block      , 0                   , 0   , 32,
18744        0xfc00ffff, 0x20006d7f, 0                      , 0,
18745        0x0                 },        /* POOL32Axf_5_group1~*(22) */
18746     { reserved_block      , 0                   , 0   , 32,
18747        0xfc00ffff, 0x20006f7f, 0                      , 0,
18748        0x0                 },        /* POOL32Axf_5_group1~*(23) */
18749     { reserved_block      , 0                   , 0   , 32,
18750        0xfc00ffff, 0x2000717f, 0                      , 0,
18751        0x0                 },        /* POOL32Axf_5_group1~*(24) */
18752     { reserved_block      , 0                   , 0   , 32,
18753        0xfc00ffff, 0x2000737f, 0                      , 0,
18754        0x0                 },        /* POOL32Axf_5_group1~*(25) */
18755     { reserved_block      , 0                   , 0   , 32,
18756        0xfc00ffff, 0x2000757f, 0                      , 0,
18757        0x0                 },        /* POOL32Axf_5_group1~*(26) */
18758     { reserved_block      , 0                   , 0   , 32,
18759        0xfc00ffff, 0x2000777f, 0                      , 0,
18760        0x0                 },        /* POOL32Axf_5_group1~*(27) */
18761     { reserved_block      , 0                   , 0   , 32,
18762        0xfc00ffff, 0x2000797f, 0                      , 0,
18763        0x0                 },        /* POOL32Axf_5_group1~*(28) */
18764     { reserved_block      , 0                   , 0   , 32,
18765        0xfc00ffff, 0x20007b7f, 0                      , 0,
18766        0x0                 },        /* POOL32Axf_5_group1~*(29) */
18767     { reserved_block      , 0                   , 0   , 32,
18768        0xfc00ffff, 0x20007d7f, 0                      , 0,
18769        0x0                 },        /* POOL32Axf_5_group1~*(30) */
18770     { reserved_block      , 0                   , 0   , 32,
18771        0xfc00ffff, 0x20007f7f, 0                      , 0,
18772        0x0                 },        /* POOL32Axf_5_group1~*(31) */
18773 };
18774
18775
18776 NMD::Pool NMD::ERETx[2] = {
18777     { instruction         , 0                   , 0   , 32,
18778        0xfc01ffff, 0x2000f37f, &NMD::ERET             , 0,
18779        0x0                 },        /* ERET */
18780     { instruction         , 0                   , 0   , 32,
18781        0xfc01ffff, 0x2001f37f, &NMD::ERETNC           , 0,
18782        0x0                 },        /* ERETNC */
18783 };
18784
18785
18786 NMD::Pool NMD::POOL32Axf_5_group3[32] = {
18787     { reserved_block      , 0                   , 0   , 32,
18788        0xfc00ffff, 0x2000c17f, 0                      , 0,
18789        0x0                 },        /* POOL32Axf_5_group3~*(0) */
18790     { instruction         , 0                   , 0   , 32,
18791        0xfc00ffff, 0x2000c37f, &NMD::WAIT             , 0,
18792        0x0                 },        /* WAIT */
18793     { reserved_block      , 0                   , 0   , 32,
18794        0xfc00ffff, 0x2000c57f, 0                      , 0,
18795        0x0                 },        /* POOL32Axf_5_group3~*(2) */
18796     { reserved_block      , 0                   , 0   , 32,
18797        0xfc00ffff, 0x2000c77f, 0                      , 0,
18798        0x0                 },        /* POOL32Axf_5_group3~*(3) */
18799     { reserved_block      , 0                   , 0   , 32,
18800        0xfc00ffff, 0x2000c97f, 0                      , 0,
18801        0x0                 },        /* POOL32Axf_5_group3~*(4) */
18802     { reserved_block      , 0                   , 0   , 32,
18803        0xfc00ffff, 0x2000cb7f, 0                      , 0,
18804        0x0                 },        /* POOL32Axf_5_group3~*(5) */
18805     { reserved_block      , 0                   , 0   , 32,
18806        0xfc00ffff, 0x2000cd7f, 0                      , 0,
18807        0x0                 },        /* POOL32Axf_5_group3~*(6) */
18808     { reserved_block      , 0                   , 0   , 32,
18809        0xfc00ffff, 0x2000cf7f, 0                      , 0,
18810        0x0                 },        /* POOL32Axf_5_group3~*(7) */
18811     { reserved_block      , 0                   , 0   , 32,
18812        0xfc00ffff, 0x2000d17f, 0                      , 0,
18813        0x0                 },        /* POOL32Axf_5_group3~*(8) */
18814     { instruction         , 0                   , 0   , 32,
18815        0xfc00ffff, 0x2000d37f, &NMD::IRET             , 0,
18816        MCU_                },        /* IRET */
18817     { reserved_block      , 0                   , 0   , 32,
18818        0xfc00ffff, 0x2000d57f, 0                      , 0,
18819        0x0                 },        /* POOL32Axf_5_group3~*(10) */
18820     { reserved_block      , 0                   , 0   , 32,
18821        0xfc00ffff, 0x2000d77f, 0                      , 0,
18822        0x0                 },        /* POOL32Axf_5_group3~*(11) */
18823     { reserved_block      , 0                   , 0   , 32,
18824        0xfc00ffff, 0x2000d97f, 0                      , 0,
18825        0x0                 },        /* POOL32Axf_5_group3~*(12) */
18826     { reserved_block      , 0                   , 0   , 32,
18827        0xfc00ffff, 0x2000db7f, 0                      , 0,
18828        0x0                 },        /* POOL32Axf_5_group3~*(13) */
18829     { reserved_block      , 0                   , 0   , 32,
18830        0xfc00ffff, 0x2000dd7f, 0                      , 0,
18831        0x0                 },        /* POOL32Axf_5_group3~*(14) */
18832     { reserved_block      , 0                   , 0   , 32,
18833        0xfc00ffff, 0x2000df7f, 0                      , 0,
18834        0x0                 },        /* POOL32Axf_5_group3~*(15) */
18835     { instruction         , 0                   , 0   , 32,
18836        0xfc00ffff, 0x2000e17f, &NMD::RDPGPR           , 0,
18837        CP0_                },        /* RDPGPR */
18838     { instruction         , 0                   , 0   , 32,
18839        0xfc00ffff, 0x2000e37f, &NMD::DERET            , 0,
18840        EJTAG_              },        /* DERET */
18841     { reserved_block      , 0                   , 0   , 32,
18842        0xfc00ffff, 0x2000e57f, 0                      , 0,
18843        0x0                 },        /* POOL32Axf_5_group3~*(18) */
18844     { reserved_block      , 0                   , 0   , 32,
18845        0xfc00ffff, 0x2000e77f, 0                      , 0,
18846        0x0                 },        /* POOL32Axf_5_group3~*(19) */
18847     { reserved_block      , 0                   , 0   , 32,
18848        0xfc00ffff, 0x2000e97f, 0                      , 0,
18849        0x0                 },        /* POOL32Axf_5_group3~*(20) */
18850     { reserved_block      , 0                   , 0   , 32,
18851        0xfc00ffff, 0x2000eb7f, 0                      , 0,
18852        0x0                 },        /* POOL32Axf_5_group3~*(21) */
18853     { reserved_block      , 0                   , 0   , 32,
18854        0xfc00ffff, 0x2000ed7f, 0                      , 0,
18855        0x0                 },        /* POOL32Axf_5_group3~*(22) */
18856     { reserved_block      , 0                   , 0   , 32,
18857        0xfc00ffff, 0x2000ef7f, 0                      , 0,
18858        0x0                 },        /* POOL32Axf_5_group3~*(23) */
18859     { instruction         , 0                   , 0   , 32,
18860        0xfc00ffff, 0x2000f17f, &NMD::WRPGPR           , 0,
18861        CP0_                },        /* WRPGPR */
18862     { pool                , ERETx               , 2   , 32,
18863        0xfc00ffff, 0x2000f37f, 0                      , 0,
18864        0x0                 },        /* ERETx */
18865     { reserved_block      , 0                   , 0   , 32,
18866        0xfc00ffff, 0x2000f57f, 0                      , 0,
18867        0x0                 },        /* POOL32Axf_5_group3~*(26) */
18868     { reserved_block      , 0                   , 0   , 32,
18869        0xfc00ffff, 0x2000f77f, 0                      , 0,
18870        0x0                 },        /* POOL32Axf_5_group3~*(27) */
18871     { reserved_block      , 0                   , 0   , 32,
18872        0xfc00ffff, 0x2000f97f, 0                      , 0,
18873        0x0                 },        /* POOL32Axf_5_group3~*(28) */
18874     { reserved_block      , 0                   , 0   , 32,
18875        0xfc00ffff, 0x2000fb7f, 0                      , 0,
18876        0x0                 },        /* POOL32Axf_5_group3~*(29) */
18877     { reserved_block      , 0                   , 0   , 32,
18878        0xfc00ffff, 0x2000fd7f, 0                      , 0,
18879        0x0                 },        /* POOL32Axf_5_group3~*(30) */
18880     { reserved_block      , 0                   , 0   , 32,
18881        0xfc00ffff, 0x2000ff7f, 0                      , 0,
18882        0x0                 },        /* POOL32Axf_5_group3~*(31) */
18883 };
18884
18885
18886 NMD::Pool NMD::POOL32Axf_5[4] = {
18887     { pool                , POOL32Axf_5_group0  , 32  , 32,
18888        0xfc00c1ff, 0x2000017f, 0                      , 0,
18889        0x0                 },        /* POOL32Axf_5_group0 */
18890     { pool                , POOL32Axf_5_group1  , 32  , 32,
18891        0xfc00c1ff, 0x2000417f, 0                      , 0,
18892        0x0                 },        /* POOL32Axf_5_group1 */
18893     { reserved_block      , 0                   , 0   , 32,
18894        0xfc00c1ff, 0x2000817f, 0                      , 0,
18895        0x0                 },        /* POOL32Axf_5~*(2) */
18896     { pool                , POOL32Axf_5_group3  , 32  , 32,
18897        0xfc00c1ff, 0x2000c17f, 0                      , 0,
18898        0x0                 },        /* POOL32Axf_5_group3 */
18899 };
18900
18901
18902 NMD::Pool NMD::SHRA__R__QB[2] = {
18903     { instruction         , 0                   , 0   , 32,
18904        0xfc001fff, 0x200001ff, &NMD::SHRA_QB          , 0,
18905        DSP_                },        /* SHRA.QB */
18906     { instruction         , 0                   , 0   , 32,
18907        0xfc001fff, 0x200011ff, &NMD::SHRA_R_QB        , 0,
18908        DSP_                },        /* SHRA_R.QB */
18909 };
18910
18911
18912 NMD::Pool NMD::POOL32Axf_7[8] = {
18913     { pool                , SHRA__R__QB         , 2   , 32,
18914        0xfc000fff, 0x200001ff, 0                      , 0,
18915        0x0                 },        /* SHRA[_R].QB */
18916     { instruction         , 0                   , 0   , 32,
18917        0xfc000fff, 0x200003ff, &NMD::SHRL_PH          , 0,
18918        DSP_                },        /* SHRL.PH */
18919     { instruction         , 0                   , 0   , 32,
18920        0xfc000fff, 0x200005ff, &NMD::REPL_QB          , 0,
18921        DSP_                },        /* REPL.QB */
18922     { reserved_block      , 0                   , 0   , 32,
18923        0xfc000fff, 0x200007ff, 0                      , 0,
18924        0x0                 },        /* POOL32Axf_7~*(3) */
18925     { reserved_block      , 0                   , 0   , 32,
18926        0xfc000fff, 0x200009ff, 0                      , 0,
18927        0x0                 },        /* POOL32Axf_7~*(4) */
18928     { reserved_block      , 0                   , 0   , 32,
18929        0xfc000fff, 0x20000bff, 0                      , 0,
18930        0x0                 },        /* POOL32Axf_7~*(5) */
18931     { reserved_block      , 0                   , 0   , 32,
18932        0xfc000fff, 0x20000dff, 0                      , 0,
18933        0x0                 },        /* POOL32Axf_7~*(6) */
18934     { reserved_block      , 0                   , 0   , 32,
18935        0xfc000fff, 0x20000fff, 0                      , 0,
18936        0x0                 },        /* POOL32Axf_7~*(7) */
18937 };
18938
18939
18940 NMD::Pool NMD::POOL32Axf[8] = {
18941     { reserved_block      , 0                   , 0   , 32,
18942        0xfc0001ff, 0x2000003f, 0                      , 0,
18943        0x0                 },        /* POOL32Axf~*(0) */
18944     { pool                , POOL32Axf_1         , 8   , 32,
18945        0xfc0001ff, 0x2000007f, 0                      , 0,
18946        0x0                 },        /* POOL32Axf_1 */
18947     { pool                , POOL32Axf_2         , 4   , 32,
18948        0xfc0001ff, 0x200000bf, 0                      , 0,
18949        0x0                 },        /* POOL32Axf_2 */
18950     { reserved_block      , 0                   , 0   , 32,
18951        0xfc0001ff, 0x200000ff, 0                      , 0,
18952        0x0                 },        /* POOL32Axf~*(3) */
18953     { pool                , POOL32Axf_4         , 128 , 32,
18954        0xfc0001ff, 0x2000013f, 0                      , 0,
18955        0x0                 },        /* POOL32Axf_4 */
18956     { pool                , POOL32Axf_5         , 4   , 32,
18957        0xfc0001ff, 0x2000017f, 0                      , 0,
18958        0x0                 },        /* POOL32Axf_5 */
18959     { reserved_block      , 0                   , 0   , 32,
18960        0xfc0001ff, 0x200001bf, 0                      , 0,
18961        0x0                 },        /* POOL32Axf~*(6) */
18962     { pool                , POOL32Axf_7         , 8   , 32,
18963        0xfc0001ff, 0x200001ff, 0                      , 0,
18964        0x0                 },        /* POOL32Axf_7 */
18965 };
18966
18967
18968 NMD::Pool NMD::_POOL32A7[8] = {
18969     { pool                , P_LSX               , 2   , 32,
18970        0xfc00003f, 0x20000007, 0                      , 0,
18971        0x0                 },        /* P.LSX */
18972     { instruction         , 0                   , 0   , 32,
18973        0xfc00003f, 0x2000000f, &NMD::LSA              , 0,
18974        0x0                 },        /* LSA */
18975     { reserved_block      , 0                   , 0   , 32,
18976        0xfc00003f, 0x20000017, 0                      , 0,
18977        0x0                 },        /* _POOL32A7~*(2) */
18978     { instruction         , 0                   , 0   , 32,
18979        0xfc00003f, 0x2000001f, &NMD::EXTW             , 0,
18980        0x0                 },        /* EXTW */
18981     { reserved_block      , 0                   , 0   , 32,
18982        0xfc00003f, 0x20000027, 0                      , 0,
18983        0x0                 },        /* _POOL32A7~*(4) */
18984     { reserved_block      , 0                   , 0   , 32,
18985        0xfc00003f, 0x2000002f, 0                      , 0,
18986        0x0                 },        /* _POOL32A7~*(5) */
18987     { reserved_block      , 0                   , 0   , 32,
18988        0xfc00003f, 0x20000037, 0                      , 0,
18989        0x0                 },        /* _POOL32A7~*(6) */
18990     { pool                , POOL32Axf           , 8   , 32,
18991        0xfc00003f, 0x2000003f, 0                      , 0,
18992        0x0                 },        /* POOL32Axf */
18993 };
18994
18995
18996 NMD::Pool NMD::P32A[8] = {
18997     { pool                , _POOL32A0           , 128 , 32,
18998        0xfc000007, 0x20000000, 0                      , 0,
18999        0x0                 },        /* _POOL32A0 */
19000     { instruction         , 0                   , 0   , 32,
19001        0xfc000007, 0x20000001, &NMD::SPECIAL2         , 0,
19002        UDI_                },        /* SPECIAL2 */
19003     { instruction         , 0                   , 0   , 32,
19004        0xfc000007, 0x20000002, &NMD::COP2_1           , 0,
19005        CP2_                },        /* COP2_1 */
19006     { instruction         , 0                   , 0   , 32,
19007        0xfc000007, 0x20000003, &NMD::UDI              , 0,
19008        UDI_                },        /* UDI */
19009     { reserved_block      , 0                   , 0   , 32,
19010        0xfc000007, 0x20000004, 0                      , 0,
19011        0x0                 },        /* P32A~*(4) */
19012     { pool                , _POOL32A5           , 128 , 32,
19013        0xfc000007, 0x20000005, 0                      , 0,
19014        0x0                 },        /* _POOL32A5 */
19015     { reserved_block      , 0                   , 0   , 32,
19016        0xfc000007, 0x20000006, 0                      , 0,
19017        0x0                 },        /* P32A~*(6) */
19018     { pool                , _POOL32A7           , 8   , 32,
19019        0xfc000007, 0x20000007, 0                      , 0,
19020        0x0                 },        /* _POOL32A7 */
19021 };
19022
19023
19024 NMD::Pool NMD::P_GP_D[2] = {
19025     { instruction         , 0                   , 0   , 32,
19026        0xfc000007, 0x40000001, &NMD::LD_GP_           , 0,
19027        MIPS64_             },        /* LD[GP] */
19028     { instruction         , 0                   , 0   , 32,
19029        0xfc000007, 0x40000005, &NMD::SD_GP_           , 0,
19030        MIPS64_             },        /* SD[GP] */
19031 };
19032
19033
19034 NMD::Pool NMD::P_GP_W[4] = {
19035     { instruction         , 0                   , 0   , 32,
19036        0xfc000003, 0x40000000, &NMD::ADDIU_GP_W_      , 0,
19037        0x0                 },        /* ADDIU[GP.W] */
19038     { pool                , P_GP_D              , 2   , 32,
19039        0xfc000003, 0x40000001, 0                      , 0,
19040        0x0                 },        /* P.GP.D */
19041     { instruction         , 0                   , 0   , 32,
19042        0xfc000003, 0x40000002, &NMD::LW_GP_           , 0,
19043        0x0                 },        /* LW[GP] */
19044     { instruction         , 0                   , 0   , 32,
19045        0xfc000003, 0x40000003, &NMD::SW_GP_           , 0,
19046        0x0                 },        /* SW[GP] */
19047 };
19048
19049
19050 NMD::Pool NMD::POOL48I[32] = {
19051     { instruction         , 0                   , 0   , 48,
19052        0xfc1f00000000ull, 0x600000000000ull, &NMD::LI_48_           , 0,
19053        XMMS_               },        /* LI[48] */
19054     { instruction         , 0                   , 0   , 48,
19055        0xfc1f00000000ull, 0x600100000000ull, &NMD::ADDIU_48_        , 0,
19056        XMMS_               },        /* ADDIU[48] */
19057     { instruction         , 0                   , 0   , 48,
19058        0xfc1f00000000ull, 0x600200000000ull, &NMD::ADDIU_GP48_      , 0,
19059        XMMS_               },        /* ADDIU[GP48] */
19060     { instruction         , 0                   , 0   , 48,
19061        0xfc1f00000000ull, 0x600300000000ull, &NMD::ADDIUPC_48_      , 0,
19062        XMMS_               },        /* ADDIUPC[48] */
19063     { reserved_block      , 0                   , 0   , 48,
19064        0xfc1f00000000ull, 0x600400000000ull, 0                      , 0,
19065        0x0                 },        /* POOL48I~*(4) */
19066     { reserved_block      , 0                   , 0   , 48,
19067        0xfc1f00000000ull, 0x600500000000ull, 0                      , 0,
19068        0x0                 },        /* POOL48I~*(5) */
19069     { reserved_block      , 0                   , 0   , 48,
19070        0xfc1f00000000ull, 0x600600000000ull, 0                      , 0,
19071        0x0                 },        /* POOL48I~*(6) */
19072     { reserved_block      , 0                   , 0   , 48,
19073        0xfc1f00000000ull, 0x600700000000ull, 0                      , 0,
19074        0x0                 },        /* POOL48I~*(7) */
19075     { reserved_block      , 0                   , 0   , 48,
19076        0xfc1f00000000ull, 0x600800000000ull, 0                      , 0,
19077        0x0                 },        /* POOL48I~*(8) */
19078     { reserved_block      , 0                   , 0   , 48,
19079        0xfc1f00000000ull, 0x600900000000ull, 0                      , 0,
19080        0x0                 },        /* POOL48I~*(9) */
19081     { reserved_block      , 0                   , 0   , 48,
19082        0xfc1f00000000ull, 0x600a00000000ull, 0                      , 0,
19083        0x0                 },        /* POOL48I~*(10) */
19084     { instruction         , 0                   , 0   , 48,
19085        0xfc1f00000000ull, 0x600b00000000ull, &NMD::LWPC_48_         , 0,
19086        XMMS_               },        /* LWPC[48] */
19087     { reserved_block      , 0                   , 0   , 48,
19088        0xfc1f00000000ull, 0x600c00000000ull, 0                      , 0,
19089        0x0                 },        /* POOL48I~*(12) */
19090     { reserved_block      , 0                   , 0   , 48,
19091        0xfc1f00000000ull, 0x600d00000000ull, 0                      , 0,
19092        0x0                 },        /* POOL48I~*(13) */
19093     { reserved_block      , 0                   , 0   , 48,
19094        0xfc1f00000000ull, 0x600e00000000ull, 0                      , 0,
19095        0x0                 },        /* POOL48I~*(14) */
19096     { instruction         , 0                   , 0   , 48,
19097        0xfc1f00000000ull, 0x600f00000000ull, &NMD::SWPC_48_         , 0,
19098        XMMS_               },        /* SWPC[48] */
19099     { reserved_block      , 0                   , 0   , 48,
19100        0xfc1f00000000ull, 0x601000000000ull, 0                      , 0,
19101        0x0                 },        /* POOL48I~*(16) */
19102     { instruction         , 0                   , 0   , 48,
19103        0xfc1f00000000ull, 0x601100000000ull, &NMD::DADDIU_48_       , 0,
19104        MIPS64_             },        /* DADDIU[48] */
19105     { reserved_block      , 0                   , 0   , 48,
19106        0xfc1f00000000ull, 0x601200000000ull, 0                      , 0,
19107        0x0                 },        /* POOL48I~*(18) */
19108     { reserved_block      , 0                   , 0   , 48,
19109        0xfc1f00000000ull, 0x601300000000ull, 0                      , 0,
19110        0x0                 },        /* POOL48I~*(19) */
19111     { instruction         , 0                   , 0   , 48,
19112        0xfc1f00000000ull, 0x601400000000ull, &NMD::DLUI_48_         , 0,
19113        MIPS64_             },        /* DLUI[48] */
19114     { reserved_block      , 0                   , 0   , 48,
19115        0xfc1f00000000ull, 0x601500000000ull, 0                      , 0,
19116        0x0                 },        /* POOL48I~*(21) */
19117     { reserved_block      , 0                   , 0   , 48,
19118        0xfc1f00000000ull, 0x601600000000ull, 0                      , 0,
19119        0x0                 },        /* POOL48I~*(22) */
19120     { reserved_block      , 0                   , 0   , 48,
19121        0xfc1f00000000ull, 0x601700000000ull, 0                      , 0,
19122        0x0                 },        /* POOL48I~*(23) */
19123     { reserved_block      , 0                   , 0   , 48,
19124        0xfc1f00000000ull, 0x601800000000ull, 0                      , 0,
19125        0x0                 },        /* POOL48I~*(24) */
19126     { reserved_block      , 0                   , 0   , 48,
19127        0xfc1f00000000ull, 0x601900000000ull, 0                      , 0,
19128        0x0                 },        /* POOL48I~*(25) */
19129     { reserved_block      , 0                   , 0   , 48,
19130        0xfc1f00000000ull, 0x601a00000000ull, 0                      , 0,
19131        0x0                 },        /* POOL48I~*(26) */
19132     { instruction         , 0                   , 0   , 48,
19133        0xfc1f00000000ull, 0x601b00000000ull, &NMD::LDPC_48_         , 0,
19134        MIPS64_             },        /* LDPC[48] */
19135     { reserved_block      , 0                   , 0   , 48,
19136        0xfc1f00000000ull, 0x601c00000000ull, 0                      , 0,
19137        0x0                 },        /* POOL48I~*(28) */
19138     { reserved_block      , 0                   , 0   , 48,
19139        0xfc1f00000000ull, 0x601d00000000ull, 0                      , 0,
19140        0x0                 },        /* POOL48I~*(29) */
19141     { reserved_block      , 0                   , 0   , 48,
19142        0xfc1f00000000ull, 0x601e00000000ull, 0                      , 0,
19143        0x0                 },        /* POOL48I~*(30) */
19144     { instruction         , 0                   , 0   , 48,
19145        0xfc1f00000000ull, 0x601f00000000ull, &NMD::SDPC_48_         , 0,
19146        MIPS64_             },        /* SDPC[48] */
19147 };
19148
19149
19150 NMD::Pool NMD::PP_SR[4] = {
19151     { instruction         , 0                   , 0   , 32,
19152        0xfc10f003, 0x80003000, &NMD::SAVE_32_         , 0,
19153        0x0                 },        /* SAVE[32] */
19154     { reserved_block      , 0                   , 0   , 32,
19155        0xfc10f003, 0x80003001, 0                      , 0,
19156        0x0                 },        /* PP.SR~*(1) */
19157     { instruction         , 0                   , 0   , 32,
19158        0xfc10f003, 0x80003002, &NMD::RESTORE_32_      , 0,
19159        0x0                 },        /* RESTORE[32] */
19160     { return_instruction  , 0                   , 0   , 32,
19161        0xfc10f003, 0x80003003, &NMD::RESTORE_JRC_32_  , 0,
19162        0x0                 },        /* RESTORE.JRC[32] */
19163 };
19164
19165
19166 NMD::Pool NMD::P_SR_F[8] = {
19167     { instruction         , 0                   , 0   , 32,
19168        0xfc10f007, 0x80103000, &NMD::SAVEF            , 0,
19169        CP1_                },        /* SAVEF */
19170     { instruction         , 0                   , 0   , 32,
19171        0xfc10f007, 0x80103001, &NMD::RESTOREF         , 0,
19172        CP1_                },        /* RESTOREF */
19173     { reserved_block      , 0                   , 0   , 32,
19174        0xfc10f007, 0x80103002, 0                      , 0,
19175        0x0                 },        /* P.SR.F~*(2) */
19176     { reserved_block      , 0                   , 0   , 32,
19177        0xfc10f007, 0x80103003, 0                      , 0,
19178        0x0                 },        /* P.SR.F~*(3) */
19179     { reserved_block      , 0                   , 0   , 32,
19180        0xfc10f007, 0x80103004, 0                      , 0,
19181        0x0                 },        /* P.SR.F~*(4) */
19182     { reserved_block      , 0                   , 0   , 32,
19183        0xfc10f007, 0x80103005, 0                      , 0,
19184        0x0                 },        /* P.SR.F~*(5) */
19185     { reserved_block      , 0                   , 0   , 32,
19186        0xfc10f007, 0x80103006, 0                      , 0,
19187        0x0                 },        /* P.SR.F~*(6) */
19188     { reserved_block      , 0                   , 0   , 32,
19189        0xfc10f007, 0x80103007, 0                      , 0,
19190        0x0                 },        /* P.SR.F~*(7) */
19191 };
19192
19193
19194 NMD::Pool NMD::P_SR[2] = {
19195     { pool                , PP_SR               , 4   , 32,
19196        0xfc10f000, 0x80003000, 0                      , 0,
19197        0x0                 },        /* PP.SR */
19198     { pool                , P_SR_F              , 8   , 32,
19199        0xfc10f000, 0x80103000, 0                      , 0,
19200        0x0                 },        /* P.SR.F */
19201 };
19202
19203
19204 NMD::Pool NMD::P_SLL[5] = {
19205     { instruction         , 0                   , 0   , 32,
19206        0xffe0f1ff, 0x8000c000, &NMD::NOP_32_          , 0,
19207        0x0                 },        /* NOP[32] */
19208     { instruction         , 0                   , 0   , 32,
19209        0xffe0f1ff, 0x8000c003, &NMD::EHB              , 0,
19210        0x0                 },        /* EHB */
19211     { instruction         , 0                   , 0   , 32,
19212        0xffe0f1ff, 0x8000c005, &NMD::PAUSE            , 0,
19213        0x0                 },        /* PAUSE */
19214     { instruction         , 0                   , 0   , 32,
19215        0xffe0f1ff, 0x8000c006, &NMD::SYNC             , 0,
19216        0x0                 },        /* SYNC */
19217     { instruction         , 0                   , 0   , 32,
19218        0xfc00f1e0, 0x8000c000, &NMD::SLL_32_          , 0,
19219        0x0                 },        /* SLL[32] */
19220 };
19221
19222
19223 NMD::Pool NMD::P_SHIFT[16] = {
19224     { pool                , P_SLL               , 5   , 32,
19225        0xfc00f1e0, 0x8000c000, 0                      , 0,
19226        0x0                 },        /* P.SLL */
19227     { reserved_block      , 0                   , 0   , 32,
19228        0xfc00f1e0, 0x8000c020, 0                      , 0,
19229        0x0                 },        /* P.SHIFT~*(1) */
19230     { instruction         , 0                   , 0   , 32,
19231        0xfc00f1e0, 0x8000c040, &NMD::SRL_32_          , 0,
19232        0x0                 },        /* SRL[32] */
19233     { reserved_block      , 0                   , 0   , 32,
19234        0xfc00f1e0, 0x8000c060, 0                      , 0,
19235        0x0                 },        /* P.SHIFT~*(3) */
19236     { instruction         , 0                   , 0   , 32,
19237        0xfc00f1e0, 0x8000c080, &NMD::SRA              , 0,
19238        0x0                 },        /* SRA */
19239     { reserved_block      , 0                   , 0   , 32,
19240        0xfc00f1e0, 0x8000c0a0, 0                      , 0,
19241        0x0                 },        /* P.SHIFT~*(5) */
19242     { instruction         , 0                   , 0   , 32,
19243        0xfc00f1e0, 0x8000c0c0, &NMD::ROTR             , 0,
19244        0x0                 },        /* ROTR */
19245     { reserved_block      , 0                   , 0   , 32,
19246        0xfc00f1e0, 0x8000c0e0, 0                      , 0,
19247        0x0                 },        /* P.SHIFT~*(7) */
19248     { instruction         , 0                   , 0   , 32,
19249        0xfc00f1e0, 0x8000c100, &NMD::DSLL             , 0,
19250        MIPS64_             },        /* DSLL */
19251     { instruction         , 0                   , 0   , 32,
19252        0xfc00f1e0, 0x8000c120, &NMD::DSLL32           , 0,
19253        MIPS64_             },        /* DSLL32 */
19254     { instruction         , 0                   , 0   , 32,
19255        0xfc00f1e0, 0x8000c140, &NMD::DSRL             , 0,
19256        MIPS64_             },        /* DSRL */
19257     { instruction         , 0                   , 0   , 32,
19258        0xfc00f1e0, 0x8000c160, &NMD::DSRL32           , 0,
19259        MIPS64_             },        /* DSRL32 */
19260     { instruction         , 0                   , 0   , 32,
19261        0xfc00f1e0, 0x8000c180, &NMD::DSRA             , 0,
19262        MIPS64_             },        /* DSRA */
19263     { instruction         , 0                   , 0   , 32,
19264        0xfc00f1e0, 0x8000c1a0, &NMD::DSRA32           , 0,
19265        MIPS64_             },        /* DSRA32 */
19266     { instruction         , 0                   , 0   , 32,
19267        0xfc00f1e0, 0x8000c1c0, &NMD::DROTR            , 0,
19268        MIPS64_             },        /* DROTR */
19269     { instruction         , 0                   , 0   , 32,
19270        0xfc00f1e0, 0x8000c1e0, &NMD::DROTR32          , 0,
19271        MIPS64_             },        /* DROTR32 */
19272 };
19273
19274
19275 NMD::Pool NMD::P_ROTX[4] = {
19276     { instruction         , 0                   , 0   , 32,
19277        0xfc00f820, 0x8000d000, &NMD::ROTX             , 0,
19278        XMMS_               },        /* ROTX */
19279     { reserved_block      , 0                   , 0   , 32,
19280        0xfc00f820, 0x8000d020, 0                      , 0,
19281        0x0                 },        /* P.ROTX~*(1) */
19282     { reserved_block      , 0                   , 0   , 32,
19283        0xfc00f820, 0x8000d800, 0                      , 0,
19284        0x0                 },        /* P.ROTX~*(2) */
19285     { reserved_block      , 0                   , 0   , 32,
19286        0xfc00f820, 0x8000d820, 0                      , 0,
19287        0x0                 },        /* P.ROTX~*(3) */
19288 };
19289
19290
19291 NMD::Pool NMD::P_INS[4] = {
19292     { instruction         , 0                   , 0   , 32,
19293        0xfc00f820, 0x8000e000, &NMD::INS              , 0,
19294        XMMS_               },        /* INS */
19295     { instruction         , 0                   , 0   , 32,
19296        0xfc00f820, 0x8000e020, &NMD::DINSU            , 0,
19297        MIPS64_             },        /* DINSU */
19298     { instruction         , 0                   , 0   , 32,
19299        0xfc00f820, 0x8000e800, &NMD::DINSM            , 0,
19300        MIPS64_             },        /* DINSM */
19301     { instruction         , 0                   , 0   , 32,
19302        0xfc00f820, 0x8000e820, &NMD::DINS             , 0,
19303        MIPS64_             },        /* DINS */
19304 };
19305
19306
19307 NMD::Pool NMD::P_EXT[4] = {
19308     { instruction         , 0                   , 0   , 32,
19309        0xfc00f820, 0x8000f000, &NMD::EXT              , 0,
19310        XMMS_               },        /* EXT */
19311     { instruction         , 0                   , 0   , 32,
19312        0xfc00f820, 0x8000f020, &NMD::DEXTU            , 0,
19313        MIPS64_             },        /* DEXTU */
19314     { instruction         , 0                   , 0   , 32,
19315        0xfc00f820, 0x8000f800, &NMD::DEXTM            , 0,
19316        MIPS64_             },        /* DEXTM */
19317     { instruction         , 0                   , 0   , 32,
19318        0xfc00f820, 0x8000f820, &NMD::DEXT             , 0,
19319        MIPS64_             },        /* DEXT */
19320 };
19321
19322
19323 NMD::Pool NMD::P_U12[16] = {
19324     { instruction         , 0                   , 0   , 32,
19325        0xfc00f000, 0x80000000, &NMD::ORI              , 0,
19326        0x0                 },        /* ORI */
19327     { instruction         , 0                   , 0   , 32,
19328        0xfc00f000, 0x80001000, &NMD::XORI             , 0,
19329        0x0                 },        /* XORI */
19330     { instruction         , 0                   , 0   , 32,
19331        0xfc00f000, 0x80002000, &NMD::ANDI_32_         , 0,
19332        0x0                 },        /* ANDI[32] */
19333     { pool                , P_SR                , 2   , 32,
19334        0xfc00f000, 0x80003000, 0                      , 0,
19335        0x0                 },        /* P.SR */
19336     { instruction         , 0                   , 0   , 32,
19337        0xfc00f000, 0x80004000, &NMD::SLTI             , 0,
19338        0x0                 },        /* SLTI */
19339     { instruction         , 0                   , 0   , 32,
19340        0xfc00f000, 0x80005000, &NMD::SLTIU            , 0,
19341        0x0                 },        /* SLTIU */
19342     { instruction         , 0                   , 0   , 32,
19343        0xfc00f000, 0x80006000, &NMD::SEQI             , 0,
19344        0x0                 },        /* SEQI */
19345     { reserved_block      , 0                   , 0   , 32,
19346        0xfc00f000, 0x80007000, 0                      , 0,
19347        0x0                 },        /* P.U12~*(7) */
19348     { instruction         , 0                   , 0   , 32,
19349        0xfc00f000, 0x80008000, &NMD::ADDIU_NEG_       , 0,
19350        0x0                 },        /* ADDIU[NEG] */
19351     { instruction         , 0                   , 0   , 32,
19352        0xfc00f000, 0x80009000, &NMD::DADDIU_U12_      , 0,
19353        MIPS64_             },        /* DADDIU[U12] */
19354     { instruction         , 0                   , 0   , 32,
19355        0xfc00f000, 0x8000a000, &NMD::DADDIU_NEG_      , 0,
19356        MIPS64_             },        /* DADDIU[NEG] */
19357     { instruction         , 0                   , 0   , 32,
19358        0xfc00f000, 0x8000b000, &NMD::DROTX            , 0,
19359        MIPS64_             },        /* DROTX */
19360     { pool                , P_SHIFT             , 16  , 32,
19361        0xfc00f000, 0x8000c000, 0                      , 0,
19362        0x0                 },        /* P.SHIFT */
19363     { pool                , P_ROTX              , 4   , 32,
19364        0xfc00f000, 0x8000d000, 0                      , 0,
19365        0x0                 },        /* P.ROTX */
19366     { pool                , P_INS               , 4   , 32,
19367        0xfc00f000, 0x8000e000, 0                      , 0,
19368        0x0                 },        /* P.INS */
19369     { pool                , P_EXT               , 4   , 32,
19370        0xfc00f000, 0x8000f000, 0                      , 0,
19371        0x0                 },        /* P.EXT */
19372 };
19373
19374
19375 NMD::Pool NMD::RINT_fmt[2] = {
19376     { instruction         , 0                   , 0   , 32,
19377        0xfc0003ff, 0xa0000020, &NMD::RINT_S           , 0,
19378        CP1_                },        /* RINT.S */
19379     { instruction         , 0                   , 0   , 32,
19380        0xfc0003ff, 0xa0000220, &NMD::RINT_D           , 0,
19381        CP1_                },        /* RINT.D */
19382 };
19383
19384
19385 NMD::Pool NMD::ADD_fmt0[2] = {
19386     { instruction         , 0                   , 0   , 32,
19387        0xfc0003ff, 0xa0000030, &NMD::ADD_S            , 0,
19388        CP1_                },        /* ADD.S */
19389     { reserved_block      , 0                   , 0   , 32,
19390        0xfc0003ff, 0xa0000230, 0                      , 0,
19391        CP1_                },        /* ADD.fmt0~*(1) */
19392 };
19393
19394
19395 NMD::Pool NMD::SELEQZ_fmt[2] = {
19396     { instruction         , 0                   , 0   , 32,
19397        0xfc0003ff, 0xa0000038, &NMD::SELEQZ_S         , 0,
19398        CP1_                },        /* SELEQZ.S */
19399     { instruction         , 0                   , 0   , 32,
19400        0xfc0003ff, 0xa0000238, &NMD::SELEQZ_D         , 0,
19401        CP1_                },        /* SELEQZ.D */
19402 };
19403
19404
19405 NMD::Pool NMD::CLASS_fmt[2] = {
19406     { instruction         , 0                   , 0   , 32,
19407        0xfc0003ff, 0xa0000060, &NMD::CLASS_S          , 0,
19408        CP1_                },        /* CLASS.S */
19409     { instruction         , 0                   , 0   , 32,
19410        0xfc0003ff, 0xa0000260, &NMD::CLASS_D          , 0,
19411        CP1_                },        /* CLASS.D */
19412 };
19413
19414
19415 NMD::Pool NMD::SUB_fmt0[2] = {
19416     { instruction         , 0                   , 0   , 32,
19417        0xfc0003ff, 0xa0000070, &NMD::SUB_S            , 0,
19418        CP1_                },        /* SUB.S */
19419     { reserved_block      , 0                   , 0   , 32,
19420        0xfc0003ff, 0xa0000270, 0                      , 0,
19421        CP1_                },        /* SUB.fmt0~*(1) */
19422 };
19423
19424
19425 NMD::Pool NMD::SELNEZ_fmt[2] = {
19426     { instruction         , 0                   , 0   , 32,
19427        0xfc0003ff, 0xa0000078, &NMD::SELNEZ_S         , 0,
19428        CP1_                },        /* SELNEZ.S */
19429     { instruction         , 0                   , 0   , 32,
19430        0xfc0003ff, 0xa0000278, &NMD::SELNEZ_D         , 0,
19431        CP1_                },        /* SELNEZ.D */
19432 };
19433
19434
19435 NMD::Pool NMD::MUL_fmt0[2] = {
19436     { instruction         , 0                   , 0   , 32,
19437        0xfc0003ff, 0xa00000b0, &NMD::MUL_S            , 0,
19438        CP1_                },        /* MUL.S */
19439     { reserved_block      , 0                   , 0   , 32,
19440        0xfc0003ff, 0xa00002b0, 0                      , 0,
19441        CP1_                },        /* MUL.fmt0~*(1) */
19442 };
19443
19444
19445 NMD::Pool NMD::SEL_fmt[2] = {
19446     { instruction         , 0                   , 0   , 32,
19447        0xfc0003ff, 0xa00000b8, &NMD::SEL_S            , 0,
19448        CP1_                },        /* SEL.S */
19449     { instruction         , 0                   , 0   , 32,
19450        0xfc0003ff, 0xa00002b8, &NMD::SEL_D            , 0,
19451        CP1_                },        /* SEL.D */
19452 };
19453
19454
19455 NMD::Pool NMD::DIV_fmt0[2] = {
19456     { instruction         , 0                   , 0   , 32,
19457        0xfc0003ff, 0xa00000f0, &NMD::DIV_S            , 0,
19458        CP1_                },        /* DIV.S */
19459     { reserved_block      , 0                   , 0   , 32,
19460        0xfc0003ff, 0xa00002f0, 0                      , 0,
19461        CP1_                },        /* DIV.fmt0~*(1) */
19462 };
19463
19464
19465 NMD::Pool NMD::ADD_fmt1[2] = {
19466     { instruction         , 0                   , 0   , 32,
19467        0xfc0003ff, 0xa0000130, &NMD::ADD_D            , 0,
19468        CP1_                },        /* ADD.D */
19469     { reserved_block      , 0                   , 0   , 32,
19470        0xfc0003ff, 0xa0000330, 0                      , 0,
19471        CP1_                },        /* ADD.fmt1~*(1) */
19472 };
19473
19474
19475 NMD::Pool NMD::SUB_fmt1[2] = {
19476     { instruction         , 0                   , 0   , 32,
19477        0xfc0003ff, 0xa0000170, &NMD::SUB_D            , 0,
19478        CP1_                },        /* SUB.D */
19479     { reserved_block      , 0                   , 0   , 32,
19480        0xfc0003ff, 0xa0000370, 0                      , 0,
19481        CP1_                },        /* SUB.fmt1~*(1) */
19482 };
19483
19484
19485 NMD::Pool NMD::MUL_fmt1[2] = {
19486     { instruction         , 0                   , 0   , 32,
19487        0xfc0003ff, 0xa00001b0, &NMD::MUL_D            , 0,
19488        CP1_                },        /* MUL.D */
19489     { reserved_block      , 0                   , 0   , 32,
19490        0xfc0003ff, 0xa00003b0, 0                      , 0,
19491        CP1_                },        /* MUL.fmt1~*(1) */
19492 };
19493
19494
19495 NMD::Pool NMD::MADDF_fmt[2] = {
19496     { instruction         , 0                   , 0   , 32,
19497        0xfc0003ff, 0xa00001b8, &NMD::MADDF_S          , 0,
19498        CP1_                },        /* MADDF.S */
19499     { instruction         , 0                   , 0   , 32,
19500        0xfc0003ff, 0xa00003b8, &NMD::MADDF_D          , 0,
19501        CP1_                },        /* MADDF.D */
19502 };
19503
19504
19505 NMD::Pool NMD::DIV_fmt1[2] = {
19506     { instruction         , 0                   , 0   , 32,
19507        0xfc0003ff, 0xa00001f0, &NMD::DIV_D            , 0,
19508        CP1_                },        /* DIV.D */
19509     { reserved_block      , 0                   , 0   , 32,
19510        0xfc0003ff, 0xa00003f0, 0                      , 0,
19511        CP1_                },        /* DIV.fmt1~*(1) */
19512 };
19513
19514
19515 NMD::Pool NMD::MSUBF_fmt[2] = {
19516     { instruction         , 0                   , 0   , 32,
19517        0xfc0003ff, 0xa00001f8, &NMD::MSUBF_S          , 0,
19518        CP1_                },        /* MSUBF.S */
19519     { instruction         , 0                   , 0   , 32,
19520        0xfc0003ff, 0xa00003f8, &NMD::MSUBF_D          , 0,
19521        CP1_                },        /* MSUBF.D */
19522 };
19523
19524
19525 NMD::Pool NMD::POOL32F_0[64] = {
19526     { reserved_block      , 0                   , 0   , 32,
19527        0xfc0001ff, 0xa0000000, 0                      , 0,
19528        CP1_                },        /* POOL32F_0~*(0) */
19529     { reserved_block      , 0                   , 0   , 32,
19530        0xfc0001ff, 0xa0000008, 0                      , 0,
19531        CP1_                },        /* POOL32F_0~*(1) */
19532     { reserved_block      , 0                   , 0   , 32,
19533        0xfc0001ff, 0xa0000010, 0                      , 0,
19534        CP1_                },        /* POOL32F_0~*(2) */
19535     { reserved_block      , 0                   , 0   , 32,
19536        0xfc0001ff, 0xa0000018, 0                      , 0,
19537        CP1_                },        /* POOL32F_0~*(3) */
19538     { pool                , RINT_fmt            , 2   , 32,
19539        0xfc0001ff, 0xa0000020, 0                      , 0,
19540        CP1_                },        /* RINT.fmt */
19541     { reserved_block      , 0                   , 0   , 32,
19542        0xfc0001ff, 0xa0000028, 0                      , 0,
19543        CP1_                },        /* POOL32F_0~*(5) */
19544     { pool                , ADD_fmt0            , 2   , 32,
19545        0xfc0001ff, 0xa0000030, 0                      , 0,
19546        CP1_                },        /* ADD.fmt0 */
19547     { pool                , SELEQZ_fmt          , 2   , 32,
19548        0xfc0001ff, 0xa0000038, 0                      , 0,
19549        CP1_                },        /* SELEQZ.fmt */
19550     { reserved_block      , 0                   , 0   , 32,
19551        0xfc0001ff, 0xa0000040, 0                      , 0,
19552        CP1_                },        /* POOL32F_0~*(8) */
19553     { reserved_block      , 0                   , 0   , 32,
19554        0xfc0001ff, 0xa0000048, 0                      , 0,
19555        CP1_                },        /* POOL32F_0~*(9) */
19556     { reserved_block      , 0                   , 0   , 32,
19557        0xfc0001ff, 0xa0000050, 0                      , 0,
19558        CP1_                },        /* POOL32F_0~*(10) */
19559     { reserved_block      , 0                   , 0   , 32,
19560        0xfc0001ff, 0xa0000058, 0                      , 0,
19561        CP1_                },        /* POOL32F_0~*(11) */
19562     { pool                , CLASS_fmt           , 2   , 32,
19563        0xfc0001ff, 0xa0000060, 0                      , 0,
19564        CP1_                },        /* CLASS.fmt */
19565     { reserved_block      , 0                   , 0   , 32,
19566        0xfc0001ff, 0xa0000068, 0                      , 0,
19567        CP1_                },        /* POOL32F_0~*(13) */
19568     { pool                , SUB_fmt0            , 2   , 32,
19569        0xfc0001ff, 0xa0000070, 0                      , 0,
19570        CP1_                },        /* SUB.fmt0 */
19571     { pool                , SELNEZ_fmt          , 2   , 32,
19572        0xfc0001ff, 0xa0000078, 0                      , 0,
19573        CP1_                },        /* SELNEZ.fmt */
19574     { reserved_block      , 0                   , 0   , 32,
19575        0xfc0001ff, 0xa0000080, 0                      , 0,
19576        CP1_                },        /* POOL32F_0~*(16) */
19577     { reserved_block      , 0                   , 0   , 32,
19578        0xfc0001ff, 0xa0000088, 0                      , 0,
19579        CP1_                },        /* POOL32F_0~*(17) */
19580     { reserved_block      , 0                   , 0   , 32,
19581        0xfc0001ff, 0xa0000090, 0                      , 0,
19582        CP1_                },        /* POOL32F_0~*(18) */
19583     { reserved_block      , 0                   , 0   , 32,
19584        0xfc0001ff, 0xa0000098, 0                      , 0,
19585        CP1_                },        /* POOL32F_0~*(19) */
19586     { reserved_block      , 0                   , 0   , 32,
19587        0xfc0001ff, 0xa00000a0, 0                      , 0,
19588        CP1_                },        /* POOL32F_0~*(20) */
19589     { reserved_block      , 0                   , 0   , 32,
19590        0xfc0001ff, 0xa00000a8, 0                      , 0,
19591        CP1_                },        /* POOL32F_0~*(21) */
19592     { pool                , MUL_fmt0            , 2   , 32,
19593        0xfc0001ff, 0xa00000b0, 0                      , 0,
19594        CP1_                },        /* MUL.fmt0 */
19595     { pool                , SEL_fmt             , 2   , 32,
19596        0xfc0001ff, 0xa00000b8, 0                      , 0,
19597        CP1_                },        /* SEL.fmt */
19598     { reserved_block      , 0                   , 0   , 32,
19599        0xfc0001ff, 0xa00000c0, 0                      , 0,
19600        CP1_                },        /* POOL32F_0~*(24) */
19601     { reserved_block      , 0                   , 0   , 32,
19602        0xfc0001ff, 0xa00000c8, 0                      , 0,
19603        CP1_                },        /* POOL32F_0~*(25) */
19604     { reserved_block      , 0                   , 0   , 32,
19605        0xfc0001ff, 0xa00000d0, 0                      , 0,
19606        CP1_                },        /* POOL32F_0~*(26) */
19607     { reserved_block      , 0                   , 0   , 32,
19608        0xfc0001ff, 0xa00000d8, 0                      , 0,
19609        CP1_                },        /* POOL32F_0~*(27) */
19610     { reserved_block      , 0                   , 0   , 32,
19611        0xfc0001ff, 0xa00000e0, 0                      , 0,
19612        CP1_                },        /* POOL32F_0~*(28) */
19613     { reserved_block      , 0                   , 0   , 32,
19614        0xfc0001ff, 0xa00000e8, 0                      , 0,
19615        CP1_                },        /* POOL32F_0~*(29) */
19616     { pool                , DIV_fmt0            , 2   , 32,
19617        0xfc0001ff, 0xa00000f0, 0                      , 0,
19618        CP1_                },        /* DIV.fmt0 */
19619     { reserved_block      , 0                   , 0   , 32,
19620        0xfc0001ff, 0xa00000f8, 0                      , 0,
19621        CP1_                },        /* POOL32F_0~*(31) */
19622     { reserved_block      , 0                   , 0   , 32,
19623        0xfc0001ff, 0xa0000100, 0                      , 0,
19624        CP1_                },        /* POOL32F_0~*(32) */
19625     { reserved_block      , 0                   , 0   , 32,
19626        0xfc0001ff, 0xa0000108, 0                      , 0,
19627        CP1_                },        /* POOL32F_0~*(33) */
19628     { reserved_block      , 0                   , 0   , 32,
19629        0xfc0001ff, 0xa0000110, 0                      , 0,
19630        CP1_                },        /* POOL32F_0~*(34) */
19631     { reserved_block      , 0                   , 0   , 32,
19632        0xfc0001ff, 0xa0000118, 0                      , 0,
19633        CP1_                },        /* POOL32F_0~*(35) */
19634     { reserved_block      , 0                   , 0   , 32,
19635        0xfc0001ff, 0xa0000120, 0                      , 0,
19636        CP1_                },        /* POOL32F_0~*(36) */
19637     { reserved_block      , 0                   , 0   , 32,
19638        0xfc0001ff, 0xa0000128, 0                      , 0,
19639        CP1_                },        /* POOL32F_0~*(37) */
19640     { pool                , ADD_fmt1            , 2   , 32,
19641        0xfc0001ff, 0xa0000130, 0                      , 0,
19642        CP1_                },        /* ADD.fmt1 */
19643     { reserved_block      , 0                   , 0   , 32,
19644        0xfc0001ff, 0xa0000138, 0                      , 0,
19645        CP1_                },        /* POOL32F_0~*(39) */
19646     { reserved_block      , 0                   , 0   , 32,
19647        0xfc0001ff, 0xa0000140, 0                      , 0,
19648        CP1_                },        /* POOL32F_0~*(40) */
19649     { reserved_block      , 0                   , 0   , 32,
19650        0xfc0001ff, 0xa0000148, 0                      , 0,
19651        CP1_                },        /* POOL32F_0~*(41) */
19652     { reserved_block      , 0                   , 0   , 32,
19653        0xfc0001ff, 0xa0000150, 0                      , 0,
19654        CP1_                },        /* POOL32F_0~*(42) */
19655     { reserved_block      , 0                   , 0   , 32,
19656        0xfc0001ff, 0xa0000158, 0                      , 0,
19657        CP1_                },        /* POOL32F_0~*(43) */
19658     { reserved_block      , 0                   , 0   , 32,
19659        0xfc0001ff, 0xa0000160, 0                      , 0,
19660        CP1_                },        /* POOL32F_0~*(44) */
19661     { reserved_block      , 0                   , 0   , 32,
19662        0xfc0001ff, 0xa0000168, 0                      , 0,
19663        CP1_                },        /* POOL32F_0~*(45) */
19664     { pool                , SUB_fmt1            , 2   , 32,
19665        0xfc0001ff, 0xa0000170, 0                      , 0,
19666        CP1_                },        /* SUB.fmt1 */
19667     { reserved_block      , 0                   , 0   , 32,
19668        0xfc0001ff, 0xa0000178, 0                      , 0,
19669        CP1_                },        /* POOL32F_0~*(47) */
19670     { reserved_block      , 0                   , 0   , 32,
19671        0xfc0001ff, 0xa0000180, 0                      , 0,
19672        CP1_                },        /* POOL32F_0~*(48) */
19673     { reserved_block      , 0                   , 0   , 32,
19674        0xfc0001ff, 0xa0000188, 0                      , 0,
19675        CP1_                },        /* POOL32F_0~*(49) */
19676     { reserved_block      , 0                   , 0   , 32,
19677        0xfc0001ff, 0xa0000190, 0                      , 0,
19678        CP1_                },        /* POOL32F_0~*(50) */
19679     { reserved_block      , 0                   , 0   , 32,
19680        0xfc0001ff, 0xa0000198, 0                      , 0,
19681        CP1_                },        /* POOL32F_0~*(51) */
19682     { reserved_block      , 0                   , 0   , 32,
19683        0xfc0001ff, 0xa00001a0, 0                      , 0,
19684        CP1_                },        /* POOL32F_0~*(52) */
19685     { reserved_block      , 0                   , 0   , 32,
19686        0xfc0001ff, 0xa00001a8, 0                      , 0,
19687        CP1_                },        /* POOL32F_0~*(53) */
19688     { pool                , MUL_fmt1            , 2   , 32,
19689        0xfc0001ff, 0xa00001b0, 0                      , 0,
19690        CP1_                },        /* MUL.fmt1 */
19691     { pool                , MADDF_fmt           , 2   , 32,
19692        0xfc0001ff, 0xa00001b8, 0                      , 0,
19693        CP1_                },        /* MADDF.fmt */
19694     { reserved_block      , 0                   , 0   , 32,
19695        0xfc0001ff, 0xa00001c0, 0                      , 0,
19696        CP1_                },        /* POOL32F_0~*(56) */
19697     { reserved_block      , 0                   , 0   , 32,
19698        0xfc0001ff, 0xa00001c8, 0                      , 0,
19699        CP1_                },        /* POOL32F_0~*(57) */
19700     { reserved_block      , 0                   , 0   , 32,
19701        0xfc0001ff, 0xa00001d0, 0                      , 0,
19702        CP1_                },        /* POOL32F_0~*(58) */
19703     { reserved_block      , 0                   , 0   , 32,
19704        0xfc0001ff, 0xa00001d8, 0                      , 0,
19705        CP1_                },        /* POOL32F_0~*(59) */
19706     { reserved_block      , 0                   , 0   , 32,
19707        0xfc0001ff, 0xa00001e0, 0                      , 0,
19708        CP1_                },        /* POOL32F_0~*(60) */
19709     { reserved_block      , 0                   , 0   , 32,
19710        0xfc0001ff, 0xa00001e8, 0                      , 0,
19711        CP1_                },        /* POOL32F_0~*(61) */
19712     { pool                , DIV_fmt1            , 2   , 32,
19713        0xfc0001ff, 0xa00001f0, 0                      , 0,
19714        CP1_                },        /* DIV.fmt1 */
19715     { pool                , MSUBF_fmt           , 2   , 32,
19716        0xfc0001ff, 0xa00001f8, 0                      , 0,
19717        CP1_                },        /* MSUBF.fmt */
19718 };
19719
19720
19721 NMD::Pool NMD::MIN_fmt[2] = {
19722     { instruction         , 0                   , 0   , 32,
19723        0xfc00023f, 0xa0000003, &NMD::MIN_S            , 0,
19724        CP1_                },        /* MIN.S */
19725     { instruction         , 0                   , 0   , 32,
19726        0xfc00023f, 0xa0000203, &NMD::MIN_D            , 0,
19727        CP1_                },        /* MIN.D */
19728 };
19729
19730
19731 NMD::Pool NMD::MAX_fmt[2] = {
19732     { instruction         , 0                   , 0   , 32,
19733        0xfc00023f, 0xa000000b, &NMD::MAX_S            , 0,
19734        CP1_                },        /* MAX.S */
19735     { instruction         , 0                   , 0   , 32,
19736        0xfc00023f, 0xa000020b, &NMD::MAX_D            , 0,
19737        CP1_                },        /* MAX.D */
19738 };
19739
19740
19741 NMD::Pool NMD::MINA_fmt[2] = {
19742     { instruction         , 0                   , 0   , 32,
19743        0xfc00023f, 0xa0000023, &NMD::MINA_S           , 0,
19744        CP1_                },        /* MINA.S */
19745     { instruction         , 0                   , 0   , 32,
19746        0xfc00023f, 0xa0000223, &NMD::MINA_D           , 0,
19747        CP1_                },        /* MINA.D */
19748 };
19749
19750
19751 NMD::Pool NMD::MAXA_fmt[2] = {
19752     { instruction         , 0                   , 0   , 32,
19753        0xfc00023f, 0xa000002b, &NMD::MAXA_S           , 0,
19754        CP1_                },        /* MAXA.S */
19755     { instruction         , 0                   , 0   , 32,
19756        0xfc00023f, 0xa000022b, &NMD::MAXA_D           , 0,
19757        CP1_                },        /* MAXA.D */
19758 };
19759
19760
19761 NMD::Pool NMD::CVT_L_fmt[2] = {
19762     { instruction         , 0                   , 0   , 32,
19763        0xfc007fff, 0xa000013b, &NMD::CVT_L_S          , 0,
19764        CP1_                },        /* CVT.L.S */
19765     { instruction         , 0                   , 0   , 32,
19766        0xfc007fff, 0xa000413b, &NMD::CVT_L_D          , 0,
19767        CP1_                },        /* CVT.L.D */
19768 };
19769
19770
19771 NMD::Pool NMD::RSQRT_fmt[2] = {
19772     { instruction         , 0                   , 0   , 32,
19773        0xfc007fff, 0xa000023b, &NMD::RSQRT_S          , 0,
19774        CP1_                },        /* RSQRT.S */
19775     { instruction         , 0                   , 0   , 32,
19776        0xfc007fff, 0xa000423b, &NMD::RSQRT_D          , 0,
19777        CP1_                },        /* RSQRT.D */
19778 };
19779
19780
19781 NMD::Pool NMD::FLOOR_L_fmt[2] = {
19782     { instruction         , 0                   , 0   , 32,
19783        0xfc007fff, 0xa000033b, &NMD::FLOOR_L_S        , 0,
19784        CP1_                },        /* FLOOR.L.S */
19785     { instruction         , 0                   , 0   , 32,
19786        0xfc007fff, 0xa000433b, &NMD::FLOOR_L_D        , 0,
19787        CP1_                },        /* FLOOR.L.D */
19788 };
19789
19790
19791 NMD::Pool NMD::CVT_W_fmt[2] = {
19792     { instruction         , 0                   , 0   , 32,
19793        0xfc007fff, 0xa000093b, &NMD::CVT_W_S          , 0,
19794        CP1_                },        /* CVT.W.S */
19795     { instruction         , 0                   , 0   , 32,
19796        0xfc007fff, 0xa000493b, &NMD::CVT_W_D          , 0,
19797        CP1_                },        /* CVT.W.D */
19798 };
19799
19800
19801 NMD::Pool NMD::SQRT_fmt[2] = {
19802     { instruction         , 0                   , 0   , 32,
19803        0xfc007fff, 0xa0000a3b, &NMD::SQRT_S           , 0,
19804        CP1_                },        /* SQRT.S */
19805     { instruction         , 0                   , 0   , 32,
19806        0xfc007fff, 0xa0004a3b, &NMD::SQRT_D           , 0,
19807        CP1_                },        /* SQRT.D */
19808 };
19809
19810
19811 NMD::Pool NMD::FLOOR_W_fmt[2] = {
19812     { instruction         , 0                   , 0   , 32,
19813        0xfc007fff, 0xa0000b3b, &NMD::FLOOR_W_S        , 0,
19814        CP1_                },        /* FLOOR.W.S */
19815     { instruction         , 0                   , 0   , 32,
19816        0xfc007fff, 0xa0004b3b, &NMD::FLOOR_W_D        , 0,
19817        CP1_                },        /* FLOOR.W.D */
19818 };
19819
19820
19821 NMD::Pool NMD::RECIP_fmt[2] = {
19822     { instruction         , 0                   , 0   , 32,
19823        0xfc007fff, 0xa000123b, &NMD::RECIP_S          , 0,
19824        CP1_                },        /* RECIP.S */
19825     { instruction         , 0                   , 0   , 32,
19826        0xfc007fff, 0xa000523b, &NMD::RECIP_D          , 0,
19827        CP1_                },        /* RECIP.D */
19828 };
19829
19830
19831 NMD::Pool NMD::CEIL_L_fmt[2] = {
19832     { instruction         , 0                   , 0   , 32,
19833        0xfc007fff, 0xa000133b, &NMD::CEIL_L_S         , 0,
19834        CP1_                },        /* CEIL.L.S */
19835     { instruction         , 0                   , 0   , 32,
19836        0xfc007fff, 0xa000533b, &NMD::CEIL_L_D         , 0,
19837        CP1_                },        /* CEIL.L.D */
19838 };
19839
19840
19841 NMD::Pool NMD::CEIL_W_fmt[2] = {
19842     { instruction         , 0                   , 0   , 32,
19843        0xfc007fff, 0xa0001b3b, &NMD::CEIL_W_S         , 0,
19844        CP1_                },        /* CEIL.W.S */
19845     { instruction         , 0                   , 0   , 32,
19846        0xfc007fff, 0xa0005b3b, &NMD::CEIL_W_D         , 0,
19847        CP1_                },        /* CEIL.W.D */
19848 };
19849
19850
19851 NMD::Pool NMD::TRUNC_L_fmt[2] = {
19852     { instruction         , 0                   , 0   , 32,
19853        0xfc007fff, 0xa000233b, &NMD::TRUNC_L_S        , 0,
19854        CP1_                },        /* TRUNC.L.S */
19855     { instruction         , 0                   , 0   , 32,
19856        0xfc007fff, 0xa000633b, &NMD::TRUNC_L_D        , 0,
19857        CP1_                },        /* TRUNC.L.D */
19858 };
19859
19860
19861 NMD::Pool NMD::TRUNC_W_fmt[2] = {
19862     { instruction         , 0                   , 0   , 32,
19863        0xfc007fff, 0xa0002b3b, &NMD::TRUNC_W_S        , 0,
19864        CP1_                },        /* TRUNC.W.S */
19865     { instruction         , 0                   , 0   , 32,
19866        0xfc007fff, 0xa0006b3b, &NMD::TRUNC_W_D        , 0,
19867        CP1_                },        /* TRUNC.W.D */
19868 };
19869
19870
19871 NMD::Pool NMD::ROUND_L_fmt[2] = {
19872     { instruction         , 0                   , 0   , 32,
19873        0xfc007fff, 0xa000333b, &NMD::ROUND_L_S        , 0,
19874        CP1_                },        /* ROUND.L.S */
19875     { instruction         , 0                   , 0   , 32,
19876        0xfc007fff, 0xa000733b, &NMD::ROUND_L_D        , 0,
19877        CP1_                },        /* ROUND.L.D */
19878 };
19879
19880
19881 NMD::Pool NMD::ROUND_W_fmt[2] = {
19882     { instruction         , 0                   , 0   , 32,
19883        0xfc007fff, 0xa0003b3b, &NMD::ROUND_W_S        , 0,
19884        CP1_                },        /* ROUND.W.S */
19885     { instruction         , 0                   , 0   , 32,
19886        0xfc007fff, 0xa0007b3b, &NMD::ROUND_W_D        , 0,
19887        CP1_                },        /* ROUND.W.D */
19888 };
19889
19890
19891 NMD::Pool NMD::POOL32Fxf_0[64] = {
19892     { reserved_block      , 0                   , 0   , 32,
19893        0xfc003fff, 0xa000003b, 0                      , 0,
19894        CP1_                },        /* POOL32Fxf_0~*(0) */
19895     { pool                , CVT_L_fmt           , 2   , 32,
19896        0xfc003fff, 0xa000013b, 0                      , 0,
19897        CP1_                },        /* CVT.L.fmt */
19898     { pool                , RSQRT_fmt           , 2   , 32,
19899        0xfc003fff, 0xa000023b, 0                      , 0,
19900        CP1_                },        /* RSQRT.fmt */
19901     { pool                , FLOOR_L_fmt         , 2   , 32,
19902        0xfc003fff, 0xa000033b, 0                      , 0,
19903        CP1_                },        /* FLOOR.L.fmt */
19904     { reserved_block      , 0                   , 0   , 32,
19905        0xfc003fff, 0xa000043b, 0                      , 0,
19906        CP1_                },        /* POOL32Fxf_0~*(4) */
19907     { reserved_block      , 0                   , 0   , 32,
19908        0xfc003fff, 0xa000053b, 0                      , 0,
19909        CP1_                },        /* POOL32Fxf_0~*(5) */
19910     { reserved_block      , 0                   , 0   , 32,
19911        0xfc003fff, 0xa000063b, 0                      , 0,
19912        CP1_                },        /* POOL32Fxf_0~*(6) */
19913     { reserved_block      , 0                   , 0   , 32,
19914        0xfc003fff, 0xa000073b, 0                      , 0,
19915        CP1_                },        /* POOL32Fxf_0~*(7) */
19916     { reserved_block      , 0                   , 0   , 32,
19917        0xfc003fff, 0xa000083b, 0                      , 0,
19918        CP1_                },        /* POOL32Fxf_0~*(8) */
19919     { pool                , CVT_W_fmt           , 2   , 32,
19920        0xfc003fff, 0xa000093b, 0                      , 0,
19921        CP1_                },        /* CVT.W.fmt */
19922     { pool                , SQRT_fmt            , 2   , 32,
19923        0xfc003fff, 0xa0000a3b, 0                      , 0,
19924        CP1_                },        /* SQRT.fmt */
19925     { pool                , FLOOR_W_fmt         , 2   , 32,
19926        0xfc003fff, 0xa0000b3b, 0                      , 0,
19927        CP1_                },        /* FLOOR.W.fmt */
19928     { reserved_block      , 0                   , 0   , 32,
19929        0xfc003fff, 0xa0000c3b, 0                      , 0,
19930        CP1_                },        /* POOL32Fxf_0~*(12) */
19931     { reserved_block      , 0                   , 0   , 32,
19932        0xfc003fff, 0xa0000d3b, 0                      , 0,
19933        CP1_                },        /* POOL32Fxf_0~*(13) */
19934     { reserved_block      , 0                   , 0   , 32,
19935        0xfc003fff, 0xa0000e3b, 0                      , 0,
19936        CP1_                },        /* POOL32Fxf_0~*(14) */
19937     { reserved_block      , 0                   , 0   , 32,
19938        0xfc003fff, 0xa0000f3b, 0                      , 0,
19939        CP1_                },        /* POOL32Fxf_0~*(15) */
19940     { instruction         , 0                   , 0   , 32,
19941        0xfc003fff, 0xa000103b, &NMD::CFC1             , 0,
19942        CP1_                },        /* CFC1 */
19943     { reserved_block      , 0                   , 0   , 32,
19944        0xfc003fff, 0xa000113b, 0                      , 0,
19945        CP1_                },        /* POOL32Fxf_0~*(17) */
19946     { pool                , RECIP_fmt           , 2   , 32,
19947        0xfc003fff, 0xa000123b, 0                      , 0,
19948        CP1_                },        /* RECIP.fmt */
19949     { pool                , CEIL_L_fmt          , 2   , 32,
19950        0xfc003fff, 0xa000133b, 0                      , 0,
19951        CP1_                },        /* CEIL.L.fmt */
19952     { reserved_block      , 0                   , 0   , 32,
19953        0xfc003fff, 0xa000143b, 0                      , 0,
19954        CP1_                },        /* POOL32Fxf_0~*(20) */
19955     { reserved_block      , 0                   , 0   , 32,
19956        0xfc003fff, 0xa000153b, 0                      , 0,
19957        CP1_                },        /* POOL32Fxf_0~*(21) */
19958     { reserved_block      , 0                   , 0   , 32,
19959        0xfc003fff, 0xa000163b, 0                      , 0,
19960        CP1_                },        /* POOL32Fxf_0~*(22) */
19961     { reserved_block      , 0                   , 0   , 32,
19962        0xfc003fff, 0xa000173b, 0                      , 0,
19963        CP1_                },        /* POOL32Fxf_0~*(23) */
19964     { instruction         , 0                   , 0   , 32,
19965        0xfc003fff, 0xa000183b, &NMD::CTC1             , 0,
19966        CP1_                },        /* CTC1 */
19967     { reserved_block      , 0                   , 0   , 32,
19968        0xfc003fff, 0xa000193b, 0                      , 0,
19969        CP1_                },        /* POOL32Fxf_0~*(25) */
19970     { reserved_block      , 0                   , 0   , 32,
19971        0xfc003fff, 0xa0001a3b, 0                      , 0,
19972        CP1_                },        /* POOL32Fxf_0~*(26) */
19973     { pool                , CEIL_W_fmt          , 2   , 32,
19974        0xfc003fff, 0xa0001b3b, 0                      , 0,
19975        CP1_                },        /* CEIL.W.fmt */
19976     { reserved_block      , 0                   , 0   , 32,
19977        0xfc003fff, 0xa0001c3b, 0                      , 0,
19978        CP1_                },        /* POOL32Fxf_0~*(28) */
19979     { reserved_block      , 0                   , 0   , 32,
19980        0xfc003fff, 0xa0001d3b, 0                      , 0,
19981        CP1_                },        /* POOL32Fxf_0~*(29) */
19982     { reserved_block      , 0                   , 0   , 32,
19983        0xfc003fff, 0xa0001e3b, 0                      , 0,
19984        CP1_                },        /* POOL32Fxf_0~*(30) */
19985     { reserved_block      , 0                   , 0   , 32,
19986        0xfc003fff, 0xa0001f3b, 0                      , 0,
19987        CP1_                },        /* POOL32Fxf_0~*(31) */
19988     { instruction         , 0                   , 0   , 32,
19989        0xfc003fff, 0xa000203b, &NMD::MFC1             , 0,
19990        CP1_                },        /* MFC1 */
19991     { instruction         , 0                   , 0   , 32,
19992        0xfc003fff, 0xa000213b, &NMD::CVT_S_PL         , 0,
19993        CP1_                },        /* CVT.S.PL */
19994     { reserved_block      , 0                   , 0   , 32,
19995        0xfc003fff, 0xa000223b, 0                      , 0,
19996        CP1_                },        /* POOL32Fxf_0~*(34) */
19997     { pool                , TRUNC_L_fmt         , 2   , 32,
19998        0xfc003fff, 0xa000233b, 0                      , 0,
19999        CP1_                },        /* TRUNC.L.fmt */
20000     { instruction         , 0                   , 0   , 32,
20001        0xfc003fff, 0xa000243b, &NMD::DMFC1            , 0,
20002        CP1_ | MIPS64_      },        /* DMFC1 */
20003     { reserved_block      , 0                   , 0   , 32,
20004        0xfc003fff, 0xa000253b, 0                      , 0,
20005        CP1_                },        /* POOL32Fxf_0~*(37) */
20006     { reserved_block      , 0                   , 0   , 32,
20007        0xfc003fff, 0xa000263b, 0                      , 0,
20008        CP1_                },        /* POOL32Fxf_0~*(38) */
20009     { reserved_block      , 0                   , 0   , 32,
20010        0xfc003fff, 0xa000273b, 0                      , 0,
20011        CP1_                },        /* POOL32Fxf_0~*(39) */
20012     { instruction         , 0                   , 0   , 32,
20013        0xfc003fff, 0xa000283b, &NMD::MTC1             , 0,
20014        CP1_                },        /* MTC1 */
20015     { instruction         , 0                   , 0   , 32,
20016        0xfc003fff, 0xa000293b, &NMD::CVT_S_PU         , 0,
20017        CP1_                },        /* CVT.S.PU */
20018     { reserved_block      , 0                   , 0   , 32,
20019        0xfc003fff, 0xa0002a3b, 0                      , 0,
20020        CP1_                },        /* POOL32Fxf_0~*(42) */
20021     { pool                , TRUNC_W_fmt         , 2   , 32,
20022        0xfc003fff, 0xa0002b3b, 0                      , 0,
20023        CP1_                },        /* TRUNC.W.fmt */
20024     { instruction         , 0                   , 0   , 32,
20025        0xfc003fff, 0xa0002c3b, &NMD::DMTC1            , 0,
20026        CP1_ | MIPS64_      },        /* DMTC1 */
20027     { reserved_block      , 0                   , 0   , 32,
20028        0xfc003fff, 0xa0002d3b, 0                      , 0,
20029        CP1_                },        /* POOL32Fxf_0~*(45) */
20030     { reserved_block      , 0                   , 0   , 32,
20031        0xfc003fff, 0xa0002e3b, 0                      , 0,
20032        CP1_                },        /* POOL32Fxf_0~*(46) */
20033     { reserved_block      , 0                   , 0   , 32,
20034        0xfc003fff, 0xa0002f3b, 0                      , 0,
20035        CP1_                },        /* POOL32Fxf_0~*(47) */
20036     { instruction         , 0                   , 0   , 32,
20037        0xfc003fff, 0xa000303b, &NMD::MFHC1            , 0,
20038        CP1_                },        /* MFHC1 */
20039     { reserved_block      , 0                   , 0   , 32,
20040        0xfc003fff, 0xa000313b, 0                      , 0,
20041        CP1_                },        /* POOL32Fxf_0~*(49) */
20042     { reserved_block      , 0                   , 0   , 32,
20043        0xfc003fff, 0xa000323b, 0                      , 0,
20044        CP1_                },        /* POOL32Fxf_0~*(50) */
20045     { pool                , ROUND_L_fmt         , 2   , 32,
20046        0xfc003fff, 0xa000333b, 0                      , 0,
20047        CP1_                },        /* ROUND.L.fmt */
20048     { reserved_block      , 0                   , 0   , 32,
20049        0xfc003fff, 0xa000343b, 0                      , 0,
20050        CP1_                },        /* POOL32Fxf_0~*(52) */
20051     { reserved_block      , 0                   , 0   , 32,
20052        0xfc003fff, 0xa000353b, 0                      , 0,
20053        CP1_                },        /* POOL32Fxf_0~*(53) */
20054     { reserved_block      , 0                   , 0   , 32,
20055        0xfc003fff, 0xa000363b, 0                      , 0,
20056        CP1_                },        /* POOL32Fxf_0~*(54) */
20057     { reserved_block      , 0                   , 0   , 32,
20058        0xfc003fff, 0xa000373b, 0                      , 0,
20059        CP1_                },        /* POOL32Fxf_0~*(55) */
20060     { instruction         , 0                   , 0   , 32,
20061        0xfc003fff, 0xa000383b, &NMD::MTHC1            , 0,
20062        CP1_                },        /* MTHC1 */
20063     { reserved_block      , 0                   , 0   , 32,
20064        0xfc003fff, 0xa000393b, 0                      , 0,
20065        CP1_                },        /* POOL32Fxf_0~*(57) */
20066     { reserved_block      , 0                   , 0   , 32,
20067        0xfc003fff, 0xa0003a3b, 0                      , 0,
20068        CP1_                },        /* POOL32Fxf_0~*(58) */
20069     { pool                , ROUND_W_fmt         , 2   , 32,
20070        0xfc003fff, 0xa0003b3b, 0                      , 0,
20071        CP1_                },        /* ROUND.W.fmt */
20072     { reserved_block      , 0                   , 0   , 32,
20073        0xfc003fff, 0xa0003c3b, 0                      , 0,
20074        CP1_                },        /* POOL32Fxf_0~*(60) */
20075     { reserved_block      , 0                   , 0   , 32,
20076        0xfc003fff, 0xa0003d3b, 0                      , 0,
20077        CP1_                },        /* POOL32Fxf_0~*(61) */
20078     { reserved_block      , 0                   , 0   , 32,
20079        0xfc003fff, 0xa0003e3b, 0                      , 0,
20080        CP1_                },        /* POOL32Fxf_0~*(62) */
20081     { reserved_block      , 0                   , 0   , 32,
20082        0xfc003fff, 0xa0003f3b, 0                      , 0,
20083        CP1_                },        /* POOL32Fxf_0~*(63) */
20084 };
20085
20086
20087 NMD::Pool NMD::MOV_fmt[4] = {
20088     { instruction         , 0                   , 0   , 32,
20089        0xfc007fff, 0xa000007b, &NMD::MOV_S            , 0,
20090        CP1_                },        /* MOV.S */
20091     { instruction         , 0                   , 0   , 32,
20092        0xfc007fff, 0xa000207b, &NMD::MOV_D            , 0,
20093        CP1_                },        /* MOV.D */
20094     { reserved_block      , 0                   , 0   , 32,
20095        0xfc007fff, 0xa000407b, 0                      , 0,
20096        CP1_                },        /* MOV.fmt~*(2) */
20097     { reserved_block      , 0                   , 0   , 32,
20098        0xfc007fff, 0xa000607b, 0                      , 0,
20099        CP1_                },        /* MOV.fmt~*(3) */
20100 };
20101
20102
20103 NMD::Pool NMD::ABS_fmt[4] = {
20104     { instruction         , 0                   , 0   , 32,
20105        0xfc007fff, 0xa000037b, &NMD::ABS_S            , 0,
20106        CP1_                },        /* ABS.S */
20107     { instruction         , 0                   , 0   , 32,
20108        0xfc007fff, 0xa000237b, &NMD::ABS_D            , 0,
20109        CP1_                },        /* ABS.D */
20110     { reserved_block      , 0                   , 0   , 32,
20111        0xfc007fff, 0xa000437b, 0                      , 0,
20112        CP1_                },        /* ABS.fmt~*(2) */
20113     { reserved_block      , 0                   , 0   , 32,
20114        0xfc007fff, 0xa000637b, 0                      , 0,
20115        CP1_                },        /* ABS.fmt~*(3) */
20116 };
20117
20118
20119 NMD::Pool NMD::NEG_fmt[4] = {
20120     { instruction         , 0                   , 0   , 32,
20121        0xfc007fff, 0xa0000b7b, &NMD::NEG_S            , 0,
20122        CP1_                },        /* NEG.S */
20123     { instruction         , 0                   , 0   , 32,
20124        0xfc007fff, 0xa0002b7b, &NMD::NEG_D            , 0,
20125        CP1_                },        /* NEG.D */
20126     { reserved_block      , 0                   , 0   , 32,
20127        0xfc007fff, 0xa0004b7b, 0                      , 0,
20128        CP1_                },        /* NEG.fmt~*(2) */
20129     { reserved_block      , 0                   , 0   , 32,
20130        0xfc007fff, 0xa0006b7b, 0                      , 0,
20131        CP1_                },        /* NEG.fmt~*(3) */
20132 };
20133
20134
20135 NMD::Pool NMD::CVT_D_fmt[4] = {
20136     { instruction         , 0                   , 0   , 32,
20137        0xfc007fff, 0xa000137b, &NMD::CVT_D_S          , 0,
20138        CP1_                },        /* CVT.D.S */
20139     { instruction         , 0                   , 0   , 32,
20140        0xfc007fff, 0xa000337b, &NMD::CVT_D_W          , 0,
20141        CP1_                },        /* CVT.D.W */
20142     { instruction         , 0                   , 0   , 32,
20143        0xfc007fff, 0xa000537b, &NMD::CVT_D_L          , 0,
20144        CP1_                },        /* CVT.D.L */
20145     { reserved_block      , 0                   , 0   , 32,
20146        0xfc007fff, 0xa000737b, 0                      , 0,
20147        CP1_                },        /* CVT.D.fmt~*(3) */
20148 };
20149
20150
20151 NMD::Pool NMD::CVT_S_fmt[4] = {
20152     { instruction         , 0                   , 0   , 32,
20153        0xfc007fff, 0xa0001b7b, &NMD::CVT_S_D          , 0,
20154        CP1_                },        /* CVT.S.D */
20155     { instruction         , 0                   , 0   , 32,
20156        0xfc007fff, 0xa0003b7b, &NMD::CVT_S_W          , 0,
20157        CP1_                },        /* CVT.S.W */
20158     { instruction         , 0                   , 0   , 32,
20159        0xfc007fff, 0xa0005b7b, &NMD::CVT_S_L          , 0,
20160        CP1_                },        /* CVT.S.L */
20161     { reserved_block      , 0                   , 0   , 32,
20162        0xfc007fff, 0xa0007b7b, 0                      , 0,
20163        CP1_                },        /* CVT.S.fmt~*(3) */
20164 };
20165
20166
20167 NMD::Pool NMD::POOL32Fxf_1[32] = {
20168     { pool                , MOV_fmt             , 4   , 32,
20169        0xfc001fff, 0xa000007b, 0                      , 0,
20170        CP1_                },        /* MOV.fmt */
20171     { reserved_block      , 0                   , 0   , 32,
20172        0xfc001fff, 0xa000017b, 0                      , 0,
20173        CP1_                },        /* POOL32Fxf_1~*(1) */
20174     { reserved_block      , 0                   , 0   , 32,
20175        0xfc001fff, 0xa000027b, 0                      , 0,
20176        CP1_                },        /* POOL32Fxf_1~*(2) */
20177     { pool                , ABS_fmt             , 4   , 32,
20178        0xfc001fff, 0xa000037b, 0                      , 0,
20179        CP1_                },        /* ABS.fmt */
20180     { reserved_block      , 0                   , 0   , 32,
20181        0xfc001fff, 0xa000047b, 0                      , 0,
20182        CP1_                },        /* POOL32Fxf_1~*(4) */
20183     { reserved_block      , 0                   , 0   , 32,
20184        0xfc001fff, 0xa000057b, 0                      , 0,
20185        CP1_                },        /* POOL32Fxf_1~*(5) */
20186     { reserved_block      , 0                   , 0   , 32,
20187        0xfc001fff, 0xa000067b, 0                      , 0,
20188        CP1_                },        /* POOL32Fxf_1~*(6) */
20189     { reserved_block      , 0                   , 0   , 32,
20190        0xfc001fff, 0xa000077b, 0                      , 0,
20191        CP1_                },        /* POOL32Fxf_1~*(7) */
20192     { reserved_block      , 0                   , 0   , 32,
20193        0xfc001fff, 0xa000087b, 0                      , 0,
20194        CP1_                },        /* POOL32Fxf_1~*(8) */
20195     { reserved_block      , 0                   , 0   , 32,
20196        0xfc001fff, 0xa000097b, 0                      , 0,
20197        CP1_                },        /* POOL32Fxf_1~*(9) */
20198     { reserved_block      , 0                   , 0   , 32,
20199        0xfc001fff, 0xa0000a7b, 0                      , 0,
20200        CP1_                },        /* POOL32Fxf_1~*(10) */
20201     { pool                , NEG_fmt             , 4   , 32,
20202        0xfc001fff, 0xa0000b7b, 0                      , 0,
20203        CP1_                },        /* NEG.fmt */
20204     { reserved_block      , 0                   , 0   , 32,
20205        0xfc001fff, 0xa0000c7b, 0                      , 0,
20206        CP1_                },        /* POOL32Fxf_1~*(12) */
20207     { reserved_block      , 0                   , 0   , 32,
20208        0xfc001fff, 0xa0000d7b, 0                      , 0,
20209        CP1_                },        /* POOL32Fxf_1~*(13) */
20210     { reserved_block      , 0                   , 0   , 32,
20211        0xfc001fff, 0xa0000e7b, 0                      , 0,
20212        CP1_                },        /* POOL32Fxf_1~*(14) */
20213     { reserved_block      , 0                   , 0   , 32,
20214        0xfc001fff, 0xa0000f7b, 0                      , 0,
20215        CP1_                },        /* POOL32Fxf_1~*(15) */
20216     { reserved_block      , 0                   , 0   , 32,
20217        0xfc001fff, 0xa000107b, 0                      , 0,
20218        CP1_                },        /* POOL32Fxf_1~*(16) */
20219     { reserved_block      , 0                   , 0   , 32,
20220        0xfc001fff, 0xa000117b, 0                      , 0,
20221        CP1_                },        /* POOL32Fxf_1~*(17) */
20222     { reserved_block      , 0                   , 0   , 32,
20223        0xfc001fff, 0xa000127b, 0                      , 0,
20224        CP1_                },        /* POOL32Fxf_1~*(18) */
20225     { pool                , CVT_D_fmt           , 4   , 32,
20226        0xfc001fff, 0xa000137b, 0                      , 0,
20227        CP1_                },        /* CVT.D.fmt */
20228     { reserved_block      , 0                   , 0   , 32,
20229        0xfc001fff, 0xa000147b, 0                      , 0,
20230        CP1_                },        /* POOL32Fxf_1~*(20) */
20231     { reserved_block      , 0                   , 0   , 32,
20232        0xfc001fff, 0xa000157b, 0                      , 0,
20233        CP1_                },        /* POOL32Fxf_1~*(21) */
20234     { reserved_block      , 0                   , 0   , 32,
20235        0xfc001fff, 0xa000167b, 0                      , 0,
20236        CP1_                },        /* POOL32Fxf_1~*(22) */
20237     { reserved_block      , 0                   , 0   , 32,
20238        0xfc001fff, 0xa000177b, 0                      , 0,
20239        CP1_                },        /* POOL32Fxf_1~*(23) */
20240     { reserved_block      , 0                   , 0   , 32,
20241        0xfc001fff, 0xa000187b, 0                      , 0,
20242        CP1_                },        /* POOL32Fxf_1~*(24) */
20243     { reserved_block      , 0                   , 0   , 32,
20244        0xfc001fff, 0xa000197b, 0                      , 0,
20245        CP1_                },        /* POOL32Fxf_1~*(25) */
20246     { reserved_block      , 0                   , 0   , 32,
20247        0xfc001fff, 0xa0001a7b, 0                      , 0,
20248        CP1_                },        /* POOL32Fxf_1~*(26) */
20249     { pool                , CVT_S_fmt           , 4   , 32,
20250        0xfc001fff, 0xa0001b7b, 0                      , 0,
20251        CP1_                },        /* CVT.S.fmt */
20252     { reserved_block      , 0                   , 0   , 32,
20253        0xfc001fff, 0xa0001c7b, 0                      , 0,
20254        CP1_                },        /* POOL32Fxf_1~*(28) */
20255     { reserved_block      , 0                   , 0   , 32,
20256        0xfc001fff, 0xa0001d7b, 0                      , 0,
20257        CP1_                },        /* POOL32Fxf_1~*(29) */
20258     { reserved_block      , 0                   , 0   , 32,
20259        0xfc001fff, 0xa0001e7b, 0                      , 0,
20260        CP1_                },        /* POOL32Fxf_1~*(30) */
20261     { reserved_block      , 0                   , 0   , 32,
20262        0xfc001fff, 0xa0001f7b, 0                      , 0,
20263        CP1_                },        /* POOL32Fxf_1~*(31) */
20264 };
20265
20266
20267 NMD::Pool NMD::POOL32Fxf[4] = {
20268     { pool                , POOL32Fxf_0         , 64  , 32,
20269        0xfc0000ff, 0xa000003b, 0                      , 0,
20270        CP1_                },        /* POOL32Fxf_0 */
20271     { pool                , POOL32Fxf_1         , 32  , 32,
20272        0xfc0000ff, 0xa000007b, 0                      , 0,
20273        CP1_                },        /* POOL32Fxf_1 */
20274     { reserved_block      , 0                   , 0   , 32,
20275        0xfc0000ff, 0xa00000bb, 0                      , 0,
20276        CP1_                },        /* POOL32Fxf~*(2) */
20277     { reserved_block      , 0                   , 0   , 32,
20278        0xfc0000ff, 0xa00000fb, 0                      , 0,
20279        CP1_                },        /* POOL32Fxf~*(3) */
20280 };
20281
20282
20283 NMD::Pool NMD::POOL32F_3[8] = {
20284     { pool                , MIN_fmt             , 2   , 32,
20285        0xfc00003f, 0xa0000003, 0                      , 0,
20286        CP1_                },        /* MIN.fmt */
20287     { pool                , MAX_fmt             , 2   , 32,
20288        0xfc00003f, 0xa000000b, 0                      , 0,
20289        CP1_                },        /* MAX.fmt */
20290     { reserved_block      , 0                   , 0   , 32,
20291        0xfc00003f, 0xa0000013, 0                      , 0,
20292        CP1_                },        /* POOL32F_3~*(2) */
20293     { reserved_block      , 0                   , 0   , 32,
20294        0xfc00003f, 0xa000001b, 0                      , 0,
20295        CP1_                },        /* POOL32F_3~*(3) */
20296     { pool                , MINA_fmt            , 2   , 32,
20297        0xfc00003f, 0xa0000023, 0                      , 0,
20298        CP1_                },        /* MINA.fmt */
20299     { pool                , MAXA_fmt            , 2   , 32,
20300        0xfc00003f, 0xa000002b, 0                      , 0,
20301        CP1_                },        /* MAXA.fmt */
20302     { reserved_block      , 0                   , 0   , 32,
20303        0xfc00003f, 0xa0000033, 0                      , 0,
20304        CP1_                },        /* POOL32F_3~*(6) */
20305     { pool                , POOL32Fxf           , 4   , 32,
20306        0xfc00003f, 0xa000003b, 0                      , 0,
20307        CP1_                },        /* POOL32Fxf */
20308 };
20309
20310
20311 NMD::Pool NMD::CMP_condn_S[32] = {
20312     { instruction         , 0                   , 0   , 32,
20313        0xfc0007ff, 0xa0000005, &NMD::CMP_AF_S         , 0,
20314        CP1_                },        /* CMP.AF.S */
20315     { instruction         , 0                   , 0   , 32,
20316        0xfc0007ff, 0xa0000045, &NMD::CMP_UN_S         , 0,
20317        CP1_                },        /* CMP.UN.S */
20318     { instruction         , 0                   , 0   , 32,
20319        0xfc0007ff, 0xa0000085, &NMD::CMP_EQ_S         , 0,
20320        CP1_                },        /* CMP.EQ.S */
20321     { instruction         , 0                   , 0   , 32,
20322        0xfc0007ff, 0xa00000c5, &NMD::CMP_UEQ_S        , 0,
20323        CP1_                },        /* CMP.UEQ.S */
20324     { instruction         , 0                   , 0   , 32,
20325        0xfc0007ff, 0xa0000105, &NMD::CMP_LT_S         , 0,
20326        CP1_                },        /* CMP.LT.S */
20327     { instruction         , 0                   , 0   , 32,
20328        0xfc0007ff, 0xa0000145, &NMD::CMP_ULT_S        , 0,
20329        CP1_                },        /* CMP.ULT.S */
20330     { instruction         , 0                   , 0   , 32,
20331        0xfc0007ff, 0xa0000185, &NMD::CMP_LE_S         , 0,
20332        CP1_                },        /* CMP.LE.S */
20333     { instruction         , 0                   , 0   , 32,
20334        0xfc0007ff, 0xa00001c5, &NMD::CMP_ULE_S        , 0,
20335        CP1_                },        /* CMP.ULE.S */
20336     { instruction         , 0                   , 0   , 32,
20337        0xfc0007ff, 0xa0000205, &NMD::CMP_SAF_S        , 0,
20338        CP1_                },        /* CMP.SAF.S */
20339     { instruction         , 0                   , 0   , 32,
20340        0xfc0007ff, 0xa0000245, &NMD::CMP_SUN_S        , 0,
20341        CP1_                },        /* CMP.SUN.S */
20342     { instruction         , 0                   , 0   , 32,
20343        0xfc0007ff, 0xa0000285, &NMD::CMP_SEQ_S        , 0,
20344        CP1_                },        /* CMP.SEQ.S */
20345     { instruction         , 0                   , 0   , 32,
20346        0xfc0007ff, 0xa00002c5, &NMD::CMP_SUEQ_S       , 0,
20347        CP1_                },        /* CMP.SUEQ.S */
20348     { instruction         , 0                   , 0   , 32,
20349        0xfc0007ff, 0xa0000305, &NMD::CMP_SLT_S        , 0,
20350        CP1_                },        /* CMP.SLT.S */
20351     { instruction         , 0                   , 0   , 32,
20352        0xfc0007ff, 0xa0000345, &NMD::CMP_SULT_S       , 0,
20353        CP1_                },        /* CMP.SULT.S */
20354     { instruction         , 0                   , 0   , 32,
20355        0xfc0007ff, 0xa0000385, &NMD::CMP_SLE_S        , 0,
20356        CP1_                },        /* CMP.SLE.S */
20357     { instruction         , 0                   , 0   , 32,
20358        0xfc0007ff, 0xa00003c5, &NMD::CMP_SULE_S       , 0,
20359        CP1_                },        /* CMP.SULE.S */
20360     { reserved_block      , 0                   , 0   , 32,
20361        0xfc0007ff, 0xa0000405, 0                      , 0,
20362        CP1_                },        /* CMP.condn.S~*(16) */
20363     { instruction         , 0                   , 0   , 32,
20364        0xfc0007ff, 0xa0000445, &NMD::CMP_OR_S         , 0,
20365        CP1_                },        /* CMP.OR.S */
20366     { instruction         , 0                   , 0   , 32,
20367        0xfc0007ff, 0xa0000485, &NMD::CMP_UNE_S        , 0,
20368        CP1_                },        /* CMP.UNE.S */
20369     { instruction         , 0                   , 0   , 32,
20370        0xfc0007ff, 0xa00004c5, &NMD::CMP_NE_S         , 0,
20371        CP1_                },        /* CMP.NE.S */
20372     { reserved_block      , 0                   , 0   , 32,
20373        0xfc0007ff, 0xa0000505, 0                      , 0,
20374        CP1_                },        /* CMP.condn.S~*(20) */
20375     { reserved_block      , 0                   , 0   , 32,
20376        0xfc0007ff, 0xa0000545, 0                      , 0,
20377        CP1_                },        /* CMP.condn.S~*(21) */
20378     { reserved_block      , 0                   , 0   , 32,
20379        0xfc0007ff, 0xa0000585, 0                      , 0,
20380        CP1_                },        /* CMP.condn.S~*(22) */
20381     { reserved_block      , 0                   , 0   , 32,
20382        0xfc0007ff, 0xa00005c5, 0                      , 0,
20383        CP1_                },        /* CMP.condn.S~*(23) */
20384     { reserved_block      , 0                   , 0   , 32,
20385        0xfc0007ff, 0xa0000605, 0                      , 0,
20386        CP1_                },        /* CMP.condn.S~*(24) */
20387     { instruction         , 0                   , 0   , 32,
20388        0xfc0007ff, 0xa0000645, &NMD::CMP_SOR_S        , 0,
20389        CP1_                },        /* CMP.SOR.S */
20390     { instruction         , 0                   , 0   , 32,
20391        0xfc0007ff, 0xa0000685, &NMD::CMP_SUNE_S       , 0,
20392        CP1_                },        /* CMP.SUNE.S */
20393     { instruction         , 0                   , 0   , 32,
20394        0xfc0007ff, 0xa00006c5, &NMD::CMP_SNE_S        , 0,
20395        CP1_                },        /* CMP.SNE.S */
20396     { reserved_block      , 0                   , 0   , 32,
20397        0xfc0007ff, 0xa0000705, 0                      , 0,
20398        CP1_                },        /* CMP.condn.S~*(28) */
20399     { reserved_block      , 0                   , 0   , 32,
20400        0xfc0007ff, 0xa0000745, 0                      , 0,
20401        CP1_                },        /* CMP.condn.S~*(29) */
20402     { reserved_block      , 0                   , 0   , 32,
20403        0xfc0007ff, 0xa0000785, 0                      , 0,
20404        CP1_                },        /* CMP.condn.S~*(30) */
20405     { reserved_block      , 0                   , 0   , 32,
20406        0xfc0007ff, 0xa00007c5, 0                      , 0,
20407        CP1_                },        /* CMP.condn.S~*(31) */
20408 };
20409
20410
20411 NMD::Pool NMD::CMP_condn_D[32] = {
20412     { instruction         , 0                   , 0   , 32,
20413        0xfc0007ff, 0xa0000015, &NMD::CMP_AF_D         , 0,
20414        CP1_                },        /* CMP.AF.D */
20415     { instruction         , 0                   , 0   , 32,
20416        0xfc0007ff, 0xa0000055, &NMD::CMP_UN_D         , 0,
20417        CP1_                },        /* CMP.UN.D */
20418     { instruction         , 0                   , 0   , 32,
20419        0xfc0007ff, 0xa0000095, &NMD::CMP_EQ_D         , 0,
20420        CP1_                },        /* CMP.EQ.D */
20421     { instruction         , 0                   , 0   , 32,
20422        0xfc0007ff, 0xa00000d5, &NMD::CMP_UEQ_D        , 0,
20423        CP1_                },        /* CMP.UEQ.D */
20424     { instruction         , 0                   , 0   , 32,
20425        0xfc0007ff, 0xa0000115, &NMD::CMP_LT_D         , 0,
20426        CP1_                },        /* CMP.LT.D */
20427     { instruction         , 0                   , 0   , 32,
20428        0xfc0007ff, 0xa0000155, &NMD::CMP_ULT_D        , 0,
20429        CP1_                },        /* CMP.ULT.D */
20430     { instruction         , 0                   , 0   , 32,
20431        0xfc0007ff, 0xa0000195, &NMD::CMP_LE_D         , 0,
20432        CP1_                },        /* CMP.LE.D */
20433     { instruction         , 0                   , 0   , 32,
20434        0xfc0007ff, 0xa00001d5, &NMD::CMP_ULE_D        , 0,
20435        CP1_                },        /* CMP.ULE.D */
20436     { instruction         , 0                   , 0   , 32,
20437        0xfc0007ff, 0xa0000215, &NMD::CMP_SAF_D        , 0,
20438        CP1_                },        /* CMP.SAF.D */
20439     { instruction         , 0                   , 0   , 32,
20440        0xfc0007ff, 0xa0000255, &NMD::CMP_SUN_D        , 0,
20441        CP1_                },        /* CMP.SUN.D */
20442     { instruction         , 0                   , 0   , 32,
20443        0xfc0007ff, 0xa0000295, &NMD::CMP_SEQ_D        , 0,
20444        CP1_                },        /* CMP.SEQ.D */
20445     { instruction         , 0                   , 0   , 32,
20446        0xfc0007ff, 0xa00002d5, &NMD::CMP_SUEQ_D       , 0,
20447        CP1_                },        /* CMP.SUEQ.D */
20448     { instruction         , 0                   , 0   , 32,
20449        0xfc0007ff, 0xa0000315, &NMD::CMP_SLT_D        , 0,
20450        CP1_                },        /* CMP.SLT.D */
20451     { instruction         , 0                   , 0   , 32,
20452        0xfc0007ff, 0xa0000355, &NMD::CMP_SULT_D       , 0,
20453        CP1_                },        /* CMP.SULT.D */
20454     { instruction         , 0                   , 0   , 32,
20455        0xfc0007ff, 0xa0000395, &NMD::CMP_SLE_D        , 0,
20456        CP1_                },        /* CMP.SLE.D */
20457     { instruction         , 0                   , 0   , 32,
20458        0xfc0007ff, 0xa00003d5, &NMD::CMP_SULE_D       , 0,
20459        CP1_                },        /* CMP.SULE.D */
20460     { reserved_block      , 0                   , 0   , 32,
20461        0xfc0007ff, 0xa0000415, 0                      , 0,
20462        CP1_                },        /* CMP.condn.D~*(16) */
20463     { instruction         , 0                   , 0   , 32,
20464        0xfc0007ff, 0xa0000455, &NMD::CMP_OR_D         , 0,
20465        CP1_                },        /* CMP.OR.D */
20466     { instruction         , 0                   , 0   , 32,
20467        0xfc0007ff, 0xa0000495, &NMD::CMP_UNE_D        , 0,
20468        CP1_                },        /* CMP.UNE.D */
20469     { instruction         , 0                   , 0   , 32,
20470        0xfc0007ff, 0xa00004d5, &NMD::CMP_NE_D         , 0,
20471        CP1_                },        /* CMP.NE.D */
20472     { reserved_block      , 0                   , 0   , 32,
20473        0xfc0007ff, 0xa0000515, 0                      , 0,
20474        CP1_                },        /* CMP.condn.D~*(20) */
20475     { reserved_block      , 0                   , 0   , 32,
20476        0xfc0007ff, 0xa0000555, 0                      , 0,
20477        CP1_                },        /* CMP.condn.D~*(21) */
20478     { reserved_block      , 0                   , 0   , 32,
20479        0xfc0007ff, 0xa0000595, 0                      , 0,
20480        CP1_                },        /* CMP.condn.D~*(22) */
20481     { reserved_block      , 0                   , 0   , 32,
20482        0xfc0007ff, 0xa00005d5, 0                      , 0,
20483        CP1_                },        /* CMP.condn.D~*(23) */
20484     { reserved_block      , 0                   , 0   , 32,
20485        0xfc0007ff, 0xa0000615, 0                      , 0,
20486        CP1_                },        /* CMP.condn.D~*(24) */
20487     { instruction         , 0                   , 0   , 32,
20488        0xfc0007ff, 0xa0000655, &NMD::CMP_SOR_D        , 0,
20489        CP1_                },        /* CMP.SOR.D */
20490     { instruction         , 0                   , 0   , 32,
20491        0xfc0007ff, 0xa0000695, &NMD::CMP_SUNE_D       , 0,
20492        CP1_                },        /* CMP.SUNE.D */
20493     { instruction         , 0                   , 0   , 32,
20494        0xfc0007ff, 0xa00006d5, &NMD::CMP_SNE_D        , 0,
20495        CP1_                },        /* CMP.SNE.D */
20496     { reserved_block      , 0                   , 0   , 32,
20497        0xfc0007ff, 0xa0000715, 0                      , 0,
20498        CP1_                },        /* CMP.condn.D~*(28) */
20499     { reserved_block      , 0                   , 0   , 32,
20500        0xfc0007ff, 0xa0000755, 0                      , 0,
20501        CP1_                },        /* CMP.condn.D~*(29) */
20502     { reserved_block      , 0                   , 0   , 32,
20503        0xfc0007ff, 0xa0000795, 0                      , 0,
20504        CP1_                },        /* CMP.condn.D~*(30) */
20505     { reserved_block      , 0                   , 0   , 32,
20506        0xfc0007ff, 0xa00007d5, 0                      , 0,
20507        CP1_                },        /* CMP.condn.D~*(31) */
20508 };
20509
20510
20511 NMD::Pool NMD::POOL32F_5[8] = {
20512     { pool                , CMP_condn_S         , 32  , 32,
20513        0xfc00003f, 0xa0000005, 0                      , 0,
20514        CP1_                },        /* CMP.condn.S */
20515     { reserved_block      , 0                   , 0   , 32,
20516        0xfc00003f, 0xa000000d, 0                      , 0,
20517        CP1_                },        /* POOL32F_5~*(1) */
20518     { pool                , CMP_condn_D         , 32  , 32,
20519        0xfc00003f, 0xa0000015, 0                      , 0,
20520        CP1_                },        /* CMP.condn.D */
20521     { reserved_block      , 0                   , 0   , 32,
20522        0xfc00003f, 0xa000001d, 0                      , 0,
20523        CP1_                },        /* POOL32F_5~*(3) */
20524     { reserved_block      , 0                   , 0   , 32,
20525        0xfc00003f, 0xa0000025, 0                      , 0,
20526        CP1_                },        /* POOL32F_5~*(4) */
20527     { reserved_block      , 0                   , 0   , 32,
20528        0xfc00003f, 0xa000002d, 0                      , 0,
20529        CP1_                },        /* POOL32F_5~*(5) */
20530     { reserved_block      , 0                   , 0   , 32,
20531        0xfc00003f, 0xa0000035, 0                      , 0,
20532        CP1_                },        /* POOL32F_5~*(6) */
20533     { reserved_block      , 0                   , 0   , 32,
20534        0xfc00003f, 0xa000003d, 0                      , 0,
20535        CP1_                },        /* POOL32F_5~*(7) */
20536 };
20537
20538
20539 NMD::Pool NMD::POOL32F[8] = {
20540     { pool                , POOL32F_0           , 64  , 32,
20541        0xfc000007, 0xa0000000, 0                      , 0,
20542        CP1_                },        /* POOL32F_0 */
20543     { reserved_block      , 0                   , 0   , 32,
20544        0xfc000007, 0xa0000001, 0                      , 0,
20545        CP1_                },        /* POOL32F~*(1) */
20546     { reserved_block      , 0                   , 0   , 32,
20547        0xfc000007, 0xa0000002, 0                      , 0,
20548        CP1_                },        /* POOL32F~*(2) */
20549     { pool                , POOL32F_3           , 8   , 32,
20550        0xfc000007, 0xa0000003, 0                      , 0,
20551        CP1_                },        /* POOL32F_3 */
20552     { reserved_block      , 0                   , 0   , 32,
20553        0xfc000007, 0xa0000004, 0                      , 0,
20554        CP1_                },        /* POOL32F~*(4) */
20555     { pool                , POOL32F_5           , 8   , 32,
20556        0xfc000007, 0xa0000005, 0                      , 0,
20557        CP1_                },        /* POOL32F_5 */
20558     { reserved_block      , 0                   , 0   , 32,
20559        0xfc000007, 0xa0000006, 0                      , 0,
20560        CP1_                },        /* POOL32F~*(6) */
20561     { reserved_block      , 0                   , 0   , 32,
20562        0xfc000007, 0xa0000007, 0                      , 0,
20563        CP1_                },        /* POOL32F~*(7) */
20564 };
20565
20566
20567 NMD::Pool NMD::POOL32S_0[64] = {
20568     { reserved_block      , 0                   , 0   , 32,
20569        0xfc0001ff, 0xc0000000, 0                      , 0,
20570        0x0                 },        /* POOL32S_0~*(0) */
20571     { instruction         , 0                   , 0   , 32,
20572        0xfc0001ff, 0xc0000008, &NMD::DLSA             , 0,
20573        MIPS64_             },        /* DLSA */
20574     { instruction         , 0                   , 0   , 32,
20575        0xfc0001ff, 0xc0000010, &NMD::DSLLV            , 0,
20576        MIPS64_             },        /* DSLLV */
20577     { instruction         , 0                   , 0   , 32,
20578        0xfc0001ff, 0xc0000018, &NMD::DMUL             , 0,
20579        MIPS64_             },        /* DMUL */
20580     { reserved_block      , 0                   , 0   , 32,
20581        0xfc0001ff, 0xc0000020, 0                      , 0,
20582        0x0                 },        /* POOL32S_0~*(4) */
20583     { reserved_block      , 0                   , 0   , 32,
20584        0xfc0001ff, 0xc0000028, 0                      , 0,
20585        0x0                 },        /* POOL32S_0~*(5) */
20586     { reserved_block      , 0                   , 0   , 32,
20587        0xfc0001ff, 0xc0000030, 0                      , 0,
20588        0x0                 },        /* POOL32S_0~*(6) */
20589     { reserved_block      , 0                   , 0   , 32,
20590        0xfc0001ff, 0xc0000038, 0                      , 0,
20591        0x0                 },        /* POOL32S_0~*(7) */
20592     { reserved_block      , 0                   , 0   , 32,
20593        0xfc0001ff, 0xc0000040, 0                      , 0,
20594        0x0                 },        /* POOL32S_0~*(8) */
20595     { reserved_block      , 0                   , 0   , 32,
20596        0xfc0001ff, 0xc0000048, 0                      , 0,
20597        0x0                 },        /* POOL32S_0~*(9) */
20598     { instruction         , 0                   , 0   , 32,
20599        0xfc0001ff, 0xc0000050, &NMD::DSRLV            , 0,
20600        MIPS64_             },        /* DSRLV */
20601     { instruction         , 0                   , 0   , 32,
20602        0xfc0001ff, 0xc0000058, &NMD::DMUH             , 0,
20603        MIPS64_             },        /* DMUH */
20604     { reserved_block      , 0                   , 0   , 32,
20605        0xfc0001ff, 0xc0000060, 0                      , 0,
20606        0x0                 },        /* POOL32S_0~*(12) */
20607     { reserved_block      , 0                   , 0   , 32,
20608        0xfc0001ff, 0xc0000068, 0                      , 0,
20609        0x0                 },        /* POOL32S_0~*(13) */
20610     { reserved_block      , 0                   , 0   , 32,
20611        0xfc0001ff, 0xc0000070, 0                      , 0,
20612        0x0                 },        /* POOL32S_0~*(14) */
20613     { reserved_block      , 0                   , 0   , 32,
20614        0xfc0001ff, 0xc0000078, 0                      , 0,
20615        0x0                 },        /* POOL32S_0~*(15) */
20616     { reserved_block      , 0                   , 0   , 32,
20617        0xfc0001ff, 0xc0000080, 0                      , 0,
20618        0x0                 },        /* POOL32S_0~*(16) */
20619     { reserved_block      , 0                   , 0   , 32,
20620        0xfc0001ff, 0xc0000088, 0                      , 0,
20621        0x0                 },        /* POOL32S_0~*(17) */
20622     { instruction         , 0                   , 0   , 32,
20623        0xfc0001ff, 0xc0000090, &NMD::DSRAV            , 0,
20624        MIPS64_             },        /* DSRAV */
20625     { instruction         , 0                   , 0   , 32,
20626        0xfc0001ff, 0xc0000098, &NMD::DMULU            , 0,
20627        MIPS64_             },        /* DMULU */
20628     { reserved_block      , 0                   , 0   , 32,
20629        0xfc0001ff, 0xc00000a0, 0                      , 0,
20630        0x0                 },        /* POOL32S_0~*(20) */
20631     { reserved_block      , 0                   , 0   , 32,
20632        0xfc0001ff, 0xc00000a8, 0                      , 0,
20633        0x0                 },        /* POOL32S_0~*(21) */
20634     { reserved_block      , 0                   , 0   , 32,
20635        0xfc0001ff, 0xc00000b0, 0                      , 0,
20636        0x0                 },        /* POOL32S_0~*(22) */
20637     { reserved_block      , 0                   , 0   , 32,
20638        0xfc0001ff, 0xc00000b8, 0                      , 0,
20639        0x0                 },        /* POOL32S_0~*(23) */
20640     { reserved_block      , 0                   , 0   , 32,
20641        0xfc0001ff, 0xc00000c0, 0                      , 0,
20642        0x0                 },        /* POOL32S_0~*(24) */
20643     { reserved_block      , 0                   , 0   , 32,
20644        0xfc0001ff, 0xc00000c8, 0                      , 0,
20645        0x0                 },        /* POOL32S_0~*(25) */
20646     { instruction         , 0                   , 0   , 32,
20647        0xfc0001ff, 0xc00000d0, &NMD::DROTRV           , 0,
20648        MIPS64_             },        /* DROTRV */
20649     { instruction         , 0                   , 0   , 32,
20650        0xfc0001ff, 0xc00000d8, &NMD::DMUHU            , 0,
20651        MIPS64_             },        /* DMUHU */
20652     { reserved_block      , 0                   , 0   , 32,
20653        0xfc0001ff, 0xc00000e0, 0                      , 0,
20654        0x0                 },        /* POOL32S_0~*(28) */
20655     { reserved_block      , 0                   , 0   , 32,
20656        0xfc0001ff, 0xc00000e8, 0                      , 0,
20657        0x0                 },        /* POOL32S_0~*(29) */
20658     { reserved_block      , 0                   , 0   , 32,
20659        0xfc0001ff, 0xc00000f0, 0                      , 0,
20660        0x0                 },        /* POOL32S_0~*(30) */
20661     { reserved_block      , 0                   , 0   , 32,
20662        0xfc0001ff, 0xc00000f8, 0                      , 0,
20663        0x0                 },        /* POOL32S_0~*(31) */
20664     { reserved_block      , 0                   , 0   , 32,
20665        0xfc0001ff, 0xc0000100, 0                      , 0,
20666        0x0                 },        /* POOL32S_0~*(32) */
20667     { reserved_block      , 0                   , 0   , 32,
20668        0xfc0001ff, 0xc0000108, 0                      , 0,
20669        0x0                 },        /* POOL32S_0~*(33) */
20670     { instruction         , 0                   , 0   , 32,
20671        0xfc0001ff, 0xc0000110, &NMD::DADD             , 0,
20672        MIPS64_             },        /* DADD */
20673     { instruction         , 0                   , 0   , 32,
20674        0xfc0001ff, 0xc0000118, &NMD::DDIV             , 0,
20675        MIPS64_             },        /* DDIV */
20676     { reserved_block      , 0                   , 0   , 32,
20677        0xfc0001ff, 0xc0000120, 0                      , 0,
20678        0x0                 },        /* POOL32S_0~*(36) */
20679     { reserved_block      , 0                   , 0   , 32,
20680        0xfc0001ff, 0xc0000128, 0                      , 0,
20681        0x0                 },        /* POOL32S_0~*(37) */
20682     { reserved_block      , 0                   , 0   , 32,
20683        0xfc0001ff, 0xc0000130, 0                      , 0,
20684        0x0                 },        /* POOL32S_0~*(38) */
20685     { reserved_block      , 0                   , 0   , 32,
20686        0xfc0001ff, 0xc0000138, 0                      , 0,
20687        0x0                 },        /* POOL32S_0~*(39) */
20688     { reserved_block      , 0                   , 0   , 32,
20689        0xfc0001ff, 0xc0000140, 0                      , 0,
20690        0x0                 },        /* POOL32S_0~*(40) */
20691     { reserved_block      , 0                   , 0   , 32,
20692        0xfc0001ff, 0xc0000148, 0                      , 0,
20693        0x0                 },        /* POOL32S_0~*(41) */
20694     { instruction         , 0                   , 0   , 32,
20695        0xfc0001ff, 0xc0000150, &NMD::DADDU            , 0,
20696        MIPS64_             },        /* DADDU */
20697     { instruction         , 0                   , 0   , 32,
20698        0xfc0001ff, 0xc0000158, &NMD::DMOD             , 0,
20699        MIPS64_             },        /* DMOD */
20700     { reserved_block      , 0                   , 0   , 32,
20701        0xfc0001ff, 0xc0000160, 0                      , 0,
20702        0x0                 },        /* POOL32S_0~*(44) */
20703     { reserved_block      , 0                   , 0   , 32,
20704        0xfc0001ff, 0xc0000168, 0                      , 0,
20705        0x0                 },        /* POOL32S_0~*(45) */
20706     { reserved_block      , 0                   , 0   , 32,
20707        0xfc0001ff, 0xc0000170, 0                      , 0,
20708        0x0                 },        /* POOL32S_0~*(46) */
20709     { reserved_block      , 0                   , 0   , 32,
20710        0xfc0001ff, 0xc0000178, 0                      , 0,
20711        0x0                 },        /* POOL32S_0~*(47) */
20712     { reserved_block      , 0                   , 0   , 32,
20713        0xfc0001ff, 0xc0000180, 0                      , 0,
20714        0x0                 },        /* POOL32S_0~*(48) */
20715     { reserved_block      , 0                   , 0   , 32,
20716        0xfc0001ff, 0xc0000188, 0                      , 0,
20717        0x0                 },        /* POOL32S_0~*(49) */
20718     { instruction         , 0                   , 0   , 32,
20719        0xfc0001ff, 0xc0000190, &NMD::DSUB             , 0,
20720        MIPS64_             },        /* DSUB */
20721     { instruction         , 0                   , 0   , 32,
20722        0xfc0001ff, 0xc0000198, &NMD::DDIVU            , 0,
20723        MIPS64_             },        /* DDIVU */
20724     { reserved_block      , 0                   , 0   , 32,
20725        0xfc0001ff, 0xc00001a0, 0                      , 0,
20726        0x0                 },        /* POOL32S_0~*(52) */
20727     { reserved_block      , 0                   , 0   , 32,
20728        0xfc0001ff, 0xc00001a8, 0                      , 0,
20729        0x0                 },        /* POOL32S_0~*(53) */
20730     { reserved_block      , 0                   , 0   , 32,
20731        0xfc0001ff, 0xc00001b0, 0                      , 0,
20732        0x0                 },        /* POOL32S_0~*(54) */
20733     { reserved_block      , 0                   , 0   , 32,
20734        0xfc0001ff, 0xc00001b8, 0                      , 0,
20735        0x0                 },        /* POOL32S_0~*(55) */
20736     { reserved_block      , 0                   , 0   , 32,
20737        0xfc0001ff, 0xc00001c0, 0                      , 0,
20738        0x0                 },        /* POOL32S_0~*(56) */
20739     { reserved_block      , 0                   , 0   , 32,
20740        0xfc0001ff, 0xc00001c8, 0                      , 0,
20741        0x0                 },        /* POOL32S_0~*(57) */
20742     { instruction         , 0                   , 0   , 32,
20743        0xfc0001ff, 0xc00001d0, &NMD::DSUBU            , 0,
20744        MIPS64_             },        /* DSUBU */
20745     { instruction         , 0                   , 0   , 32,
20746        0xfc0001ff, 0xc00001d8, &NMD::DMODU            , 0,
20747        MIPS64_             },        /* DMODU */
20748     { reserved_block      , 0                   , 0   , 32,
20749        0xfc0001ff, 0xc00001e0, 0                      , 0,
20750        0x0                 },        /* POOL32S_0~*(60) */
20751     { reserved_block      , 0                   , 0   , 32,
20752        0xfc0001ff, 0xc00001e8, 0                      , 0,
20753        0x0                 },        /* POOL32S_0~*(61) */
20754     { reserved_block      , 0                   , 0   , 32,
20755        0xfc0001ff, 0xc00001f0, 0                      , 0,
20756        0x0                 },        /* POOL32S_0~*(62) */
20757     { reserved_block      , 0                   , 0   , 32,
20758        0xfc0001ff, 0xc00001f8, 0                      , 0,
20759        0x0                 },        /* POOL32S_0~*(63) */
20760 };
20761
20762
20763 NMD::Pool NMD::POOL32Sxf_4[128] = {
20764     { reserved_block      , 0                   , 0   , 32,
20765        0xfc00ffff, 0xc000013c, 0                      , 0,
20766        0x0                 },        /* POOL32Sxf_4~*(0) */
20767     { reserved_block      , 0                   , 0   , 32,
20768        0xfc00ffff, 0xc000033c, 0                      , 0,
20769        0x0                 },        /* POOL32Sxf_4~*(1) */
20770     { reserved_block      , 0                   , 0   , 32,
20771        0xfc00ffff, 0xc000053c, 0                      , 0,
20772        0x0                 },        /* POOL32Sxf_4~*(2) */
20773     { reserved_block      , 0                   , 0   , 32,
20774        0xfc00ffff, 0xc000073c, 0                      , 0,
20775        0x0                 },        /* POOL32Sxf_4~*(3) */
20776     { reserved_block      , 0                   , 0   , 32,
20777        0xfc00ffff, 0xc000093c, 0                      , 0,
20778        0x0                 },        /* POOL32Sxf_4~*(4) */
20779     { reserved_block      , 0                   , 0   , 32,
20780        0xfc00ffff, 0xc0000b3c, 0                      , 0,
20781        0x0                 },        /* POOL32Sxf_4~*(5) */
20782     { reserved_block      , 0                   , 0   , 32,
20783        0xfc00ffff, 0xc0000d3c, 0                      , 0,
20784        0x0                 },        /* POOL32Sxf_4~*(6) */
20785     { reserved_block      , 0                   , 0   , 32,
20786        0xfc00ffff, 0xc0000f3c, 0                      , 0,
20787        0x0                 },        /* POOL32Sxf_4~*(7) */
20788     { reserved_block      , 0                   , 0   , 32,
20789        0xfc00ffff, 0xc000113c, 0                      , 0,
20790        0x0                 },        /* POOL32Sxf_4~*(8) */
20791     { reserved_block      , 0                   , 0   , 32,
20792        0xfc00ffff, 0xc000133c, 0                      , 0,
20793        0x0                 },        /* POOL32Sxf_4~*(9) */
20794     { reserved_block      , 0                   , 0   , 32,
20795        0xfc00ffff, 0xc000153c, 0                      , 0,
20796        0x0                 },        /* POOL32Sxf_4~*(10) */
20797     { reserved_block      , 0                   , 0   , 32,
20798        0xfc00ffff, 0xc000173c, 0                      , 0,
20799        0x0                 },        /* POOL32Sxf_4~*(11) */
20800     { reserved_block      , 0                   , 0   , 32,
20801        0xfc00ffff, 0xc000193c, 0                      , 0,
20802        0x0                 },        /* POOL32Sxf_4~*(12) */
20803     { reserved_block      , 0                   , 0   , 32,
20804        0xfc00ffff, 0xc0001b3c, 0                      , 0,
20805        0x0                 },        /* POOL32Sxf_4~*(13) */
20806     { reserved_block      , 0                   , 0   , 32,
20807        0xfc00ffff, 0xc0001d3c, 0                      , 0,
20808        0x0                 },        /* POOL32Sxf_4~*(14) */
20809     { reserved_block      , 0                   , 0   , 32,
20810        0xfc00ffff, 0xc0001f3c, 0                      , 0,
20811        0x0                 },        /* POOL32Sxf_4~*(15) */
20812     { reserved_block      , 0                   , 0   , 32,
20813        0xfc00ffff, 0xc000213c, 0                      , 0,
20814        0x0                 },        /* POOL32Sxf_4~*(16) */
20815     { reserved_block      , 0                   , 0   , 32,
20816        0xfc00ffff, 0xc000233c, 0                      , 0,
20817        0x0                 },        /* POOL32Sxf_4~*(17) */
20818     { reserved_block      , 0                   , 0   , 32,
20819        0xfc00ffff, 0xc000253c, 0                      , 0,
20820        0x0                 },        /* POOL32Sxf_4~*(18) */
20821     { reserved_block      , 0                   , 0   , 32,
20822        0xfc00ffff, 0xc000273c, 0                      , 0,
20823        0x0                 },        /* POOL32Sxf_4~*(19) */
20824     { reserved_block      , 0                   , 0   , 32,
20825        0xfc00ffff, 0xc000293c, 0                      , 0,
20826        0x0                 },        /* POOL32Sxf_4~*(20) */
20827     { reserved_block      , 0                   , 0   , 32,
20828        0xfc00ffff, 0xc0002b3c, 0                      , 0,
20829        0x0                 },        /* POOL32Sxf_4~*(21) */
20830     { reserved_block      , 0                   , 0   , 32,
20831        0xfc00ffff, 0xc0002d3c, 0                      , 0,
20832        0x0                 },        /* POOL32Sxf_4~*(22) */
20833     { reserved_block      , 0                   , 0   , 32,
20834        0xfc00ffff, 0xc0002f3c, 0                      , 0,
20835        0x0                 },        /* POOL32Sxf_4~*(23) */
20836     { reserved_block      , 0                   , 0   , 32,
20837        0xfc00ffff, 0xc000313c, 0                      , 0,
20838        0x0                 },        /* POOL32Sxf_4~*(24) */
20839     { reserved_block      , 0                   , 0   , 32,
20840        0xfc00ffff, 0xc000333c, 0                      , 0,
20841        0x0                 },        /* POOL32Sxf_4~*(25) */
20842     { reserved_block      , 0                   , 0   , 32,
20843        0xfc00ffff, 0xc000353c, 0                      , 0,
20844        0x0                 },        /* POOL32Sxf_4~*(26) */
20845     { reserved_block      , 0                   , 0   , 32,
20846        0xfc00ffff, 0xc000373c, 0                      , 0,
20847        0x0                 },        /* POOL32Sxf_4~*(27) */
20848     { reserved_block      , 0                   , 0   , 32,
20849        0xfc00ffff, 0xc000393c, 0                      , 0,
20850        0x0                 },        /* POOL32Sxf_4~*(28) */
20851     { reserved_block      , 0                   , 0   , 32,
20852        0xfc00ffff, 0xc0003b3c, 0                      , 0,
20853        0x0                 },        /* POOL32Sxf_4~*(29) */
20854     { reserved_block      , 0                   , 0   , 32,
20855        0xfc00ffff, 0xc0003d3c, 0                      , 0,
20856        0x0                 },        /* POOL32Sxf_4~*(30) */
20857     { reserved_block      , 0                   , 0   , 32,
20858        0xfc00ffff, 0xc0003f3c, 0                      , 0,
20859        0x0                 },        /* POOL32Sxf_4~*(31) */
20860     { reserved_block      , 0                   , 0   , 32,
20861        0xfc00ffff, 0xc000413c, 0                      , 0,
20862        0x0                 },        /* POOL32Sxf_4~*(32) */
20863     { reserved_block      , 0                   , 0   , 32,
20864        0xfc00ffff, 0xc000433c, 0                      , 0,
20865        0x0                 },        /* POOL32Sxf_4~*(33) */
20866     { reserved_block      , 0                   , 0   , 32,
20867        0xfc00ffff, 0xc000453c, 0                      , 0,
20868        0x0                 },        /* POOL32Sxf_4~*(34) */
20869     { reserved_block      , 0                   , 0   , 32,
20870        0xfc00ffff, 0xc000473c, 0                      , 0,
20871        0x0                 },        /* POOL32Sxf_4~*(35) */
20872     { reserved_block      , 0                   , 0   , 32,
20873        0xfc00ffff, 0xc000493c, 0                      , 0,
20874        0x0                 },        /* POOL32Sxf_4~*(36) */
20875     { instruction         , 0                   , 0   , 32,
20876        0xfc00ffff, 0xc0004b3c, &NMD::DCLO             , 0,
20877        MIPS64_             },        /* DCLO */
20878     { reserved_block      , 0                   , 0   , 32,
20879        0xfc00ffff, 0xc0004d3c, 0                      , 0,
20880        0x0                 },        /* POOL32Sxf_4~*(38) */
20881     { reserved_block      , 0                   , 0   , 32,
20882        0xfc00ffff, 0xc0004f3c, 0                      , 0,
20883        0x0                 },        /* POOL32Sxf_4~*(39) */
20884     { reserved_block      , 0                   , 0   , 32,
20885        0xfc00ffff, 0xc000513c, 0                      , 0,
20886        0x0                 },        /* POOL32Sxf_4~*(40) */
20887     { reserved_block      , 0                   , 0   , 32,
20888        0xfc00ffff, 0xc000533c, 0                      , 0,
20889        0x0                 },        /* POOL32Sxf_4~*(41) */
20890     { reserved_block      , 0                   , 0   , 32,
20891        0xfc00ffff, 0xc000553c, 0                      , 0,
20892        0x0                 },        /* POOL32Sxf_4~*(42) */
20893     { reserved_block      , 0                   , 0   , 32,
20894        0xfc00ffff, 0xc000573c, 0                      , 0,
20895        0x0                 },        /* POOL32Sxf_4~*(43) */
20896     { reserved_block      , 0                   , 0   , 32,
20897        0xfc00ffff, 0xc000593c, 0                      , 0,
20898        0x0                 },        /* POOL32Sxf_4~*(44) */
20899     { instruction         , 0                   , 0   , 32,
20900        0xfc00ffff, 0xc0005b3c, &NMD::DCLZ             , 0,
20901        MIPS64_             },        /* DCLZ */
20902     { reserved_block      , 0                   , 0   , 32,
20903        0xfc00ffff, 0xc0005d3c, 0                      , 0,
20904        0x0                 },        /* POOL32Sxf_4~*(46) */
20905     { reserved_block      , 0                   , 0   , 32,
20906        0xfc00ffff, 0xc0005f3c, 0                      , 0,
20907        0x0                 },        /* POOL32Sxf_4~*(47) */
20908     { reserved_block      , 0                   , 0   , 32,
20909        0xfc00ffff, 0xc000613c, 0                      , 0,
20910        0x0                 },        /* POOL32Sxf_4~*(48) */
20911     { reserved_block      , 0                   , 0   , 32,
20912        0xfc00ffff, 0xc000633c, 0                      , 0,
20913        0x0                 },        /* POOL32Sxf_4~*(49) */
20914     { reserved_block      , 0                   , 0   , 32,
20915        0xfc00ffff, 0xc000653c, 0                      , 0,
20916        0x0                 },        /* POOL32Sxf_4~*(50) */
20917     { reserved_block      , 0                   , 0   , 32,
20918        0xfc00ffff, 0xc000673c, 0                      , 0,
20919        0x0                 },        /* POOL32Sxf_4~*(51) */
20920     { reserved_block      , 0                   , 0   , 32,
20921        0xfc00ffff, 0xc000693c, 0                      , 0,
20922        0x0                 },        /* POOL32Sxf_4~*(52) */
20923     { reserved_block      , 0                   , 0   , 32,
20924        0xfc00ffff, 0xc0006b3c, 0                      , 0,
20925        0x0                 },        /* POOL32Sxf_4~*(53) */
20926     { reserved_block      , 0                   , 0   , 32,
20927        0xfc00ffff, 0xc0006d3c, 0                      , 0,
20928        0x0                 },        /* POOL32Sxf_4~*(54) */
20929     { reserved_block      , 0                   , 0   , 32,
20930        0xfc00ffff, 0xc0006f3c, 0                      , 0,
20931        0x0                 },        /* POOL32Sxf_4~*(55) */
20932     { reserved_block      , 0                   , 0   , 32,
20933        0xfc00ffff, 0xc000713c, 0                      , 0,
20934        0x0                 },        /* POOL32Sxf_4~*(56) */
20935     { reserved_block      , 0                   , 0   , 32,
20936        0xfc00ffff, 0xc000733c, 0                      , 0,
20937        0x0                 },        /* POOL32Sxf_4~*(57) */
20938     { reserved_block      , 0                   , 0   , 32,
20939        0xfc00ffff, 0xc000753c, 0                      , 0,
20940        0x0                 },        /* POOL32Sxf_4~*(58) */
20941     { reserved_block      , 0                   , 0   , 32,
20942        0xfc00ffff, 0xc000773c, 0                      , 0,
20943        0x0                 },        /* POOL32Sxf_4~*(59) */
20944     { reserved_block      , 0                   , 0   , 32,
20945        0xfc00ffff, 0xc000793c, 0                      , 0,
20946        0x0                 },        /* POOL32Sxf_4~*(60) */
20947     { reserved_block      , 0                   , 0   , 32,
20948        0xfc00ffff, 0xc0007b3c, 0                      , 0,
20949        0x0                 },        /* POOL32Sxf_4~*(61) */
20950     { reserved_block      , 0                   , 0   , 32,
20951        0xfc00ffff, 0xc0007d3c, 0                      , 0,
20952        0x0                 },        /* POOL32Sxf_4~*(62) */
20953     { reserved_block      , 0                   , 0   , 32,
20954        0xfc00ffff, 0xc0007f3c, 0                      , 0,
20955        0x0                 },        /* POOL32Sxf_4~*(63) */
20956     { reserved_block      , 0                   , 0   , 32,
20957        0xfc00ffff, 0xc000813c, 0                      , 0,
20958        0x0                 },        /* POOL32Sxf_4~*(64) */
20959     { reserved_block      , 0                   , 0   , 32,
20960        0xfc00ffff, 0xc000833c, 0                      , 0,
20961        0x0                 },        /* POOL32Sxf_4~*(65) */
20962     { reserved_block      , 0                   , 0   , 32,
20963        0xfc00ffff, 0xc000853c, 0                      , 0,
20964        0x0                 },        /* POOL32Sxf_4~*(66) */
20965     { reserved_block      , 0                   , 0   , 32,
20966        0xfc00ffff, 0xc000873c, 0                      , 0,
20967        0x0                 },        /* POOL32Sxf_4~*(67) */
20968     { reserved_block      , 0                   , 0   , 32,
20969        0xfc00ffff, 0xc000893c, 0                      , 0,
20970        0x0                 },        /* POOL32Sxf_4~*(68) */
20971     { reserved_block      , 0                   , 0   , 32,
20972        0xfc00ffff, 0xc0008b3c, 0                      , 0,
20973        0x0                 },        /* POOL32Sxf_4~*(69) */
20974     { reserved_block      , 0                   , 0   , 32,
20975        0xfc00ffff, 0xc0008d3c, 0                      , 0,
20976        0x0                 },        /* POOL32Sxf_4~*(70) */
20977     { reserved_block      , 0                   , 0   , 32,
20978        0xfc00ffff, 0xc0008f3c, 0                      , 0,
20979        0x0                 },        /* POOL32Sxf_4~*(71) */
20980     { reserved_block      , 0                   , 0   , 32,
20981        0xfc00ffff, 0xc000913c, 0                      , 0,
20982        0x0                 },        /* POOL32Sxf_4~*(72) */
20983     { reserved_block      , 0                   , 0   , 32,
20984        0xfc00ffff, 0xc000933c, 0                      , 0,
20985        0x0                 },        /* POOL32Sxf_4~*(73) */
20986     { reserved_block      , 0                   , 0   , 32,
20987        0xfc00ffff, 0xc000953c, 0                      , 0,
20988        0x0                 },        /* POOL32Sxf_4~*(74) */
20989     { reserved_block      , 0                   , 0   , 32,
20990        0xfc00ffff, 0xc000973c, 0                      , 0,
20991        0x0                 },        /* POOL32Sxf_4~*(75) */
20992     { reserved_block      , 0                   , 0   , 32,
20993        0xfc00ffff, 0xc000993c, 0                      , 0,
20994        0x0                 },        /* POOL32Sxf_4~*(76) */
20995     { reserved_block      , 0                   , 0   , 32,
20996        0xfc00ffff, 0xc0009b3c, 0                      , 0,
20997        0x0                 },        /* POOL32Sxf_4~*(77) */
20998     { reserved_block      , 0                   , 0   , 32,
20999        0xfc00ffff, 0xc0009d3c, 0                      , 0,
21000        0x0                 },        /* POOL32Sxf_4~*(78) */
21001     { reserved_block      , 0                   , 0   , 32,
21002        0xfc00ffff, 0xc0009f3c, 0                      , 0,
21003        0x0                 },        /* POOL32Sxf_4~*(79) */
21004     { reserved_block      , 0                   , 0   , 32,
21005        0xfc00ffff, 0xc000a13c, 0                      , 0,
21006        0x0                 },        /* POOL32Sxf_4~*(80) */
21007     { reserved_block      , 0                   , 0   , 32,
21008        0xfc00ffff, 0xc000a33c, 0                      , 0,
21009        0x0                 },        /* POOL32Sxf_4~*(81) */
21010     { reserved_block      , 0                   , 0   , 32,
21011        0xfc00ffff, 0xc000a53c, 0                      , 0,
21012        0x0                 },        /* POOL32Sxf_4~*(82) */
21013     { reserved_block      , 0                   , 0   , 32,
21014        0xfc00ffff, 0xc000a73c, 0                      , 0,
21015        0x0                 },        /* POOL32Sxf_4~*(83) */
21016     { reserved_block      , 0                   , 0   , 32,
21017        0xfc00ffff, 0xc000a93c, 0                      , 0,
21018        0x0                 },        /* POOL32Sxf_4~*(84) */
21019     { reserved_block      , 0                   , 0   , 32,
21020        0xfc00ffff, 0xc000ab3c, 0                      , 0,
21021        0x0                 },        /* POOL32Sxf_4~*(85) */
21022     { reserved_block      , 0                   , 0   , 32,
21023        0xfc00ffff, 0xc000ad3c, 0                      , 0,
21024        0x0                 },        /* POOL32Sxf_4~*(86) */
21025     { reserved_block      , 0                   , 0   , 32,
21026        0xfc00ffff, 0xc000af3c, 0                      , 0,
21027        0x0                 },        /* POOL32Sxf_4~*(87) */
21028     { reserved_block      , 0                   , 0   , 32,
21029        0xfc00ffff, 0xc000b13c, 0                      , 0,
21030        0x0                 },        /* POOL32Sxf_4~*(88) */
21031     { reserved_block      , 0                   , 0   , 32,
21032        0xfc00ffff, 0xc000b33c, 0                      , 0,
21033        0x0                 },        /* POOL32Sxf_4~*(89) */
21034     { reserved_block      , 0                   , 0   , 32,
21035        0xfc00ffff, 0xc000b53c, 0                      , 0,
21036        0x0                 },        /* POOL32Sxf_4~*(90) */
21037     { reserved_block      , 0                   , 0   , 32,
21038        0xfc00ffff, 0xc000b73c, 0                      , 0,
21039        0x0                 },        /* POOL32Sxf_4~*(91) */
21040     { reserved_block      , 0                   , 0   , 32,
21041        0xfc00ffff, 0xc000b93c, 0                      , 0,
21042        0x0                 },        /* POOL32Sxf_4~*(92) */
21043     { reserved_block      , 0                   , 0   , 32,
21044        0xfc00ffff, 0xc000bb3c, 0                      , 0,
21045        0x0                 },        /* POOL32Sxf_4~*(93) */
21046     { reserved_block      , 0                   , 0   , 32,
21047        0xfc00ffff, 0xc000bd3c, 0                      , 0,
21048        0x0                 },        /* POOL32Sxf_4~*(94) */
21049     { reserved_block      , 0                   , 0   , 32,
21050        0xfc00ffff, 0xc000bf3c, 0                      , 0,
21051        0x0                 },        /* POOL32Sxf_4~*(95) */
21052     { reserved_block      , 0                   , 0   , 32,
21053        0xfc00ffff, 0xc000c13c, 0                      , 0,
21054        0x0                 },        /* POOL32Sxf_4~*(96) */
21055     { reserved_block      , 0                   , 0   , 32,
21056        0xfc00ffff, 0xc000c33c, 0                      , 0,
21057        0x0                 },        /* POOL32Sxf_4~*(97) */
21058     { reserved_block      , 0                   , 0   , 32,
21059        0xfc00ffff, 0xc000c53c, 0                      , 0,
21060        0x0                 },        /* POOL32Sxf_4~*(98) */
21061     { reserved_block      , 0                   , 0   , 32,
21062        0xfc00ffff, 0xc000c73c, 0                      , 0,
21063        0x0                 },        /* POOL32Sxf_4~*(99) */
21064     { reserved_block      , 0                   , 0   , 32,
21065        0xfc00ffff, 0xc000c93c, 0                      , 0,
21066        0x0                 },        /* POOL32Sxf_4~*(100) */
21067     { reserved_block      , 0                   , 0   , 32,
21068        0xfc00ffff, 0xc000cb3c, 0                      , 0,
21069        0x0                 },        /* POOL32Sxf_4~*(101) */
21070     { reserved_block      , 0                   , 0   , 32,
21071        0xfc00ffff, 0xc000cd3c, 0                      , 0,
21072        0x0                 },        /* POOL32Sxf_4~*(102) */
21073     { reserved_block      , 0                   , 0   , 32,
21074        0xfc00ffff, 0xc000cf3c, 0                      , 0,
21075        0x0                 },        /* POOL32Sxf_4~*(103) */
21076     { reserved_block      , 0                   , 0   , 32,
21077        0xfc00ffff, 0xc000d13c, 0                      , 0,
21078        0x0                 },        /* POOL32Sxf_4~*(104) */
21079     { reserved_block      , 0                   , 0   , 32,
21080        0xfc00ffff, 0xc000d33c, 0                      , 0,
21081        0x0                 },        /* POOL32Sxf_4~*(105) */
21082     { reserved_block      , 0                   , 0   , 32,
21083        0xfc00ffff, 0xc000d53c, 0                      , 0,
21084        0x0                 },        /* POOL32Sxf_4~*(106) */
21085     { reserved_block      , 0                   , 0   , 32,
21086        0xfc00ffff, 0xc000d73c, 0                      , 0,
21087        0x0                 },        /* POOL32Sxf_4~*(107) */
21088     { reserved_block      , 0                   , 0   , 32,
21089        0xfc00ffff, 0xc000d93c, 0                      , 0,
21090        0x0                 },        /* POOL32Sxf_4~*(108) */
21091     { reserved_block      , 0                   , 0   , 32,
21092        0xfc00ffff, 0xc000db3c, 0                      , 0,
21093        0x0                 },        /* POOL32Sxf_4~*(109) */
21094     { reserved_block      , 0                   , 0   , 32,
21095        0xfc00ffff, 0xc000dd3c, 0                      , 0,
21096        0x0                 },        /* POOL32Sxf_4~*(110) */
21097     { reserved_block      , 0                   , 0   , 32,
21098        0xfc00ffff, 0xc000df3c, 0                      , 0,
21099        0x0                 },        /* POOL32Sxf_4~*(111) */
21100     { reserved_block      , 0                   , 0   , 32,
21101        0xfc00ffff, 0xc000e13c, 0                      , 0,
21102        0x0                 },        /* POOL32Sxf_4~*(112) */
21103     { reserved_block      , 0                   , 0   , 32,
21104        0xfc00ffff, 0xc000e33c, 0                      , 0,
21105        0x0                 },        /* POOL32Sxf_4~*(113) */
21106     { reserved_block      , 0                   , 0   , 32,
21107        0xfc00ffff, 0xc000e53c, 0                      , 0,
21108        0x0                 },        /* POOL32Sxf_4~*(114) */
21109     { reserved_block      , 0                   , 0   , 32,
21110        0xfc00ffff, 0xc000e73c, 0                      , 0,
21111        0x0                 },        /* POOL32Sxf_4~*(115) */
21112     { reserved_block      , 0                   , 0   , 32,
21113        0xfc00ffff, 0xc000e93c, 0                      , 0,
21114        0x0                 },        /* POOL32Sxf_4~*(116) */
21115     { reserved_block      , 0                   , 0   , 32,
21116        0xfc00ffff, 0xc000eb3c, 0                      , 0,
21117        0x0                 },        /* POOL32Sxf_4~*(117) */
21118     { reserved_block      , 0                   , 0   , 32,
21119        0xfc00ffff, 0xc000ed3c, 0                      , 0,
21120        0x0                 },        /* POOL32Sxf_4~*(118) */
21121     { reserved_block      , 0                   , 0   , 32,
21122        0xfc00ffff, 0xc000ef3c, 0                      , 0,
21123        0x0                 },        /* POOL32Sxf_4~*(119) */
21124     { reserved_block      , 0                   , 0   , 32,
21125        0xfc00ffff, 0xc000f13c, 0                      , 0,
21126        0x0                 },        /* POOL32Sxf_4~*(120) */
21127     { reserved_block      , 0                   , 0   , 32,
21128        0xfc00ffff, 0xc000f33c, 0                      , 0,
21129        0x0                 },        /* POOL32Sxf_4~*(121) */
21130     { reserved_block      , 0                   , 0   , 32,
21131        0xfc00ffff, 0xc000f53c, 0                      , 0,
21132        0x0                 },        /* POOL32Sxf_4~*(122) */
21133     { reserved_block      , 0                   , 0   , 32,
21134        0xfc00ffff, 0xc000f73c, 0                      , 0,
21135        0x0                 },        /* POOL32Sxf_4~*(123) */
21136     { reserved_block      , 0                   , 0   , 32,
21137        0xfc00ffff, 0xc000f93c, 0                      , 0,
21138        0x0                 },        /* POOL32Sxf_4~*(124) */
21139     { reserved_block      , 0                   , 0   , 32,
21140        0xfc00ffff, 0xc000fb3c, 0                      , 0,
21141        0x0                 },        /* POOL32Sxf_4~*(125) */
21142     { reserved_block      , 0                   , 0   , 32,
21143        0xfc00ffff, 0xc000fd3c, 0                      , 0,
21144        0x0                 },        /* POOL32Sxf_4~*(126) */
21145     { reserved_block      , 0                   , 0   , 32,
21146        0xfc00ffff, 0xc000ff3c, 0                      , 0,
21147        0x0                 },        /* POOL32Sxf_4~*(127) */
21148 };
21149
21150
21151 NMD::Pool NMD::POOL32Sxf[8] = {
21152     { reserved_block      , 0                   , 0   , 32,
21153        0xfc0001ff, 0xc000003c, 0                      , 0,
21154        0x0                 },        /* POOL32Sxf~*(0) */
21155     { reserved_block      , 0                   , 0   , 32,
21156        0xfc0001ff, 0xc000007c, 0                      , 0,
21157        0x0                 },        /* POOL32Sxf~*(1) */
21158     { reserved_block      , 0                   , 0   , 32,
21159        0xfc0001ff, 0xc00000bc, 0                      , 0,
21160        0x0                 },        /* POOL32Sxf~*(2) */
21161     { reserved_block      , 0                   , 0   , 32,
21162        0xfc0001ff, 0xc00000fc, 0                      , 0,
21163        0x0                 },        /* POOL32Sxf~*(3) */
21164     { pool                , POOL32Sxf_4         , 128 , 32,
21165        0xfc0001ff, 0xc000013c, 0                      , 0,
21166        0x0                 },        /* POOL32Sxf_4 */
21167     { reserved_block      , 0                   , 0   , 32,
21168        0xfc0001ff, 0xc000017c, 0                      , 0,
21169        0x0                 },        /* POOL32Sxf~*(5) */
21170     { reserved_block      , 0                   , 0   , 32,
21171        0xfc0001ff, 0xc00001bc, 0                      , 0,
21172        0x0                 },        /* POOL32Sxf~*(6) */
21173     { reserved_block      , 0                   , 0   , 32,
21174        0xfc0001ff, 0xc00001fc, 0                      , 0,
21175        0x0                 },        /* POOL32Sxf~*(7) */
21176 };
21177
21178
21179 NMD::Pool NMD::POOL32S_4[8] = {
21180     { instruction         , 0                   , 0   , 32,
21181        0xfc00003f, 0xc0000004, &NMD::EXTD             , 0,
21182        MIPS64_             },        /* EXTD */
21183     { instruction         , 0                   , 0   , 32,
21184        0xfc00003f, 0xc000000c, &NMD::EXTD32           , 0,
21185        MIPS64_             },        /* EXTD32 */
21186     { reserved_block      , 0                   , 0   , 32,
21187        0xfc00003f, 0xc0000014, 0                      , 0,
21188        0x0                 },        /* POOL32S_4~*(2) */
21189     { reserved_block      , 0                   , 0   , 32,
21190        0xfc00003f, 0xc000001c, 0                      , 0,
21191        0x0                 },        /* POOL32S_4~*(3) */
21192     { reserved_block      , 0                   , 0   , 32,
21193        0xfc00003f, 0xc0000024, 0                      , 0,
21194        0x0                 },        /* POOL32S_4~*(4) */
21195     { reserved_block      , 0                   , 0   , 32,
21196        0xfc00003f, 0xc000002c, 0                      , 0,
21197        0x0                 },        /* POOL32S_4~*(5) */
21198     { reserved_block      , 0                   , 0   , 32,
21199        0xfc00003f, 0xc0000034, 0                      , 0,
21200        0x0                 },        /* POOL32S_4~*(6) */
21201     { pool                , POOL32Sxf           , 8   , 32,
21202        0xfc00003f, 0xc000003c, 0                      , 0,
21203        0x0                 },        /* POOL32Sxf */
21204 };
21205
21206
21207 NMD::Pool NMD::POOL32S[8] = {
21208     { pool                , POOL32S_0           , 64  , 32,
21209        0xfc000007, 0xc0000000, 0                      , 0,
21210        0x0                 },        /* POOL32S_0 */
21211     { reserved_block      , 0                   , 0   , 32,
21212        0xfc000007, 0xc0000001, 0                      , 0,
21213        0x0                 },        /* POOL32S~*(1) */
21214     { reserved_block      , 0                   , 0   , 32,
21215        0xfc000007, 0xc0000002, 0                      , 0,
21216        0x0                 },        /* POOL32S~*(2) */
21217     { reserved_block      , 0                   , 0   , 32,
21218        0xfc000007, 0xc0000003, 0                      , 0,
21219        0x0                 },        /* POOL32S~*(3) */
21220     { pool                , POOL32S_4           , 8   , 32,
21221        0xfc000007, 0xc0000004, 0                      , 0,
21222        0x0                 },        /* POOL32S_4 */
21223     { reserved_block      , 0                   , 0   , 32,
21224        0xfc000007, 0xc0000005, 0                      , 0,
21225        0x0                 },        /* POOL32S~*(5) */
21226     { reserved_block      , 0                   , 0   , 32,
21227        0xfc000007, 0xc0000006, 0                      , 0,
21228        0x0                 },        /* POOL32S~*(6) */
21229     { reserved_block      , 0                   , 0   , 32,
21230        0xfc000007, 0xc0000007, 0                      , 0,
21231        0x0                 },        /* POOL32S~*(7) */
21232 };
21233
21234
21235 NMD::Pool NMD::P_LUI[2] = {
21236     { instruction         , 0                   , 0   , 32,
21237        0xfc000002, 0xe0000000, &NMD::LUI              , 0,
21238        0x0                 },        /* LUI */
21239     { instruction         , 0                   , 0   , 32,
21240        0xfc000002, 0xe0000002, &NMD::ALUIPC           , 0,
21241        0x0                 },        /* ALUIPC */
21242 };
21243
21244
21245 NMD::Pool NMD::P_GP_LH[2] = {
21246     { instruction         , 0                   , 0   , 32,
21247        0xfc1c0001, 0x44100000, &NMD::LH_GP_           , 0,
21248        0x0                 },        /* LH[GP] */
21249     { instruction         , 0                   , 0   , 32,
21250        0xfc1c0001, 0x44100001, &NMD::LHU_GP_          , 0,
21251        0x0                 },        /* LHU[GP] */
21252 };
21253
21254
21255 NMD::Pool NMD::P_GP_SH[2] = {
21256     { instruction         , 0                   , 0   , 32,
21257        0xfc1c0001, 0x44140000, &NMD::SH_GP_           , 0,
21258        0x0                 },        /* SH[GP] */
21259     { reserved_block      , 0                   , 0   , 32,
21260        0xfc1c0001, 0x44140001, 0                      , 0,
21261        0x0                 },        /* P.GP.SH~*(1) */
21262 };
21263
21264
21265 NMD::Pool NMD::P_GP_CP1[4] = {
21266     { instruction         , 0                   , 0   , 32,
21267        0xfc1c0003, 0x44180000, &NMD::LWC1_GP_         , 0,
21268        CP1_                },        /* LWC1[GP] */
21269     { instruction         , 0                   , 0   , 32,
21270        0xfc1c0003, 0x44180001, &NMD::SWC1_GP_         , 0,
21271        CP1_                },        /* SWC1[GP] */
21272     { instruction         , 0                   , 0   , 32,
21273        0xfc1c0003, 0x44180002, &NMD::LDC1_GP_         , 0,
21274        CP1_                },        /* LDC1[GP] */
21275     { instruction         , 0                   , 0   , 32,
21276        0xfc1c0003, 0x44180003, &NMD::SDC1_GP_         , 0,
21277        CP1_                },        /* SDC1[GP] */
21278 };
21279
21280
21281 NMD::Pool NMD::P_GP_M64[4] = {
21282     { instruction         , 0                   , 0   , 32,
21283        0xfc1c0003, 0x441c0000, &NMD::LWU_GP_          , 0,
21284        MIPS64_             },        /* LWU[GP] */
21285     { reserved_block      , 0                   , 0   , 32,
21286        0xfc1c0003, 0x441c0001, 0                      , 0,
21287        0x0                 },        /* P.GP.M64~*(1) */
21288     { reserved_block      , 0                   , 0   , 32,
21289        0xfc1c0003, 0x441c0002, 0                      , 0,
21290        0x0                 },        /* P.GP.M64~*(2) */
21291     { reserved_block      , 0                   , 0   , 32,
21292        0xfc1c0003, 0x441c0003, 0                      , 0,
21293        0x0                 },        /* P.GP.M64~*(3) */
21294 };
21295
21296
21297 NMD::Pool NMD::P_GP_BH[8] = {
21298     { instruction         , 0                   , 0   , 32,
21299        0xfc1c0000, 0x44000000, &NMD::LB_GP_           , 0,
21300        0x0                 },        /* LB[GP] */
21301     { instruction         , 0                   , 0   , 32,
21302        0xfc1c0000, 0x44040000, &NMD::SB_GP_           , 0,
21303        0x0                 },        /* SB[GP] */
21304     { instruction         , 0                   , 0   , 32,
21305        0xfc1c0000, 0x44080000, &NMD::LBU_GP_          , 0,
21306        0x0                 },        /* LBU[GP] */
21307     { instruction         , 0                   , 0   , 32,
21308        0xfc1c0000, 0x440c0000, &NMD::ADDIU_GP_B_      , 0,
21309        0x0                 },        /* ADDIU[GP.B] */
21310     { pool                , P_GP_LH             , 2   , 32,
21311        0xfc1c0000, 0x44100000, 0                      , 0,
21312        0x0                 },        /* P.GP.LH */
21313     { pool                , P_GP_SH             , 2   , 32,
21314        0xfc1c0000, 0x44140000, 0                      , 0,
21315        0x0                 },        /* P.GP.SH */
21316     { pool                , P_GP_CP1            , 4   , 32,
21317        0xfc1c0000, 0x44180000, 0                      , 0,
21318        0x0                 },        /* P.GP.CP1 */
21319     { pool                , P_GP_M64            , 4   , 32,
21320        0xfc1c0000, 0x441c0000, 0                      , 0,
21321        0x0                 },        /* P.GP.M64 */
21322 };
21323
21324
21325 NMD::Pool NMD::P_LS_U12[16] = {
21326     { instruction         , 0                   , 0   , 32,
21327        0xfc00f000, 0x84000000, &NMD::LB_U12_          , 0,
21328        0x0                 },        /* LB[U12] */
21329     { instruction         , 0                   , 0   , 32,
21330        0xfc00f000, 0x84001000, &NMD::SB_U12_          , 0,
21331        0x0                 },        /* SB[U12] */
21332     { instruction         , 0                   , 0   , 32,
21333        0xfc00f000, 0x84002000, &NMD::LBU_U12_         , 0,
21334        0x0                 },        /* LBU[U12] */
21335     { instruction         , 0                   , 0   , 32,
21336        0xfc00f000, 0x84003000, &NMD::PREF_U12_        , 0,
21337        0x0                 },        /* PREF[U12] */
21338     { instruction         , 0                   , 0   , 32,
21339        0xfc00f000, 0x84004000, &NMD::LH_U12_          , 0,
21340        0x0                 },        /* LH[U12] */
21341     { instruction         , 0                   , 0   , 32,
21342        0xfc00f000, 0x84005000, &NMD::SH_U12_          , 0,
21343        0x0                 },        /* SH[U12] */
21344     { instruction         , 0                   , 0   , 32,
21345        0xfc00f000, 0x84006000, &NMD::LHU_U12_         , 0,
21346        0x0                 },        /* LHU[U12] */
21347     { instruction         , 0                   , 0   , 32,
21348        0xfc00f000, 0x84007000, &NMD::LWU_U12_         , 0,
21349        MIPS64_             },        /* LWU[U12] */
21350     { instruction         , 0                   , 0   , 32,
21351        0xfc00f000, 0x84008000, &NMD::LW_U12_          , 0,
21352        0x0                 },        /* LW[U12] */
21353     { instruction         , 0                   , 0   , 32,
21354        0xfc00f000, 0x84009000, &NMD::SW_U12_          , 0,
21355        0x0                 },        /* SW[U12] */
21356     { instruction         , 0                   , 0   , 32,
21357        0xfc00f000, 0x8400a000, &NMD::LWC1_U12_        , 0,
21358        CP1_                },        /* LWC1[U12] */
21359     { instruction         , 0                   , 0   , 32,
21360        0xfc00f000, 0x8400b000, &NMD::SWC1_U12_        , 0,
21361        CP1_                },        /* SWC1[U12] */
21362     { instruction         , 0                   , 0   , 32,
21363        0xfc00f000, 0x8400c000, &NMD::LD_U12_          , 0,
21364        MIPS64_             },        /* LD[U12] */
21365     { instruction         , 0                   , 0   , 32,
21366        0xfc00f000, 0x8400d000, &NMD::SD_U12_          , 0,
21367        MIPS64_             },        /* SD[U12] */
21368     { instruction         , 0                   , 0   , 32,
21369        0xfc00f000, 0x8400e000, &NMD::LDC1_U12_        , 0,
21370        CP1_                },        /* LDC1[U12] */
21371     { instruction         , 0                   , 0   , 32,
21372        0xfc00f000, 0x8400f000, &NMD::SDC1_U12_        , 0,
21373        CP1_                },        /* SDC1[U12] */
21374 };
21375
21376
21377 NMD::Pool NMD::P_PREF_S9_[2] = {
21378     { instruction         , 0                   , 0   , 32,
21379        0xffe07f00, 0xa7e01800, &NMD::SYNCI            , 0,
21380        0x0                 },        /* SYNCI */
21381     { instruction         , 0                   , 0   , 32,
21382        0xfc007f00, 0xa4001800, &NMD::PREF_S9_         , &NMD::PREF_S9__cond    ,
21383        0x0                 },        /* PREF[S9] */
21384 };
21385
21386
21387 NMD::Pool NMD::P_LS_S0[16] = {
21388     { instruction         , 0                   , 0   , 32,
21389        0xfc007f00, 0xa4000000, &NMD::LB_S9_           , 0,
21390        0x0                 },        /* LB[S9] */
21391     { instruction         , 0                   , 0   , 32,
21392        0xfc007f00, 0xa4000800, &NMD::SB_S9_           , 0,
21393        0x0                 },        /* SB[S9] */
21394     { instruction         , 0                   , 0   , 32,
21395        0xfc007f00, 0xa4001000, &NMD::LBU_S9_          , 0,
21396        0x0                 },        /* LBU[S9] */
21397     { pool                , P_PREF_S9_          , 2   , 32,
21398        0xfc007f00, 0xa4001800, 0                      , 0,
21399        0x0                 },        /* P.PREF[S9] */
21400     { instruction         , 0                   , 0   , 32,
21401        0xfc007f00, 0xa4002000, &NMD::LH_S9_           , 0,
21402        0x0                 },        /* LH[S9] */
21403     { instruction         , 0                   , 0   , 32,
21404        0xfc007f00, 0xa4002800, &NMD::SH_S9_           , 0,
21405        0x0                 },        /* SH[S9] */
21406     { instruction         , 0                   , 0   , 32,
21407        0xfc007f00, 0xa4003000, &NMD::LHU_S9_          , 0,
21408        0x0                 },        /* LHU[S9] */
21409     { instruction         , 0                   , 0   , 32,
21410        0xfc007f00, 0xa4003800, &NMD::LWU_S9_          , 0,
21411        MIPS64_             },        /* LWU[S9] */
21412     { instruction         , 0                   , 0   , 32,
21413        0xfc007f00, 0xa4004000, &NMD::LW_S9_           , 0,
21414        0x0                 },        /* LW[S9] */
21415     { instruction         , 0                   , 0   , 32,
21416        0xfc007f00, 0xa4004800, &NMD::SW_S9_           , 0,
21417        0x0                 },        /* SW[S9] */
21418     { instruction         , 0                   , 0   , 32,
21419        0xfc007f00, 0xa4005000, &NMD::LWC1_S9_         , 0,
21420        CP1_                },        /* LWC1[S9] */
21421     { instruction         , 0                   , 0   , 32,
21422        0xfc007f00, 0xa4005800, &NMD::SWC1_S9_         , 0,
21423        CP1_                },        /* SWC1[S9] */
21424     { instruction         , 0                   , 0   , 32,
21425        0xfc007f00, 0xa4006000, &NMD::LD_S9_           , 0,
21426        MIPS64_             },        /* LD[S9] */
21427     { instruction         , 0                   , 0   , 32,
21428        0xfc007f00, 0xa4006800, &NMD::SD_S9_           , 0,
21429        MIPS64_             },        /* SD[S9] */
21430     { instruction         , 0                   , 0   , 32,
21431        0xfc007f00, 0xa4007000, &NMD::LDC1_S9_         , 0,
21432        CP1_                },        /* LDC1[S9] */
21433     { instruction         , 0                   , 0   , 32,
21434        0xfc007f00, 0xa4007800, &NMD::SDC1_S9_         , 0,
21435        CP1_                },        /* SDC1[S9] */
21436 };
21437
21438
21439 NMD::Pool NMD::ASET_ACLR[2] = {
21440     { instruction         , 0                   , 0   , 32,
21441        0xfe007f00, 0xa4001100, &NMD::ASET             , 0,
21442        MCU_                },        /* ASET */
21443     { instruction         , 0                   , 0   , 32,
21444        0xfe007f00, 0xa6001100, &NMD::ACLR             , 0,
21445        MCU_                },        /* ACLR */
21446 };
21447
21448
21449 NMD::Pool NMD::P_LL[4] = {
21450     { instruction         , 0                   , 0   , 32,
21451        0xfc007f03, 0xa4005100, &NMD::LL               , 0,
21452        0x0                 },        /* LL */
21453     { instruction         , 0                   , 0   , 32,
21454        0xfc007f03, 0xa4005101, &NMD::LLWP             , 0,
21455        XNP_                },        /* LLWP */
21456     { reserved_block      , 0                   , 0   , 32,
21457        0xfc007f03, 0xa4005102, 0                      , 0,
21458        0x0                 },        /* P.LL~*(2) */
21459     { reserved_block      , 0                   , 0   , 32,
21460        0xfc007f03, 0xa4005103, 0                      , 0,
21461        0x0                 },        /* P.LL~*(3) */
21462 };
21463
21464
21465 NMD::Pool NMD::P_SC[4] = {
21466     { instruction         , 0                   , 0   , 32,
21467        0xfc007f03, 0xa4005900, &NMD::SC               , 0,
21468        0x0                 },        /* SC */
21469     { instruction         , 0                   , 0   , 32,
21470        0xfc007f03, 0xa4005901, &NMD::SCWP             , 0,
21471        XNP_                },        /* SCWP */
21472     { reserved_block      , 0                   , 0   , 32,
21473        0xfc007f03, 0xa4005902, 0                      , 0,
21474        0x0                 },        /* P.SC~*(2) */
21475     { reserved_block      , 0                   , 0   , 32,
21476        0xfc007f03, 0xa4005903, 0                      , 0,
21477        0x0                 },        /* P.SC~*(3) */
21478 };
21479
21480
21481 NMD::Pool NMD::P_LLD[8] = {
21482     { instruction         , 0                   , 0   , 32,
21483        0xfc007f07, 0xa4007100, &NMD::LLD              , 0,
21484        MIPS64_             },        /* LLD */
21485     { instruction         , 0                   , 0   , 32,
21486        0xfc007f07, 0xa4007101, &NMD::LLDP             , 0,
21487        MIPS64_             },        /* LLDP */
21488     { reserved_block      , 0                   , 0   , 32,
21489        0xfc007f07, 0xa4007102, 0                      , 0,
21490        0x0                 },        /* P.LLD~*(2) */
21491     { reserved_block      , 0                   , 0   , 32,
21492        0xfc007f07, 0xa4007103, 0                      , 0,
21493        0x0                 },        /* P.LLD~*(3) */
21494     { reserved_block      , 0                   , 0   , 32,
21495        0xfc007f07, 0xa4007104, 0                      , 0,
21496        0x0                 },        /* P.LLD~*(4) */
21497     { reserved_block      , 0                   , 0   , 32,
21498        0xfc007f07, 0xa4007105, 0                      , 0,
21499        0x0                 },        /* P.LLD~*(5) */
21500     { reserved_block      , 0                   , 0   , 32,
21501        0xfc007f07, 0xa4007106, 0                      , 0,
21502        0x0                 },        /* P.LLD~*(6) */
21503     { reserved_block      , 0                   , 0   , 32,
21504        0xfc007f07, 0xa4007107, 0                      , 0,
21505        0x0                 },        /* P.LLD~*(7) */
21506 };
21507
21508
21509 NMD::Pool NMD::P_SCD[8] = {
21510     { instruction         , 0                   , 0   , 32,
21511        0xfc007f07, 0xa4007900, &NMD::SCD              , 0,
21512        MIPS64_             },        /* SCD */
21513     { instruction         , 0                   , 0   , 32,
21514        0xfc007f07, 0xa4007901, &NMD::SCDP             , 0,
21515        MIPS64_             },        /* SCDP */
21516     { reserved_block      , 0                   , 0   , 32,
21517        0xfc007f07, 0xa4007902, 0                      , 0,
21518        0x0                 },        /* P.SCD~*(2) */
21519     { reserved_block      , 0                   , 0   , 32,
21520        0xfc007f07, 0xa4007903, 0                      , 0,
21521        0x0                 },        /* P.SCD~*(3) */
21522     { reserved_block      , 0                   , 0   , 32,
21523        0xfc007f07, 0xa4007904, 0                      , 0,
21524        0x0                 },        /* P.SCD~*(4) */
21525     { reserved_block      , 0                   , 0   , 32,
21526        0xfc007f07, 0xa4007905, 0                      , 0,
21527        0x0                 },        /* P.SCD~*(5) */
21528     { reserved_block      , 0                   , 0   , 32,
21529        0xfc007f07, 0xa4007906, 0                      , 0,
21530        0x0                 },        /* P.SCD~*(6) */
21531     { reserved_block      , 0                   , 0   , 32,
21532        0xfc007f07, 0xa4007907, 0                      , 0,
21533        0x0                 },        /* P.SCD~*(7) */
21534 };
21535
21536
21537 NMD::Pool NMD::P_LS_S1[16] = {
21538     { reserved_block      , 0                   , 0   , 32,
21539        0xfc007f00, 0xa4000100, 0                      , 0,
21540        0x0                 },        /* P.LS.S1~*(0) */
21541     { reserved_block      , 0                   , 0   , 32,
21542        0xfc007f00, 0xa4000900, 0                      , 0,
21543        0x0                 },        /* P.LS.S1~*(1) */
21544     { pool                , ASET_ACLR           , 2   , 32,
21545        0xfc007f00, 0xa4001100, 0                      , 0,
21546        0x0                 },        /* ASET_ACLR */
21547     { reserved_block      , 0                   , 0   , 32,
21548        0xfc007f00, 0xa4001900, 0                      , 0,
21549        0x0                 },        /* P.LS.S1~*(3) */
21550     { instruction         , 0                   , 0   , 32,
21551        0xfc007f00, 0xa4002100, &NMD::UALH             , 0,
21552        XMMS_               },        /* UALH */
21553     { instruction         , 0                   , 0   , 32,
21554        0xfc007f00, 0xa4002900, &NMD::UASH             , 0,
21555        XMMS_               },        /* UASH */
21556     { reserved_block      , 0                   , 0   , 32,
21557        0xfc007f00, 0xa4003100, 0                      , 0,
21558        0x0                 },        /* P.LS.S1~*(6) */
21559     { instruction         , 0                   , 0   , 32,
21560        0xfc007f00, 0xa4003900, &NMD::CACHE            , 0,
21561        CP0_                },        /* CACHE */
21562     { instruction         , 0                   , 0   , 32,
21563        0xfc007f00, 0xa4004100, &NMD::LWC2             , 0,
21564        CP2_                },        /* LWC2 */
21565     { instruction         , 0                   , 0   , 32,
21566        0xfc007f00, 0xa4004900, &NMD::SWC2             , 0,
21567        CP2_                },        /* SWC2 */
21568     { pool                , P_LL                , 4   , 32,
21569        0xfc007f00, 0xa4005100, 0                      , 0,
21570        0x0                 },        /* P.LL */
21571     { pool                , P_SC                , 4   , 32,
21572        0xfc007f00, 0xa4005900, 0                      , 0,
21573        0x0                 },        /* P.SC */
21574     { instruction         , 0                   , 0   , 32,
21575        0xfc007f00, 0xa4006100, &NMD::LDC2             , 0,
21576        CP2_                },        /* LDC2 */
21577     { instruction         , 0                   , 0   , 32,
21578        0xfc007f00, 0xa4006900, &NMD::SDC2             , 0,
21579        CP2_                },        /* SDC2 */
21580     { pool                , P_LLD               , 8   , 32,
21581        0xfc007f00, 0xa4007100, 0                      , 0,
21582        0x0                 },        /* P.LLD */
21583     { pool                , P_SCD               , 8   , 32,
21584        0xfc007f00, 0xa4007900, 0                      , 0,
21585        0x0                 },        /* P.SCD */
21586 };
21587
21588
21589 NMD::Pool NMD::P_PREFE[2] = {
21590     { instruction         , 0                   , 0   , 32,
21591        0xffe07f00, 0xa7e01a00, &NMD::SYNCIE           , 0,
21592        CP0_ | EVA_         },        /* SYNCIE */
21593     { instruction         , 0                   , 0   , 32,
21594        0xfc007f00, 0xa4001a00, &NMD::PREFE            , &NMD::PREFE_cond       ,
21595        CP0_ | EVA_         },        /* PREFE */
21596 };
21597
21598
21599 NMD::Pool NMD::P_LLE[4] = {
21600     { instruction         , 0                   , 0   , 32,
21601        0xfc007f03, 0xa4005200, &NMD::LLE              , 0,
21602        CP0_ | EVA_         },        /* LLE */
21603     { instruction         , 0                   , 0   , 32,
21604        0xfc007f03, 0xa4005201, &NMD::LLWPE            , 0,
21605        CP0_ | EVA_         },        /* LLWPE */
21606     { reserved_block      , 0                   , 0   , 32,
21607        0xfc007f03, 0xa4005202, 0                      , 0,
21608        0x0                 },        /* P.LLE~*(2) */
21609     { reserved_block      , 0                   , 0   , 32,
21610        0xfc007f03, 0xa4005203, 0                      , 0,
21611        0x0                 },        /* P.LLE~*(3) */
21612 };
21613
21614
21615 NMD::Pool NMD::P_SCE[4] = {
21616     { instruction         , 0                   , 0   , 32,
21617        0xfc007f03, 0xa4005a00, &NMD::SCE              , 0,
21618        CP0_ | EVA_         },        /* SCE */
21619     { instruction         , 0                   , 0   , 32,
21620        0xfc007f03, 0xa4005a01, &NMD::SCWPE            , 0,
21621        CP0_ | EVA_         },        /* SCWPE */
21622     { reserved_block      , 0                   , 0   , 32,
21623        0xfc007f03, 0xa4005a02, 0                      , 0,
21624        0x0                 },        /* P.SCE~*(2) */
21625     { reserved_block      , 0                   , 0   , 32,
21626        0xfc007f03, 0xa4005a03, 0                      , 0,
21627        0x0                 },        /* P.SCE~*(3) */
21628 };
21629
21630
21631 NMD::Pool NMD::P_LS_E0[16] = {
21632     { instruction         , 0                   , 0   , 32,
21633        0xfc007f00, 0xa4000200, &NMD::LBE              , 0,
21634        CP0_ | EVA_         },        /* LBE */
21635     { instruction         , 0                   , 0   , 32,
21636        0xfc007f00, 0xa4000a00, &NMD::SBE              , 0,
21637        CP0_ | EVA_         },        /* SBE */
21638     { instruction         , 0                   , 0   , 32,
21639        0xfc007f00, 0xa4001200, &NMD::LBUE             , 0,
21640        CP0_ | EVA_         },        /* LBUE */
21641     { pool                , P_PREFE             , 2   , 32,
21642        0xfc007f00, 0xa4001a00, 0                      , 0,
21643        0x0                 },        /* P.PREFE */
21644     { instruction         , 0                   , 0   , 32,
21645        0xfc007f00, 0xa4002200, &NMD::LHE              , 0,
21646        CP0_ | EVA_         },        /* LHE */
21647     { instruction         , 0                   , 0   , 32,
21648        0xfc007f00, 0xa4002a00, &NMD::SHE              , 0,
21649        CP0_ | EVA_         },        /* SHE */
21650     { instruction         , 0                   , 0   , 32,
21651        0xfc007f00, 0xa4003200, &NMD::LHUE             , 0,
21652        CP0_ | EVA_         },        /* LHUE */
21653     { instruction         , 0                   , 0   , 32,
21654        0xfc007f00, 0xa4003a00, &NMD::CACHEE           , 0,
21655        CP0_ | EVA_         },        /* CACHEE */
21656     { instruction         , 0                   , 0   , 32,
21657        0xfc007f00, 0xa4004200, &NMD::LWE              , 0,
21658        CP0_ | EVA_         },        /* LWE */
21659     { instruction         , 0                   , 0   , 32,
21660        0xfc007f00, 0xa4004a00, &NMD::SWE              , 0,
21661        CP0_ | EVA_         },        /* SWE */
21662     { pool                , P_LLE               , 4   , 32,
21663        0xfc007f00, 0xa4005200, 0                      , 0,
21664        0x0                 },        /* P.LLE */
21665     { pool                , P_SCE               , 4   , 32,
21666        0xfc007f00, 0xa4005a00, 0                      , 0,
21667        0x0                 },        /* P.SCE */
21668     { reserved_block      , 0                   , 0   , 32,
21669        0xfc007f00, 0xa4006200, 0                      , 0,
21670        0x0                 },        /* P.LS.E0~*(12) */
21671     { reserved_block      , 0                   , 0   , 32,
21672        0xfc007f00, 0xa4006a00, 0                      , 0,
21673        0x0                 },        /* P.LS.E0~*(13) */
21674     { reserved_block      , 0                   , 0   , 32,
21675        0xfc007f00, 0xa4007200, 0                      , 0,
21676        0x0                 },        /* P.LS.E0~*(14) */
21677     { reserved_block      , 0                   , 0   , 32,
21678        0xfc007f00, 0xa4007a00, 0                      , 0,
21679        0x0                 },        /* P.LS.E0~*(15) */
21680 };
21681
21682
21683 NMD::Pool NMD::P_LS_WM[2] = {
21684     { instruction         , 0                   , 0   , 32,
21685        0xfc000f00, 0xa4000400, &NMD::LWM              , 0,
21686        XMMS_               },        /* LWM */
21687     { instruction         , 0                   , 0   , 32,
21688        0xfc000f00, 0xa4000c00, &NMD::SWM              , 0,
21689        XMMS_               },        /* SWM */
21690 };
21691
21692
21693 NMD::Pool NMD::P_LS_UAWM[2] = {
21694     { instruction         , 0                   , 0   , 32,
21695        0xfc000f00, 0xa4000500, &NMD::UALWM            , 0,
21696        XMMS_               },        /* UALWM */
21697     { instruction         , 0                   , 0   , 32,
21698        0xfc000f00, 0xa4000d00, &NMD::UASWM            , 0,
21699        XMMS_               },        /* UASWM */
21700 };
21701
21702
21703 NMD::Pool NMD::P_LS_DM[2] = {
21704     { instruction         , 0                   , 0   , 32,
21705        0xfc000f00, 0xa4000600, &NMD::LDM              , 0,
21706        MIPS64_             },        /* LDM */
21707     { instruction         , 0                   , 0   , 32,
21708        0xfc000f00, 0xa4000e00, &NMD::SDM              , 0,
21709        MIPS64_             },        /* SDM */
21710 };
21711
21712
21713 NMD::Pool NMD::P_LS_UADM[2] = {
21714     { instruction         , 0                   , 0   , 32,
21715        0xfc000f00, 0xa4000700, &NMD::UALDM            , 0,
21716        MIPS64_             },        /* UALDM */
21717     { instruction         , 0                   , 0   , 32,
21718        0xfc000f00, 0xa4000f00, &NMD::UASDM            , 0,
21719        MIPS64_             },        /* UASDM */
21720 };
21721
21722
21723 NMD::Pool NMD::P_LS_S9[8] = {
21724     { pool                , P_LS_S0             , 16  , 32,
21725        0xfc000700, 0xa4000000, 0                      , 0,
21726        0x0                 },        /* P.LS.S0 */
21727     { pool                , P_LS_S1             , 16  , 32,
21728        0xfc000700, 0xa4000100, 0                      , 0,
21729        0x0                 },        /* P.LS.S1 */
21730     { pool                , P_LS_E0             , 16  , 32,
21731        0xfc000700, 0xa4000200, 0                      , 0,
21732        0x0                 },        /* P.LS.E0 */
21733     { reserved_block      , 0                   , 0   , 32,
21734        0xfc000700, 0xa4000300, 0                      , 0,
21735        0x0                 },        /* P.LS.S9~*(3) */
21736     { pool                , P_LS_WM             , 2   , 32,
21737        0xfc000700, 0xa4000400, 0                      , 0,
21738        0x0                 },        /* P.LS.WM */
21739     { pool                , P_LS_UAWM           , 2   , 32,
21740        0xfc000700, 0xa4000500, 0                      , 0,
21741        0x0                 },        /* P.LS.UAWM */
21742     { pool                , P_LS_DM             , 2   , 32,
21743        0xfc000700, 0xa4000600, 0                      , 0,
21744        0x0                 },        /* P.LS.DM */
21745     { pool                , P_LS_UADM           , 2   , 32,
21746        0xfc000700, 0xa4000700, 0                      , 0,
21747        0x0                 },        /* P.LS.UADM */
21748 };
21749
21750
21751 NMD::Pool NMD::P_BAL[2] = {
21752     { branch_instruction  , 0                   , 0   , 32,
21753        0xfe000000, 0x28000000, &NMD::BC_32_           , 0,
21754        0x0                 },        /* BC[32] */
21755     { call_instruction    , 0                   , 0   , 32,
21756        0xfe000000, 0x2a000000, &NMD::BALC_32_         , 0,
21757        0x0                 },        /* BALC[32] */
21758 };
21759
21760
21761 NMD::Pool NMD::P_BALRSC[2] = {
21762     { branch_instruction  , 0                   , 0   , 32,
21763        0xffe0f000, 0x48008000, &NMD::BRSC             , 0,
21764        0x0                 },        /* BRSC */
21765     { call_instruction    , 0                   , 0   , 32,
21766        0xfc00f000, 0x48008000, &NMD::BALRSC           , &NMD::BALRSC_cond      ,
21767        0x0                 },        /* BALRSC */
21768 };
21769
21770
21771 NMD::Pool NMD::P_J[16] = {
21772     { call_instruction    , 0                   , 0   , 32,
21773        0xfc00f000, 0x48000000, &NMD::JALRC_32_        , 0,
21774        0x0                 },        /* JALRC[32] */
21775     { call_instruction    , 0                   , 0   , 32,
21776        0xfc00f000, 0x48001000, &NMD::JALRC_HB         , 0,
21777        0x0                 },        /* JALRC.HB */
21778     { reserved_block      , 0                   , 0   , 32,
21779        0xfc00f000, 0x48002000, 0                      , 0,
21780        0x0                 },        /* P.J~*(2) */
21781     { reserved_block      , 0                   , 0   , 32,
21782        0xfc00f000, 0x48003000, 0                      , 0,
21783        0x0                 },        /* P.J~*(3) */
21784     { reserved_block      , 0                   , 0   , 32,
21785        0xfc00f000, 0x48004000, 0                      , 0,
21786        0x0                 },        /* P.J~*(4) */
21787     { reserved_block      , 0                   , 0   , 32,
21788        0xfc00f000, 0x48005000, 0                      , 0,
21789        0x0                 },        /* P.J~*(5) */
21790     { reserved_block      , 0                   , 0   , 32,
21791        0xfc00f000, 0x48006000, 0                      , 0,
21792        0x0                 },        /* P.J~*(6) */
21793     { reserved_block      , 0                   , 0   , 32,
21794        0xfc00f000, 0x48007000, 0                      , 0,
21795        0x0                 },        /* P.J~*(7) */
21796     { pool                , P_BALRSC            , 2   , 32,
21797        0xfc00f000, 0x48008000, 0                      , 0,
21798        0x0                 },        /* P.BALRSC */
21799     { reserved_block      , 0                   , 0   , 32,
21800        0xfc00f000, 0x48009000, 0                      , 0,
21801        0x0                 },        /* P.J~*(9) */
21802     { reserved_block      , 0                   , 0   , 32,
21803        0xfc00f000, 0x4800a000, 0                      , 0,
21804        0x0                 },        /* P.J~*(10) */
21805     { reserved_block      , 0                   , 0   , 32,
21806        0xfc00f000, 0x4800b000, 0                      , 0,
21807        0x0                 },        /* P.J~*(11) */
21808     { reserved_block      , 0                   , 0   , 32,
21809        0xfc00f000, 0x4800c000, 0                      , 0,
21810        0x0                 },        /* P.J~*(12) */
21811     { reserved_block      , 0                   , 0   , 32,
21812        0xfc00f000, 0x4800d000, 0                      , 0,
21813        0x0                 },        /* P.J~*(13) */
21814     { reserved_block      , 0                   , 0   , 32,
21815        0xfc00f000, 0x4800e000, 0                      , 0,
21816        0x0                 },        /* P.J~*(14) */
21817     { reserved_block      , 0                   , 0   , 32,
21818        0xfc00f000, 0x4800f000, 0                      , 0,
21819        0x0                 },        /* P.J~*(15) */
21820 };
21821
21822
21823 NMD::Pool NMD::P_BR3A[32] = {
21824     { branch_instruction  , 0                   , 0   , 32,
21825        0xfc1fc000, 0x88004000, &NMD::BC1EQZC          , 0,
21826        CP1_                },        /* BC1EQZC */
21827     { branch_instruction  , 0                   , 0   , 32,
21828        0xfc1fc000, 0x88014000, &NMD::BC1NEZC          , 0,
21829        CP1_                },        /* BC1NEZC */
21830     { branch_instruction  , 0                   , 0   , 32,
21831        0xfc1fc000, 0x88024000, &NMD::BC2EQZC          , 0,
21832        CP2_                },        /* BC2EQZC */
21833     { branch_instruction  , 0                   , 0   , 32,
21834        0xfc1fc000, 0x88034000, &NMD::BC2NEZC          , 0,
21835        CP2_                },        /* BC2NEZC */
21836     { branch_instruction  , 0                   , 0   , 32,
21837        0xfc1fc000, 0x88044000, &NMD::BPOSGE32C        , 0,
21838        DSP_                },        /* BPOSGE32C */
21839     { reserved_block      , 0                   , 0   , 32,
21840        0xfc1fc000, 0x88054000, 0                      , 0,
21841        0x0                 },        /* P.BR3A~*(5) */
21842     { reserved_block      , 0                   , 0   , 32,
21843        0xfc1fc000, 0x88064000, 0                      , 0,
21844        0x0                 },        /* P.BR3A~*(6) */
21845     { reserved_block      , 0                   , 0   , 32,
21846        0xfc1fc000, 0x88074000, 0                      , 0,
21847        0x0                 },        /* P.BR3A~*(7) */
21848     { reserved_block      , 0                   , 0   , 32,
21849        0xfc1fc000, 0x88084000, 0                      , 0,
21850        0x0                 },        /* P.BR3A~*(8) */
21851     { reserved_block      , 0                   , 0   , 32,
21852        0xfc1fc000, 0x88094000, 0                      , 0,
21853        0x0                 },        /* P.BR3A~*(9) */
21854     { reserved_block      , 0                   , 0   , 32,
21855        0xfc1fc000, 0x880a4000, 0                      , 0,
21856        0x0                 },        /* P.BR3A~*(10) */
21857     { reserved_block      , 0                   , 0   , 32,
21858        0xfc1fc000, 0x880b4000, 0                      , 0,
21859        0x0                 },        /* P.BR3A~*(11) */
21860     { reserved_block      , 0                   , 0   , 32,
21861        0xfc1fc000, 0x880c4000, 0                      , 0,
21862        0x0                 },        /* P.BR3A~*(12) */
21863     { reserved_block      , 0                   , 0   , 32,
21864        0xfc1fc000, 0x880d4000, 0                      , 0,
21865        0x0                 },        /* P.BR3A~*(13) */
21866     { reserved_block      , 0                   , 0   , 32,
21867        0xfc1fc000, 0x880e4000, 0                      , 0,
21868        0x0                 },        /* P.BR3A~*(14) */
21869     { reserved_block      , 0                   , 0   , 32,
21870        0xfc1fc000, 0x880f4000, 0                      , 0,
21871        0x0                 },        /* P.BR3A~*(15) */
21872     { reserved_block      , 0                   , 0   , 32,
21873        0xfc1fc000, 0x88104000, 0                      , 0,
21874        0x0                 },        /* P.BR3A~*(16) */
21875     { reserved_block      , 0                   , 0   , 32,
21876        0xfc1fc000, 0x88114000, 0                      , 0,
21877        0x0                 },        /* P.BR3A~*(17) */
21878     { reserved_block      , 0                   , 0   , 32,
21879        0xfc1fc000, 0x88124000, 0                      , 0,
21880        0x0                 },        /* P.BR3A~*(18) */
21881     { reserved_block      , 0                   , 0   , 32,
21882        0xfc1fc000, 0x88134000, 0                      , 0,
21883        0x0                 },        /* P.BR3A~*(19) */
21884     { reserved_block      , 0                   , 0   , 32,
21885        0xfc1fc000, 0x88144000, 0                      , 0,
21886        0x0                 },        /* P.BR3A~*(20) */
21887     { reserved_block      , 0                   , 0   , 32,
21888        0xfc1fc000, 0x88154000, 0                      , 0,
21889        0x0                 },        /* P.BR3A~*(21) */
21890     { reserved_block      , 0                   , 0   , 32,
21891        0xfc1fc000, 0x88164000, 0                      , 0,
21892        0x0                 },        /* P.BR3A~*(22) */
21893     { reserved_block      , 0                   , 0   , 32,
21894        0xfc1fc000, 0x88174000, 0                      , 0,
21895        0x0                 },        /* P.BR3A~*(23) */
21896     { reserved_block      , 0                   , 0   , 32,
21897        0xfc1fc000, 0x88184000, 0                      , 0,
21898        0x0                 },        /* P.BR3A~*(24) */
21899     { reserved_block      , 0                   , 0   , 32,
21900        0xfc1fc000, 0x88194000, 0                      , 0,
21901        0x0                 },        /* P.BR3A~*(25) */
21902     { reserved_block      , 0                   , 0   , 32,
21903        0xfc1fc000, 0x881a4000, 0                      , 0,
21904        0x0                 },        /* P.BR3A~*(26) */
21905     { reserved_block      , 0                   , 0   , 32,
21906        0xfc1fc000, 0x881b4000, 0                      , 0,
21907        0x0                 },        /* P.BR3A~*(27) */
21908     { reserved_block      , 0                   , 0   , 32,
21909        0xfc1fc000, 0x881c4000, 0                      , 0,
21910        0x0                 },        /* P.BR3A~*(28) */
21911     { reserved_block      , 0                   , 0   , 32,
21912        0xfc1fc000, 0x881d4000, 0                      , 0,
21913        0x0                 },        /* P.BR3A~*(29) */
21914     { reserved_block      , 0                   , 0   , 32,
21915        0xfc1fc000, 0x881e4000, 0                      , 0,
21916        0x0                 },        /* P.BR3A~*(30) */
21917     { reserved_block      , 0                   , 0   , 32,
21918        0xfc1fc000, 0x881f4000, 0                      , 0,
21919        0x0                 },        /* P.BR3A~*(31) */
21920 };
21921
21922
21923 NMD::Pool NMD::P_BR1[4] = {
21924     { branch_instruction  , 0                   , 0   , 32,
21925        0xfc00c000, 0x88000000, &NMD::BEQC_32_         , 0,
21926        0x0                 },        /* BEQC[32] */
21927     { pool                , P_BR3A              , 32  , 32,
21928        0xfc00c000, 0x88004000, 0                      , 0,
21929        0x0                 },        /* P.BR3A */
21930     { branch_instruction  , 0                   , 0   , 32,
21931        0xfc00c000, 0x88008000, &NMD::BGEC             , 0,
21932        0x0                 },        /* BGEC */
21933     { branch_instruction  , 0                   , 0   , 32,
21934        0xfc00c000, 0x8800c000, &NMD::BGEUC            , 0,
21935        0x0                 },        /* BGEUC */
21936 };
21937
21938
21939 NMD::Pool NMD::P_BR2[4] = {
21940     { branch_instruction  , 0                   , 0   , 32,
21941        0xfc00c000, 0xa8000000, &NMD::BNEC_32_         , 0,
21942        0x0                 },        /* BNEC[32] */
21943     { reserved_block      , 0                   , 0   , 32,
21944        0xfc00c000, 0xa8004000, 0                      , 0,
21945        0x0                 },        /* P.BR2~*(1) */
21946     { branch_instruction  , 0                   , 0   , 32,
21947        0xfc00c000, 0xa8008000, &NMD::BLTC             , 0,
21948        0x0                 },        /* BLTC */
21949     { branch_instruction  , 0                   , 0   , 32,
21950        0xfc00c000, 0xa800c000, &NMD::BLTUC            , 0,
21951        0x0                 },        /* BLTUC */
21952 };
21953
21954
21955 NMD::Pool NMD::P_BRI[8] = {
21956     { branch_instruction  , 0                   , 0   , 32,
21957        0xfc1c0000, 0xc8000000, &NMD::BEQIC            , 0,
21958        0x0                 },        /* BEQIC */
21959     { branch_instruction  , 0                   , 0   , 32,
21960        0xfc1c0000, 0xc8040000, &NMD::BBEQZC           , 0,
21961        XMMS_               },        /* BBEQZC */
21962     { branch_instruction  , 0                   , 0   , 32,
21963        0xfc1c0000, 0xc8080000, &NMD::BGEIC            , 0,
21964        0x0                 },        /* BGEIC */
21965     { branch_instruction  , 0                   , 0   , 32,
21966        0xfc1c0000, 0xc80c0000, &NMD::BGEIUC           , 0,
21967        0x0                 },        /* BGEIUC */
21968     { branch_instruction  , 0                   , 0   , 32,
21969        0xfc1c0000, 0xc8100000, &NMD::BNEIC            , 0,
21970        0x0                 },        /* BNEIC */
21971     { branch_instruction  , 0                   , 0   , 32,
21972        0xfc1c0000, 0xc8140000, &NMD::BBNEZC           , 0,
21973        XMMS_               },        /* BBNEZC */
21974     { branch_instruction  , 0                   , 0   , 32,
21975        0xfc1c0000, 0xc8180000, &NMD::BLTIC            , 0,
21976        0x0                 },        /* BLTIC */
21977     { branch_instruction  , 0                   , 0   , 32,
21978        0xfc1c0000, 0xc81c0000, &NMD::BLTIUC           , 0,
21979        0x0                 },        /* BLTIUC */
21980 };
21981
21982
21983 NMD::Pool NMD::P32[32] = {
21984     { pool                , P_ADDIU             , 2   , 32,
21985        0xfc000000, 0x00000000, 0                      , 0,
21986        0x0                 },        /* P.ADDIU */
21987     { pool                , P32A                , 8   , 32,
21988        0xfc000000, 0x20000000, 0                      , 0,
21989        0x0                 },        /* P32A */
21990     { pool                , P_GP_W              , 4   , 32,
21991        0xfc000000, 0x40000000, 0                      , 0,
21992        0x0                 },        /* P.GP.W */
21993     { pool                , POOL48I             , 32  , 48,
21994        0xfc0000000000ull, 0x600000000000ull, 0                      , 0,
21995        0x0                 },        /* POOL48I */
21996     { pool                , P_U12               , 16  , 32,
21997        0xfc000000, 0x80000000, 0                      , 0,
21998        0x0                 },        /* P.U12 */
21999     { pool                , POOL32F             , 8   , 32,
22000        0xfc000000, 0xa0000000, 0                      , 0,
22001        CP1_                },        /* POOL32F */
22002     { pool                , POOL32S             , 8   , 32,
22003        0xfc000000, 0xc0000000, 0                      , 0,
22004        0x0                 },        /* POOL32S */
22005     { pool                , P_LUI               , 2   , 32,
22006        0xfc000000, 0xe0000000, 0                      , 0,
22007        0x0                 },        /* P.LUI */
22008     { instruction         , 0                   , 0   , 32,
22009        0xfc000000, 0x04000000, &NMD::ADDIUPC_32_      , 0,
22010        0x0                 },        /* ADDIUPC[32] */
22011     { reserved_block      , 0                   , 0   , 32,
22012        0xfc000000, 0x24000000, 0                      , 0,
22013        0x0                 },        /* P32~*(5) */
22014     { pool                , P_GP_BH             , 8   , 32,
22015        0xfc000000, 0x44000000, 0                      , 0,
22016        0x0                 },        /* P.GP.BH */
22017     { reserved_block      , 0                   , 0   , 32,
22018        0xfc000000, 0x64000000, 0                      , 0,
22019        0x0                 },        /* P32~*(13) */
22020     { pool                , P_LS_U12            , 16  , 32,
22021        0xfc000000, 0x84000000, 0                      , 0,
22022        0x0                 },        /* P.LS.U12 */
22023     { pool                , P_LS_S9             , 8   , 32,
22024        0xfc000000, 0xa4000000, 0                      , 0,
22025        0x0                 },        /* P.LS.S9 */
22026     { reserved_block      , 0                   , 0   , 32,
22027        0xfc000000, 0xc4000000, 0                      , 0,
22028        0x0                 },        /* P32~*(25) */
22029     { reserved_block      , 0                   , 0   , 32,
22030        0xfc000000, 0xe4000000, 0                      , 0,
22031        0x0                 },        /* P32~*(29) */
22032     { call_instruction    , 0                   , 0   , 32,
22033        0xfc000000, 0x08000000, &NMD::MOVE_BALC        , 0,
22034        XMMS_               },        /* MOVE.BALC */
22035     { pool                , P_BAL               , 2   , 32,
22036        0xfc000000, 0x28000000, 0                      , 0,
22037        0x0                 },        /* P.BAL */
22038     { pool                , P_J                 , 16  , 32,
22039        0xfc000000, 0x48000000, 0                      , 0,
22040        0x0                 },        /* P.J */
22041     { reserved_block      , 0                   , 0   , 32,
22042        0xfc000000, 0x68000000, 0                      , 0,
22043        0x0                 },        /* P32~*(14) */
22044     { pool                , P_BR1               , 4   , 32,
22045        0xfc000000, 0x88000000, 0                      , 0,
22046        0x0                 },        /* P.BR1 */
22047     { pool                , P_BR2               , 4   , 32,
22048        0xfc000000, 0xa8000000, 0                      , 0,
22049        0x0                 },        /* P.BR2 */
22050     { pool                , P_BRI               , 8   , 32,
22051        0xfc000000, 0xc8000000, 0                      , 0,
22052        0x0                 },        /* P.BRI */
22053     { reserved_block      , 0                   , 0   , 32,
22054        0xfc000000, 0xe8000000, 0                      , 0,
22055        0x0                 },        /* P32~*(30) */
22056     { reserved_block      , 0                   , 0   , 32,
22057        0xfc000000, 0x0c000000, 0                      , 0,
22058        0x0                 },        /* P32~*(3) */
22059     { reserved_block      , 0                   , 0   , 32,
22060        0xfc000000, 0x2c000000, 0                      , 0,
22061        0x0                 },        /* P32~*(7) */
22062     { reserved_block      , 0                   , 0   , 32,
22063        0xfc000000, 0x4c000000, 0                      , 0,
22064        0x0                 },        /* P32~*(11) */
22065     { reserved_block      , 0                   , 0   , 32,
22066        0xfc000000, 0x6c000000, 0                      , 0,
22067        0x0                 },        /* P32~*(15) */
22068     { reserved_block      , 0                   , 0   , 32,
22069        0xfc000000, 0x8c000000, 0                      , 0,
22070        0x0                 },        /* P32~*(19) */
22071     { reserved_block      , 0                   , 0   , 32,
22072        0xfc000000, 0xac000000, 0                      , 0,
22073        0x0                 },        /* P32~*(23) */
22074     { reserved_block      , 0                   , 0   , 32,
22075        0xfc000000, 0xcc000000, 0                      , 0,
22076        0x0                 },        /* P32~*(27) */
22077     { reserved_block      , 0                   , 0   , 32,
22078        0xfc000000, 0xec000000, 0                      , 0,
22079        0x0                 },        /* P32~*(31) */
22080 };
22081
22082
22083 NMD::Pool NMD::P16_SYSCALL[2] = {
22084     { instruction         , 0                   , 0   , 16,
22085        0xfffc    , 0x1008    , &NMD::SYSCALL_16_      , 0,
22086        0x0                 },        /* SYSCALL[16] */
22087     { instruction         , 0                   , 0   , 16,
22088        0xfffc    , 0x100c    , &NMD::HYPCALL_16_      , 0,
22089        CP0_ | VZ_          },        /* HYPCALL[16] */
22090 };
22091
22092
22093 NMD::Pool NMD::P16_RI[4] = {
22094     { reserved_block      , 0                   , 0   , 16,
22095        0xfff8    , 0x1000    , 0                      , 0,
22096        0x0                 },        /* P16.RI~*(0) */
22097     { pool                , P16_SYSCALL         , 2   , 16,
22098        0xfff8    , 0x1008    , 0                      , 0,
22099        0x0                 },        /* P16.SYSCALL */
22100     { instruction         , 0                   , 0   , 16,
22101        0xfff8    , 0x1010    , &NMD::BREAK_16_        , 0,
22102        0x0                 },        /* BREAK[16] */
22103     { instruction         , 0                   , 0   , 16,
22104        0xfff8    , 0x1018    , &NMD::SDBBP_16_        , 0,
22105        EJTAG_              },        /* SDBBP[16] */
22106 };
22107
22108
22109 NMD::Pool NMD::P16_MV[2] = {
22110     { pool                , P16_RI              , 4   , 16,
22111        0xffe0    , 0x1000    , 0                      , 0,
22112        0x0                 },        /* P16.RI */
22113     { instruction         , 0                   , 0   , 16,
22114        0xfc00    , 0x1000    , &NMD::MOVE             , &NMD::MOVE_cond        ,
22115        0x0                 },        /* MOVE */
22116 };
22117
22118
22119 NMD::Pool NMD::P16_SHIFT[2] = {
22120     { instruction         , 0                   , 0   , 16,
22121        0xfc08    , 0x3000    , &NMD::SLL_16_          , 0,
22122        0x0                 },        /* SLL[16] */
22123     { instruction         , 0                   , 0   , 16,
22124        0xfc08    , 0x3008    , &NMD::SRL_16_          , 0,
22125        0x0                 },        /* SRL[16] */
22126 };
22127
22128
22129 NMD::Pool NMD::POOL16C_00[4] = {
22130     { instruction         , 0                   , 0   , 16,
22131        0xfc0f    , 0x5000    , &NMD::NOT_16_          , 0,
22132        0x0                 },        /* NOT[16] */
22133     { instruction         , 0                   , 0   , 16,
22134        0xfc0f    , 0x5004    , &NMD::XOR_16_          , 0,
22135        0x0                 },        /* XOR[16] */
22136     { instruction         , 0                   , 0   , 16,
22137        0xfc0f    , 0x5008    , &NMD::AND_16_          , 0,
22138        0x0                 },        /* AND[16] */
22139     { instruction         , 0                   , 0   , 16,
22140        0xfc0f    , 0x500c    , &NMD::OR_16_           , 0,
22141        0x0                 },        /* OR[16] */
22142 };
22143
22144
22145 NMD::Pool NMD::POOL16C_0[2] = {
22146     { pool                , POOL16C_00          , 4   , 16,
22147        0xfc03    , 0x5000    , 0                      , 0,
22148        0x0                 },        /* POOL16C_00 */
22149     { reserved_block      , 0                   , 0   , 16,
22150        0xfc03    , 0x5002    , 0                      , 0,
22151        0x0                 },        /* POOL16C_0~*(1) */
22152 };
22153
22154
22155 NMD::Pool NMD::P16C[2] = {
22156     { pool                , POOL16C_0           , 2   , 16,
22157        0xfc01    , 0x5000    , 0                      , 0,
22158        0x0                 },        /* POOL16C_0 */
22159     { instruction         , 0                   , 0   , 16,
22160        0xfc01    , 0x5001    , &NMD::LWXS_16_         , 0,
22161        0x0                 },        /* LWXS[16] */
22162 };
22163
22164
22165 NMD::Pool NMD::P16_A1[2] = {
22166     { reserved_block      , 0                   , 0   , 16,
22167        0xfc40    , 0x7000    , 0                      , 0,
22168        0x0                 },        /* P16.A1~*(0) */
22169     { instruction         , 0                   , 0   , 16,
22170        0xfc40    , 0x7040    , &NMD::ADDIU_R1_SP_     , 0,
22171        0x0                 },        /* ADDIU[R1.SP] */
22172 };
22173
22174
22175 NMD::Pool NMD::P_ADDIU_RS5_[2] = {
22176     { instruction         , 0                   , 0   , 16,
22177        0xffe8    , 0x9008    , &NMD::NOP_16_          , 0,
22178        0x0                 },        /* NOP[16] */
22179     { instruction         , 0                   , 0   , 16,
22180        0xfc08    , 0x9008    , &NMD::ADDIU_RS5_       , &NMD::ADDIU_RS5__cond  ,
22181        0x0                 },        /* ADDIU[RS5] */
22182 };
22183
22184
22185 NMD::Pool NMD::P16_A2[2] = {
22186     { instruction         , 0                   , 0   , 16,
22187        0xfc08    , 0x9000    , &NMD::ADDIU_R2_        , 0,
22188        0x0                 },        /* ADDIU[R2] */
22189     { pool                , P_ADDIU_RS5_        , 2   , 16,
22190        0xfc08    , 0x9008    , 0                      , 0,
22191        0x0                 },        /* P.ADDIU[RS5] */
22192 };
22193
22194
22195 NMD::Pool NMD::P16_ADDU[2] = {
22196     { instruction         , 0                   , 0   , 16,
22197        0xfc01    , 0xb000    , &NMD::ADDU_16_         , 0,
22198        0x0                 },        /* ADDU[16] */
22199     { instruction         , 0                   , 0   , 16,
22200        0xfc01    , 0xb001    , &NMD::SUBU_16_         , 0,
22201        0x0                 },        /* SUBU[16] */
22202 };
22203
22204
22205 NMD::Pool NMD::P16_JRC[2] = {
22206     { branch_instruction  , 0                   , 0   , 16,
22207        0xfc1f    , 0xd800    , &NMD::JRC              , 0,
22208        0x0                 },        /* JRC */
22209     { call_instruction    , 0                   , 0   , 16,
22210        0xfc1f    , 0xd810    , &NMD::JALRC_16_        , 0,
22211        0x0                 },        /* JALRC[16] */
22212 };
22213
22214
22215 NMD::Pool NMD::P16_BR1[2] = {
22216     { branch_instruction  , 0                   , 0   , 16,
22217        0xfc00    , 0xd800    , &NMD::BEQC_16_         , &NMD::BEQC_16__cond    ,
22218        XMMS_               },        /* BEQC[16] */
22219     { branch_instruction  , 0                   , 0   , 16,
22220        0xfc00    , 0xd800    , &NMD::BNEC_16_         , &NMD::BNEC_16__cond    ,
22221        XMMS_               },        /* BNEC[16] */
22222 };
22223
22224
22225 NMD::Pool NMD::P16_BR[2] = {
22226     { pool                , P16_JRC             , 2   , 16,
22227        0xfc0f    , 0xd800    , 0                      , 0,
22228        0x0                 },        /* P16.JRC */
22229     { pool                , P16_BR1             , 2   , 16,
22230        0xfc00    , 0xd800    , 0                      , &NMD::P16_BR1_cond     ,
22231        0x0                 },        /* P16.BR1 */
22232 };
22233
22234
22235 NMD::Pool NMD::P16_SR[2] = {
22236     { instruction         , 0                   , 0   , 16,
22237        0xfd00    , 0x1c00    , &NMD::SAVE_16_         , 0,
22238        0x0                 },        /* SAVE[16] */
22239     { return_instruction  , 0                   , 0   , 16,
22240        0xfd00    , 0x1d00    , &NMD::RESTORE_JRC_16_  , 0,
22241        0x0                 },        /* RESTORE.JRC[16] */
22242 };
22243
22244
22245 NMD::Pool NMD::P16_4X4[4] = {
22246     { instruction         , 0                   , 0   , 16,
22247        0xfd08    , 0x3c00    , &NMD::ADDU_4X4_        , 0,
22248        XMMS_               },        /* ADDU[4X4] */
22249     { instruction         , 0                   , 0   , 16,
22250        0xfd08    , 0x3c08    , &NMD::MUL_4X4_         , 0,
22251        XMMS_               },        /* MUL[4X4] */
22252     { reserved_block      , 0                   , 0   , 16,
22253        0xfd08    , 0x3d00    , 0                      , 0,
22254        0x0                 },        /* P16.4X4~*(2) */
22255     { reserved_block      , 0                   , 0   , 16,
22256        0xfd08    , 0x3d08    , 0                      , 0,
22257        0x0                 },        /* P16.4X4~*(3) */
22258 };
22259
22260
22261 NMD::Pool NMD::P16_LB[4] = {
22262     { instruction         , 0                   , 0   , 16,
22263        0xfc0c    , 0x5c00    , &NMD::LB_16_           , 0,
22264        0x0                 },        /* LB[16] */
22265     { instruction         , 0                   , 0   , 16,
22266        0xfc0c    , 0x5c04    , &NMD::SB_16_           , 0,
22267        0x0                 },        /* SB[16] */
22268     { instruction         , 0                   , 0   , 16,
22269        0xfc0c    , 0x5c08    , &NMD::LBU_16_          , 0,
22270        0x0                 },        /* LBU[16] */
22271     { reserved_block      , 0                   , 0   , 16,
22272        0xfc0c    , 0x5c0c    , 0                      , 0,
22273        0x0                 },        /* P16.LB~*(3) */
22274 };
22275
22276
22277 NMD::Pool NMD::P16_LH[4] = {
22278     { instruction         , 0                   , 0   , 16,
22279        0xfc09    , 0x7c00    , &NMD::LH_16_           , 0,
22280        0x0                 },        /* LH[16] */
22281     { instruction         , 0                   , 0   , 16,
22282        0xfc09    , 0x7c01    , &NMD::SH_16_           , 0,
22283        0x0                 },        /* SH[16] */
22284     { instruction         , 0                   , 0   , 16,
22285        0xfc09    , 0x7c08    , &NMD::LHU_16_          , 0,
22286        0x0                 },        /* LHU[16] */
22287     { reserved_block      , 0                   , 0   , 16,
22288        0xfc09    , 0x7c09    , 0                      , 0,
22289        0x0                 },        /* P16.LH~*(3) */
22290 };
22291
22292
22293 NMD::Pool NMD::P16[32] = {
22294     { pool                , P16_MV              , 2   , 16,
22295        0xfc00    , 0x1000    , 0                      , 0,
22296        0x0                 },        /* P16.MV */
22297     { pool                , P16_SHIFT           , 2   , 16,
22298        0xfc00    , 0x3000    , 0                      , 0,
22299        0x0                 },        /* P16.SHIFT */
22300     { pool                , P16C                , 2   , 16,
22301        0xfc00    , 0x5000    , 0                      , 0,
22302        0x0                 },        /* P16C */
22303     { pool                , P16_A1              , 2   , 16,
22304        0xfc00    , 0x7000    , 0                      , 0,
22305        0x0                 },        /* P16.A1 */
22306     { pool                , P16_A2              , 2   , 16,
22307        0xfc00    , 0x9000    , 0                      , 0,
22308        0x0                 },        /* P16.A2 */
22309     { pool                , P16_ADDU            , 2   , 16,
22310        0xfc00    , 0xb000    , 0                      , 0,
22311        0x0                 },        /* P16.ADDU */
22312     { instruction         , 0                   , 0   , 16,
22313        0xfc00    , 0xd000    , &NMD::LI_16_           , 0,
22314        0x0                 },        /* LI[16] */
22315     { instruction         , 0                   , 0   , 16,
22316        0xfc00    , 0xf000    , &NMD::ANDI_16_         , 0,
22317        0x0                 },        /* ANDI[16] */
22318     { instruction         , 0                   , 0   , 16,
22319        0xfc00    , 0x1400    , &NMD::LW_16_           , 0,
22320        0x0                 },        /* LW[16] */
22321     { instruction         , 0                   , 0   , 16,
22322        0xfc00    , 0x3400    , &NMD::LW_SP_           , 0,
22323        0x0                 },        /* LW[SP] */
22324     { instruction         , 0                   , 0   , 16,
22325        0xfc00    , 0x5400    , &NMD::LW_GP16_         , 0,
22326        0x0                 },        /* LW[GP16] */
22327     { instruction         , 0                   , 0   , 16,
22328        0xfc00    , 0x7400    , &NMD::LW_4X4_          , 0,
22329        XMMS_               },        /* LW[4X4] */
22330     { instruction         , 0                   , 0   , 16,
22331        0xfc00    , 0x9400    , &NMD::SW_16_           , 0,
22332        0x0                 },        /* SW[16] */
22333     { instruction         , 0                   , 0   , 16,
22334        0xfc00    , 0xb400    , &NMD::SW_SP_           , 0,
22335        0x0                 },        /* SW[SP] */
22336     { instruction         , 0                   , 0   , 16,
22337        0xfc00    , 0xd400    , &NMD::SW_GP16_         , 0,
22338        0x0                 },        /* SW[GP16] */
22339     { instruction         , 0                   , 0   , 16,
22340        0xfc00    , 0xf400    , &NMD::SW_4X4_          , 0,
22341        XMMS_               },        /* SW[4X4] */
22342     { branch_instruction  , 0                   , 0   , 16,
22343        0xfc00    , 0x1800    , &NMD::BC_16_           , 0,
22344        0x0                 },        /* BC[16] */
22345     { call_instruction    , 0                   , 0   , 16,
22346        0xfc00    , 0x3800    , &NMD::BALC_16_         , 0,
22347        0x0                 },        /* BALC[16] */
22348     { reserved_block      , 0                   , 0   , 16,
22349        0xfc00    , 0x5800    , 0                      , 0,
22350        0x0                 },        /* P16~*(10) */
22351     { reserved_block      , 0                   , 0   , 16,
22352        0xfc00    , 0x7800    , 0                      , 0,
22353        0x0                 },        /* P16~*(14) */
22354     { branch_instruction  , 0                   , 0   , 16,
22355        0xfc00    , 0x9800    , &NMD::BEQZC_16_        , 0,
22356        0x0                 },        /* BEQZC[16] */
22357     { branch_instruction  , 0                   , 0   , 16,
22358        0xfc00    , 0xb800    , &NMD::BNEZC_16_        , 0,
22359        0x0                 },        /* BNEZC[16] */
22360     { pool                , P16_BR              , 2   , 16,
22361        0xfc00    , 0xd800    , 0                      , 0,
22362        0x0                 },        /* P16.BR */
22363     { reserved_block      , 0                   , 0   , 16,
22364        0xfc00    , 0xf800    , 0                      , 0,
22365        0x0                 },        /* P16~*(30) */
22366     { pool                , P16_SR              , 2   , 16,
22367        0xfc00    , 0x1c00    , 0                      , 0,
22368        0x0                 },        /* P16.SR */
22369     { pool                , P16_4X4             , 4   , 16,
22370        0xfc00    , 0x3c00    , 0                      , 0,
22371        0x0                 },        /* P16.4X4 */
22372     { pool                , P16_LB              , 4   , 16,
22373        0xfc00    , 0x5c00    , 0                      , 0,
22374        0x0                 },        /* P16.LB */
22375     { pool                , P16_LH              , 4   , 16,
22376        0xfc00    , 0x7c00    , 0                      , 0,
22377        0x0                 },        /* P16.LH */
22378     { reserved_block      , 0                   , 0   , 16,
22379        0xfc00    , 0x9c00    , 0                      , 0,
22380        0x0                 },        /* P16~*(19) */
22381     { instruction         , 0                   , 0   , 16,
22382        0xfc00    , 0xbc00    , &NMD::MOVEP            , 0,
22383        XMMS_               },        /* MOVEP */
22384     { reserved_block      , 0                   , 0   , 16,
22385        0xfc00    , 0xdc00    , 0                      , 0,
22386        0x0                 },        /* P16~*(27) */
22387     { instruction         , 0                   , 0   , 16,
22388        0xfc00    , 0xfc00    , &NMD::MOVEP_REV_       , 0,
22389        XMMS_               },        /* MOVEP[REV] */
22390 };
22391
22392
22393 NMD::Pool NMD::MAJOR[2] = {
22394     { pool                , P32                 , 32  , 32,
22395        0x10000000, 0x00000000, 0                      , 0,
22396        0x0                 },        /* P32 */
22397     { pool                , P16                 , 32  , 16,
22398        0x1000    , 0x1000    , 0                      , 0,
22399        0x0                 },        /* P16 */
22400 };