2 * Copyright (C) 2012 The Android Open Source Project
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 #include "disassembler_x86.h"
24 #include "base/logging.h"
25 #include "base/stringprintf.h"
31 size_t DisassemblerX86::Dump(std::ostream& os, const uint8_t* begin) {
32 return DumpInstruction(os, begin);
35 void DisassemblerX86::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
37 for (const uint8_t* cur = begin; cur < end; cur += length) {
38 length = DumpInstruction(os, cur);
42 static const char* gReg8Names[] = {
43 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
45 static const char* gExtReg8Names[] = {
46 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
47 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"
49 static const char* gReg16Names[] = {
50 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
51 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
53 static const char* gReg32Names[] = {
54 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
55 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
57 static const char* gReg64Names[] = {
58 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
59 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
62 // 64-bit opcode REX modifier.
63 constexpr uint8_t REX_W = 8U /* 0b1000 */;
64 constexpr uint8_t REX_R = 4U /* 0b0100 */;
65 constexpr uint8_t REX_X = 2U /* 0b0010 */;
66 constexpr uint8_t REX_B = 1U /* 0b0001 */;
68 static void DumpReg0(std::ostream& os, uint8_t rex, size_t reg,
69 bool byte_operand, uint8_t size_override) {
70 DCHECK_LT(reg, (rex == 0) ? 8u : 16u);
71 bool rex_w = (rex & REX_W) != 0;
73 os << ((rex == 0) ? gReg8Names[reg] : gExtReg8Names[reg]);
75 os << gReg64Names[reg];
76 } else if (size_override == 0x66) {
77 os << gReg16Names[reg];
79 os << gReg32Names[reg];
83 static void DumpAnyReg(std::ostream& os, uint8_t rex, size_t reg,
84 bool byte_operand, uint8_t size_override, RegFile reg_file) {
85 if (reg_file == GPR) {
86 DumpReg0(os, rex, reg, byte_operand, size_override);
87 } else if (reg_file == SSE) {
94 static void DumpReg(std::ostream& os, uint8_t rex, uint8_t reg,
95 bool byte_operand, uint8_t size_override, RegFile reg_file) {
96 bool rex_r = (rex & REX_R) != 0;
97 size_t reg_num = rex_r ? (reg + 8) : reg;
98 DumpAnyReg(os, rex, reg_num, byte_operand, size_override, reg_file);
101 static void DumpRmReg(std::ostream& os, uint8_t rex, uint8_t reg,
102 bool byte_operand, uint8_t size_override, RegFile reg_file) {
103 bool rex_b = (rex & REX_B) != 0;
104 size_t reg_num = rex_b ? (reg + 8) : reg;
105 DumpAnyReg(os, rex, reg_num, byte_operand, size_override, reg_file);
108 static void DumpAddrReg(std::ostream& os, uint8_t rex, uint8_t reg) {
110 os << gReg64Names[reg];
112 os << gReg32Names[reg];
116 static void DumpBaseReg(std::ostream& os, uint8_t rex, uint8_t reg) {
117 bool rex_b = (rex & REX_B) != 0;
118 size_t reg_num = rex_b ? (reg + 8) : reg;
119 DumpAddrReg(os, rex, reg_num);
122 static void DumpOpcodeReg(std::ostream& os, uint8_t rex, uint8_t reg,
123 bool byte_operand, uint8_t size_override) {
124 bool rex_b = (rex & REX_B) != 0;
125 size_t reg_num = rex_b ? (reg + 8) : reg;
126 DumpReg0(os, rex, reg_num, byte_operand, size_override);
138 static void DumpSegmentOverride(std::ostream& os, uint8_t segment_prefix) {
139 switch (segment_prefix) {
140 case kCs: os << "cs:"; break;
141 case kSs: os << "ss:"; break;
142 case kDs: os << "ds:"; break;
143 case kEs: os << "es:"; break;
144 case kFs: os << "fs:"; break;
145 case kGs: os << "gs:"; break;
150 // Do not inline to avoid Clang stack frame problems. b/18733806
152 static std::string DumpCodeHex(const uint8_t* begin, const uint8_t* end) {
153 std::stringstream hex;
154 for (size_t i = 0; begin + i < end; ++i) {
155 hex << StringPrintf("%02X", begin[i]);
160 std::string DisassemblerX86::DumpAddress(uint8_t mod, uint8_t rm, uint8_t rex64, uint8_t rex_w,
161 bool no_ops, bool byte_operand, bool byte_second_operand,
162 uint8_t* prefix, bool load, RegFile src_reg_file,
163 RegFile dst_reg_file, const uint8_t** instr,
164 uint32_t* address_bits) {
165 std::ostringstream address;
166 if (mod == 0 && rm == 5) {
167 if (!supports_rex_) { // Absolute address.
168 *address_bits = *reinterpret_cast<const uint32_t*>(*instr);
169 address << StringPrintf("[0x%x]", *address_bits);
170 } else { // 64-bit RIP relative addressing.
171 address << StringPrintf("[RIP + 0x%x]", *reinterpret_cast<const uint32_t*>(*instr));
174 } else if (rm == 4 && mod != 3) { // SIB
175 uint8_t sib = **instr;
177 uint8_t scale = (sib >> 6) & 3;
178 uint8_t index = (sib >> 3) & 7;
179 uint8_t base = sib & 7;
182 // REX.x is bit 3 of index.
183 if ((rex64 & REX_X) != 0) {
187 // Mod = 0 && base = 5 (ebp): no base (ignores REX.b).
188 bool has_base = false;
189 if (base != 5 || mod != 0) {
191 DumpBaseReg(address, rex64, base);
194 // Index = 4 (esp/rsp) is disallowed.
199 DumpAddrReg(address, rex64, index);
201 address << StringPrintf(" * %d", 1 << scale);
208 address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr));
210 // 64-bit low 32-bit absolute address, redundant absolute address encoding on 32-bit.
211 *address_bits = *reinterpret_cast<const uint32_t*>(*instr);
212 address << StringPrintf("%d", *address_bits);
216 } else if (mod == 1) {
217 address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(*instr));
219 } else if (mod == 2) {
220 address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr));
227 DumpRmReg(address, rex_w, rm, byte_operand || byte_second_operand,
228 prefix[2], load ? src_reg_file : dst_reg_file);
232 DumpBaseReg(address, rex64, rm);
234 address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(*instr));
236 } else if (mod == 2) {
237 address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr));
243 return address.str();
246 size_t DisassemblerX86::DumpInstruction(std::ostream& os, const uint8_t* instr) {
247 const uint8_t* begin_instr = instr;
248 bool have_prefixes = true;
249 uint8_t prefix[4] = {0, 0, 0, 0};
252 // Group 1 - lock and repeat prefixes:
258 // Group 2 - segment override prefixes:
267 // Group 3 - operand size override:
271 // Group 4 - address size override:
276 have_prefixes = false;
282 } while (have_prefixes);
283 uint8_t rex = (supports_rex_ && (*instr >= 0x40) && (*instr <= 0x4F)) ? *instr : 0;
287 const char** modrm_opcodes = nullptr;
288 bool has_modrm = false;
289 bool reg_is_opcode = false;
290 size_t immediate_bytes = 0;
291 size_t branch_bytes = 0;
292 std::string opcode_tmp; // Storage to keep StringPrintf result alive.
293 const char* opcode0 = ""; // Prefix part.
294 const char* opcode1 = ""; // Main opcode.
295 const char* opcode2 = ""; // Sub-opcode. E.g., jump type.
296 const char* opcode3 = ""; // Mod-rm part.
297 const char* opcode4 = ""; // Suffix part.
298 bool store = false; // stores to memory (ie rm is on the left)
299 bool load = false; // loads from memory (ie rm is on the right)
300 bool byte_operand = false; // true when the opcode is dealing with byte operands
301 // true when the source operand is a byte register but the target register isn't
302 // (ie movsxb/movzxb).
303 bool byte_second_operand = false;
304 bool target_specific = false; // register name depends on target (64 vs 32 bits).
305 bool ax = false; // implicit use of ax
306 bool cx = false; // implicit use of cx
307 bool reg_in_opcode = false; // low 3-bits of opcode encode register parameter
309 RegFile src_reg_file = GPR;
310 RegFile dst_reg_file = GPR;
312 #define DISASSEMBLER_ENTRY(opname, \
316 case rm8_r8: opcode1 = #opname; store = true; has_modrm = true; byte_operand = true; break; \
317 case rm32_r32: opcode1 = #opname; store = true; has_modrm = true; break; \
318 case r8_rm8: opcode1 = #opname; load = true; has_modrm = true; byte_operand = true; break; \
319 case r32_rm32: opcode1 = #opname; load = true; has_modrm = true; break; \
320 case ax8_i8: opcode1 = #opname; ax = true; immediate_bytes = 1; byte_operand = true; break; \
321 case ax32_i32: opcode1 = #opname; ax = true; immediate_bytes = 4; break;
323 DISASSEMBLER_ENTRY(add,
324 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,
325 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,
326 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */)
327 DISASSEMBLER_ENTRY(or,
328 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,
329 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,
330 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */)
331 DISASSEMBLER_ENTRY(adc,
332 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,
333 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,
334 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */)
335 DISASSEMBLER_ENTRY(sbb,
336 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,
337 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,
338 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */)
339 DISASSEMBLER_ENTRY(and,
340 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,
341 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,
342 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */)
343 DISASSEMBLER_ENTRY(sub,
344 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,
345 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,
346 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */)
347 DISASSEMBLER_ENTRY(xor,
348 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,
349 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,
350 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */)
351 DISASSEMBLER_ENTRY(cmp,
352 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,
353 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,
354 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */)
356 #undef DISASSEMBLER_ENTRY
357 case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
359 reg_in_opcode = true;
360 target_specific = true;
362 case 0x58: case 0x59: case 0x5A: case 0x5B: case 0x5C: case 0x5D: case 0x5E: case 0x5F:
364 reg_in_opcode = true;
365 target_specific = true;
368 if ((rex & REX_W) != 0) {
373 // In 32-bit mode (!supports_rex_) this is ARPL, with no REX prefix the functionality is the
374 // same as 'mov' but the use of the instruction is discouraged.
375 opcode_tmp = StringPrintf("unknown opcode '%02X'", *instr);
376 opcode1 = opcode_tmp.c_str();
379 case 0x68: opcode1 = "push"; immediate_bytes = 4; break;
380 case 0x69: opcode1 = "imul"; load = true; has_modrm = true; immediate_bytes = 4; break;
381 case 0x6A: opcode1 = "push"; immediate_bytes = 1; break;
382 case 0x6B: opcode1 = "imul"; load = true; has_modrm = true; immediate_bytes = 1; break;
383 case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
384 case 0x78: case 0x79: case 0x7A: case 0x7B: case 0x7C: case 0x7D: case 0x7E: case 0x7F:
385 static const char* condition_codes[] =
386 {"o", "no", "b/nae/c", "nb/ae/nc", "z/eq", "nz/ne", "be/na", "nbe/a",
387 "s", "ns", "p/pe", "np/po", "l/nge", "nl/ge", "le/ng", "nle/g"
390 opcode2 = condition_codes[*instr & 0xF];
393 case 0x86: case 0x87:
397 byte_operand = (*instr == 0x86);
399 case 0x88: opcode1 = "mov"; store = true; has_modrm = true; byte_operand = true; break;
400 case 0x89: opcode1 = "mov"; store = true; has_modrm = true; break;
401 case 0x8A: opcode1 = "mov"; load = true; has_modrm = true; byte_operand = true; break;
402 case 0x8B: opcode1 = "mov"; load = true; has_modrm = true; break;
404 case 0x0F: // 2 byte extended opcode
407 case 0x10: case 0x11:
408 if (prefix[0] == 0xF2) {
410 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
411 } else if (prefix[0] == 0xF3) {
413 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
414 } else if (prefix[2] == 0x66) {
416 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
421 src_reg_file = dst_reg_file = SSE;
422 load = *instr == 0x10;
425 case 0x12: case 0x13:
426 if (prefix[2] == 0x66) {
428 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
429 } else if (prefix[0] == 0) {
433 src_reg_file = dst_reg_file = SSE;
434 load = *instr == 0x12;
437 case 0x16: case 0x17:
438 if (prefix[2] == 0x66) {
440 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
441 } else if (prefix[0] == 0) {
445 src_reg_file = dst_reg_file = SSE;
446 load = *instr == 0x16;
449 case 0x28: case 0x29:
450 if (prefix[2] == 0x66) {
452 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
453 } else if (prefix[0] == 0) {
457 src_reg_file = dst_reg_file = SSE;
458 load = *instr == 0x28;
462 if (prefix[2] == 0x66) {
463 opcode1 = "cvtpi2pd";
464 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
465 } else if (prefix[0] == 0xF2) {
466 opcode1 = "cvtsi2sd";
467 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
468 } else if (prefix[0] == 0xF3) {
469 opcode1 = "cvtsi2ss";
470 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
472 opcode1 = "cvtpi2ps";
479 if (prefix[2] == 0x66) {
480 opcode1 = "cvttpd2pi";
481 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
482 } else if (prefix[0] == 0xF2) {
483 opcode1 = "cvttsd2si";
484 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
485 } else if (prefix[0] == 0xF3) {
486 opcode1 = "cvttss2si";
487 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
489 opcode1 = "cvttps2pi";
496 if (prefix[2] == 0x66) {
497 opcode1 = "cvtpd2pi";
498 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
499 } else if (prefix[0] == 0xF2) {
500 opcode1 = "cvtsd2si";
501 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
502 } else if (prefix[0] == 0xF3) {
503 opcode1 = "cvtss2si";
504 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
506 opcode1 = "cvtps2pi";
514 FALLTHROUGH_INTENDED;
516 if (prefix[2] == 0x66) {
518 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
524 src_reg_file = dst_reg_file = SSE;
526 case 0x38: // 3 byte extended opcode
528 if (prefix[2] == 0x66) {
535 src_reg_file = dst_reg_file = SSE;
542 src_reg_file = dst_reg_file = SSE;
549 src_reg_file = dst_reg_file = SSE;
552 opcode_tmp = StringPrintf("unknown opcode '0F 38 %02X'", *instr);
553 opcode1 = opcode_tmp.c_str();
556 opcode_tmp = StringPrintf("unknown opcode '0F 38 %02X'", *instr);
557 opcode1 = opcode_tmp.c_str();
560 case 0x3A: // 3 byte extended opcode
562 if (prefix[2] == 0x66) {
607 opcode_tmp = StringPrintf("unknown opcode '0F 3A %02X'", *instr);
608 opcode1 = opcode_tmp.c_str();
611 opcode_tmp = StringPrintf("unknown opcode '0F 3A %02X'", *instr);
612 opcode1 = opcode_tmp.c_str();
615 case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
616 case 0x48: case 0x49: case 0x4A: case 0x4B: case 0x4C: case 0x4D: case 0x4E: case 0x4F:
618 opcode2 = condition_codes[*instr & 0xF];
622 case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
623 case 0x58: case 0x59: case 0x5C: case 0x5D: case 0x5E: case 0x5F: {
625 case 0x50: opcode1 = "movmsk"; break;
626 case 0x51: opcode1 = "sqrt"; break;
627 case 0x52: opcode1 = "rsqrt"; break;
628 case 0x53: opcode1 = "rcp"; break;
629 case 0x54: opcode1 = "and"; break;
630 case 0x55: opcode1 = "andn"; break;
631 case 0x56: opcode1 = "or"; break;
632 case 0x57: opcode1 = "xor"; break;
633 case 0x58: opcode1 = "add"; break;
634 case 0x59: opcode1 = "mul"; break;
635 case 0x5C: opcode1 = "sub"; break;
636 case 0x5D: opcode1 = "min"; break;
637 case 0x5E: opcode1 = "div"; break;
638 case 0x5F: opcode1 = "max"; break;
639 default: LOG(FATAL) << "Unreachable"; UNREACHABLE();
641 if (prefix[2] == 0x66) {
643 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
644 } else if (prefix[0] == 0xF2) {
646 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
647 } else if (prefix[0] == 0xF3) {
649 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
655 src_reg_file = dst_reg_file = SSE;
659 if (prefix[2] == 0x66) {
660 opcode1 = "cvtpd2ps";
661 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
662 } else if (prefix[0] == 0xF2) {
663 opcode1 = "cvtsd2ss";
664 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
665 } else if (prefix[0] == 0xF3) {
666 opcode1 = "cvtss2sd";
667 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
669 opcode1 = "cvtps2pd";
673 src_reg_file = dst_reg_file = SSE;
676 if (prefix[2] == 0x66) {
677 opcode1 = "cvtps2dq";
678 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
679 } else if (prefix[0] == 0xF2) {
680 opcode1 = "bad opcode F2 0F 5B";
681 } else if (prefix[0] == 0xF3) {
682 opcode1 = "cvttps2dq";
683 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
685 opcode1 = "cvtdq2ps";
689 src_reg_file = dst_reg_file = SSE;
691 case 0x60: case 0x61: case 0x62: case 0x6C:
692 if (prefix[2] == 0x66) {
693 src_reg_file = dst_reg_file = SSE;
694 prefix[2] = 0; // Clear prefix now. It has served its purpose as part of the opcode.
696 src_reg_file = dst_reg_file = MMX;
699 case 0x60: opcode1 = "punpcklbw"; break;
700 case 0x61: opcode1 = "punpcklwd"; break;
701 case 0x62: opcode1 = "punpckldq"; break;
702 case 0x6c: opcode1 = "punpcklqdq"; break;
708 if (prefix[2] == 0x66) {
710 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
719 if (prefix[2] == 0x66) {
720 src_reg_file = dst_reg_file = SSE;
722 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
723 } else if (prefix[0] == 0xF3) {
724 src_reg_file = dst_reg_file = SSE;
726 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
735 if (prefix[2] == 0x66) {
740 src_reg_file = dst_reg_file = SSE;
742 } else if (prefix[0] == 0xF2) {
747 src_reg_file = dst_reg_file = SSE;
750 opcode_tmp = StringPrintf("unknown opcode '0F %02X'", *instr);
751 opcode1 = opcode_tmp.c_str();
755 if (prefix[2] == 0x66) {
757 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
761 static const char* x71_opcodes[] = {
762 "unknown-71", "unknown-71", "psrlw", "unknown-71",
763 "psraw", "unknown-71", "psllw", "unknown-71"};
764 modrm_opcodes = x71_opcodes;
765 reg_is_opcode = true;
771 if (prefix[2] == 0x66) {
773 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
777 static const char* x72_opcodes[] = {
778 "unknown-72", "unknown-72", "psrld", "unknown-72",
779 "psrad", "unknown-72", "pslld", "unknown-72"};
780 modrm_opcodes = x72_opcodes;
781 reg_is_opcode = true;
787 if (prefix[2] == 0x66) {
789 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
793 static const char* x73_opcodes[] = {
794 "unknown-73", "unknown-73", "psrlq", "psrldq",
795 "unknown-73", "unknown-73", "psllq", "unknown-73"};
796 modrm_opcodes = x73_opcodes;
797 reg_is_opcode = true;
803 if (prefix[0] == 0xF2) {
805 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
806 } else if (prefix[2] == 0x66) {
808 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
810 opcode_tmp = StringPrintf("unknown opcode '0F %02X'", *instr);
811 opcode1 = opcode_tmp.c_str();
814 src_reg_file = dst_reg_file = SSE;
819 if (prefix[2] == 0x66) {
821 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
829 case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
830 case 0x88: case 0x89: case 0x8A: case 0x8B: case 0x8C: case 0x8D: case 0x8E: case 0x8F:
832 opcode2 = condition_codes[*instr & 0xF];
835 case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
836 case 0x98: case 0x99: case 0x9A: case 0x9B: case 0x9C: case 0x9D: case 0x9E: case 0x9F:
838 opcode2 = condition_codes[*instr & 0xF];
839 modrm_opcodes = nullptr;
840 reg_is_opcode = true;
869 if (prefix[0] == 0xF3) {
870 prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
871 static const char* xAE_opcodes[] = {
872 "rdfsbase", "rdgsbase", "wrfsbase", "wrgsbase",
873 "unknown-AE", "unknown-AE", "unknown-AE", "unknown-AE"};
874 modrm_opcodes = xAE_opcodes;
875 reg_is_opcode = true;
877 uint8_t reg_or_opcode = (instr[1] >> 3) & 7;
878 switch (reg_or_opcode) {
900 static const char* xAE_opcodes[] = {
901 "unknown-AE", "unknown-AE", "unknown-AE", "unknown-AE",
902 "unknown-AE", "lfence", "mfence", "sfence"};
903 modrm_opcodes = xAE_opcodes;
904 reg_is_opcode = true;
924 byte_second_operand = true;
950 byte_second_operand = true;
951 rex |= (rex == 0 ? 0 : REX_W);
964 if (prefix[2] == 0x66) {
972 opcode_tmp = StringPrintf("unknown opcode '0F %02X'", *instr);
973 opcode1 = opcode_tmp.c_str();
977 if (prefix[2] == 0x66) {
985 src_reg_file = dst_reg_file = SSE;
989 static const char* x0FxC7_opcodes[] = {
990 "unknown-0f-c7", "cmpxchg8b", "unknown-0f-c7", "unknown-0f-c7",
991 "unknown-0f-c7", "unknown-0f-c7", "unknown-0f-c7", "unknown-0f-c7"};
992 modrm_opcodes = x0FxC7_opcodes;
994 reg_is_opcode = true;
997 case 0xC8: case 0xC9: case 0xCA: case 0xCB: case 0xCC: case 0xCD: case 0xCE: case 0xCF:
999 reg_in_opcode = true;
1002 if (prefix[2] == 0x66) {
1003 src_reg_file = dst_reg_file = SSE;
1006 src_reg_file = dst_reg_file = MMX;
1014 if (prefix[2] == 0x66) {
1015 src_reg_file = dst_reg_file = SSE;
1016 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
1018 src_reg_file = dst_reg_file = MMX;
1026 if (prefix[2] == 0x66) {
1031 src_reg_file = dst_reg_file = SSE;
1033 opcode_tmp = StringPrintf("unknown opcode '0F %02X'", *instr);
1034 opcode1 = opcode_tmp.c_str();
1038 if (prefix[2] == 0x66) {
1039 src_reg_file = dst_reg_file = SSE;
1040 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
1042 src_reg_file = dst_reg_file = MMX;
1050 if (prefix[2] == 0x66) {
1051 src_reg_file = dst_reg_file = SSE;
1052 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
1054 src_reg_file = dst_reg_file = MMX;
1070 if (prefix[2] == 0x66) {
1071 src_reg_file = dst_reg_file = SSE;
1072 prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
1074 src_reg_file = dst_reg_file = MMX;
1077 case 0xF4: opcode1 = "pmuludq"; break;
1078 case 0xF6: opcode1 = "psadbw"; break;
1079 case 0xF8: opcode1 = "psubb"; break;
1080 case 0xF9: opcode1 = "psubw"; break;
1081 case 0xFA: opcode1 = "psubd"; break;
1082 case 0xFB: opcode1 = "psubq"; break;
1083 case 0xFC: opcode1 = "paddb"; break;
1084 case 0xFD: opcode1 = "paddw"; break;
1085 case 0xFE: opcode1 = "paddd"; break;
1092 opcode_tmp = StringPrintf("unknown opcode '0F %02X'", *instr);
1093 opcode1 = opcode_tmp.c_str();
1097 case 0x80: case 0x81: case 0x82: case 0x83:
1098 static const char* x80_opcodes[] = {"add", "or", "adc", "sbb", "and", "sub", "xor", "cmp"};
1099 modrm_opcodes = x80_opcodes;
1101 reg_is_opcode = true;
1103 byte_operand = (*instr & 1) == 0;
1104 immediate_bytes = *instr == 0x81 ? 4 : 1;
1106 case 0x84: case 0x85:
1110 byte_operand = (*instr & 1) == 0;
1120 reg_is_opcode = true;
1127 if (instr[1] == 0xDF && instr[2] == 0xE0) {
1128 opcode1 = "fstsw\tax";
1131 opcode_tmp = StringPrintf("unknown opcode '%02X'", *instr);
1132 opcode1 = opcode_tmp.c_str();
1136 opcode1 = (prefix[2] == 0x66 ? "movsw" : "movsl");
1139 opcode1 = (prefix[2] == 0x66 ? "cmpsw" : "cmpsl");
1142 opcode1 = (prefix[2] == 0x66 ? "scasw" : "scasl");
1144 case 0xB0: case 0xB1: case 0xB2: case 0xB3: case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1146 immediate_bytes = 1;
1147 byte_operand = true;
1148 reg_in_opcode = true;
1149 byte_operand = true;
1151 case 0xB8: case 0xB9: case 0xBA: case 0xBB: case 0xBC: case 0xBD: case 0xBE: case 0xBF:
1152 if ((rex & REX_W) != 0) {
1153 opcode1 = "movabsq";
1154 immediate_bytes = 8;
1155 reg_in_opcode = true;
1159 immediate_bytes = 4;
1160 reg_in_opcode = true;
1162 case 0xC0: case 0xC1:
1163 case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1164 static const char* shift_opcodes[] =
1165 {"rol", "ror", "rcl", "rcr", "shl", "shr", "unknown-shift", "sar"};
1166 modrm_opcodes = shift_opcodes;
1168 reg_is_opcode = true;
1170 immediate_bytes = ((*instr & 0xf0) == 0xc0) ? 1 : 0;
1171 cx = (*instr == 0xD2) || (*instr == 0xD3);
1172 byte_operand = (*instr == 0xC0);
1174 case 0xC3: opcode1 = "ret"; break;
1176 static const char* c6_opcodes[] = {"mov", "unknown-c6", "unknown-c6",
1177 "unknown-c6", "unknown-c6", "unknown-c6",
1178 "unknown-c6", "unknown-c6"};
1179 modrm_opcodes = c6_opcodes;
1181 immediate_bytes = 1;
1183 reg_is_opcode = true;
1184 byte_operand = true;
1187 static const char* c7_opcodes[] = {"mov", "unknown-c7", "unknown-c7",
1188 "unknown-c7", "unknown-c7", "unknown-c7",
1189 "unknown-c7", "unknown-c7"};
1190 modrm_opcodes = c7_opcodes;
1192 immediate_bytes = 4;
1194 reg_is_opcode = true;
1196 case 0xCC: opcode1 = "int 3"; break;
1198 if (instr[1] == 0xF8) {
1202 static const char* d9_opcodes[] = {"flds", "unknown-d9", "fsts", "fstps", "fldenv", "fldcw",
1203 "fnstenv", "fnstcw"};
1204 modrm_opcodes = d9_opcodes;
1207 reg_is_opcode = true;
1211 if (instr[1] == 0xE9) {
1212 opcode1 = "fucompp";
1215 opcode_tmp = StringPrintf("unknown opcode '%02X'", *instr);
1216 opcode1 = opcode_tmp.c_str();
1220 static const char* db_opcodes[] = {"fildl", "unknown-db", "unknown-db",
1221 "unknown-db", "unknown-db", "unknown-db",
1222 "unknown-db", "unknown-db"};
1223 modrm_opcodes = db_opcodes;
1226 reg_is_opcode = true;
1229 static const char* dd_opcodes[] = {"fldl", "fisttp", "fstl",
1230 "fstpl", "frstor", "unknown-dd",
1231 "fnsave", "fnstsw"};
1232 modrm_opcodes = dd_opcodes;
1235 reg_is_opcode = true;
1238 static const char* df_opcodes[] = {"fild", "unknown-df", "unknown-df",
1239 "unknown-df", "unknown-df", "fildll",
1240 "unknown-df", "unknown-df"};
1241 modrm_opcodes = df_opcodes;
1244 reg_is_opcode = true;
1246 case 0xE3: opcode1 = "jecxz"; branch_bytes = 1; break;
1247 case 0xE8: opcode1 = "call"; branch_bytes = 4; break;
1248 case 0xE9: opcode1 = "jmp"; branch_bytes = 4; break;
1249 case 0xEB: opcode1 = "jmp"; branch_bytes = 1; break;
1250 case 0xF5: opcode1 = "cmc"; break;
1251 case 0xF6: case 0xF7:
1252 static const char* f7_opcodes[] = {
1253 "test", "unknown-f7", "not", "neg", "mul edx:eax, eax *",
1254 "imul edx:eax, eax *", "div edx:eax, edx:eax /",
1255 "idiv edx:eax, edx:eax /"};
1256 modrm_opcodes = f7_opcodes;
1258 reg_is_opcode = true;
1260 immediate_bytes = ((instr[1] & 0x38) == 0) ? 1 : 0;
1264 static const char* ff_opcodes[] = {
1265 "inc", "dec", "call", "call",
1266 "jmp", "jmp", "push", "unknown-ff"};
1267 modrm_opcodes = ff_opcodes;
1269 reg_is_opcode = true;
1271 const uint8_t opcode_digit = (instr[1] >> 3) & 7;
1272 // 'call', 'jmp' and 'push' are target specific instructions
1273 if (opcode_digit == 2 || opcode_digit == 4 || opcode_digit == 6) {
1274 target_specific = true;
1279 opcode_tmp = StringPrintf("unknown opcode '%02X'", *instr);
1280 opcode1 = opcode_tmp.c_str();
1283 std::ostringstream args;
1284 // We force the REX prefix to be available for 64-bit target
1285 // in order to dump addr (base/index) registers correctly.
1286 uint8_t rex64 = supports_rex_ ? (rex | 0x40) : rex;
1287 // REX.W should be forced for 64-target and target-specific instructions (i.e., push or pop).
1288 uint8_t rex_w = (supports_rex_ && target_specific) ? (rex | 0x48) : rex;
1289 if (reg_in_opcode) {
1291 DumpOpcodeReg(args, rex_w, *instr & 0x7, byte_operand, prefix[2]);
1294 uint32_t address_bits = 0;
1296 uint8_t modrm = *instr;
1298 uint8_t mod = modrm >> 6;
1299 uint8_t reg_or_opcode = (modrm >> 3) & 7;
1300 uint8_t rm = modrm & 7;
1301 std::string address = DumpAddress(mod, rm, rex64, rex_w, no_ops, byte_operand,
1302 byte_second_operand, prefix, load, src_reg_file, dst_reg_file,
1303 &instr, &address_bits);
1305 if (reg_is_opcode && modrm_opcodes != nullptr) {
1306 opcode3 = modrm_opcodes[reg_or_opcode];
1309 // Add opcode suffixes to indicate size.
1312 } else if ((rex & REX_W) != 0) {
1314 } else if (prefix[2] == 0x66) {
1319 if (!reg_is_opcode) {
1320 DumpReg(args, rex, reg_or_opcode, byte_operand, prefix[2], dst_reg_file);
1323 DumpSegmentOverride(args, prefix[1]);
1327 DumpSegmentOverride(args, prefix[1]);
1329 if (!reg_is_opcode) {
1331 DumpReg(args, rex, reg_or_opcode, byte_operand, prefix[2], src_reg_file);
1336 // If this opcode implicitly uses ax, ax is always the first arg.
1337 DumpReg(args, rex, 0 /* EAX */, byte_operand, prefix[2], GPR);
1341 DumpReg(args, rex, 1 /* ECX */, true, prefix[2], GPR);
1343 if (immediate_bytes > 0) {
1344 if (has_modrm || reg_in_opcode || ax || cx) {
1347 if (immediate_bytes == 1) {
1348 args << StringPrintf("%d", *reinterpret_cast<const int8_t*>(instr));
1350 } else if (immediate_bytes == 4) {
1351 if (prefix[2] == 0x66) { // Operand size override from 32-bit to 16-bit.
1352 args << StringPrintf("%d", *reinterpret_cast<const int16_t*>(instr));
1355 args << StringPrintf("%d", *reinterpret_cast<const int32_t*>(instr));
1359 CHECK_EQ(immediate_bytes, 8u);
1360 args << StringPrintf("%" PRId64, *reinterpret_cast<const int64_t*>(instr));
1363 } else if (branch_bytes > 0) {
1365 int32_t displacement;
1366 if (branch_bytes == 1) {
1367 displacement = *reinterpret_cast<const int8_t*>(instr);
1370 CHECK_EQ(branch_bytes, 4u);
1371 displacement = *reinterpret_cast<const int32_t*>(instr);
1374 args << StringPrintf("%+d (", displacement)
1375 << FormatInstructionPointer(instr + displacement)
1378 if (prefix[1] == kFs && !supports_rex_) {
1380 Thread::DumpThreadOffset<4>(args, address_bits);
1382 if (prefix[1] == kGs && supports_rex_) {
1384 Thread::DumpThreadOffset<8>(args, address_bits);
1386 const char* prefix_str;
1387 switch (prefix[0]) {
1388 case 0xF0: prefix_str = "lock "; break;
1389 case 0xF2: prefix_str = "repne "; break;
1390 case 0xF3: prefix_str = "repe "; break;
1391 case 0: prefix_str = ""; break;
1392 default: LOG(FATAL) << "Unreachable"; UNREACHABLE();
1394 os << FormatInstructionPointer(begin_instr)
1395 << StringPrintf(": %22s \t%-7s%s%s%s%s%s ", DumpCodeHex(begin_instr, instr).c_str(),
1396 prefix_str, opcode0, opcode1, opcode2, opcode3, opcode4)
1397 << args.str() << '\n';
1398 return instr - begin_instr;
1399 } // NOLINT(readability/fn_size)