1 =============================
2 User Guide for AMDGPU Backend
3 =============================
11 The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the
12 R600 family up until the current GCN families. It lives in the
13 ``lib/Target/AMDGPU`` directory.
18 .. _amdgpu-target-triples:
23 Use the ``clang -target <Architecture>-<Vendor>-<OS>-<Environment>`` option to
24 specify the target triple:
26 .. table:: AMDGPU Architectures
27 :name: amdgpu-architecture-table
29 ============ ==============================================================
30 Architecture Description
31 ============ ==============================================================
32 ``r600`` AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders.
33 ``amdgcn`` AMD GPUs GCN GFX6 onwards for graphics and compute shaders.
34 ============ ==============================================================
36 .. table:: AMDGPU Vendors
37 :name: amdgpu-vendor-table
39 ============ ==============================================================
41 ============ ==============================================================
42 ``amd`` Can be used for all AMD GPU usage.
43 ``mesa3d`` Can be used if the OS is ``mesa3d``.
44 ============ ==============================================================
46 .. table:: AMDGPU Operating Systems
47 :name: amdgpu-os-table
49 ============== ============================================================
51 ============== ============================================================
52 *<empty>* Defaults to the *unknown* OS.
53 ``amdhsa`` Compute kernels executed on HSA [HSA]_ compatible runtimes
54 such as AMD's ROCm [AMD-ROCm]_.
55 ``amdpal`` Graphic shaders and compute kernels executed on AMD PAL
57 ``mesa3d`` Graphic shaders and compute kernels executed on Mesa 3D
59 ============== ============================================================
61 .. table:: AMDGPU Environments
62 :name: amdgpu-environment-table
64 ============ ==============================================================
65 Environment Description
66 ============ ==============================================================
68 ============ ==============================================================
70 .. _amdgpu-processors:
75 Use the ``clang -mcpu <Processor>`` option to specify the AMD GPU processor. The
76 names from both the *Processor* and *Alternative Processor* can be used.
78 .. table:: AMDGPU Processors
79 :name: amdgpu-processor-table
81 =========== =============== ============ ===== ========== ======= ======================
82 Processor Alternative Target dGPU/ Target ROCm Example
83 Processor Triple APU Features Support Products
84 Architecture Supported
86 =========== =============== ============ ===== ========== ======= ======================
87 **Radeon HD 2000/3000 Series (R600)** [AMD-RADEON-HD-2000-3000]_
88 ----------------------------------------------------------------------------------------
89 ``r600`` ``r600`` dGPU
90 ``r630`` ``r600`` dGPU
91 ``rs880`` ``r600`` dGPU
92 ``rv670`` ``r600`` dGPU
93 **Radeon HD 4000 Series (R700)** [AMD-RADEON-HD-4000]_
94 ----------------------------------------------------------------------------------------
95 ``rv710`` ``r600`` dGPU
96 ``rv730`` ``r600`` dGPU
97 ``rv770`` ``r600`` dGPU
98 **Radeon HD 5000 Series (Evergreen)** [AMD-RADEON-HD-5000]_
99 ----------------------------------------------------------------------------------------
100 ``cedar`` ``r600`` dGPU
101 ``cypress`` ``r600`` dGPU
102 ``juniper`` ``r600`` dGPU
103 ``redwood`` ``r600`` dGPU
104 ``sumo`` ``r600`` dGPU
105 **Radeon HD 6000 Series (Northern Islands)** [AMD-RADEON-HD-6000]_
106 ----------------------------------------------------------------------------------------
107 ``barts`` ``r600`` dGPU
108 ``caicos`` ``r600`` dGPU
109 ``cayman`` ``r600`` dGPU
110 ``turks`` ``r600`` dGPU
111 **GCN GFX6 (Southern Islands (SI))** [AMD-GCN-GFX6]_
112 ----------------------------------------------------------------------------------------
113 ``gfx600`` - ``tahiti`` ``amdgcn`` dGPU
114 ``gfx601`` - ``hainan`` ``amdgcn`` dGPU
118 **GCN GFX7 (Sea Islands (CI))** [AMD-GCN-GFX7]_
119 ----------------------------------------------------------------------------------------
120 ``gfx700`` - ``kaveri`` ``amdgcn`` APU - A6-7000
130 ``gfx701`` - ``hawaii`` ``amdgcn`` dGPU ROCm - FirePro W8100
134 ``gfx702`` ``amdgcn`` dGPU ROCm - Radeon R9 290
138 ``gfx703`` - ``kabini`` ``amdgcn`` APU - E1-2100
139 - ``mullins`` - E1-2200
147 ``gfx704`` - ``bonaire`` ``amdgcn`` dGPU - Radeon HD 7790
151 **GCN GFX8 (Volcanic Islands (VI))** [AMD-GCN-GFX8]_
152 ----------------------------------------------------------------------------------------
153 ``gfx801`` - ``carrizo`` ``amdgcn`` APU - xnack - A6-8500P
159 \ ``amdgcn`` APU - xnack ROCm - A10-8700P
162 \ ``amdgcn`` APU - xnack - A10-9600P
168 \ ``amdgcn`` APU - xnack - E2-9010
171 ``gfx802`` - ``iceland`` ``amdgcn`` dGPU - xnack ROCm - FirePro S7150
172 - ``tonga`` [off] - FirePro S7100
179 ``gfx803`` - ``fiji`` ``amdgcn`` dGPU - xnack ROCm - Radeon R9 Nano
180 [off] - Radeon R9 Fury
184 - Radeon Instinct MI8
185 \ - ``polaris10`` ``amdgcn`` dGPU - xnack ROCm - Radeon RX 470
186 [off] - Radeon RX 480
187 - Radeon Instinct MI6
188 \ - ``polaris11`` ``amdgcn`` dGPU - xnack ROCm - Radeon RX 460
190 ``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack
192 **GCN GFX9** [AMD-GCN-GFX9]_
193 ----------------------------------------------------------------------------------------
194 ``gfx900`` ``amdgcn`` dGPU - xnack ROCm - Radeon Vega
195 [off] Frontier Edition
200 - Radeon Instinct MI25
201 ``gfx902`` ``amdgcn`` APU - xnack - Ryzen 3 2200G
203 ``gfx904`` ``amdgcn`` dGPU - xnack *TBA*
208 ``gfx906`` ``amdgcn`` dGPU - xnack - Radeon Instinct MI50
209 [off] - Radeon Instinct MI60
210 ``gfx909`` ``amdgcn`` APU - xnack *TBA* (Raven Ridge 2)
215 =========== =============== ============ ===== ========== ======= ======================
217 .. _amdgpu-target-features:
222 Target features control how code is generated to support certain
223 processor specific features. Not all target features are supported by
224 all processors. The runtime must ensure that the features supported by
225 the device used to execute the code match the features enabled when
226 generating the code. A mismatch of features may result in incorrect
227 execution, or a reduction in performance.
229 The target features supported by each processor, and the default value
230 used if not specified explicitly, is listed in
231 :ref:`amdgpu-processor-table`.
233 Use the ``clang -m[no-]<TargetFeature>`` option to specify the AMD GPU
239 Enable the ``xnack`` feature.
241 Disable the ``xnack`` feature.
243 .. table:: AMDGPU Target Features
244 :name: amdgpu-target-feature-table
246 =============== ==================================================
247 Target Feature Description
248 =============== ==================================================
249 -m[no-]xnack Enable/disable generating code that has
250 memory clauses that are compatible with
251 having XNACK replay enabled.
253 This is used for demand paging and page
254 migration. If XNACK replay is enabled in
255 the device, then if a page fault occurs
256 the code may execute incorrectly if the
257 ``xnack`` feature is not enabled. Executing
258 code that has the feature enabled on a
259 device that does not have XNACK replay
260 enabled will execute correctly, but may
261 be less performant than code with the
263 -m[no-]sram-ecc Enable/disable generating code that assumes SRAM
264 ECC is enabled/disabled.
265 =============== ==================================================
267 .. _amdgpu-address-spaces:
272 The AMDGPU backend uses the following address space mappings.
274 The memory space names used in the table, aside from the region memory space, is
275 from the OpenCL standard.
277 LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).
279 .. table:: Address Space Mapping
280 :name: amdgpu-address-space-mapping-table
282 ================== =================================
283 LLVM Address Space Memory Space
284 ================== =================================
292 7 Buffer Fat Pointer (experimental)
293 ================== =================================
295 The buffer fat pointer is an experimental address space that is currently
296 unsupported in the backend. It exposes a non-integral pointer that is in future
297 intended to support the modelling of 128-bit buffer descriptors + a 32-bit
298 offset into the buffer descriptor (in total encapsulating a 160-bit 'pointer'),
299 allowing us to use normal LLVM load/store/atomic operations to model the buffer
300 descriptors used heavily in graphics workloads targeting the backend.
302 .. _amdgpu-memory-scopes:
307 This section provides LLVM memory synchronization scopes supported by the AMDGPU
308 backend memory model when the target triple OS is ``amdhsa`` (see
309 :ref:`amdgpu-amdhsa-memory-model` and :ref:`amdgpu-target-triples`).
311 The memory model supported is based on the HSA memory model [HSA]_ which is
312 based in turn on HRF-indirect with scope inclusion [HRF]_. The happens-before
313 relation is transitive over the synchonizes-with relation independent of scope,
314 and synchonizes-with allows the memory scope instances to be inclusive (see
315 table :ref:`amdgpu-amdhsa-llvm-sync-scopes-table`).
317 This is different to the OpenCL [OpenCL]_ memory model which does not have scope
318 inclusion and requires the memory scopes to exactly match. However, this
319 is conservatively correct for OpenCL.
321 .. table:: AMDHSA LLVM Sync Scopes
322 :name: amdgpu-amdhsa-llvm-sync-scopes-table
324 ======================= ===================================================
325 LLVM Sync Scope Description
326 ======================= ===================================================
327 *none* The default: ``system``.
329 Synchronizes with, and participates in modification
330 and seq_cst total orderings with, other operations
331 (except image operations) for all address spaces
332 (except private, or generic that accesses private)
333 provided the other operation's sync scope is:
336 - ``agent`` and executed by a thread on the same
338 - ``workgroup`` and executed by a thread in the
340 - ``wavefront`` and executed by a thread in the
343 ``agent`` Synchronizes with, and participates in modification
344 and seq_cst total orderings with, other operations
345 (except image operations) for all address spaces
346 (except private, or generic that accesses private)
347 provided the other operation's sync scope is:
349 - ``system`` or ``agent`` and executed by a thread
351 - ``workgroup`` and executed by a thread in the
353 - ``wavefront`` and executed by a thread in the
356 ``workgroup`` Synchronizes with, and participates in modification
357 and seq_cst total orderings with, other operations
358 (except image operations) for all address spaces
359 (except private, or generic that accesses private)
360 provided the other operation's sync scope is:
362 - ``system``, ``agent`` or ``workgroup`` and
363 executed by a thread in the same workgroup.
364 - ``wavefront`` and executed by a thread in the
367 ``wavefront`` Synchronizes with, and participates in modification
368 and seq_cst total orderings with, other operations
369 (except image operations) for all address spaces
370 (except private, or generic that accesses private)
371 provided the other operation's sync scope is:
373 - ``system``, ``agent``, ``workgroup`` or
374 ``wavefront`` and executed by a thread in the
377 ``singlethread`` Only synchronizes with, and participates in
378 modification and seq_cst total orderings with,
379 other operations (except image operations) running
380 in the same thread for all address spaces (for
381 example, in signal handlers).
383 ``one-as`` Same as ``system`` but only synchronizes with other
384 operations within the same address space.
386 ``agent-one-as`` Same as ``agent`` but only synchronizes with other
387 operations within the same address space.
389 ``workgroup-one-as`` Same as ``workgroup`` but only synchronizes with
390 other operations within the same address space.
392 ``wavefront-one-as`` Same as ``wavefront`` but only synchronizes with
393 other operations within the same address space.
395 ``singlethread-one-as`` Same as ``singlethread`` but only synchronizes with
396 other operations within the same address space.
397 ======================= ===================================================
402 The AMDGPU backend implements the following LLVM IR intrinsics.
404 *This section is WIP.*
407 List AMDGPU intrinsics
412 The AMDGPU backend supports the following LLVM IR attributes.
414 .. table:: AMDGPU LLVM IR Attributes
415 :name: amdgpu-llvm-ir-attributes-table
417 ======================================= ==========================================================
418 LLVM Attribute Description
419 ======================================= ==========================================================
420 "amdgpu-flat-work-group-size"="min,max" Specify the minimum and maximum flat work group sizes that
421 will be specified when the kernel is dispatched. Generated
422 by the ``amdgpu_flat_work_group_size`` CLANG attribute [CLANG-ATTR]_.
423 "amdgpu-implicitarg-num-bytes"="n" Number of kernel argument bytes to add to the kernel
424 argument block size for the implicit arguments. This
425 varies by OS and language (for OpenCL see
426 :ref:`opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table`).
427 "amdgpu-max-work-group-size"="n" Specify the maximum work-group size that will be specifed
428 when the kernel is dispatched.
429 "amdgpu-num-sgpr"="n" Specifies the number of SGPRs to use. Generated by
430 the ``amdgpu_num_sgpr`` CLANG attribute [CLANG-ATTR]_.
431 "amdgpu-num-vgpr"="n" Specifies the number of VGPRs to use. Generated by the
432 ``amdgpu_num_vgpr`` CLANG attribute [CLANG-ATTR]_.
433 "amdgpu-waves-per-eu"="m,n" Specify the minimum and maximum number of waves per
434 execution unit. Generated by the ``amdgpu_waves_per_eu``
435 CLANG attribute [CLANG-ATTR]_.
436 ======================================= ==========================================================
441 The AMDGPU backend generates a standard ELF [ELF]_ relocatable code object that
442 can be linked by ``lld`` to produce a standard ELF shared code object which can
443 be loaded and executed on an AMDGPU target.
448 The AMDGPU backend uses the following ELF header:
450 .. table:: AMDGPU ELF Header
451 :name: amdgpu-elf-header-table
453 ========================== ===============================
455 ========================== ===============================
456 ``e_ident[EI_CLASS]`` ``ELFCLASS64``
457 ``e_ident[EI_DATA]`` ``ELFDATA2LSB``
458 ``e_ident[EI_OSABI]`` - ``ELFOSABI_NONE``
459 - ``ELFOSABI_AMDGPU_HSA``
460 - ``ELFOSABI_AMDGPU_PAL``
461 - ``ELFOSABI_AMDGPU_MESA3D``
462 ``e_ident[EI_ABIVERSION]`` - ``ELFABIVERSION_AMDGPU_HSA``
463 - ``ELFABIVERSION_AMDGPU_PAL``
464 - ``ELFABIVERSION_AMDGPU_MESA3D``
465 ``e_type`` - ``ET_REL``
467 ``e_machine`` ``EM_AMDGPU``
469 ``e_flags`` See :ref:`amdgpu-elf-header-e_flags-table`
470 ========================== ===============================
474 .. table:: AMDGPU ELF Header Enumeration Values
475 :name: amdgpu-elf-header-enumeration-values-table
477 =============================== =====
479 =============================== =====
482 ``ELFOSABI_AMDGPU_HSA`` 64
483 ``ELFOSABI_AMDGPU_PAL`` 65
484 ``ELFOSABI_AMDGPU_MESA3D`` 66
485 ``ELFABIVERSION_AMDGPU_HSA`` 1
486 ``ELFABIVERSION_AMDGPU_PAL`` 0
487 ``ELFABIVERSION_AMDGPU_MESA3D`` 0
488 =============================== =====
490 ``e_ident[EI_CLASS]``
493 * ``ELFCLASS32`` for ``r600`` architecture.
495 * ``ELFCLASS64`` for ``amdgcn`` architecture which only supports 64
499 All AMDGPU targets use ``ELFDATA2LSB`` for little-endian byte ordering.
501 ``e_ident[EI_OSABI]``
502 One of the following AMD GPU architecture specific OS ABIs
503 (see :ref:`amdgpu-os-table`):
505 * ``ELFOSABI_NONE`` for *unknown* OS.
507 * ``ELFOSABI_AMDGPU_HSA`` for ``amdhsa`` OS.
509 * ``ELFOSABI_AMDGPU_PAL`` for ``amdpal`` OS.
511 * ``ELFOSABI_AMDGPU_MESA3D`` for ``mesa3D`` OS.
513 ``e_ident[EI_ABIVERSION]``
514 The ABI version of the AMD GPU architecture specific OS ABI to which the code
517 * ``ELFABIVERSION_AMDGPU_HSA`` is used to specify the version of AMD HSA
520 * ``ELFABIVERSION_AMDGPU_PAL`` is used to specify the version of AMD PAL
523 * ``ELFABIVERSION_AMDGPU_MESA3D`` is used to specify the version of AMD MESA
527 Can be one of the following values:
531 The type produced by the AMD GPU backend compiler as it is relocatable code
535 The type produced by the linker as it is a shared code object.
537 The AMD HSA runtime loader requires a ``ET_DYN`` code object.
540 The value ``EM_AMDGPU`` is used for the machine for all processors supported
541 by the ``r600`` and ``amdgcn`` architectures (see
542 :ref:`amdgpu-processor-table`). The specific processor is specified in the
543 ``EF_AMDGPU_MACH`` bit field of the ``e_flags`` (see
544 :ref:`amdgpu-elf-header-e_flags-table`).
547 The entry point is 0 as the entry points for individual kernels must be
548 selected in order to invoke them through AQL packets.
551 The AMDGPU backend uses the following ELF header flags:
553 .. table:: AMDGPU ELF Header ``e_flags``
554 :name: amdgpu-elf-header-e_flags-table
556 ================================= ========== =============================
557 Name Value Description
558 ================================= ========== =============================
559 **AMDGPU Processor Flag** See :ref:`amdgpu-processor-table`.
560 -------------------------------------------- -----------------------------
561 ``EF_AMDGPU_MACH`` 0x000000ff AMDGPU processor selection
563 ``EF_AMDGPU_MACH_xxx`` values
565 :ref:`amdgpu-ef-amdgpu-mach-table`.
566 ``EF_AMDGPU_XNACK`` 0x00000100 Indicates if the ``xnack``
569 contained in the code object.
576 :ref:`amdgpu-target-features`.
577 ``EF_AMDGPU_SRAM_ECC`` 0x00000200 Indicates if the ``sram-ecc``
580 contained in the code object.
587 :ref:`amdgpu-target-features`.
588 ================================= ========== =============================
590 .. table:: AMDGPU ``EF_AMDGPU_MACH`` Values
591 :name: amdgpu-ef-amdgpu-mach-table
593 ================================= ========== =============================
594 Name Value Description (see
595 :ref:`amdgpu-processor-table`)
596 ================================= ========== =============================
597 ``EF_AMDGPU_MACH_NONE`` 0x000 *not specified*
598 ``EF_AMDGPU_MACH_R600_R600`` 0x001 ``r600``
599 ``EF_AMDGPU_MACH_R600_R630`` 0x002 ``r630``
600 ``EF_AMDGPU_MACH_R600_RS880`` 0x003 ``rs880``
601 ``EF_AMDGPU_MACH_R600_RV670`` 0x004 ``rv670``
602 ``EF_AMDGPU_MACH_R600_RV710`` 0x005 ``rv710``
603 ``EF_AMDGPU_MACH_R600_RV730`` 0x006 ``rv730``
604 ``EF_AMDGPU_MACH_R600_RV770`` 0x007 ``rv770``
605 ``EF_AMDGPU_MACH_R600_CEDAR`` 0x008 ``cedar``
606 ``EF_AMDGPU_MACH_R600_CYPRESS`` 0x009 ``cypress``
607 ``EF_AMDGPU_MACH_R600_JUNIPER`` 0x00a ``juniper``
608 ``EF_AMDGPU_MACH_R600_REDWOOD`` 0x00b ``redwood``
609 ``EF_AMDGPU_MACH_R600_SUMO`` 0x00c ``sumo``
610 ``EF_AMDGPU_MACH_R600_BARTS`` 0x00d ``barts``
611 ``EF_AMDGPU_MACH_R600_CAICOS`` 0x00e ``caicos``
612 ``EF_AMDGPU_MACH_R600_CAYMAN`` 0x00f ``cayman``
613 ``EF_AMDGPU_MACH_R600_TURKS`` 0x010 ``turks``
614 *reserved* 0x011 - Reserved for ``r600``
615 0x01f architecture processors.
616 ``EF_AMDGPU_MACH_AMDGCN_GFX600`` 0x020 ``gfx600``
617 ``EF_AMDGPU_MACH_AMDGCN_GFX601`` 0x021 ``gfx601``
618 ``EF_AMDGPU_MACH_AMDGCN_GFX700`` 0x022 ``gfx700``
619 ``EF_AMDGPU_MACH_AMDGCN_GFX701`` 0x023 ``gfx701``
620 ``EF_AMDGPU_MACH_AMDGCN_GFX702`` 0x024 ``gfx702``
621 ``EF_AMDGPU_MACH_AMDGCN_GFX703`` 0x025 ``gfx703``
622 ``EF_AMDGPU_MACH_AMDGCN_GFX704`` 0x026 ``gfx704``
623 *reserved* 0x027 Reserved.
624 ``EF_AMDGPU_MACH_AMDGCN_GFX801`` 0x028 ``gfx801``
625 ``EF_AMDGPU_MACH_AMDGCN_GFX802`` 0x029 ``gfx802``
626 ``EF_AMDGPU_MACH_AMDGCN_GFX803`` 0x02a ``gfx803``
627 ``EF_AMDGPU_MACH_AMDGCN_GFX810`` 0x02b ``gfx810``
628 ``EF_AMDGPU_MACH_AMDGCN_GFX900`` 0x02c ``gfx900``
629 ``EF_AMDGPU_MACH_AMDGCN_GFX902`` 0x02d ``gfx902``
630 ``EF_AMDGPU_MACH_AMDGCN_GFX904`` 0x02e ``gfx904``
631 ``EF_AMDGPU_MACH_AMDGCN_GFX906`` 0x02f ``gfx906``
632 *reserved* 0x030 Reserved.
633 ``EF_AMDGPU_MACH_AMDGCN_GFX909`` 0x031 ``gfx909``
634 ================================= ========== =============================
639 An AMDGPU target ELF code object has the standard ELF sections which include:
641 .. table:: AMDGPU ELF Sections
642 :name: amdgpu-elf-sections-table
644 ================== ================ =================================
646 ================== ================ =================================
647 ``.bss`` ``SHT_NOBITS`` ``SHF_ALLOC`` + ``SHF_WRITE``
648 ``.data`` ``SHT_PROGBITS`` ``SHF_ALLOC`` + ``SHF_WRITE``
649 ``.debug_``\ *\** ``SHT_PROGBITS`` *none*
650 ``.dynamic`` ``SHT_DYNAMIC`` ``SHF_ALLOC``
651 ``.dynstr`` ``SHT_PROGBITS`` ``SHF_ALLOC``
652 ``.dynsym`` ``SHT_PROGBITS`` ``SHF_ALLOC``
653 ``.got`` ``SHT_PROGBITS`` ``SHF_ALLOC`` + ``SHF_WRITE``
654 ``.hash`` ``SHT_HASH`` ``SHF_ALLOC``
655 ``.note`` ``SHT_NOTE`` *none*
656 ``.rela``\ *name* ``SHT_RELA`` *none*
657 ``.rela.dyn`` ``SHT_RELA`` *none*
658 ``.rodata`` ``SHT_PROGBITS`` ``SHF_ALLOC``
659 ``.shstrtab`` ``SHT_STRTAB`` *none*
660 ``.strtab`` ``SHT_STRTAB`` *none*
661 ``.symtab`` ``SHT_SYMTAB`` *none*
662 ``.text`` ``SHT_PROGBITS`` ``SHF_ALLOC`` + ``SHF_EXECINSTR``
663 ================== ================ =================================
665 These sections have their standard meanings (see [ELF]_) and are only generated
669 The standard DWARF sections. See :ref:`amdgpu-dwarf` for information on the
670 DWARF produced by the AMDGPU backend.
672 ``.dynamic``, ``.dynstr``, ``.dynsym``, ``.hash``
673 The standard sections used by a dynamic loader.
676 See :ref:`amdgpu-note-records` for the note records supported by the AMDGPU
679 ``.rela``\ *name*, ``.rela.dyn``
680 For relocatable code objects, *name* is the name of the section that the
681 relocation records apply. For example, ``.rela.text`` is the section name for
682 relocation records associated with the ``.text`` section.
684 For linked shared code objects, ``.rela.dyn`` contains all the relocation
685 records from each of the relocatable code object's ``.rela``\ *name* sections.
687 See :ref:`amdgpu-relocation-records` for the relocation records supported by
691 The executable machine code for the kernels and functions they call. Generated
692 as position independent code. See :ref:`amdgpu-code-conventions` for
693 information on conventions used in the isa generation.
695 .. _amdgpu-note-records:
700 The AMDGPU backend code object contains ELF note records in the ``.note``
701 section. The set of generated notes and their semantics depend on the code
702 object version; see :ref:`amdgpu-note-records-v2` and
703 :ref:`amdgpu-note-records-v3`.
705 As required by ``ELFCLASS32`` and ``ELFCLASS64``, minimal zero byte padding
706 must be generated after the ``name`` field to ensure the ``desc`` field is 4
707 byte aligned. In addition, minimal zero byte padding must be generated to
708 ensure the ``desc`` field size is a multiple of 4 bytes. The ``sh_addralign``
709 field of the ``.note`` section must be at least 4 to indicate at least 8 byte
712 .. _amdgpu-note-records-v2:
714 Code Object V2 Note Records (-mattr=-code-object-v3)
715 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
717 .. warning:: Code Object V2 is not the default code object version emitted by
718 this version of LLVM. For a description of the notes generated with the
719 default configuration (Code Object V3) see :ref:`amdgpu-note-records-v3`.
721 The AMDGPU backend code object uses the following ELF note record in the
722 ``.note`` section when compiling for Code Object V2 (-mattr=-code-object-v3).
724 Additional note records may be present, but any which are not documented here
725 are deprecated and should not be used.
727 .. table:: AMDGPU Code Object V2 ELF Note Records
728 :name: amdgpu-elf-note-records-table-v2
730 ===== ============================== ======================================
731 Name Type Description
732 ===== ============================== ======================================
733 "AMD" ``NT_AMD_AMDGPU_HSA_METADATA`` <metadata null terminated string>
734 ===== ============================== ======================================
738 .. table:: AMDGPU Code Object V2 ELF Note Record Enumeration Values
739 :name: amdgpu-elf-note-record-enumeration-values-table-v2
741 ============================== =====
743 ============================== =====
745 ``NT_AMD_AMDGPU_HSA_METADATA`` 10
747 ============================== =====
749 ``NT_AMD_AMDGPU_HSA_METADATA``
750 Specifies extensible metadata associated with the code objects executed on HSA
751 [HSA]_ compatible runtimes such as AMD's ROCm [AMD-ROCm]_. It is required when
752 the target triple OS is ``amdhsa`` (see :ref:`amdgpu-target-triples`). See
753 :ref:`amdgpu-amdhsa-code-object-metadata-v2` for the syntax of the code
754 object metadata string.
756 .. _amdgpu-note-records-v3:
758 Code Object V3 Note Records (-mattr=+code-object-v3)
759 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
761 The AMDGPU backend code object uses the following ELF note record in the
762 ``.note`` section when compiling for Code Object V3 (-mattr=+code-object-v3).
764 Additional note records may be present, but any which are not documented here
765 are deprecated and should not be used.
767 .. table:: AMDGPU Code Object V3 ELF Note Records
768 :name: amdgpu-elf-note-records-table-v3
770 ======== ============================== ======================================
771 Name Type Description
772 ======== ============================== ======================================
773 "AMDGPU" ``NT_AMDGPU_METADATA`` Metadata in Message Pack [MsgPack]_
775 ======== ============================== ======================================
779 .. table:: AMDGPU Code Object V3 ELF Note Record Enumeration Values
780 :name: amdgpu-elf-note-record-enumeration-values-table-v3
782 ============================== =====
784 ============================== =====
786 ``NT_AMDGPU_METADATA`` 32
787 ============================== =====
789 ``NT_AMDGPU_METADATA``
790 Specifies extensible metadata associated with an AMDGPU code
791 object. It is encoded as a map in the Message Pack [MsgPack]_ binary
792 data format. See :ref:`amdgpu-amdhsa-code-object-metadata-v3` for the
793 map keys defined for the ``amdhsa`` OS.
800 Symbols include the following:
802 .. table:: AMDGPU ELF Symbols
803 :name: amdgpu-elf-symbols-table
805 ===================== ============== ============= ==================
806 Name Type Section Description
807 ===================== ============== ============= ==================
808 *link-name* ``STT_OBJECT`` - ``.data`` Global variable
811 *link-name*\ ``.kd`` ``STT_OBJECT`` - ``.rodata`` Kernel descriptor
812 *link-name* ``STT_FUNC`` - ``.text`` Kernel entry point
813 ===================== ============== ============= ==================
816 Global variables both used and defined by the compilation unit.
818 If the symbol is defined in the compilation unit then it is allocated in the
819 appropriate section according to if it has initialized data or is readonly.
821 If the symbol is external then its section is ``STN_UNDEF`` and the loader
822 will resolve relocations using the definition provided by another code object
823 or explicitly defined by the runtime.
825 All global symbols, whether defined in the compilation unit or external, are
826 accessed by the machine code indirectly through a GOT table entry. This
827 allows them to be preemptable. The GOT table is only supported when the target
828 triple OS is ``amdhsa`` (see :ref:`amdgpu-target-triples`).
831 Add description of linked shared object symbols. Seems undefined symbols
832 are marked as STT_NOTYPE.
835 Every HSA kernel has an associated kernel descriptor. It is the address of the
836 kernel descriptor that is used in the AQL dispatch packet used to invoke the
837 kernel, not the kernel entry point. The layout of the HSA kernel descriptor is
838 defined in :ref:`amdgpu-amdhsa-kernel-descriptor`.
841 Every HSA kernel also has a symbol for its machine code entry point.
843 .. _amdgpu-relocation-records:
848 AMDGPU backend generates ``Elf64_Rela`` relocation records. Supported
849 relocatable fields are:
852 This specifies a 32-bit field occupying 4 bytes with arbitrary byte
853 alignment. These values use the same byte order as other word values in the
854 AMD GPU architecture.
857 This specifies a 64-bit field occupying 8 bytes with arbitrary byte
858 alignment. These values use the same byte order as other word values in the
859 AMD GPU architecture.
861 Following notations are used for specifying relocation calculations:
864 Represents the addend used to compute the value of the relocatable field.
867 Represents the offset into the global offset table at which the relocation
868 entry's symbol will reside during execution.
871 Represents the address of the global offset table.
874 Represents the place (section offset for ``et_rel`` or address for ``et_dyn``)
875 of the storage unit being relocated (computed using ``r_offset``).
878 Represents the value of the symbol whose index resides in the relocation
879 entry. Relocations not using this must specify a symbol index of ``STN_UNDEF``.
882 Represents the base address of a loaded executable or shared object which is
883 the difference between the ELF address and the actual load address. Relocations
884 using this are only valid in executable or shared objects.
886 The following relocation types are supported:
888 .. table:: AMDGPU ELF Relocation Records
889 :name: amdgpu-elf-relocation-records-table
891 ========================== ======= ===== ========== ==============================
892 Relocation Type Kind Value Field Calculation
893 ========================== ======= ===== ========== ==============================
894 ``R_AMDGPU_NONE`` 0 *none* *none*
895 ``R_AMDGPU_ABS32_LO`` Static, 1 ``word32`` (S + A) & 0xFFFFFFFF
897 ``R_AMDGPU_ABS32_HI`` Static, 2 ``word32`` (S + A) >> 32
899 ``R_AMDGPU_ABS64`` Static, 3 ``word64`` S + A
901 ``R_AMDGPU_REL32`` Static 4 ``word32`` S + A - P
902 ``R_AMDGPU_REL64`` Static 5 ``word64`` S + A - P
903 ``R_AMDGPU_ABS32`` Static, 6 ``word32`` S + A
905 ``R_AMDGPU_GOTPCREL`` Static 7 ``word32`` G + GOT + A - P
906 ``R_AMDGPU_GOTPCREL32_LO`` Static 8 ``word32`` (G + GOT + A - P) & 0xFFFFFFFF
907 ``R_AMDGPU_GOTPCREL32_HI`` Static 9 ``word32`` (G + GOT + A - P) >> 32
908 ``R_AMDGPU_REL32_LO`` Static 10 ``word32`` (S + A - P) & 0xFFFFFFFF
909 ``R_AMDGPU_REL32_HI`` Static 11 ``word32`` (S + A - P) >> 32
911 ``R_AMDGPU_RELATIVE64`` Dynamic 13 ``word64`` B + A
912 ========================== ======= ===== ========== ==============================
914 ``R_AMDGPU_ABS32_LO`` and ``R_AMDGPU_ABS32_HI`` are only supported by
915 the ``mesa3d`` OS, which does not support ``R_AMDGPU_ABS64``.
917 There is no current OS loader support for 32 bit programs and so
918 ``R_AMDGPU_ABS32`` is not used.
925 Standard DWARF [DWARF]_ Version 5 sections can be generated. These contain
926 information that maps the code object executable code and data to the source
927 language constructs. It can be used by tools such as debuggers and profilers.
929 Address Space Mapping
930 ~~~~~~~~~~~~~~~~~~~~~
932 The following address space mapping is used:
934 .. table:: AMDGPU DWARF Address Space Mapping
935 :name: amdgpu-dwarf-address-space-mapping-table
937 =================== =================
938 DWARF Address Space Memory Space
939 =================== =================
944 *omitted* Generic (Flat)
945 *not supported* Region (GDS)
946 =================== =================
948 See :ref:`amdgpu-address-spaces` for information on the memory space terminology
951 An ``address_class`` attribute is generated on pointer type DIEs to specify the
952 DWARF address space of the value of the pointer when it is in the *private* or
953 *local* address space. Otherwise the attribute is omitted.
955 An ``XDEREF`` operation is generated in location list expressions for variables
956 that are allocated in the *private* and *local* address space. Otherwise no
957 ``XDREF`` is omitted.
962 *This section is WIP.*
965 Define DWARF register enumeration.
967 If want to present a wavefront state then should expose vector registers as
968 64 wide (rather than per work-item view that LLVM uses). Either as separate
969 registers, or a 64x4 byte single register. In either case use a new LANE op
970 (akin to XDREF) to select the current lane usage in a location
971 expression. This would also allow scalar register spilling to vector register
972 lanes to be expressed (currently no debug information is being generated for
973 spilling). If choose a wide single register approach then use LANE in
974 conjunction with PIECE operation to select the dword part of the register for
975 the current lane. If the separate register approach then use LANE to select
981 Source text for online-compiled programs (e.g. those compiled by the OpenCL
982 runtime) may be embedded into the DWARF v5 line table using the ``clang
983 -gembed-source`` option, described in table :ref:`amdgpu-debug-options`.
988 Enable the embedded source DWARF v5 extension.
989 ``-gno-embed-source``
990 Disable the embedded source DWARF v5 extension.
992 .. table:: AMDGPU Debug Options
993 :name: amdgpu-debug-options
995 ==================== ==================================================
996 Debug Flag Description
997 ==================== ==================================================
998 -g[no-]embed-source Enable/disable embedding source text in DWARF
999 debug sections. Useful for environments where
1000 source cannot be written to disk, such as
1001 when performing online compilation.
1002 ==================== ==================================================
1004 This option enables one extended content types in the DWARF v5 Line Number
1005 Program Header, which is used to encode embedded source.
1007 .. table:: AMDGPU DWARF Line Number Program Header Extended Content Types
1008 :name: amdgpu-dwarf-extended-content-types
1010 ============================ ======================
1012 ============================ ======================
1013 ``DW_LNCT_LLVM_source`` ``DW_FORM_line_strp``
1014 ============================ ======================
1016 The source field will contain the UTF-8 encoded, null-terminated source text
1017 with ``'\n'`` line endings. When the source field is present, consumers can use
1018 the embedded source instead of attempting to discover the source on disk. When
1019 the source field is absent, consumers can access the file to get the source
1022 The above content type appears in the ``file_name_entry_format`` field of the
1023 line table prologue, and its corresponding value appear in the ``file_names``
1024 field. The current encoding of the content type is documented in table
1025 :ref:`amdgpu-dwarf-extended-content-types-encoding`
1027 .. table:: AMDGPU DWARF Line Number Program Header Extended Content Types Encoding
1028 :name: amdgpu-dwarf-extended-content-types-encoding
1030 ============================ ====================
1032 ============================ ====================
1033 ``DW_LNCT_LLVM_source`` 0x2001
1034 ============================ ====================
1036 .. _amdgpu-code-conventions:
1041 This section provides code conventions used for each supported target triple OS
1042 (see :ref:`amdgpu-target-triples`).
1047 This section provides code conventions used when the target triple OS is
1048 ``amdhsa`` (see :ref:`amdgpu-target-triples`).
1050 .. _amdgpu-amdhsa-code-object-target-identification:
1052 Code Object Target Identification
1053 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1055 The AMDHSA OS uses the following syntax to specify the code object
1056 target as a single string:
1058 ``<Architecture>-<Vendor>-<OS>-<Environment>-<Processor><Target Features>``
1062 - ``<Architecture>``, ``<Vendor>``, ``<OS>`` and ``<Environment>``
1063 are the same as the *Target Triple* (see
1064 :ref:`amdgpu-target-triples`).
1066 - ``<Processor>`` is the same as the *Processor* (see
1067 :ref:`amdgpu-processors`).
1069 - ``<Target Features>`` is a list of the enabled *Target Features*
1070 (see :ref:`amdgpu-target-features`), each prefixed by a plus, that
1071 apply to *Processor*. The list must be in the same order as listed
1072 in the table :ref:`amdgpu-target-feature-table`. Note that *Target
1073 Features* must be included in the list if they are enabled even if
1074 that is the default for *Processor*.
1078 ``"amdgcn-amd-amdhsa--gfx902+xnack"``
1080 .. _amdgpu-amdhsa-code-object-metadata:
1082 Code Object Metadata
1083 ~~~~~~~~~~~~~~~~~~~~
1085 The code object metadata specifies extensible metadata associated with the code
1086 objects executed on HSA [HSA]_ compatible runtimes such as AMD's ROCm
1087 [AMD-ROCm]_. The encoding and semantics of this metadata depends on the code
1088 object version; see :ref:`amdgpu-amdhsa-code-object-metadata-v2` and
1089 :ref:`amdgpu-amdhsa-code-object-metadata-v3`.
1091 Code object metadata is specified in a note record (see
1092 :ref:`amdgpu-note-records`) and is required when the target triple OS is
1093 ``amdhsa`` (see :ref:`amdgpu-target-triples`). It must contain the minimum
1094 information necessary to support the ROCM kernel queries. For example, the
1095 segment sizes needed in a dispatch packet. In addition, a high level language
1096 runtime may require other information to be included. For example, the AMD
1097 OpenCL runtime records kernel argument information.
1099 .. _amdgpu-amdhsa-code-object-metadata-v2:
1101 Code Object V2 Metadata (-mattr=-code-object-v3)
1102 ++++++++++++++++++++++++++++++++++++++++++++++++
1104 .. warning:: Code Object V2 is not the default code object version emitted by
1105 this version of LLVM. For a description of the metadata generated with the
1106 default configuration (Code Object V3) see
1107 :ref:`amdgpu-amdhsa-code-object-metadata-v3`.
1109 Code object V2 metadata is specified by the ``NT_AMD_AMDGPU_METADATA`` note
1110 record (see :ref:`amdgpu-note-records-v2`).
1112 The metadata is specified as a YAML formatted string (see [YAML]_ and
1116 Is the string null terminated? It probably should not if YAML allows it to
1117 contain null characters, otherwise it should be.
1119 The metadata is represented as a single YAML document comprised of the mapping
1120 defined in table :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v2` and
1123 For boolean values, the string values of ``false`` and ``true`` are used for
1124 false and true respectively.
1126 Additional information can be added to the mappings. To avoid conflicts, any
1127 non-AMD key names should be prefixed by "*vendor-name*.".
1129 .. table:: AMDHSA Code Object V2 Metadata Map
1130 :name: amdgpu-amdhsa-code-object-metadata-map-table-v2
1132 ========== ============== ========= =======================================
1133 String Key Value Type Required? Description
1134 ========== ============== ========= =======================================
1135 "Version" sequence of Required - The first integer is the major
1136 2 integers version. Currently 1.
1137 - The second integer is the minor
1138 version. Currently 0.
1139 "Printf" sequence of Each string is encoded information
1140 strings about a printf function call. The
1141 encoded information is organized as
1142 fields separated by colon (':'):
1144 ``ID:N:S[0]:S[1]:...:S[N-1]:FormatString``
1149 A 32 bit integer as a unique id for
1150 each printf function call
1153 A 32 bit integer equal to the number
1154 of arguments of printf function call
1157 ``S[i]`` (where i = 0, 1, ... , N-1)
1158 32 bit integers for the size in bytes
1159 of the i-th FormatString argument of
1160 the printf function call
1163 The format string passed to the
1164 printf function call.
1165 "Kernels" sequence of Required Sequence of the mappings for each
1166 mapping kernel in the code object. See
1167 :ref:`amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2`
1168 for the definition of the mapping.
1169 ========== ============== ========= =======================================
1173 .. table:: AMDHSA Code Object V2 Kernel Metadata Map
1174 :name: amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2
1176 ================= ============== ========= ================================
1177 String Key Value Type Required? Description
1178 ================= ============== ========= ================================
1179 "Name" string Required Source name of the kernel.
1180 "SymbolName" string Required Name of the kernel
1181 descriptor ELF symbol.
1182 "Language" string Source language of the kernel.
1190 "LanguageVersion" sequence of - The first integer is the major
1192 - The second integer is the
1194 "Attrs" mapping Mapping of kernel attributes.
1196 :ref:`amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2`
1197 for the mapping definition.
1198 "Args" sequence of Sequence of mappings of the
1199 mapping kernel arguments. See
1200 :ref:`amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2`
1201 for the definition of the mapping.
1202 "CodeProps" mapping Mapping of properties related to
1203 the kernel code. See
1204 :ref:`amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2`
1205 for the mapping definition.
1206 ================= ============== ========= ================================
1210 .. table:: AMDHSA Code Object V2 Kernel Attribute Metadata Map
1211 :name: amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2
1213 =================== ============== ========= ==============================
1214 String Key Value Type Required? Description
1215 =================== ============== ========= ==============================
1216 "ReqdWorkGroupSize" sequence of If not 0, 0, 0 then all values
1217 3 integers must be >=1 and the dispatch
1218 work-group size X, Y, Z must
1219 correspond to the specified
1220 values. Defaults to 0, 0, 0.
1222 Corresponds to the OpenCL
1223 ``reqd_work_group_size``
1225 "WorkGroupSizeHint" sequence of The dispatch work-group size
1226 3 integers X, Y, Z is likely to be the
1229 Corresponds to the OpenCL
1230 ``work_group_size_hint``
1232 "VecTypeHint" string The name of a scalar or vector
1235 Corresponds to the OpenCL
1236 ``vec_type_hint`` attribute.
1238 "RuntimeHandle" string The external symbol name
1239 associated with a kernel.
1240 OpenCL runtime allocates a
1241 global buffer for the symbol
1242 and saves the kernel's address
1243 to it, which is used for
1244 device side enqueueing. Only
1245 available for device side
1247 =================== ============== ========= ==============================
1251 .. table:: AMDHSA Code Object V2 Kernel Argument Metadata Map
1252 :name: amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2
1254 ================= ============== ========= ================================
1255 String Key Value Type Required? Description
1256 ================= ============== ========= ================================
1257 "Name" string Kernel argument name.
1258 "TypeName" string Kernel argument type name.
1259 "Size" integer Required Kernel argument size in bytes.
1260 "Align" integer Required Kernel argument alignment in
1261 bytes. Must be a power of two.
1262 "ValueKind" string Required Kernel argument kind that
1263 specifies how to set up the
1264 corresponding argument.
1268 The argument is copied
1269 directly into the kernarg.
1272 A global address space pointer
1273 to the buffer data is passed
1276 "DynamicSharedPointer"
1277 A group address space pointer
1278 to dynamically allocated LDS
1279 is passed in the kernarg.
1282 A global address space
1283 pointer to a S# is passed in
1287 A global address space
1288 pointer to a T# is passed in
1292 A global address space pointer
1293 to an OpenCL pipe is passed in
1297 A global address space pointer
1298 to an OpenCL device enqueue
1299 queue is passed in the
1302 "HiddenGlobalOffsetX"
1303 The OpenCL grid dispatch
1304 global offset for the X
1305 dimension is passed in the
1308 "HiddenGlobalOffsetY"
1309 The OpenCL grid dispatch
1310 global offset for the Y
1311 dimension is passed in the
1314 "HiddenGlobalOffsetZ"
1315 The OpenCL grid dispatch
1316 global offset for the Z
1317 dimension is passed in the
1321 An argument that is not used
1322 by the kernel. Space needs to
1323 be left for it, but it does
1324 not need to be set up.
1326 "HiddenPrintfBuffer"
1327 A global address space pointer
1328 to the runtime printf buffer
1329 is passed in kernarg.
1331 "HiddenDefaultQueue"
1332 A global address space pointer
1333 to the OpenCL device enqueue
1334 queue that should be used by
1335 the kernel by default is
1336 passed in the kernarg.
1338 "HiddenCompletionAction"
1339 A global address space pointer
1340 to help link enqueued kernels into
1341 the ancestor tree for determining
1342 when the parent kernel has finished.
1344 "ValueType" string Required Kernel argument value type. Only
1345 present if "ValueKind" is
1346 "ByValue". For vector data
1347 types, the value is for the
1348 element type. Values include:
1364 How can it be determined if a
1365 vector type, and what size
1367 "PointeeAlign" integer Alignment in bytes of pointee
1368 type for pointer type kernel
1369 argument. Must be a power
1370 of 2. Only present if
1372 "DynamicSharedPointer".
1373 "AddrSpaceQual" string Kernel argument address space
1374 qualifier. Only present if
1375 "ValueKind" is "GlobalBuffer" or
1376 "DynamicSharedPointer". Values
1387 Is GlobalBuffer only Global
1389 DynamicSharedPointer always
1390 Local? Can HCC allow Generic?
1391 How can Private or Region
1393 "AccQual" string Kernel argument access
1394 qualifier. Only present if
1395 "ValueKind" is "Image" or
1406 "ActualAccQual" string The actual memory accesses
1407 performed by the kernel on the
1408 kernel argument. Only present if
1409 "ValueKind" is "GlobalBuffer",
1410 "Image", or "Pipe". This may be
1411 more restrictive than indicated
1412 by "AccQual" to reflect what the
1413 kernel actual does. If not
1414 present then the runtime must
1415 assume what is implied by
1416 "AccQual" and "IsConst". Values
1423 "IsConst" boolean Indicates if the kernel argument
1424 is const qualified. Only present
1428 "IsRestrict" boolean Indicates if the kernel argument
1429 is restrict qualified. Only
1430 present if "ValueKind" is
1433 "IsVolatile" boolean Indicates if the kernel argument
1434 is volatile qualified. Only
1435 present if "ValueKind" is
1438 "IsPipe" boolean Indicates if the kernel argument
1439 is pipe qualified. Only present
1440 if "ValueKind" is "Pipe".
1443 Can GlobalBuffer be pipe
1445 ================= ============== ========= ================================
1449 .. table:: AMDHSA Code Object V2 Kernel Code Properties Metadata Map
1450 :name: amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2
1452 ============================ ============== ========= =====================
1453 String Key Value Type Required? Description
1454 ============================ ============== ========= =====================
1455 "KernargSegmentSize" integer Required The size in bytes of
1457 that holds the values
1460 "GroupSegmentFixedSize" integer Required The amount of group
1464 bytes. This does not
1466 dynamically allocated
1467 group segment memory
1471 "PrivateSegmentFixedSize" integer Required The amount of fixed
1472 private address space
1473 memory required for a
1475 bytes. If the kernel
1477 stack then additional
1479 to this value for the
1481 "KernargSegmentAlign" integer Required The maximum byte
1484 kernarg segment. Must
1486 "WavefrontSize" integer Required Wavefront size. Must
1488 "NumSGPRs" integer Required Number of scalar
1492 includes the special
1498 SGPR added if a trap
1504 "NumVGPRs" integer Required Number of vector
1508 "MaxFlatWorkGroupSize" integer Required Maximum flat
1511 kernel in work-items.
1514 ReqdWorkGroupSize if
1516 "NumSpilledSGPRs" integer Number of stores from
1517 a scalar register to
1518 a register allocator
1521 "NumSpilledVGPRs" integer Number of stores from
1522 a vector register to
1523 a register allocator
1526 ============================ ============== ========= =====================
1528 .. _amdgpu-amdhsa-code-object-metadata-v3:
1530 Code Object V3 Metadata (-mattr=+code-object-v3)
1531 ++++++++++++++++++++++++++++++++++++++++++++++++
1533 Code object V3 metadata is specified by the ``NT_AMDGPU_METADATA`` note record
1534 (see :ref:`amdgpu-note-records-v3`).
1536 The metadata is represented as Message Pack formatted binary data (see
1537 [MsgPack]_). The top level is a Message Pack map that includes the
1538 keys defined in table
1539 :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3` and referenced
1542 Additional information can be added to the maps. To avoid conflicts,
1543 any key names should be prefixed by "*vendor-name*." where
1544 ``vendor-name`` can be the the name of the vendor and specific vendor
1545 tool that generates the information. The prefix is abbreviated to
1546 simply "." when it appears within a map that has been added by the
1549 .. table:: AMDHSA Code Object V3 Metadata Map
1550 :name: amdgpu-amdhsa-code-object-metadata-map-table-v3
1552 ================= ============== ========= =======================================
1553 String Key Value Type Required? Description
1554 ================= ============== ========= =======================================
1555 "amdhsa.version" sequence of Required - The first integer is the major
1556 2 integers version. Currently 1.
1557 - The second integer is the minor
1558 version. Currently 0.
1559 "amdhsa.printf" sequence of Each string is encoded information
1560 strings about a printf function call. The
1561 encoded information is organized as
1562 fields separated by colon (':'):
1564 ``ID:N:S[0]:S[1]:...:S[N-1]:FormatString``
1569 A 32 bit integer as a unique id for
1570 each printf function call
1573 A 32 bit integer equal to the number
1574 of arguments of printf function call
1577 ``S[i]`` (where i = 0, 1, ... , N-1)
1578 32 bit integers for the size in bytes
1579 of the i-th FormatString argument of
1580 the printf function call
1583 The format string passed to the
1584 printf function call.
1585 "amdhsa.kernels" sequence of Required Sequence of the maps for each
1586 map kernel in the code object. See
1587 :ref:`amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3`
1588 for the definition of the keys included
1590 ================= ============== ========= =======================================
1594 .. table:: AMDHSA Code Object V3 Kernel Metadata Map
1595 :name: amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3
1597 =================================== ============== ========= ================================
1598 String Key Value Type Required? Description
1599 =================================== ============== ========= ================================
1600 ".name" string Required Source name of the kernel.
1601 ".symbol" string Required Name of the kernel
1602 descriptor ELF symbol.
1603 ".language" string Source language of the kernel.
1613 ".language_version" sequence of - The first integer is the major
1615 - The second integer is the
1617 ".args" sequence of Sequence of maps of the
1618 map kernel arguments. See
1619 :ref:`amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3`
1620 for the definition of the keys
1621 included in that map.
1622 ".reqd_workgroup_size" sequence of If not 0, 0, 0 then all values
1623 3 integers must be >=1 and the dispatch
1624 work-group size X, Y, Z must
1625 correspond to the specified
1626 values. Defaults to 0, 0, 0.
1628 Corresponds to the OpenCL
1629 ``reqd_work_group_size``
1631 ".workgroup_size_hint" sequence of The dispatch work-group size
1632 3 integers X, Y, Z is likely to be the
1635 Corresponds to the OpenCL
1636 ``work_group_size_hint``
1638 ".vec_type_hint" string The name of a scalar or vector
1641 Corresponds to the OpenCL
1642 ``vec_type_hint`` attribute.
1644 ".device_enqueue_symbol" string The external symbol name
1645 associated with a kernel.
1646 OpenCL runtime allocates a
1647 global buffer for the symbol
1648 and saves the kernel's address
1649 to it, which is used for
1650 device side enqueueing. Only
1651 available for device side
1653 ".kernarg_segment_size" integer Required The size in bytes of
1655 that holds the values
1658 ".group_segment_fixed_size" integer Required The amount of group
1662 bytes. This does not
1664 dynamically allocated
1665 group segment memory
1669 ".private_segment_fixed_size" integer Required The amount of fixed
1670 private address space
1671 memory required for a
1673 bytes. If the kernel
1675 stack then additional
1677 to this value for the
1679 ".kernarg_segment_align" integer Required The maximum byte
1682 kernarg segment. Must
1684 ".wavefront_size" integer Required Wavefront size. Must
1686 ".sgpr_count" integer Required Number of scalar
1687 registers required by a
1689 GFX6-GFX9. A register
1690 is required if it is
1692 if a higher numbered
1695 includes the special
1701 SGPR added if a trap
1707 ".vgpr_count" integer Required Number of vector
1708 registers required by
1710 GFX6-GFX9. A register
1711 is required if it is
1713 if a higher numbered
1716 ".max_flat_workgroup_size" integer Required Maximum flat
1719 kernel in work-items.
1722 ReqdWorkGroupSize if
1724 ".sgpr_spill_count" integer Number of stores from
1725 a scalar register to
1726 a register allocator
1729 ".vgpr_spill_count" integer Number of stores from
1730 a vector register to
1731 a register allocator
1734 =================================== ============== ========= ================================
1738 .. table:: AMDHSA Code Object V3 Kernel Argument Metadata Map
1739 :name: amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3
1741 ====================== ============== ========= ================================
1742 String Key Value Type Required? Description
1743 ====================== ============== ========= ================================
1744 ".name" string Kernel argument name.
1745 ".type_name" string Kernel argument type name.
1746 ".size" integer Required Kernel argument size in bytes.
1747 ".offset" integer Required Kernel argument offset in
1748 bytes. The offset must be a
1749 multiple of the alignment
1750 required by the argument.
1751 ".value_kind" string Required Kernel argument kind that
1752 specifies how to set up the
1753 corresponding argument.
1757 The argument is copied
1758 directly into the kernarg.
1761 A global address space pointer
1762 to the buffer data is passed
1765 "dynamic_shared_pointer"
1766 A group address space pointer
1767 to dynamically allocated LDS
1768 is passed in the kernarg.
1771 A global address space
1772 pointer to a S# is passed in
1776 A global address space
1777 pointer to a T# is passed in
1781 A global address space pointer
1782 to an OpenCL pipe is passed in
1786 A global address space pointer
1787 to an OpenCL device enqueue
1788 queue is passed in the
1791 "hidden_global_offset_x"
1792 The OpenCL grid dispatch
1793 global offset for the X
1794 dimension is passed in the
1797 "hidden_global_offset_y"
1798 The OpenCL grid dispatch
1799 global offset for the Y
1800 dimension is passed in the
1803 "hidden_global_offset_z"
1804 The OpenCL grid dispatch
1805 global offset for the Z
1806 dimension is passed in the
1810 An argument that is not used
1811 by the kernel. Space needs to
1812 be left for it, but it does
1813 not need to be set up.
1815 "hidden_printf_buffer"
1816 A global address space pointer
1817 to the runtime printf buffer
1818 is passed in kernarg.
1820 "hidden_default_queue"
1821 A global address space pointer
1822 to the OpenCL device enqueue
1823 queue that should be used by
1824 the kernel by default is
1825 passed in the kernarg.
1827 "hidden_completion_action"
1828 A global address space pointer
1829 to help link enqueued kernels into
1830 the ancestor tree for determining
1831 when the parent kernel has finished.
1833 ".value_type" string Required Kernel argument value type. Only
1834 present if ".value_kind" is
1835 "by_value". For vector data
1836 types, the value is for the
1837 element type. Values include:
1853 How can it be determined if a
1854 vector type, and what size
1856 ".pointee_align" integer Alignment in bytes of pointee
1857 type for pointer type kernel
1858 argument. Must be a power
1859 of 2. Only present if
1861 "dynamic_shared_pointer".
1862 ".address_space" string Kernel argument address space
1863 qualifier. Only present if
1864 ".value_kind" is "global_buffer" or
1865 "dynamic_shared_pointer". Values
1876 Is "global_buffer" only "global"
1878 "dynamic_shared_pointer" always
1879 "local"? Can HCC allow "generic"?
1880 How can "private" or "region"
1882 ".access" string Kernel argument access
1883 qualifier. Only present if
1884 ".value_kind" is "image" or
1895 ".actual_access" string The actual memory accesses
1896 performed by the kernel on the
1897 kernel argument. Only present if
1898 ".value_kind" is "global_buffer",
1899 "image", or "pipe". This may be
1900 more restrictive than indicated
1901 by ".access" to reflect what the
1902 kernel actual does. If not
1903 present then the runtime must
1904 assume what is implied by
1905 ".access" and ".is_const" . Values
1912 ".is_const" boolean Indicates if the kernel argument
1913 is const qualified. Only present
1917 ".is_restrict" boolean Indicates if the kernel argument
1918 is restrict qualified. Only
1919 present if ".value_kind" is
1922 ".is_volatile" boolean Indicates if the kernel argument
1923 is volatile qualified. Only
1924 present if ".value_kind" is
1927 ".is_pipe" boolean Indicates if the kernel argument
1928 is pipe qualified. Only present
1929 if ".value_kind" is "pipe".
1932 Can "global_buffer" be pipe
1934 ====================== ============== ========= ================================
1941 The HSA architected queuing language (AQL) defines a user space memory interface
1942 that can be used to control the dispatch of kernels, in an agent independent
1943 way. An agent can have zero or more AQL queues created for it using the ROCm
1944 runtime, in which AQL packets (all of which are 64 bytes) can be placed. See the
1945 *HSA Platform System Architecture Specification* [HSA]_ for the AQL queue
1946 mechanics and packet layouts.
1948 The packet processor of a kernel agent is responsible for detecting and
1949 dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the
1950 packet processor is implemented by the hardware command processor (CP),
1951 asynchronous dispatch controller (ADC) and shader processor input controller
1954 The ROCm runtime can be used to allocate an AQL queue object. It uses the kernel
1955 mode driver to initialize and register the AQL queue with CP.
1957 To dispatch a kernel the following actions are performed. This can occur in the
1958 CPU host program, or from an HSA kernel executing on a GPU.
1960 1. A pointer to an AQL queue for the kernel agent on which the kernel is to be
1961 executed is obtained.
1962 2. A pointer to the kernel descriptor (see
1963 :ref:`amdgpu-amdhsa-kernel-descriptor`) of the kernel to execute is
1964 obtained. It must be for a kernel that is contained in a code object that that
1965 was loaded by the ROCm runtime on the kernel agent with which the AQL queue is
1967 3. Space is allocated for the kernel arguments using the ROCm runtime allocator
1968 for a memory region with the kernarg property for the kernel agent that will
1969 execute the kernel. It must be at least 16 byte aligned.
1970 4. Kernel argument values are assigned to the kernel argument memory
1971 allocation. The layout is defined in the *HSA Programmer's Language Reference*
1972 [HSA]_. For AMDGPU the kernel execution directly accesses the kernel argument
1973 memory in the same way constant memory is accessed. (Note that the HSA
1974 specification allows an implementation to copy the kernel argument contents to
1975 another location that is accessed by the kernel.)
1976 5. An AQL kernel dispatch packet is created on the AQL queue. The ROCm runtime
1977 api uses 64 bit atomic operations to reserve space in the AQL queue for the
1978 packet. The packet must be set up, and the final write must use an atomic
1979 store release to set the packet kind to ensure the packet contents are
1980 visible to the kernel agent. AQL defines a doorbell signal mechanism to
1981 notify the kernel agent that the AQL queue has been updated. These rules, and
1982 the layout of the AQL queue and kernel dispatch packet is defined in the *HSA
1983 System Architecture Specification* [HSA]_.
1984 6. A kernel dispatch packet includes information about the actual dispatch,
1985 such as grid and work-group size, together with information from the code
1986 object about the kernel, such as segment sizes. The ROCm runtime queries on
1987 the kernel symbol can be used to obtain the code object values which are
1988 recorded in the :ref:`amdgpu-amdhsa-code-object-metadata`.
1989 7. CP executes micro-code and is responsible for detecting and setting up the
1990 GPU to execute the wavefronts of a kernel dispatch.
1991 8. CP ensures that when the a wavefront starts executing the kernel machine
1992 code, the scalar general purpose registers (SGPR) and vector general purpose
1993 registers (VGPR) are set up as required by the machine code. The required
1994 setup is defined in the :ref:`amdgpu-amdhsa-kernel-descriptor`. The initial
1995 register state is defined in
1996 :ref:`amdgpu-amdhsa-initial-kernel-execution-state`.
1997 9. The prolog of the kernel machine code (see
1998 :ref:`amdgpu-amdhsa-kernel-prolog`) sets up the machine state as necessary
1999 before continuing executing the machine code that corresponds to the kernel.
2000 10. When the kernel dispatch has completed execution, CP signals the completion
2001 signal specified in the kernel dispatch packet if not 0.
2003 .. _amdgpu-amdhsa-memory-spaces:
2008 The memory space properties are:
2010 .. table:: AMDHSA Memory Spaces
2011 :name: amdgpu-amdhsa-memory-spaces-table
2013 ================= =========== ======== ======= ==================
2014 Memory Space Name HSA Segment Hardware Address NULL Value
2016 ================= =========== ======== ======= ==================
2017 Private private scratch 32 0x00000000
2018 Local group LDS 32 0xFFFFFFFF
2019 Global global global 64 0x0000000000000000
2020 Constant constant *same as 64 0x0000000000000000
2022 Generic flat flat 64 0x0000000000000000
2023 Region N/A GDS 32 *not implemented
2025 ================= =========== ======== ======= ==================
2027 The global and constant memory spaces both use global virtual addresses, which
2028 are the same virtual address space used by the CPU. However, some virtual
2029 addresses may only be accessible to the CPU, some only accessible by the GPU,
2032 Using the constant memory space indicates that the data will not change during
2033 the execution of the kernel. This allows scalar read instructions to be
2034 used. The vector and scalar L1 caches are invalidated of volatile data before
2035 each kernel dispatch execution to allow constant memory to change values between
2038 The local memory space uses the hardware Local Data Store (LDS) which is
2039 automatically allocated when the hardware creates work-groups of wavefronts, and
2040 freed when all the wavefronts of a work-group have terminated. The data store
2041 (DS) instructions can be used to access it.
2043 The private memory space uses the hardware scratch memory support. If the kernel
2044 uses scratch, then the hardware allocates memory that is accessed using
2045 wavefront lane dword (4 byte) interleaving. The mapping used from private
2046 address to physical address is:
2048 ``wavefront-scratch-base +
2049 (private-address * wavefront-size * 4) +
2050 (wavefront-lane-id * 4)``
2052 There are different ways that the wavefront scratch base address is determined
2053 by a wavefront (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). This
2054 memory can be accessed in an interleaved manner using buffer instruction with
2055 the scratch buffer descriptor and per wavefront scratch offset, by the scratch
2056 instructions, or by flat instructions. If each lane of a wavefront accesses the
2057 same private address, the interleaving results in adjacent dwords being accessed
2058 and hence requires fewer cache lines to be fetched. Multi-dword access is not
2059 supported except by flat and scratch instructions in GFX9.
2061 The generic address space uses the hardware flat address support available in
2062 GFX7-GFX9. This uses two fixed ranges of virtual addresses (the private and
2063 local appertures), that are outside the range of addressible global memory, to
2064 map from a flat address to a private or local address.
2066 FLAT instructions can take a flat address and access global, private (scratch)
2067 and group (LDS) memory depending in if the address is within one of the
2068 apperture ranges. Flat access to scratch requires hardware aperture setup and
2069 setup in the kernel prologue (see :ref:`amdgpu-amdhsa-flat-scratch`). Flat
2070 access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup
2071 (see :ref:`amdgpu-amdhsa-m0`).
2073 To convert between a segment address and a flat address the base address of the
2074 appertures address can be used. For GFX7-GFX8 these are available in the
2075 :ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with
2076 Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For
2077 GFX9 the appature base addresses are directly available as inline constant
2078 registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit
2079 address mode the apperture sizes are 2^32 bytes and the base is aligned to 2^32
2080 which makes it easier to convert from flat to segment or segment to flat.
2085 Image and sample handles created by the ROCm runtime are 64 bit addresses of a
2086 hardware 32 byte V# and 48 byte S# object respectively. In order to support the
2087 HSA ``query_sampler`` operations two extra dwords are used to store the HSA BRIG
2088 enumeration values for the queries that are not trivially deducible from the S#
2094 HSA signal handles created by the ROCm runtime are 64 bit addresses of a
2095 structure allocated in memory accessible from both the CPU and GPU. The
2096 structure is defined by the ROCm runtime and subject to change between releases
2097 (see [AMD-ROCm-github]_).
2099 .. _amdgpu-amdhsa-hsa-aql-queue:
2104 The HSA AQL queue structure is defined by the ROCm runtime and subject to change
2105 between releases (see [AMD-ROCm-github]_). For some processors it contains
2106 fields needed to implement certain language features such as the flat address
2107 aperture bases. It also contains fields used by CP such as managing the
2108 allocation of scratch memory.
2110 .. _amdgpu-amdhsa-kernel-descriptor:
2115 A kernel descriptor consists of the information needed by CP to initiate the
2116 execution of a kernel, including the entry point address of the machine code
2117 that implements the kernel.
2119 Kernel Descriptor for GFX6-GFX9
2120 +++++++++++++++++++++++++++++++
2122 CP microcode requires the Kernel descriptor to be allocated on 64 byte
2125 .. table:: Kernel Descriptor for GFX6-GFX9
2126 :name: amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table
2128 ======= ======= =============================== ============================
2129 Bits Size Field Name Description
2130 ======= ======= =============================== ============================
2131 31:0 4 bytes GROUP_SEGMENT_FIXED_SIZE The amount of fixed local
2132 address space memory
2133 required for a work-group
2134 in bytes. This does not
2135 include any dynamically
2136 allocated local address
2137 space memory that may be
2138 added when the kernel is
2140 63:32 4 bytes PRIVATE_SEGMENT_FIXED_SIZE The amount of fixed
2141 private address space
2142 memory required for a
2143 work-item in bytes. If
2144 is_dynamic_callstack is 1
2145 then additional space must
2146 be added to this value for
2148 127:64 8 bytes Reserved, must be 0.
2149 191:128 8 bytes KERNEL_CODE_ENTRY_BYTE_OFFSET Byte offset (possibly
2152 descriptor to kernel's
2153 entry point instruction
2154 which must be 256 byte
2156 383:192 24 Reserved, must be 0.
2158 415:384 4 bytes COMPUTE_PGM_RSRC1 Compute Shader (CS)
2159 program settings used by
2161 ``COMPUTE_PGM_RSRC1``
2164 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
2165 447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS)
2166 program settings used by
2168 ``COMPUTE_PGM_RSRC2``
2171 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
2172 448 1 bit ENABLE_SGPR_PRIVATE_SEGMENT Enable the setup of the
2173 _BUFFER SGPR user data registers
2175 :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
2177 The total number of SGPR
2179 requested must not exceed
2180 16 and match value in
2181 ``compute_pgm_rsrc2.user_sgpr.user_sgpr_count``.
2182 Any requests beyond 16
2184 449 1 bit ENABLE_SGPR_DISPATCH_PTR *see above*
2185 450 1 bit ENABLE_SGPR_QUEUE_PTR *see above*
2186 451 1 bit ENABLE_SGPR_KERNARG_SEGMENT_PTR *see above*
2187 452 1 bit ENABLE_SGPR_DISPATCH_ID *see above*
2188 453 1 bit ENABLE_SGPR_FLAT_SCRATCH_INIT *see above*
2189 454 1 bit ENABLE_SGPR_PRIVATE_SEGMENT *see above*
2191 455 1 bit Reserved, must be 0.
2192 511:456 8 bytes Reserved, must be 0.
2193 512 **Total size 64 bytes.**
2194 ======= ====================================================================
2198 .. table:: compute_pgm_rsrc1 for GFX6-GFX9
2199 :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table
2201 ======= ======= =============================== ===========================================================================
2202 Bits Size Field Name Description
2203 ======= ======= =============================== ===========================================================================
2204 5:0 6 bits GRANULATED_WORKITEM_VGPR_COUNT Number of vector register
2205 blocks used by each work-item;
2206 granularity is device
2211 - max(0, ceil(vgprs_used / 4) - 1)
2213 Where vgprs_used is defined
2214 as the highest VGPR number
2215 explicitly referenced plus
2218 Used by CP to set up
2219 ``COMPUTE_PGM_RSRC1.VGPRS``.
2222 :ref:`amdgpu-assembler`
2224 automatically for the
2225 selected processor from
2226 values provided to the
2227 `.amdhsa_kernel` directive
2229 `.amdhsa_next_free_vgpr`
2230 nested directive (see
2231 :ref:`amdhsa-kernel-directives-table`).
2232 9:6 4 bits GRANULATED_WAVEFRONT_SGPR_COUNT Number of scalar register
2233 blocks used by a wavefront;
2234 granularity is device
2239 - max(0, ceil(sgprs_used / 8) - 1)
2242 - 2 * max(0, ceil(sgprs_used / 16) - 1)
2245 defined as the highest
2246 SGPR number explicitly
2247 referenced plus one, plus
2248 a target-specific number
2249 of additional special
2251 FLAT_SCRATCH (GFX7+) and
2252 XNACK_MASK (GFX8+), and
2255 limitations. It does not
2256 include the 16 SGPRs added
2257 if a trap handler is
2261 limitations and special
2262 SGPR layout are defined in
2264 documentation, which can
2266 :ref:`amdgpu-processors`
2269 Used by CP to set up
2270 ``COMPUTE_PGM_RSRC1.SGPRS``.
2273 :ref:`amdgpu-assembler`
2275 automatically for the
2276 selected processor from
2277 values provided to the
2278 `.amdhsa_kernel` directive
2280 `.amdhsa_next_free_sgpr`
2281 and `.amdhsa_reserve_*`
2282 nested directives (see
2283 :ref:`amdhsa-kernel-directives-table`).
2284 11:10 2 bits PRIORITY Must be 0.
2286 Start executing wavefront
2287 at the specified priority.
2289 CP is responsible for
2291 ``COMPUTE_PGM_RSRC1.PRIORITY``.
2292 13:12 2 bits FLOAT_ROUND_MODE_32 Wavefront starts execution
2293 with specified rounding
2296 precision floating point
2299 Floating point rounding
2300 mode values are defined in
2301 :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
2303 Used by CP to set up
2304 ``COMPUTE_PGM_RSRC1.FLOAT_MODE``.
2305 15:14 2 bits FLOAT_ROUND_MODE_16_64 Wavefront starts execution
2306 with specified rounding
2307 denorm mode for half/double (16
2308 and 64 bit) floating point
2309 precision floating point
2312 Floating point rounding
2313 mode values are defined in
2314 :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
2316 Used by CP to set up
2317 ``COMPUTE_PGM_RSRC1.FLOAT_MODE``.
2318 17:16 2 bits FLOAT_DENORM_MODE_32 Wavefront starts execution
2319 with specified denorm mode
2322 precision floating point
2325 Floating point denorm mode
2326 values are defined in
2327 :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
2329 Used by CP to set up
2330 ``COMPUTE_PGM_RSRC1.FLOAT_MODE``.
2331 19:18 2 bits FLOAT_DENORM_MODE_16_64 Wavefront starts execution
2332 with specified denorm mode
2334 and 64 bit) floating point
2335 precision floating point
2338 Floating point denorm mode
2339 values are defined in
2340 :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
2342 Used by CP to set up
2343 ``COMPUTE_PGM_RSRC1.FLOAT_MODE``.
2344 20 1 bit PRIV Must be 0.
2346 Start executing wavefront
2347 in privilege trap handler
2350 CP is responsible for
2352 ``COMPUTE_PGM_RSRC1.PRIV``.
2353 21 1 bit ENABLE_DX10_CLAMP Wavefront starts execution
2354 with DX10 clamp mode
2355 enabled. Used by the vector
2356 ALU to force DX10 style
2357 treatment of NaN's (when
2358 set, clamp NaN to zero,
2362 Used by CP to set up
2363 ``COMPUTE_PGM_RSRC1.DX10_CLAMP``.
2364 22 1 bit DEBUG_MODE Must be 0.
2366 Start executing wavefront
2367 in single step mode.
2369 CP is responsible for
2371 ``COMPUTE_PGM_RSRC1.DEBUG_MODE``.
2372 23 1 bit ENABLE_IEEE_MODE Wavefront starts execution
2374 enabled. Floating point
2375 opcodes that support
2376 exception flag gathering
2377 will quiet and propagate
2378 signaling-NaN inputs per
2379 IEEE 754-2008. Min_dx10 and
2380 max_dx10 become IEEE
2381 754-2008 compliant due to
2382 signaling-NaN propagation
2385 Used by CP to set up
2386 ``COMPUTE_PGM_RSRC1.IEEE_MODE``.
2387 24 1 bit BULKY Must be 0.
2389 Only one work-group allowed
2390 to execute on a compute
2393 CP is responsible for
2395 ``COMPUTE_PGM_RSRC1.BULKY``.
2396 25 1 bit CDBG_USER Must be 0.
2398 Flag that can be used to
2399 control debugging code.
2401 CP is responsible for
2403 ``COMPUTE_PGM_RSRC1.CDBG_USER``.
2404 26 1 bit FP16_OVFL GFX6-GFX8
2405 Reserved, must be 0.
2407 Wavefront starts execution
2408 with specified fp16 overflow
2411 - If 0, fp16 overflow generates
2413 - If 1, fp16 overflow that is the
2414 result of an +/-INF input value
2415 or divide by 0 produces a +/-INF,
2416 otherwise clamps computed
2417 overflow to +/-MAX_FP16 as
2420 Used by CP to set up
2421 ``COMPUTE_PGM_RSRC1.FP16_OVFL``.
2422 31:27 5 bits Reserved, must be 0.
2423 32 **Total size 4 bytes**
2424 ======= ===================================================================================================================
2428 .. table:: compute_pgm_rsrc2 for GFX6-GFX9
2429 :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table
2431 ======= ======= =============================== ===========================================================================
2432 Bits Size Field Name Description
2433 ======= ======= =============================== ===========================================================================
2434 0 1 bit ENABLE_SGPR_PRIVATE_SEGMENT Enable the setup of the
2435 _WAVEFRONT_OFFSET SGPR wavefront scratch offset
2436 system register (see
2437 :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
2439 Used by CP to set up
2440 ``COMPUTE_PGM_RSRC2.SCRATCH_EN``.
2441 5:1 5 bits USER_SGPR_COUNT The total number of SGPR
2443 requested. This number must
2444 match the number of user
2445 data registers enabled.
2447 Used by CP to set up
2448 ``COMPUTE_PGM_RSRC2.USER_SGPR``.
2449 6 1 bit ENABLE_TRAP_HANDLER Must be 0.
2452 ``COMPUTE_PGM_RSRC2.TRAP_PRESENT``,
2453 which is set by the CP if
2454 the runtime has installed a
2456 7 1 bit ENABLE_SGPR_WORKGROUP_ID_X Enable the setup of the
2457 system SGPR register for
2458 the work-group id in the X
2460 :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
2462 Used by CP to set up
2463 ``COMPUTE_PGM_RSRC2.TGID_X_EN``.
2464 8 1 bit ENABLE_SGPR_WORKGROUP_ID_Y Enable the setup of the
2465 system SGPR register for
2466 the work-group id in the Y
2468 :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
2470 Used by CP to set up
2471 ``COMPUTE_PGM_RSRC2.TGID_Y_EN``.
2472 9 1 bit ENABLE_SGPR_WORKGROUP_ID_Z Enable the setup of the
2473 system SGPR register for
2474 the work-group id in the Z
2476 :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
2478 Used by CP to set up
2479 ``COMPUTE_PGM_RSRC2.TGID_Z_EN``.
2480 10 1 bit ENABLE_SGPR_WORKGROUP_INFO Enable the setup of the
2481 system SGPR register for
2482 work-group information (see
2483 :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
2485 Used by CP to set up
2486 ``COMPUTE_PGM_RSRC2.TGID_SIZE_EN``.
2487 12:11 2 bits ENABLE_VGPR_WORKITEM_ID Enable the setup of the
2488 VGPR system registers used
2489 for the work-item ID.
2490 :ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`
2493 Used by CP to set up
2494 ``COMPUTE_PGM_RSRC2.TIDIG_CMP_CNT``.
2495 13 1 bit ENABLE_EXCEPTION_ADDRESS_WATCH Must be 0.
2497 Wavefront starts execution
2499 exceptions enabled which
2500 are generated when L1 has
2501 witnessed a thread access
2505 CP is responsible for
2506 filling in the address
2508 ``COMPUTE_PGM_RSRC2.EXCP_EN_MSB``
2509 according to what the
2511 14 1 bit ENABLE_EXCEPTION_MEMORY Must be 0.
2513 Wavefront starts execution
2514 with memory violation
2515 exceptions exceptions
2516 enabled which are generated
2517 when a memory violation has
2518 occurred for this wavefront from
2520 (write-to-read-only-memory,
2521 mis-aligned atomic, LDS
2522 address out of range,
2523 illegal address, etc.).
2527 ``COMPUTE_PGM_RSRC2.EXCP_EN_MSB``
2528 according to what the
2530 23:15 9 bits GRANULATED_LDS_SIZE Must be 0.
2532 CP uses the rounded value
2533 from the dispatch packet,
2534 not this value, as the
2535 dispatch may contain
2536 dynamically allocated group
2537 segment memory. CP writes
2539 ``COMPUTE_PGM_RSRC2.LDS_SIZE``.
2541 Amount of group segment
2542 (LDS) to allocate for each
2543 work-group. Granularity is
2547 roundup(lds-size / (64 * 4))
2549 roundup(lds-size / (128 * 4))
2551 24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution
2552 _INVALID_OPERATION with specified exceptions
2555 Used by CP to set up
2556 ``COMPUTE_PGM_RSRC2.EXCP_EN``
2557 (set from bits 0..6).
2561 25 1 bit ENABLE_EXCEPTION_FP_DENORMAL FP Denormal one or more
2562 _SOURCE input operands is a
2564 26 1 bit ENABLE_EXCEPTION_IEEE_754_FP IEEE 754 FP Division by
2565 _DIVISION_BY_ZERO Zero
2566 27 1 bit ENABLE_EXCEPTION_IEEE_754_FP IEEE 754 FP FP Overflow
2568 28 1 bit ENABLE_EXCEPTION_IEEE_754_FP IEEE 754 FP Underflow
2570 29 1 bit ENABLE_EXCEPTION_IEEE_754_FP IEEE 754 FP Inexact
2572 30 1 bit ENABLE_EXCEPTION_INT_DIVIDE_BY Integer Division by Zero
2573 _ZERO (rcp_iflag_f32 instruction
2575 31 1 bit Reserved, must be 0.
2576 32 **Total size 4 bytes.**
2577 ======= ===================================================================================================================
2581 .. table:: Floating Point Rounding Mode Enumeration Values
2582 :name: amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table
2584 ====================================== ===== ==============================
2585 Enumeration Name Value Description
2586 ====================================== ===== ==============================
2587 FLOAT_ROUND_MODE_NEAR_EVEN 0 Round Ties To Even
2588 FLOAT_ROUND_MODE_PLUS_INFINITY 1 Round Toward +infinity
2589 FLOAT_ROUND_MODE_MINUS_INFINITY 2 Round Toward -infinity
2590 FLOAT_ROUND_MODE_ZERO 3 Round Toward 0
2591 ====================================== ===== ==============================
2595 .. table:: Floating Point Denorm Mode Enumeration Values
2596 :name: amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table
2598 ====================================== ===== ==============================
2599 Enumeration Name Value Description
2600 ====================================== ===== ==============================
2601 FLOAT_DENORM_MODE_FLUSH_SRC_DST 0 Flush Source and Destination
2603 FLOAT_DENORM_MODE_FLUSH_DST 1 Flush Output Denorms
2604 FLOAT_DENORM_MODE_FLUSH_SRC 2 Flush Source Denorms
2605 FLOAT_DENORM_MODE_FLUSH_NONE 3 No Flush
2606 ====================================== ===== ==============================
2610 .. table:: System VGPR Work-Item ID Enumeration Values
2611 :name: amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table
2613 ======================================== ===== ============================
2614 Enumeration Name Value Description
2615 ======================================== ===== ============================
2616 SYSTEM_VGPR_WORKITEM_ID_X 0 Set work-item X dimension
2618 SYSTEM_VGPR_WORKITEM_ID_X_Y 1 Set work-item X and Y
2620 SYSTEM_VGPR_WORKITEM_ID_X_Y_Z 2 Set work-item X, Y and Z
2622 SYSTEM_VGPR_WORKITEM_ID_UNDEFINED 3 Undefined.
2623 ======================================== ===== ============================
2625 .. _amdgpu-amdhsa-initial-kernel-execution-state:
2627 Initial Kernel Execution State
2628 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2630 This section defines the register state that will be set up by the packet
2631 processor prior to the start of execution of every wavefront. This is limited by
2632 the constraints of the hardware controllers of CP/ADC/SPI.
2634 The order of the SGPR registers is defined, but the compiler can specify which
2635 ones are actually setup in the kernel descriptor using the ``enable_sgpr_*`` bit
2636 fields (see :ref:`amdgpu-amdhsa-kernel-descriptor`). The register numbers used
2637 for enabled registers are dense starting at SGPR0: the first enabled register is
2638 SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have
2641 The initial SGPRs comprise up to 16 User SRGPs that are set by CP and apply to
2642 all wavefronts of the grid. It is possible to specify more than 16 User SGPRs using
2643 the ``enable_sgpr_*`` bit fields, in which case only the first 16 are actually
2644 initialized. These are then immediately followed by the System SGPRs that are
2645 set up by ADC/SPI and can have different values for each wavefront of the grid
2648 SGPR register initial state is defined in
2649 :ref:`amdgpu-amdhsa-sgpr-register-set-up-order-table`.
2651 .. table:: SGPR Register Set Up Order
2652 :name: amdgpu-amdhsa-sgpr-register-set-up-order-table
2654 ========== ========================== ====== ==============================
2655 SGPR Order Name Number Description
2656 (kernel descriptor enable of
2658 ========== ========================== ====== ==============================
2659 First Private Segment Buffer 4 V# that can be used, together
2660 (enable_sgpr_private with Scratch Wavefront Offset
2661 _segment_buffer) as an offset, to access the
2662 private memory space using a
2665 CP uses the value provided by
2667 then Dispatch Ptr 2 64 bit address of AQL dispatch
2668 (enable_sgpr_dispatch_ptr) packet for kernel dispatch
2670 then Queue Ptr 2 64 bit address of amd_queue_t
2671 (enable_sgpr_queue_ptr) object for AQL queue on which
2672 the dispatch packet was
2674 then Kernarg Segment Ptr 2 64 bit address of Kernarg
2675 (enable_sgpr_kernarg segment. This is directly
2676 _segment_ptr) copied from the
2677 kernarg_address in the kernel
2680 Having CP load it once avoids
2681 loading it at the beginning of
2683 then Dispatch Id 2 64 bit Dispatch ID of the
2684 (enable_sgpr_dispatch_id) dispatch packet being
2686 then Flat Scratch Init 2 This is 2 SGPRs:
2687 (enable_sgpr_flat_scratch
2691 The first SGPR is a 32 bit
2693 ``SH_HIDDEN_PRIVATE_BASE_VIMID``
2694 to per SPI base of memory
2695 for scratch for the queue
2696 executing the kernel
2697 dispatch. CP obtains this
2698 from the runtime. (The
2699 Scratch Segment Buffer base
2701 ``SH_HIDDEN_PRIVATE_BASE_VIMID``
2702 plus this offset.) The value
2703 of Scratch Wavefront Offset must
2704 be added to this offset by
2705 the kernel machine code,
2706 right shifted by 8, and
2707 moved to the FLAT_SCRATCH_HI
2709 FLAT_SCRATCH_HI corresponds
2710 to SGPRn-4 on GFX7, and
2711 SGPRn-6 on GFX8 (where SGPRn
2712 is the highest numbered SGPR
2713 allocated to the wavefront).
2715 multiplied by 256 (as it is
2716 in units of 256 bytes) and
2718 ``SH_HIDDEN_PRIVATE_BASE_VIMID``
2719 to calculate the per wavefront
2720 FLAT SCRATCH BASE in flat
2721 memory instructions that
2725 The second SGPR is 32 bit
2726 byte size of a single
2727 work-item's scratch memory
2728 usage. CP obtains this from
2729 the runtime, and it is
2730 always a multiple of DWORD.
2731 CP checks that the value in
2732 the kernel dispatch packet
2733 Private Segment Byte Size is
2734 not larger, and requests the
2735 runtime to increase the
2736 queue's scratch size if
2737 necessary. The kernel code
2739 FLAT_SCRATCH_LO which is
2740 SGPRn-3 on GFX7 and SGPRn-5
2741 on GFX8. FLAT_SCRATCH_LO is
2742 used as the FLAT SCRATCH
2744 instructions. Having CP load
2745 it once avoids loading it at
2746 the beginning of every
2750 64 bit base address of the
2751 per SPI scratch backing
2752 memory managed by SPI for
2753 the queue executing the
2754 kernel dispatch. CP obtains
2755 this from the runtime (and
2756 divides it if there are
2757 multiple Shader Arrays each
2758 with its own SPI). The value
2759 of Scratch Wavefront Offset must
2760 be added by the kernel
2761 machine code and the result
2762 moved to the FLAT_SCRATCH
2763 SGPR which is SGPRn-6 and
2764 SGPRn-5. It is used as the
2765 FLAT SCRATCH BASE in flat
2766 memory instructions.
2767 then Private Segment Size 1 The 32 bit byte size of a
2768 (enable_sgpr_private single
2770 scratch_segment_size) memory
2771 allocation. This is the
2772 value from the kernel
2773 dispatch packet Private
2774 Segment Byte Size rounded up
2775 by CP to a multiple of
2778 Having CP load it once avoids
2779 loading it at the beginning of
2782 This is not used for
2783 GFX7-GFX8 since it is the same
2784 value as the second SGPR of
2785 Flat Scratch Init. However, it
2786 may be needed for GFX9 which
2787 changes the meaning of the
2788 Flat Scratch Init value.
2789 then Grid Work-Group Count X 1 32 bit count of the number of
2790 (enable_sgpr_grid work-groups in the X dimension
2791 _workgroup_count_X) for the grid being
2792 executed. Computed from the
2793 fields in the kernel dispatch
2794 packet as ((grid_size.x +
2795 workgroup_size.x - 1) /
2797 then Grid Work-Group Count Y 1 32 bit count of the number of
2798 (enable_sgpr_grid work-groups in the Y dimension
2799 _workgroup_count_Y && for the grid being
2800 less than 16 previous executed. Computed from the
2801 SGPRs) fields in the kernel dispatch
2802 packet as ((grid_size.y +
2803 workgroup_size.y - 1) /
2806 Only initialized if <16
2807 previous SGPRs initialized.
2808 then Grid Work-Group Count Z 1 32 bit count of the number of
2809 (enable_sgpr_grid work-groups in the Z dimension
2810 _workgroup_count_Z && for the grid being
2811 less than 16 previous executed. Computed from the
2812 SGPRs) fields in the kernel dispatch
2813 packet as ((grid_size.z +
2814 workgroup_size.z - 1) /
2817 Only initialized if <16
2818 previous SGPRs initialized.
2819 then Work-Group Id X 1 32 bit work-group id in X
2820 (enable_sgpr_workgroup_id dimension of grid for
2822 then Work-Group Id Y 1 32 bit work-group id in Y
2823 (enable_sgpr_workgroup_id dimension of grid for
2825 then Work-Group Id Z 1 32 bit work-group id in Z
2826 (enable_sgpr_workgroup_id dimension of grid for
2828 then Work-Group Info 1 {first_wavefront, 14'b0000,
2829 (enable_sgpr_workgroup ordered_append_term[10:0],
2830 _info) threadgroup_size_in_wavefronts[5:0]}
2831 then Scratch Wavefront Offset 1 32 bit byte offset from base
2832 (enable_sgpr_private of scratch base of queue
2833 _segment_wavefront_offset) executing the kernel
2834 dispatch. Must be used as an
2836 segment address when using
2837 Scratch Segment Buffer. It
2838 must be used to set up FLAT
2839 SCRATCH for flat addressing
2841 :ref:`amdgpu-amdhsa-flat-scratch`).
2842 ========== ========================== ====== ==============================
2844 The order of the VGPR registers is defined, but the compiler can specify which
2845 ones are actually setup in the kernel descriptor using the ``enable_vgpr*`` bit
2846 fields (see :ref:`amdgpu-amdhsa-kernel-descriptor`). The register numbers used
2847 for enabled registers are dense starting at VGPR0: the first enabled register is
2848 VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
2851 VGPR register initial state is defined in
2852 :ref:`amdgpu-amdhsa-vgpr-register-set-up-order-table`.
2854 .. table:: VGPR Register Set Up Order
2855 :name: amdgpu-amdhsa-vgpr-register-set-up-order-table
2857 ========== ========================== ====== ==============================
2858 VGPR Order Name Number Description
2859 (kernel descriptor enable of
2861 ========== ========================== ====== ==============================
2862 First Work-Item Id X 1 32 bit work item id in X
2863 (Always initialized) dimension of work-group for
2865 then Work-Item Id Y 1 32 bit work item id in Y
2866 (enable_vgpr_workitem_id dimension of work-group for
2867 > 0) wavefront lane.
2868 then Work-Item Id Z 1 32 bit work item id in Z
2869 (enable_vgpr_workitem_id dimension of work-group for
2870 > 1) wavefront lane.
2871 ========== ========================== ====== ==============================
2873 The setting of registers is done by GPU CP/ADC/SPI hardware as follows:
2875 1. SGPRs before the Work-Group Ids are set by CP using the 16 User Data
2877 2. Work-group Id registers X, Y, Z are set by ADC which supports any
2878 combination including none.
2879 3. Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
2880 its value cannot included with the flat scratch init value which is per queue.
2881 4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
2884 Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64 bit
2885 value to the hardware required SGPRn-3 and SGPRn-4 respectively.
2887 The global segment can be accessed either using buffer instructions (GFX6 which
2888 has V# 64 bit address support), flat instructions (GFX7-GFX9), or global
2889 instructions (GFX9).
2891 If buffer operations are used then the compiler can generate a V# with the
2892 following properties:
2896 * ATC: 1 if IOMMU present (such as APU)
2898 * MTYPE set to support memory coherence that matches the runtime (such as CC for
2899 APU and NC for dGPU).
2901 .. _amdgpu-amdhsa-kernel-prolog:
2906 .. _amdgpu-amdhsa-m0:
2912 The M0 register must be initialized with a value at least the total LDS size
2913 if the kernel may access LDS via DS or flat operations. Total LDS size is
2914 available in dispatch packet. For M0, it is also possible to use maximum
2915 possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for
2918 The M0 register is not used for range checking LDS accesses and so does not
2919 need to be initialized in the prolog.
2921 .. _amdgpu-amdhsa-flat-scratch:
2926 If the kernel may use flat operations to access scratch memory, the prolog code
2927 must set up FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which
2928 are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wavefront
2929 Offset SGPR registers (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`):
2932 Flat scratch is not supported.
2935 1. The low word of Flat Scratch Init is 32 bit byte offset from
2936 ``SH_HIDDEN_PRIVATE_BASE_VIMID`` to the base of scratch backing memory
2937 being managed by SPI for the queue executing the kernel dispatch. This is
2938 the same value used in the Scratch Segment Buffer V# base address. The
2939 prolog must add the value of Scratch Wavefront Offset to get the wavefront's byte
2940 scratch backing memory offset from ``SH_HIDDEN_PRIVATE_BASE_VIMID``. Since
2941 FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right shifted
2942 by 8 before moving into FLAT_SCRATCH_LO.
2943 2. The second word of Flat Scratch Init is 32 bit byte size of a single
2944 work-items scratch memory usage. This is directly loaded from the kernel
2945 dispatch packet Private Segment Byte Size and rounded up to a multiple of
2946 DWORD. Having CP load it once avoids loading it at the beginning of every
2947 wavefront. The prolog must move it to FLAT_SCRATCH_LO for use as FLAT SCRATCH
2951 The Flat Scratch Init is the 64 bit address of the base of scratch backing
2952 memory being managed by SPI for the queue executing the kernel dispatch. The
2953 prolog must add the value of Scratch Wavefront Offset and moved to the FLAT_SCRATCH
2954 pair for use as the flat scratch base in flat memory instructions.
2956 .. _amdgpu-amdhsa-memory-model:
2961 This section describes the mapping of LLVM memory model onto AMDGPU machine code
2962 (see :ref:`memmodel`). *The implementation is WIP.*
2965 Update when implementation complete.
2967 The AMDGPU backend supports the memory synchronization scopes specified in
2968 :ref:`amdgpu-memory-scopes`.
2970 The code sequences used to implement the memory model are defined in table
2971 :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.
2973 The sequences specify the order of instructions that a single thread must
2974 execute. The ``s_waitcnt`` and ``buffer_wbinvl1_vol`` are defined with respect
2975 to other memory instructions executed by the same thread. This allows them to be
2976 moved earlier or later which can allow them to be combined with other instances
2977 of the same instruction, or hoisted/sunk out of loops to improve
2978 performance. Only the instructions related to the memory model are given;
2979 additional ``s_waitcnt`` instructions are required to ensure registers are
2980 defined before being used. These may be able to be combined with the memory
2981 model ``s_waitcnt`` instructions as described above.
2983 The AMDGPU backend supports the following memory models:
2985 HSA Memory Model [HSA]_
2986 The HSA memory model uses a single happens-before relation for all address
2987 spaces (see :ref:`amdgpu-address-spaces`).
2988 OpenCL Memory Model [OpenCL]_
2989 The OpenCL memory model which has separate happens-before relations for the
2990 global and local address spaces. Only a fence specifying both global and
2991 local address space, and seq_cst instructions join the relationships. Since
2992 the LLVM ``memfence`` instruction does not allow an address space to be
2993 specified the OpenCL fence has to convervatively assume both local and
2994 global address space was specified. However, optimizations can often be
2995 done to eliminate the additional ``s_waitcnt`` instructions when there are
2996 no intervening memory instructions which access the corresponding address
2997 space. The code sequences in the table indicate what can be omitted for the
2998 OpenCL memory. The target triple environment is used to determine if the
2999 source language is OpenCL (see :ref:`amdgpu-opencl`).
3001 ``ds/flat_load/store/atomic`` instructions to local memory are termed LDS
3004 ``buffer/global/flat_load/store/atomic`` instructions to global memory are
3005 termed vector memory operations.
3009 * Each agent has multiple compute units (CU).
3010 * Each CU has multiple SIMDs that execute wavefronts.
3011 * The wavefronts for a single work-group are executed in the same CU but may be
3012 executed by different SIMDs.
3013 * Each CU has a single LDS memory shared by the wavefronts of the work-groups
3015 * All LDS operations of a CU are performed as wavefront wide operations in a
3016 global order and involve no caching. Completion is reported to a wavefront in
3018 * The LDS memory has multiple request queues shared by the SIMDs of a
3019 CU. Therefore, the LDS operations performed by different wavefronts of a work-group
3020 can be reordered relative to each other, which can result in reordering the
3021 visibility of vector memory operations with respect to LDS operations of other
3022 wavefronts in the same work-group. A ``s_waitcnt lgkmcnt(0)`` is required to
3023 ensure synchronization between LDS operations and vector memory operations
3024 between wavefronts of a work-group, but not between operations performed by the
3026 * The vector memory operations are performed as wavefront wide operations and
3027 completion is reported to a wavefront in execution order. The exception is
3028 that for GFX7-GFX9 ``flat_load/store/atomic`` instructions can report out of
3029 vector memory order if they access LDS memory, and out of LDS operation order
3030 if they access global memory.
3031 * The vector memory operations access a single vector L1 cache shared by all
3032 SIMDs a CU. Therefore, no special action is required for coherence between the
3033 lanes of a single wavefront, or for coherence between wavefronts in the same
3034 work-group. A ``buffer_wbinvl1_vol`` is required for coherence between wavefronts
3035 executing in different work-groups as they may be executing on different CUs.
3036 * The scalar memory operations access a scalar L1 cache shared by all wavefronts
3037 on a group of CUs. The scalar and vector L1 caches are not coherent. However,
3038 scalar operations are used in a restricted way so do not impact the memory
3039 model. See :ref:`amdgpu-amdhsa-memory-spaces`.
3040 * The vector and scalar memory operations use an L2 cache shared by all CUs on
3042 * The L2 cache has independent channels to service disjoint ranges of virtual
3044 * Each CU has a separate request queue per channel. Therefore, the vector and
3045 scalar memory operations performed by wavefronts executing in different work-groups
3046 (which may be executing on different CUs) of an agent can be reordered
3047 relative to each other. A ``s_waitcnt vmcnt(0)`` is required to ensure
3048 synchronization between vector memory operations of different CUs. It ensures a
3049 previous vector memory operation has completed before executing a subsequent
3050 vector memory or LDS operation and so can be used to meet the requirements of
3051 acquire and release.
3052 * The L2 cache can be kept coherent with other agents on some targets, or ranges
3053 of virtual addresses can be set up to bypass it to ensure system coherence.
3055 Private address space uses ``buffer_load/store`` using the scratch V# (GFX6-GFX8),
3056 or ``scratch_load/store`` (GFX9). Since only a single thread is accessing the
3057 memory, atomic memory orderings are not meaningful and all accesses are treated
3060 Constant address space uses ``buffer/global_load`` instructions (or equivalent
3061 scalar memory instructions). Since the constant address space contents do not
3062 change during the execution of a kernel dispatch it is not legal to perform
3063 stores, and atomic memory orderings are not meaningful and all access are
3064 treated as non-atomic.
3066 A memory synchronization scope wider than work-group is not meaningful for the
3067 group (LDS) address space and is treated as work-group.
3069 The memory model does not support the region address space which is treated as
3072 Acquire memory ordering is not meaningful on store atomic instructions and is
3073 treated as non-atomic.
3075 Release memory ordering is not meaningful on load atomic instructions and is
3076 treated a non-atomic.
3078 Acquire-release memory ordering is not meaningful on load or store atomic
3079 instructions and is treated as acquire and release respectively.
3081 AMDGPU backend only uses scalar memory operations to access memory that is
3082 proven to not change during the execution of the kernel dispatch. This includes
3083 constant address space and global address space for program scope const
3084 variables. Therefore the kernel machine code does not have to maintain the
3085 scalar L1 cache to ensure it is coherent with the vector L1 cache. The scalar
3086 and vector L1 caches are invalidated between kernel dispatches by CP since
3087 constant address space data may change between kernel dispatch executions. See
3088 :ref:`amdgpu-amdhsa-memory-spaces`.
3090 The one execption is if scalar writes are used to spill SGPR registers. In this
3091 case the AMDGPU backend ensures the memory location used to spill is never
3092 accessed by vector memory operations at the same time. If scalar writes are used
3093 then a ``s_dcache_wb`` is inserted before the ``s_endpgm`` and before a function
3094 return since the locations may be used for vector memory instructions by a
3095 future wavefront that uses the same scratch area, or a function call that creates a
3096 frame at the same address, respectively. There is no need for a ``s_dcache_inv``
3097 as all scalar writes are write-before-read in the same thread.
3099 Scratch backing memory (which is used for the private address space)
3100 is accessed with MTYPE NC_NV (non-coherenent non-volatile). Since the private
3101 address space is only accessed by a single thread, and is always
3102 write-before-read, there is never a need to invalidate these entries from the L1
3103 cache. Hence all cache invalidates are done as ``*_vol`` to only invalidate the
3104 volatile cache lines.
3106 On dGPU the kernarg backing memory is accessed as UC (uncached) to avoid needing
3107 to invalidate the L2 cache. This also causes it to be treated as
3108 non-volatile and so is not invalidated by ``*_vol``. On APU it is accessed as CC
3109 (cache coherent) and so the L2 cache will coherent with the CPU and other
3112 .. table:: AMDHSA Memory Model Code Sequences GFX6-GFX9
3113 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table
3115 ============ ============ ============== ========== ===============================
3116 LLVM Instr LLVM Memory LLVM Memory AMDGPU AMDGPU Machine Code
3117 Ordering Sync Scope Address
3119 ============ ============ ============== ========== ===============================
3121 -----------------------------------------------------------------------------------
3122 load *none* *none* - global - !volatile & !nontemporal
3124 - private 1. buffer/global/flat_load
3126 - volatile & !nontemporal
3128 1. buffer/global/flat_load
3133 1. buffer/global/flat_load
3136 load *none* *none* - local 1. ds_load
3137 store *none* *none* - global - !nontemporal
3139 - private 1. buffer/global/flat_store
3143 1. buffer/global/flat_stote
3146 store *none* *none* - local 1. ds_store
3147 **Unordered Atomic**
3148 -----------------------------------------------------------------------------------
3149 load atomic unordered *any* *any* *Same as non-atomic*.
3150 store atomic unordered *any* *any* *Same as non-atomic*.
3151 atomicrmw unordered *any* *any* *Same as monotonic
3153 **Monotonic Atomic**
3154 -----------------------------------------------------------------------------------
3155 load atomic monotonic - singlethread - global 1. buffer/global/flat_load
3156 - wavefront - generic
3158 load atomic monotonic - singlethread - local 1. ds_load
3161 load atomic monotonic - agent - global 1. buffer/global/flat_load
3162 - system - generic glc=1
3163 store atomic monotonic - singlethread - global 1. buffer/global/flat_store
3164 - wavefront - generic
3168 store atomic monotonic - singlethread - local 1. ds_store
3171 atomicrmw monotonic - singlethread - global 1. buffer/global/flat_atomic
3172 - wavefront - generic
3176 atomicrmw monotonic - singlethread - local 1. ds_atomic
3180 -----------------------------------------------------------------------------------
3181 load atomic acquire - singlethread - global 1. buffer/global/ds/flat_load
3184 load atomic acquire - workgroup - global 1. buffer/global/flat_load
3185 load atomic acquire - workgroup - local 1. ds_load
3186 2. s_waitcnt lgkmcnt(0)
3189 - Must happen before
3201 load atomic acquire - workgroup - generic 1. flat_load
3202 2. s_waitcnt lgkmcnt(0)
3205 - Must happen before
3217 load atomic acquire - agent - global 1. buffer/global/flat_load
3219 2. s_waitcnt vmcnt(0)
3221 - Must happen before
3229 3. buffer_wbinvl1_vol
3231 - Must happen before
3241 load atomic acquire - agent - generic 1. flat_load glc=1
3242 - system 2. s_waitcnt vmcnt(0) &
3247 - Must happen before
3250 - Ensures the flat_load
3255 3. buffer_wbinvl1_vol
3257 - Must happen before
3267 atomicrmw acquire - singlethread - global 1. buffer/global/ds/flat_atomic
3270 atomicrmw acquire - workgroup - global 1. buffer/global/flat_atomic
3271 atomicrmw acquire - workgroup - local 1. ds_atomic
3272 2. waitcnt lgkmcnt(0)
3275 - Must happen before
3288 atomicrmw acquire - workgroup - generic 1. flat_atomic
3289 2. waitcnt lgkmcnt(0)
3292 - Must happen before
3305 atomicrmw acquire - agent - global 1. buffer/global/flat_atomic
3306 - system 2. s_waitcnt vmcnt(0)
3308 - Must happen before
3317 3. buffer_wbinvl1_vol
3319 - Must happen before
3329 atomicrmw acquire - agent - generic 1. flat_atomic
3330 - system 2. s_waitcnt vmcnt(0) &
3335 - Must happen before
3344 3. buffer_wbinvl1_vol
3346 - Must happen before
3356 fence acquire - singlethread *none* *none*
3358 fence acquire - workgroup *none* 1. s_waitcnt lgkmcnt(0)
3363 - However, since LLVM
3388 fence-paired-atomic).
3389 - Must happen before
3400 fence-paired-atomic.
3402 fence acquire - agent *none* 1. s_waitcnt lgkmcnt(0) &
3409 - However, since LLVM
3417 - Could be split into
3426 - s_waitcnt vmcnt(0)
3437 fence-paired-atomic).
3438 - s_waitcnt lgkmcnt(0)
3449 fence-paired-atomic).
3450 - Must happen before
3464 fence-paired-atomic.
3466 2. buffer_wbinvl1_vol
3468 - Must happen before any
3469 following global/generic
3479 -----------------------------------------------------------------------------------
3480 store atomic release - singlethread - global 1. buffer/global/ds/flat_store
3483 store atomic release - workgroup - global 1. s_waitcnt lgkmcnt(0)
3492 - Must happen before
3503 2. buffer/global/flat_store
3504 store atomic release - workgroup - local 1. ds_store
3505 store atomic release - workgroup - generic 1. s_waitcnt lgkmcnt(0)
3514 - Must happen before
3526 store atomic release - agent - global 1. s_waitcnt lgkmcnt(0) &
3527 - system - generic vmcnt(0)
3531 - Could be split into
3540 - s_waitcnt vmcnt(0)
3547 - s_waitcnt lgkmcnt(0)
3554 - Must happen before
3565 2. buffer/global/ds/flat_store
3566 atomicrmw release - singlethread - global 1. buffer/global/ds/flat_atomic
3569 atomicrmw release - workgroup - global 1. s_waitcnt lgkmcnt(0)
3578 - Must happen before
3589 2. buffer/global/flat_atomic
3590 atomicrmw release - workgroup - local 1. ds_atomic
3591 atomicrmw release - workgroup - generic 1. s_waitcnt lgkmcnt(0)
3600 - Must happen before
3612 atomicrmw release - agent - global 1. s_waitcnt lgkmcnt(0) &
3613 - system - generic vmcnt(0)
3617 - Could be split into
3626 - s_waitcnt vmcnt(0)
3633 - s_waitcnt lgkmcnt(0)
3640 - Must happen before
3651 2. buffer/global/ds/flat_atomic
3652 fence release - singlethread *none* *none*
3654 fence release - workgroup *none* 1. s_waitcnt lgkmcnt(0)
3659 - However, since LLVM
3680 - Must happen before
3689 fence-paired-atomic).
3696 fence-paired-atomic.
3698 fence release - agent *none* 1. s_waitcnt lgkmcnt(0) &
3709 - However, since LLVM
3724 - Could be split into
3733 - s_waitcnt vmcnt(0)
3740 - s_waitcnt lgkmcnt(0)
3747 - Must happen before
3756 fence-paired-atomic).
3763 fence-paired-atomic.
3765 **Acquire-Release Atomic**
3766 -----------------------------------------------------------------------------------
3767 atomicrmw acq_rel - singlethread - global 1. buffer/global/ds/flat_atomic
3770 atomicrmw acq_rel - workgroup - global 1. s_waitcnt lgkmcnt(0)
3779 - Must happen before
3790 2. buffer/global/flat_atomic
3791 atomicrmw acq_rel - workgroup - local 1. ds_atomic
3792 2. s_waitcnt lgkmcnt(0)
3795 - Must happen before
3808 atomicrmw acq_rel - workgroup - generic 1. s_waitcnt lgkmcnt(0)
3817 - Must happen before
3829 3. s_waitcnt lgkmcnt(0)
3832 - Must happen before
3845 atomicrmw acq_rel - agent - global 1. s_waitcnt lgkmcnt(0) &
3850 - Could be split into
3859 - s_waitcnt vmcnt(0)
3866 - s_waitcnt lgkmcnt(0)
3873 - Must happen before
3884 2. buffer/global/flat_atomic
3885 3. s_waitcnt vmcnt(0)
3887 - Must happen before
3896 4. buffer_wbinvl1_vol
3898 - Must happen before
3908 atomicrmw acq_rel - agent - generic 1. s_waitcnt lgkmcnt(0) &
3913 - Could be split into
3922 - s_waitcnt vmcnt(0)
3929 - s_waitcnt lgkmcnt(0)
3936 - Must happen before
3948 3. s_waitcnt vmcnt(0) &
3953 - Must happen before
3962 4. buffer_wbinvl1_vol
3964 - Must happen before
3974 fence acq_rel - singlethread *none* *none*
3976 fence acq_rel - workgroup *none* 1. s_waitcnt lgkmcnt(0)
3996 - Must happen before
4019 acquire-fence-paired-atomic
4040 release-fence-paired-atomic
4041 ). This satisfies the
4045 fence acq_rel - agent *none* 1. s_waitcnt lgkmcnt(0) &
4052 - However, since LLVM
4060 - Could be split into
4069 - s_waitcnt vmcnt(0)
4076 - s_waitcnt lgkmcnt(0)
4083 - Must happen before
4088 global/local/generic
4097 acquire-fence-paired-atomic
4109 global/local/generic
4118 release-fence-paired-atomic
4119 ). This satisfies the
4123 2. buffer_wbinvl1_vol
4125 - Must happen before
4139 **Sequential Consistent Atomic**
4140 -----------------------------------------------------------------------------------
4141 load atomic seq_cst - singlethread - global *Same as corresponding
4142 - wavefront - local load atomic acquire,
4143 - generic except must generated
4144 all instructions even
4146 load atomic seq_cst - workgroup - global 1. s_waitcnt lgkmcnt(0)
4161 lgkmcnt(0) and so do
4196 instructions same as
4199 except must generated
4200 all instructions even
4202 load atomic seq_cst - workgroup - local *Same as corresponding
4203 load atomic acquire,
4204 except must generated
4205 all instructions even
4207 load atomic seq_cst - agent - global 1. s_waitcnt lgkmcnt(0) &
4208 - system - generic vmcnt(0)
4210 - Could be split into
4219 - waitcnt lgkmcnt(0)
4232 lgkmcnt(0) and so do
4283 instructions same as
4286 except must generated
4287 all instructions even
4289 store atomic seq_cst - singlethread - global *Same as corresponding
4290 - wavefront - local store atomic release,
4291 - workgroup - generic except must generated
4292 all instructions even
4294 store atomic seq_cst - agent - global *Same as corresponding
4295 - system - generic store atomic release,
4296 except must generated
4297 all instructions even
4299 atomicrmw seq_cst - singlethread - global *Same as corresponding
4300 - wavefront - local atomicrmw acq_rel,
4301 - workgroup - generic except must generated
4302 all instructions even
4304 atomicrmw seq_cst - agent - global *Same as corresponding
4305 - system - generic atomicrmw acq_rel,
4306 except must generated
4307 all instructions even
4309 fence seq_cst - singlethread *none* *Same as corresponding
4310 - wavefront fence acq_rel,
4311 - workgroup except must generated
4312 - agent all instructions even
4313 - system for OpenCL.*
4314 ============ ============ ============== ========== ===============================
4316 The memory order also adds the single thread optimization constrains defined in
4318 :ref:`amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table`.
4320 .. table:: AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX9
4321 :name: amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table
4323 ============ ==============================================================
4324 LLVM Memory Optimization Constraints
4326 ============ ==============================================================
4329 acquire - If a load atomic/atomicrmw then no following load/load
4330 atomic/store/ store atomic/atomicrmw/fence instruction can
4331 be moved before the acquire.
4332 - If a fence then same as load atomic, plus no preceding
4333 associated fence-paired-atomic can be moved after the fence.
4334 release - If a store atomic/atomicrmw then no preceding load/load
4335 atomic/store/ store atomic/atomicrmw/fence instruction can
4336 be moved after the release.
4337 - If a fence then same as store atomic, plus no following
4338 associated fence-paired-atomic can be moved before the
4340 acq_rel Same constraints as both acquire and release.
4341 seq_cst - If a load atomic then same constraints as acquire, plus no
4342 preceding sequentially consistent load atomic/store
4343 atomic/atomicrmw/fence instruction can be moved after the
4345 - If a store atomic then the same constraints as release, plus
4346 no following sequentially consistent load atomic/store
4347 atomic/atomicrmw/fence instruction can be moved before the
4349 - If an atomicrmw/fence then same constraints as acq_rel.
4350 ============ ==============================================================
4355 For code objects generated by AMDGPU backend for HSA [HSA]_ compatible runtimes
4356 (such as ROCm [AMD-ROCm]_), the runtime installs a trap handler that supports
4357 the ``s_trap`` instruction with the following usage:
4359 .. table:: AMDGPU Trap Handler for AMDHSA OS
4360 :name: amdgpu-trap-handler-for-amdhsa-os-table
4362 =================== =============== =============== =======================
4363 Usage Code Sequence Trap Handler Description
4365 =================== =============== =============== =======================
4366 reserved ``s_trap 0x00`` Reserved by hardware.
4367 ``debugtrap(arg)`` ``s_trap 0x01`` ``SGPR0-1``: Reserved for HSA
4368 ``queue_ptr`` ``debugtrap``
4369 ``VGPR0``: intrinsic (not
4370 ``arg`` implemented).
4371 ``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: Causes dispatch to be
4372 ``queue_ptr`` terminated and its
4373 associated queue put
4374 into the error state.
4375 ``llvm.debugtrap`` ``s_trap 0x03`` - If debugger not
4385 - If the debugger is
4387 the debug trap to be
4391 the halt state until
4394 reserved ``s_trap 0x04`` Reserved.
4395 reserved ``s_trap 0x05`` Reserved.
4396 reserved ``s_trap 0x06`` Reserved.
4397 debugger breakpoint ``s_trap 0x07`` Reserved for debugger
4399 reserved ``s_trap 0x08`` Reserved.
4400 reserved ``s_trap 0xfe`` Reserved.
4401 reserved ``s_trap 0xff`` Reserved.
4402 =================== =============== =============== =======================
4407 This section provides code conventions used when the target triple OS is
4408 ``amdpal`` (see :ref:`amdgpu-target-triples`) for passing runtime parameters
4409 from the application/runtime to each invocation of a hardware shader. These
4410 parameters include both generic, application-controlled parameters called
4411 *user data* as well as system-generated parameters that are a product of the
4412 draw or dispatch execution.
4417 Each hardware stage has a set of 32-bit *user data registers* which can be
4418 written from a command buffer and then loaded into SGPRs when waves are launched
4419 via a subsequent dispatch or draw operation. This is the way most arguments are
4420 passed from the application/runtime to a hardware shader.
4425 Compute shader user data mappings are simpler than graphics shaders, and have a
4428 Note that there are always 10 available *user data entries* in registers -
4429 entries beyond that limit must be fetched from memory (via the spill table
4430 pointer) by the shader.
4432 .. table:: PAL Compute Shader User Data Registers
4433 :name: pal-compute-user-data-registers
4435 ============= ================================
4436 User Register Description
4437 ============= ================================
4438 0 Global Internal Table (32-bit pointer)
4439 1 Per-Shader Internal Table (32-bit pointer)
4440 2 - 11 Application-Controlled User Data (10 32-bit values)
4441 12 Spill Table (32-bit pointer)
4442 13 - 14 Thread Group Count (64-bit pointer)
4444 ============= ================================
4449 Graphics pipelines support a much more flexible user data mapping:
4451 .. table:: PAL Graphics Shader User Data Registers
4452 :name: pal-graphics-user-data-registers
4454 ============= ================================
4455 User Register Description
4456 ============= ================================
4457 0 Global Internal Table (32-bit pointer)
4458 + Per-Shader Internal Table (32-bit pointer)
4459 + 1-15 Application Controlled User Data
4460 (1-15 Contiguous 32-bit Values in Registers)
4461 + Spill Table (32-bit pointer)
4462 + Draw Index (First Stage Only)
4463 + Vertex Offset (First Stage Only)
4464 + Instance Offset (First Stage Only)
4465 ============= ================================
4467 The placement of the global internal table remains fixed in the first *user
4468 data SGPR register*. Otherwise all parameters are optional, and can be mapped
4469 to any desired *user data SGPR register*, with the following regstrictions:
4471 * Draw Index, Vertex Offset, and Instance Offset can only be used by the first
4472 activehardware stage in a graphics pipeline (i.e. where the API vertex
4475 * Application-controlled user data must be mapped into a contiguous range of
4476 user data registers.
4478 * The application-controlled user data range supports compaction remapping, so
4479 only *entries* that are actually consumed by the shader must be assigned to
4480 corresponding *registers*. Note that in order to support an efficient runtime
4481 implementation, the remapping must pack *registers* in the same order as
4482 *entries*, with unused *entries* removed.
4484 .. _pal_global_internal_table:
4486 Global Internal Table
4487 ~~~~~~~~~~~~~~~~~~~~~
4489 The global internal table is a table of *shader resource descriptors* (SRDs) that
4490 define how certain engine-wide, runtime-managed resources should be accessed
4491 from a shader. The majority of these resources have HW-defined formats, and it
4492 is up to the compiler to write/read data as required by the target hardware.
4494 The following table illustrates the required format:
4496 .. table:: PAL Global Internal Table
4497 :name: pal-git-table
4499 ============= ================================
4501 ============= ================================
4502 0-3 Graphics Scratch SRD
4503 4-7 Compute Scratch SRD
4504 8-11 ES/GS Ring Output SRD
4505 12-15 ES/GS Ring Input SRD
4506 16-19 GS/VS Ring Output #0
4507 20-23 GS/VS Ring Output #1
4508 24-27 GS/VS Ring Output #2
4509 28-31 GS/VS Ring Output #3
4510 32-35 GS/VS Ring Input SRD
4511 36-39 Tessellation Factor Buffer SRD
4512 40-43 Off-Chip LDS Buffer SRD
4513 44-47 Off-Chip Param Cache Buffer SRD
4514 48-51 Sample Position Buffer SRD
4515 52 vaRange::ShadowDescriptorTable High Bits
4516 ============= ================================
4518 The pointer to the global internal table passed to the shader as user data
4519 is a 32-bit pointer. The top 32 bits should be assumed to be the same as
4520 the top 32 bits of the pipeline, so the shader may use the program
4521 counter's top 32 bits.
4526 This section provides code conventions used when the target triple OS is
4527 empty (see :ref:`amdgpu-target-triples`).
4532 For code objects generated by AMDGPU backend for non-amdhsa OS, the runtime does
4533 not install a trap handler. The ``llvm.trap`` and ``llvm.debugtrap``
4534 instructions are handled as follows:
4536 .. table:: AMDGPU Trap Handler for Non-AMDHSA OS
4537 :name: amdgpu-trap-handler-for-non-amdhsa-os-table
4539 =============== =============== ===========================================
4540 Usage Code Sequence Description
4541 =============== =============== ===========================================
4542 llvm.trap s_endpgm Causes wavefront to be terminated.
4543 llvm.debugtrap *none* Compiler warning given that there is no
4544 trap handler installed.
4545 =============== =============== ===========================================
4555 When the language is OpenCL the following differences occur:
4557 1. The OpenCL memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
4558 2. The AMDGPU backend appends additional arguments to the kernel's explicit
4559 arguments for the AMDHSA OS (see
4560 :ref:`opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table`).
4561 3. Additional metadata is generated
4562 (see :ref:`amdgpu-amdhsa-code-object-metadata`).
4564 .. table:: OpenCL kernel implicit arguments appended for AMDHSA OS
4565 :name: opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table
4567 ======== ==== ========= ===========================================
4568 Position Byte Byte Description
4570 ======== ==== ========= ===========================================
4571 1 8 8 OpenCL Global Offset X
4572 2 8 8 OpenCL Global Offset Y
4573 3 8 8 OpenCL Global Offset Z
4574 4 8 8 OpenCL address of printf buffer
4575 5 8 8 OpenCL address of virtual queue used by
4577 6 8 8 OpenCL address of AqlWrap struct used by
4579 ======== ==== ========= ===========================================
4586 When the language is HCC the following differences occur:
4588 1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
4590 .. _amdgpu-assembler:
4595 AMDGPU backend has LLVM-MC based assembler which is currently in development.
4596 It supports AMDGCN GFX6-GFX9.
4598 This section describes general syntax for instructions and operands.
4606 AMDGPU/AMDGPUAsmGFX7
4607 AMDGPU/AMDGPUAsmGFX8
4608 AMDGPU/AMDGPUAsmGFX9
4609 AMDGPUModifierSyntax
4611 AMDGPUInstructionSyntax
4612 AMDGPUInstructionNotation
4614 An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:
4616 ``<``\ *opcode*\ ``> <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,... <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
4618 :doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while
4619 :doc:`modifiers<AMDGPUModifierSyntax>` are space-separated.
4621 The order of *operands* and *modifiers* is fixed.
4622 Most *modifiers* are optional and may be omitted.
4624 See detailed instruction syntax description for :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`,
4625 :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`.
4627 Note that features under development are not included in this description.
4629 For more information about instructions, their semantics and supported combinations of
4630 operands, refer to one of instruction set architecture manuals
4631 [AMD-GCN-GFX6]_, [AMD-GCN-GFX7]_, [AMD-GCN-GFX8]_ and [AMD-GCN-GFX9]_.
4636 Detailed description of operands may be found :doc:`here<AMDGPUOperandSyntax>`.
4641 Detailed description of modifiers may be found :doc:`here<AMDGPUModifierSyntax>`.
4643 Instruction Examples
4644 ~~~~~~~~~~~~~~~~~~~~
4649 .. code-block:: nasm
4651 ds_add_u32 v2, v4 offset:16
4652 ds_write_src2_b64 v2 offset0:4 offset1:8
4653 ds_cmpst_f32 v2, v4, v6
4654 ds_min_rtn_f64 v[8:9], v2, v[4:5]
4657 For full list of supported instructions, refer to "LDS/GDS instructions" in ISA Manual.
4662 .. code-block:: nasm
4664 flat_load_dword v1, v[3:4]
4665 flat_store_dwordx3 v[3:4], v[5:7]
4666 flat_atomic_swap v1, v[3:4], v5 glc
4667 flat_atomic_cmpswap v1, v[3:4], v[5:6] glc slc
4668 flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc
4670 For full list of supported instructions, refer to "FLAT instructions" in ISA Manual.
4675 .. code-block:: nasm
4677 buffer_load_dword v1, off, s[4:7], s1
4678 buffer_store_dwordx4 v[1:4], v2, ttmp[4:7], s1 offen offset:4 glc tfe
4679 buffer_store_format_xy v[1:2], off, s[4:7], s1
4681 buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc
4683 For full list of supported instructions, refer to "MUBUF Instructions" in ISA Manual.
4688 .. code-block:: nasm
4690 s_load_dword s1, s[2:3], 0xfc
4691 s_load_dwordx8 s[8:15], s[2:3], s4
4692 s_load_dwordx16 s[88:103], s[2:3], s4
4696 For full list of supported instructions, refer to "Scalar Memory Operations" in ISA Manual.
4701 .. code-block:: nasm
4704 s_mov_b64 s[0:1], 0x80000000
4706 s_wqm_b64 s[2:3], s[4:5]
4707 s_bcnt0_i32_b64 s1, s[2:3]
4708 s_swappc_b64 s[2:3], s[4:5]
4709 s_cbranch_join s[4:5]
4711 For full list of supported instructions, refer to "SOP1 Instructions" in ISA Manual.
4716 .. code-block:: nasm
4718 s_add_u32 s1, s2, s3
4719 s_and_b64 s[2:3], s[4:5], s[6:7]
4720 s_cselect_b32 s1, s2, s3
4721 s_andn2_b32 s2, s4, s6
4722 s_lshr_b64 s[2:3], s[4:5], s6
4723 s_ashr_i32 s2, s4, s6
4724 s_bfm_b64 s[2:3], s4, s6
4725 s_bfe_i64 s[2:3], s[4:5], s6
4726 s_cbranch_g_fork s[4:5], s[6:7]
4728 For full list of supported instructions, refer to "SOP2 Instructions" in ISA Manual.
4733 .. code-block:: nasm
4736 s_bitcmp1_b32 s1, s2
4737 s_bitcmp0_b64 s[2:3], s4
4740 For full list of supported instructions, refer to "SOPC Instructions" in ISA Manual.
4745 .. code-block:: nasm
4750 s_waitcnt 0 ; Wait for all counters to be 0
4751 s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0) ; Equivalent to above
4752 s_waitcnt vmcnt(1) ; Wait for vmcnt counter to be 1.
4756 s_sendmsg sendmsg(MSG_INTERRUPT)
4759 For full list of supported instructions, refer to "SOPP Instructions" in ISA Manual.
4761 Unless otherwise mentioned, little verification is performed on the operands
4762 of SOPP Instructions, so it is up to the programmer to be familiar with the
4763 range or acceptable values.
4768 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
4769 the assembler will automatically use optimal encoding based on its operands.
4770 To force specific encoding, one can add a suffix to the opcode of the instruction:
4772 * _e32 for 32-bit VOP1/VOP2/VOPC
4773 * _e64 for 64-bit VOP3
4775 * _sdwa for VOP_SDWA
4777 VOP1/VOP2/VOP3/VOPC examples:
4779 .. code-block:: nasm
4782 v_mov_b32_e32 v1, v2
4784 v_cvt_f64_i32_e32 v[1:2], v2
4785 v_floor_f32_e32 v1, v2
4786 v_bfrev_b32_e32 v1, v2
4787 v_add_f32_e32 v1, v2, v3
4788 v_mul_i32_i24_e64 v1, v2, 3
4789 v_mul_i32_i24_e32 v1, -3, v3
4790 v_mul_i32_i24_e32 v1, -100, v3
4791 v_addc_u32 v1, s[0:1], v2, v3, s[2:3]
4792 v_max_f16_e32 v1, v2, v3
4796 .. code-block:: nasm
4798 v_mov_b32 v0, v0 quad_perm:[0,2,1,1]
4799 v_sin_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
4800 v_mov_b32 v0, v0 wave_shl:1
4801 v_mov_b32 v0, v0 row_mirror
4802 v_mov_b32 v0, v0 row_bcast:31
4803 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0
4804 v_add_f32 v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
4805 v_max_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
4809 .. code-block:: nasm
4811 v_mov_b32 v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
4812 v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
4813 v_sin_f32 v0, v0 dst_unused:UNUSED_PAD src0_sel:WORD_1
4814 v_fract_f32 v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
4815 v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
4817 For full list of supported instructions, refer to "Vector ALU instructions".
4820 Remove once we switch to code object v3 by default.
4822 .. _amdgpu-amdhsa-assembler-predefined-symbols-v2:
4824 Code Object V2 Predefined Symbols (-mattr=-code-object-v3)
4825 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
4827 .. warning:: Code Object V2 is not the default code object version emitted by
4828 this version of LLVM. For a description of the predefined symbols available
4829 with the default configuration (Code Object V3) see
4830 :ref:`amdgpu-amdhsa-assembler-predefined-symbols-v3`.
4832 The AMDGPU assembler defines and updates some symbols automatically. These
4833 symbols do not affect code generation.
4835 .option.machine_version_major
4836 +++++++++++++++++++++++++++++
4838 Set to the GFX major generation number of the target being assembled for. For
4839 example, when assembling for a "GFX9" target this will be set to the integer
4840 value "9". The possible GFX major generation numbers are presented in
4841 :ref:`amdgpu-processors`.
4843 .option.machine_version_minor
4844 +++++++++++++++++++++++++++++
4846 Set to the GFX minor generation number of the target being assembled for. For
4847 example, when assembling for a "GFX810" target this will be set to the integer
4848 value "1". The possible GFX minor generation numbers are presented in
4849 :ref:`amdgpu-processors`.
4851 .option.machine_version_stepping
4852 ++++++++++++++++++++++++++++++++
4854 Set to the GFX stepping generation number of the target being assembled for.
4855 For example, when assembling for a "GFX704" target this will be set to the
4856 integer value "4". The possible GFX stepping generation numbers are presented
4857 in :ref:`amdgpu-processors`.
4862 Set to zero each time a
4863 :ref:`amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel` directive is
4864 encountered. At each instruction, if the current value of this symbol is less
4865 than or equal to the maximum VPGR number explicitly referenced within that
4866 instruction then the symbol value is updated to equal that VGPR number plus
4872 Set to zero each time a
4873 :ref:`amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel` directive is
4874 encountered. At each instruction, if the current value of this symbol is less
4875 than or equal to the maximum VPGR number explicitly referenced within that
4876 instruction then the symbol value is updated to equal that SGPR number plus
4879 .. _amdgpu-amdhsa-assembler-directives-v2:
4881 Code Object V2 Directives (-mattr=-code-object-v3)
4882 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
4884 .. warning:: Code Object V2 is not the default code object version emitted by
4885 this version of LLVM. For a description of the directives supported with
4886 the default configuration (Code Object V3) see
4887 :ref:`amdgpu-amdhsa-assembler-directives-v3`.
4889 AMDGPU ABI defines auxiliary data in output code object. In assembly source,
4890 one can specify them with assembler directives.
4892 .hsa_code_object_version major, minor
4893 +++++++++++++++++++++++++++++++++++++
4895 *major* and *minor* are integers that specify the version of the HSA code
4896 object that will be generated by the assembler.
4898 .hsa_code_object_isa [major, minor, stepping, vendor, arch]
4899 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4902 *major*, *minor*, and *stepping* are all integers that describe the instruction
4903 set architecture (ISA) version of the assembly program.
4905 *vendor* and *arch* are quoted strings. *vendor* should always be equal to
4906 "AMD" and *arch* should always be equal to "AMDGPU".
4908 By default, the assembler will derive the ISA version, *vendor*, and *arch*
4909 from the value of the -mcpu option that is passed to the assembler.
4911 .. _amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel:
4913 .amdgpu_hsa_kernel (name)
4914 +++++++++++++++++++++++++
4916 This directives specifies that the symbol with given name is a kernel entry point
4917 (label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.
4922 This directive marks the beginning of a list of key / value pairs that are used
4923 to specify the amd_kernel_code_t object that will be emitted by the assembler.
4924 The list must be terminated by the *.end_amd_kernel_code_t* directive. For
4925 any amd_kernel_code_t values that are unspecified a default value will be
4926 used. The default value for all keys is 0, with the following exceptions:
4928 - *kernel_code_version_major* defaults to 1.
4929 - *machine_kind* defaults to 1.
4930 - *machine_version_major*, *machine_version_minor*, and
4931 *machine_version_stepping* are derived from the value of the -mcpu option
4932 that is passed to the assembler.
4933 - *kernel_code_entry_byte_offset* defaults to 256.
4934 - *wavefront_size* defaults to 6.
4935 - *kernarg_segment_alignment*, *group_segment_alignment*, and
4936 *private_segment_alignment* default to 4. Note that alignments are specified
4937 as a power of 2, so a value of **n** means an alignment of 2^ **n**.
4939 The *.amd_kernel_code_t* directive must be placed immediately after the
4940 function label and before any instructions.
4942 For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
4943 comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.
4945 .. _amdgpu-amdhsa-assembler-example-v2:
4947 Code Object V2 Example Source Code (-mattr=-code-object-v3)
4948 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
4950 .. warning:: Code Object V2 is not the default code object version emitted by
4951 this version of LLVM. For a description of the directives supported with
4952 the default configuration (Code Object V3) see
4953 :ref:`amdgpu-amdhsa-assembler-example-v3`.
4955 Here is an example of a minimal assembly source file, defining one HSA kernel:
4957 .. code-block:: none
4959 .hsa_code_object_version 1,0
4960 .hsa_code_object_isa
4965 .amdgpu_hsa_kernel hello_world
4970 enable_sgpr_kernarg_segment_ptr = 1
4972 compute_pgm_rsrc1_vgprs = 0
4973 compute_pgm_rsrc1_sgprs = 0
4974 compute_pgm_rsrc2_user_sgpr = 2
4975 kernarg_segment_byte_size = 8
4976 wavefront_sgpr_count = 2
4977 workitem_vgpr_count = 3
4978 .end_amd_kernel_code_t
4980 s_load_dwordx2 s[0:1], s[0:1] 0x0
4981 v_mov_b32 v0, 3.14159
4982 s_waitcnt lgkmcnt(0)
4985 flat_store_dword v[1:2], v0
4988 .size hello_world, .Lfunc_end0-hello_world
4990 .. _amdgpu-amdhsa-assembler-predefined-symbols-v3:
4992 Code Object V3 Predefined Symbols (-mattr=+code-object-v3)
4993 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
4995 The AMDGPU assembler defines and updates some symbols automatically. These
4996 symbols do not affect code generation.
4998 .amdgcn.gfx_generation_number
4999 +++++++++++++++++++++++++++++
5001 Set to the GFX major generation number of the target being assembled for. For
5002 example, when assembling for a "GFX9" target this will be set to the integer
5003 value "9". The possible GFX major generation numbers are presented in
5004 :ref:`amdgpu-processors`.
5006 .amdgcn.gfx_generation_minor
5007 ++++++++++++++++++++++++++++
5009 Set to the GFX minor generation number of the target being assembled for. For
5010 example, when assembling for a "GFX810" target this will be set to the integer
5011 value "1". The possible GFX minor generation numbers are presented in
5012 :ref:`amdgpu-processors`.
5014 .amdgcn.gfx_generation_stepping
5015 +++++++++++++++++++++++++++++++
5017 Set to the GFX stepping generation number of the target being assembled for.
5018 For example, when assembling for a "GFX704" target this will be set to the
5019 integer value "4". The possible GFX stepping generation numbers are presented
5020 in :ref:`amdgpu-processors`.
5022 .amdgcn.next_free_vgpr
5023 ++++++++++++++++++++++
5025 Set to zero before assembly begins. At each instruction, if the current value
5026 of this symbol is less than or equal to the maximum VGPR number explicitly
5027 referenced within that instruction then the symbol value is updated to equal
5028 that VGPR number plus one.
5030 May be used to set the `.amdhsa_next_free_vpgr` directive in
5031 :ref:`amdhsa-kernel-directives-table`.
5033 May be set at any time, e.g. manually set to zero at the start of each kernel.
5035 .amdgcn.next_free_sgpr
5036 ++++++++++++++++++++++
5038 Set to zero before assembly begins. At each instruction, if the current value
5039 of this symbol is less than or equal the maximum SGPR number explicitly
5040 referenced within that instruction then the symbol value is updated to equal
5041 that SGPR number plus one.
5043 May be used to set the `.amdhsa_next_free_spgr` directive in
5044 :ref:`amdhsa-kernel-directives-table`.
5046 May be set at any time, e.g. manually set to zero at the start of each kernel.
5048 .. _amdgpu-amdhsa-assembler-directives-v3:
5050 Code Object V3 Directives (-mattr=+code-object-v3)
5051 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5053 Directives which begin with ``.amdgcn`` are valid for all ``amdgcn``
5054 architecture processors, and are not OS-specific. Directives which begin with
5055 ``.amdhsa`` are specific to ``amdgcn`` architecture processors when the
5056 ``amdhsa`` OS is specified. See :ref:`amdgpu-target-triples` and
5057 :ref:`amdgpu-processors`.
5059 .amdgcn_target <target>
5060 +++++++++++++++++++++++
5062 Optional directive which declares the target supported by the containing
5063 assembler source file. Valid values are described in
5064 :ref:`amdgpu-amdhsa-code-object-target-identification`. Used by the assembler
5065 to validate command-line options such as ``-triple``, ``-mcpu``, and those
5066 which specify target features.
5068 .amdhsa_kernel <name>
5069 +++++++++++++++++++++
5071 Creates a correctly aligned AMDHSA kernel descriptor and a symbol,
5072 ``<name>.kd``, in the current location of the current section. Only valid when
5073 the OS is ``amdhsa``. ``<name>`` must be a symbol that labels the first
5074 instruction to execute, and does not need to be previously defined.
5076 Marks the beginning of a list of directives used to generate the bytes of a
5077 kernel descriptor, as described in :ref:`amdgpu-amdhsa-kernel-descriptor`.
5078 Directives which may appear in this list are described in
5079 :ref:`amdhsa-kernel-directives-table`. Directives may appear in any order, must
5080 be valid for the target being assembled for, and cannot be repeated. Directives
5081 support the range of values specified by the field they reference in
5082 :ref:`amdgpu-amdhsa-kernel-descriptor`. If a directive is not specified, it is
5083 assumed to have its default value, unless it is marked as "Required", in which
5084 case it is an error to omit the directive. This list of directives is
5085 terminated by an ``.end_amdhsa_kernel`` directive.
5087 .. table:: AMDHSA Kernel Assembler Directives
5088 :name: amdhsa-kernel-directives-table
5090 ======================================================== ================ ============ ===================
5091 Directive Default Supported On Description
5092 ======================================================== ================ ============ ===================
5093 ``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX9 Controls GROUP_SEGMENT_FIXED_SIZE in
5094 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5095 ``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX9 Controls PRIVATE_SEGMENT_FIXED_SIZE in
5096 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5097 ``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX9 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in
5098 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5099 ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX9 Controls ENABLE_SGPR_DISPATCH_PTR in
5100 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5101 ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX9 Controls ENABLE_SGPR_QUEUE_PTR in
5102 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5103 ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX9 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in
5104 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5105 ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX9 Controls ENABLE_SGPR_DISPATCH_ID in
5106 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5107 ``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX9 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in
5108 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5109 ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX9 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in
5110 :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
5111 ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX9 Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in
5112 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5113 ``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX9 Controls ENABLE_SGPR_WORKGROUP_ID_X in
5114 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5115 ``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX9 Controls ENABLE_SGPR_WORKGROUP_ID_Y in
5116 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5117 ``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6-GFX9 Controls ENABLE_SGPR_WORKGROUP_ID_Z in
5118 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5119 ``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6-GFX9 Controls ENABLE_SGPR_WORKGROUP_INFO in
5120 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5121 ``.amdhsa_system_vgpr_workitem_id`` 0 GFX6-GFX9 Controls ENABLE_VGPR_WORKITEM_ID in
5122 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5123 Possible values are defined in
5124 :ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`.
5125 ``.amdhsa_next_free_vgpr`` Required GFX6-GFX9 Maximum VGPR number explicitly referenced, plus one.
5126 Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in
5127 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5128 ``.amdhsa_next_free_sgpr`` Required GFX6-GFX9 Maximum SGPR number explicitly referenced, plus one.
5129 Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
5130 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5131 ``.amdhsa_reserve_vcc`` 1 GFX6-GFX9 Whether the kernel may use the special VCC SGPR.
5132 Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
5133 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5134 ``.amdhsa_reserve_flat_scratch`` 1 GFX7-GFX9 Whether the kernel may use flat instructions to access
5135 scratch memory. Used to calculate
5136 GRANULATED_WAVEFRONT_SGPR_COUNT in
5137 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5138 ``.amdhsa_reserve_xnack_mask`` Target GFX8-GFX9 Whether the kernel may trigger XNACK replay.
5139 Feature Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
5140 Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5142 ``.amdhsa_float_round_mode_32`` 0 GFX6-GFX9 Controls FLOAT_ROUND_MODE_32 in
5143 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5144 Possible values are defined in
5145 :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
5146 ``.amdhsa_float_round_mode_16_64`` 0 GFX6-GFX9 Controls FLOAT_ROUND_MODE_16_64 in
5147 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5148 Possible values are defined in
5149 :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
5150 ``.amdhsa_float_denorm_mode_32`` 0 GFX6-GFX9 Controls FLOAT_DENORM_MODE_32 in
5151 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5152 Possible values are defined in
5153 :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
5154 ``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX9 Controls FLOAT_DENORM_MODE_16_64 in
5155 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5156 Possible values are defined in
5157 :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
5158 ``.amdhsa_dx10_clamp`` 1 GFX6-GFX9 Controls ENABLE_DX10_CLAMP in
5159 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5160 ``.amdhsa_ieee_mode`` 1 GFX6-GFX9 Controls ENABLE_IEEE_MODE in
5161 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5162 ``.amdhsa_fp16_overflow`` 0 GFX9 Controls FP16_OVFL in
5163 :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
5164 ``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX9 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
5165 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5166 ``.amdhsa_exception_fp_denorm_src`` 0 GFX6-GFX9 Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in
5167 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5168 ``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6-GFX9 Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in
5169 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5170 ``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6-GFX9 Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in
5171 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5172 ``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6-GFX9 Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in
5173 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5174 ``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6-GFX9 Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in
5175 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5176 ``.amdhsa_exception_int_div_zero`` 0 GFX6-GFX9 Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
5177 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
5178 ======================================================== ================ ============ ===================
5183 Optional directive which declares the contents of the ``NT_AMDGPU_METADATA``
5184 note record (see :ref:`amdgpu-elf-note-records-table-v3`).
5186 The contents must be in the [YAML]_ markup format, with the same structure and
5187 semantics described in :ref:`amdgpu-amdhsa-code-object-metadata-v3`.
5189 This directive is terminated by an ``.end_amdgpu_metadata`` directive.
5191 .. _amdgpu-amdhsa-assembler-example-v3:
5193 Code Object V3 Example Source Code (-mattr=+code-object-v3)
5194 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5196 Here is an example of a minimal assembly source file, defining one HSA kernel:
5198 .. code-block:: none
5200 .amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional
5205 .type hello_world,@function
5207 s_load_dwordx2 s[0:1], s[0:1] 0x0
5208 v_mov_b32 v0, 3.14159
5209 s_waitcnt lgkmcnt(0)
5212 flat_store_dword v[1:2], v0
5215 .size hello_world, .Lfunc_end0-hello_world
5219 .amdhsa_kernel hello_world
5220 .amdhsa_user_sgpr_kernarg_segment_ptr 1
5221 .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr
5222 .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr
5231 - .name: hello_world
5232 .symbol: hello_world.kd
5233 .kernarg_segment_size: 48
5234 .group_segment_fixed_size: 0
5235 .private_segment_fixed_size: 0
5236 .kernarg_segment_align: 4
5240 .max_flat_workgroup_size: 256
5242 .end_amdgpu_metadata
5244 Additional Documentation
5245 ========================
5247 .. [AMD-RADEON-HD-2000-3000] `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf>`__
5248 .. [AMD-RADEON-HD-4000] `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf>`__
5249 .. [AMD-RADEON-HD-5000] `AMD Evergreen shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf>`__
5250 .. [AMD-RADEON-HD-6000] `AMD Cayman/Trinity shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf>`__
5251 .. [AMD-GCN-GFX6] `AMD Southern Islands Series ISA <http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf>`__
5252 .. [AMD-GCN-GFX7] `AMD Sea Islands Series ISA <http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf>`_
5253 .. [AMD-GCN-GFX8] `AMD GCN3 Instruction Set Architecture <http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf>`__
5254 .. [AMD-GCN-GFX9] `AMD "Vega" Instruction Set Architecture <http://developer.amd.com/wordpress/media/2013/12/Vega_Shader_ISA_28July2017.pdf>`__
5255 .. [AMD-ROCm] `ROCm: Open Platform for Development, Discovery and Education Around GPU Computing <http://gpuopen.com/compute-product/rocm/>`__
5256 .. [AMD-ROCm-github] `ROCm github <http://github.com/RadeonOpenCompute>`__
5257 .. [HSA] `Heterogeneous System Architecture (HSA) Foundation <http://www.hsafoundation.com/>`__
5258 .. [ELF] `Executable and Linkable Format (ELF) <http://www.sco.com/developers/gabi/>`__
5259 .. [DWARF] `DWARF Debugging Information Format <http://dwarfstd.org/>`__
5260 .. [YAML] `YAML Ain't Markup Language (YAML™) Version 1.2 <http://www.yaml.org/spec/1.2/spec.html>`__
5261 .. [MsgPack] `Message Pack <http://www.msgpack.org/>`__
5262 .. [OpenCL] `The OpenCL Specification Version 2.0 <http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf>`__
5263 .. [HRF] `Heterogeneous-race-free Memory Models <http://benedictgaster.org/wp-content/uploads/2014/01/asplos269-FINAL.pdf>`__
5264 .. [CLANG-ATTR] `Attributes in Clang <http://clang.llvm.org/docs/AttributeReference.html>`__
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