drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/mutex.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/platform_data/x86/pmc_atom.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pwm.h>
  25 #include <linux/suspend.h>
  26 #include <linux/delay.h>
  27
  28 #include "internal.h"
  29
  30 ACPI_MODULE_NAME("acpi_lpss");
  31
  32 #ifdef CONFIG_X86_INTEL_LPSS
  33
  34 #include <asm/cpu_device_id.h>
  35 #include <asm/intel-family.h>
  36 #include <asm/iosf_mbi.h>
  37
  38 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  39
  40 #define LPSS_CLK_SIZE   0x04
  41 #define LPSS_LTR_SIZE   0x18
  42
  43 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  44 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  45 #define LPSS_RESETS                     0x04
  46 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  47 #define LPSS_RESETS_RESET_APB           BIT(1)
  48 #define LPSS_GENERAL                    0x08
  49 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  50 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  51 #define LPSS_SW_LTR                     0x10
  52 #define LPSS_AUTO_LTR                   0x14
  53 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  54 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  55 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  56 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  57 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  58 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  59 #define LPSS_LTR_MAX_VAL                0x3FF
  60 #define LPSS_TX_INT                     0x20
  61 #define LPSS_TX_INT_MASK                BIT(1)
  62
  63 #define LPSS_PRV_REG_COUNT              9
  64
  65 /* LPSS Flags */
  66 #define LPSS_CLK                        BIT(0)
  67 #define LPSS_CLK_GATE                   BIT(1)
  68 #define LPSS_CLK_DIVIDER                BIT(2)
  69 #define LPSS_LTR                        BIT(3)
  70 #define LPSS_SAVE_CTX                   BIT(4)
  71 #define LPSS_NO_D3_DELAY                BIT(5)
  72
  73 /* Crystal Cove PMIC shares same ACPI ID between different platforms */
  74 #define BYT_CRC_HRV                     2
  75 #define CHT_CRC_HRV                     3
  76
  77 struct lpss_private_data;
  78
  79 struct lpss_device_desc {
  80         unsigned int flags;
  81         const char *clk_con_id;
  82         unsigned int prv_offset;
  83         size_t prv_size_override;
  84         struct property_entry *properties;
  85         void (*setup)(struct lpss_private_data *pdata);
  86 };
  87
  88 static const struct lpss_device_desc lpss_dma_desc = {
  89         .flags = LPSS_CLK,
  90 };
  91
  92 struct lpss_private_data {
  93         struct acpi_device *adev;
  94         void __iomem *mmio_base;
  95         resource_size_t mmio_size;
  96         unsigned int fixed_clk_rate;
  97         struct clk *clk;
  98         const struct lpss_device_desc *dev_desc;
  99         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
 100 };
 101
 102 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
 103 static u32 pmc_atom_d3_mask = 0xfe000ffe;
 104
 105 /* LPSS run time quirks */
 106 static unsigned int lpss_quirks;
 107
 108 /*
 109  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
 110  *
 111  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
 112  * it can be powered off automatically whenever the last LPSS device goes down.
 113  * In case of no power any access to the DMA controller will hang the system.
 114  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
 115  * well as on ASuS T100TA transformer.
 116  *
 117  * This quirk overrides power state of entire LPSS island to keep DMA powered
 118  * on whenever we have at least one other device in use.
 119  */
 120 #define LPSS_QUIRK_ALWAYS_POWER_ON      BIT(0)
 121
 122 /* UART Component Parameter Register */
 123 #define LPSS_UART_CPR                   0xF4
 124 #define LPSS_UART_CPR_AFCE              BIT(4)
 125
 126 static void lpss_uart_setup(struct lpss_private_data *pdata)
 127 {
 128         unsigned int offset;
 129         u32 val;
 130
 131         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 132         val = readl(pdata->mmio_base + offset);
 133         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 134
 135         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 136         if (!(val & LPSS_UART_CPR_AFCE)) {
 137                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 138                 val = readl(pdata->mmio_base + offset);
 139                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 140                 writel(val, pdata->mmio_base + offset);
 141         }
 142 }
 143
 144 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 145 {
 146         unsigned int offset;
 147         u32 val;
 148
 149         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 150         val = readl(pdata->mmio_base + offset);
 151         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 152         writel(val, pdata->mmio_base + offset);
 153 }
 154
 155 /*
 156  * BYT PWM used for backlight control by the i915 driver on systems without
 157  * the Crystal Cove PMIC.
 158  */
 159 static struct pwm_lookup byt_pwm_lookup[] = {
 160         PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
 161                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 162                                "pwm-lpss-platform"),
 163 };
 164
 165 static void byt_pwm_setup(struct lpss_private_data *pdata)
 166 {
 167         struct acpi_device *adev = pdata->adev;
 168
 169         /* Only call pwm_add_table for the first PWM controller */
 170         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 171                 return;
 172
 173         if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
 174                 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
 175 }
 176
 177 #define LPSS_I2C_ENABLE                 0x6c
 178
 179 static void byt_i2c_setup(struct lpss_private_data *pdata)
 180 {
 181         const char *uid_str = acpi_device_uid(pdata->adev);
 182         acpi_handle handle = pdata->adev->handle;
 183         unsigned long long shared_host = 0;
 184         acpi_status status;
 185         long uid = 0;
 186
 187         /* Expected to always be true, but better safe then sorry */
 188         if (uid_str)
 189                 uid = simple_strtol(uid_str, NULL, 10);
 190
 191         /* Detect I2C bus shared with PUNIT and ignore its d3 status */
 192         status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
 193         if (ACPI_SUCCESS(status) && shared_host && uid)
 194                 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
 195
 196         lpss_deassert_reset(pdata);
 197
 198         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 199                 pdata->fixed_clk_rate = 133000000;
 200
 201         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 202 }
 203
 204 /* BSW PWM used for backlight control by the i915 driver */
 205 static struct pwm_lookup bsw_pwm_lookup[] = {
 206         PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
 207                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 208                                "pwm-lpss-platform"),
 209 };
 210
 211 static void bsw_pwm_setup(struct lpss_private_data *pdata)
 212 {
 213         struct acpi_device *adev = pdata->adev;
 214
 215         /* Only call pwm_add_table for the first PWM controller */
 216         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 217                 return;
 218
 219         pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
 220 }
 221
 222 static const struct lpss_device_desc lpt_dev_desc = {
 223         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 224         .prv_offset = 0x800,
 225 };
 226
 227 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 228         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 229         .prv_offset = 0x800,
 230 };
 231
 232 static struct property_entry uart_properties[] = {
 233         PROPERTY_ENTRY_U32("reg-io-width", 4),
 234         PROPERTY_ENTRY_U32("reg-shift", 2),
 235         PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
 236         { },
 237 };
 238
 239 static const struct lpss_device_desc lpt_uart_dev_desc = {
 240         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 241         .clk_con_id = "baudclk",
 242         .prv_offset = 0x800,
 243         .setup = lpss_uart_setup,
 244         .properties = uart_properties,
 245 };
 246
 247 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 248         .flags = LPSS_LTR,
 249         .prv_offset = 0x1000,
 250         .prv_size_override = 0x1018,
 251 };
 252
 253 static const struct lpss_device_desc byt_pwm_dev_desc = {
 254         .flags = LPSS_SAVE_CTX,
 255         .prv_offset = 0x800,
 256         .setup = byt_pwm_setup,
 257 };
 258
 259 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 260         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 261         .prv_offset = 0x800,
 262         .setup = bsw_pwm_setup,
 263 };
 264
 265 static const struct lpss_device_desc byt_uart_dev_desc = {
 266         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 267         .clk_con_id = "baudclk",
 268         .prv_offset = 0x800,
 269         .setup = lpss_uart_setup,
 270         .properties = uart_properties,
 271 };
 272
 273 static const struct lpss_device_desc bsw_uart_dev_desc = {
 274         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 275                         | LPSS_NO_D3_DELAY,
 276         .clk_con_id = "baudclk",
 277         .prv_offset = 0x800,
 278         .setup = lpss_uart_setup,
 279         .properties = uart_properties,
 280 };
 281
 282 static const struct lpss_device_desc byt_spi_dev_desc = {
 283         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 284         .prv_offset = 0x400,
 285 };
 286
 287 static const struct lpss_device_desc byt_sdio_dev_desc = {
 288         .flags = LPSS_CLK,
 289 };
 290
 291 static const struct lpss_device_desc byt_i2c_dev_desc = {
 292         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 293         .prv_offset = 0x800,
 294         .setup = byt_i2c_setup,
 295 };
 296
 297 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 298         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 299         .prv_offset = 0x800,
 300         .setup = byt_i2c_setup,
 301 };
 302
 303 static const struct lpss_device_desc bsw_spi_dev_desc = {
 304         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 305                         | LPSS_NO_D3_DELAY,
 306         .prv_offset = 0x400,
 307         .setup = lpss_deassert_reset,
 308 };
 309
 310 #define ICPU(model)     { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 311
 312 static const struct x86_cpu_id lpss_cpu_ids[] = {
 313         ICPU(INTEL_FAM6_ATOM_SILVERMONT1),      /* Valleyview, Bay Trail */
 314         ICPU(INTEL_FAM6_ATOM_AIRMONT),  /* Braswell, Cherry Trail */
 315         {}
 316 };
 317
 318 #else
 319
 320 #define LPSS_ADDR(desc) (0UL)
 321
 322 #endif /* CONFIG_X86_INTEL_LPSS */
 323
 324 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 325         /* Generic LPSS devices */
 326         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 327
 328         /* Lynxpoint LPSS devices */
 329         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 330         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 331         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 332         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 333         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 334         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 335         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 336         { "INT33C7", },
 337
 338         /* BayTrail LPSS devices */
 339         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 340         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 341         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 342         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 343         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 344         { "INT33B2", },
 345         { "INT33FC", },
 346
 347         /* Braswell LPSS devices */
 348         { "80862286", LPSS_ADDR(lpss_dma_desc) },
 349         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 350         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 351         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 352         { "808622C0", LPSS_ADDR(lpss_dma_desc) },
 353         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 354
 355         /* Broadwell LPSS devices */
 356         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 357         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 358         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 359         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 360         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 361         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 362         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 363         { "INT3437", },
 364
 365         /* Wildcat Point LPSS devices */
 366         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 367
 368         { }
 369 };
 370
 371 #ifdef CONFIG_X86_INTEL_LPSS
 372
 373 static int is_memory(struct acpi_resource *res, void *not_used)
 374 {
 375         struct resource r;
 376         return !acpi_dev_resource_memory(res, &r);
 377 }
 378
 379 /* LPSS main clock device. */
 380 static struct platform_device *lpss_clk_dev;
 381
 382 static inline void lpt_register_clock_device(void)
 383 {
 384         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 385 }
 386
 387 static int register_device_clock(struct acpi_device *adev,
 388                                  struct lpss_private_data *pdata)
 389 {
 390         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 391         const char *devname = dev_name(&adev->dev);
 392         struct clk *clk;
 393         struct lpss_clk_data *clk_data;
 394         const char *parent, *clk_name;
 395         void __iomem *prv_base;
 396
 397         if (!lpss_clk_dev)
 398                 lpt_register_clock_device();
 399
 400         clk_data = platform_get_drvdata(lpss_clk_dev);
 401         if (!clk_data)
 402                 return -ENODEV;
 403         clk = clk_data->clk;
 404
 405         if (!pdata->mmio_base
 406             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 407                 return -ENODATA;
 408
 409         parent = clk_data->name;
 410         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 411
 412         if (pdata->fixed_clk_rate) {
 413                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 414                                               pdata->fixed_clk_rate);
 415                 goto out;
 416         }
 417
 418         if (dev_desc->flags & LPSS_CLK_GATE) {
 419                 clk = clk_register_gate(NULL, devname, parent, 0,
 420                                         prv_base, 0, 0, NULL);
 421                 parent = devname;
 422         }
 423
 424         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 425                 /* Prevent division by zero */
 426                 if (!readl(prv_base))
 427                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 428
 429                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 430                 if (!clk_name)
 431                         return -ENOMEM;
 432                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 433                                                       0, prv_base,
 434                                                       1, 15, 16, 15, 0, NULL);
 435                 parent = clk_name;
 436
 437                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 438                 if (!clk_name) {
 439                         kfree(parent);
 440                         return -ENOMEM;
 441                 }
 442                 clk = clk_register_gate(NULL, clk_name, parent,
 443                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 444                                         prv_base, 31, 0, NULL);
 445                 kfree(parent);
 446                 kfree(clk_name);
 447         }
 448 out:
 449         if (IS_ERR(clk))
 450                 return PTR_ERR(clk);
 451
 452         pdata->clk = clk;
 453         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 454         return 0;
 455 }
 456
 457 struct lpss_device_links {
 458         const char *supplier_hid;
 459         const char *supplier_uid;
 460         const char *consumer_hid;
 461         const char *consumer_uid;
 462         u32 flags;
 463 };
 464
 465 /*
 466  * The _DEP method is used to identify dependencies but instead of creating
 467  * device links for every handle in _DEP, only links in the following list are
 468  * created. That is necessary because, in the general case, _DEP can refer to
 469  * devices that might not have drivers, or that are on different buses, or where
 470  * the supplier is not enumerated until after the consumer is probed.
 471  */
 472 static const struct lpss_device_links lpss_device_links[] = {
 473         {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
 474 };
 475
 476 static bool hid_uid_match(struct acpi_device *adev,
 477                           const char *hid2, const char *uid2)
 478 {
 479         const char *hid1 = acpi_device_hid(adev);
 480         const char *uid1 = acpi_device_uid(adev);
 481
 482         if (strcmp(hid1, hid2))
 483                 return false;
 484
 485         if (!uid2)
 486                 return true;
 487
 488         return uid1 && !strcmp(uid1, uid2);
 489 }
 490
 491 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
 492                                   const struct lpss_device_links *link)
 493 {
 494         return hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
 495 }
 496
 497 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
 498                                   const struct lpss_device_links *link)
 499 {
 500         return hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
 501 }
 502
 503 struct hid_uid {
 504         const char *hid;
 505         const char *uid;
 506 };
 507
 508 static int match_hid_uid(struct device *dev, void *data)
 509 {
 510         struct acpi_device *adev = ACPI_COMPANION(dev);
 511         struct hid_uid *id = data;
 512
 513         if (!adev)
 514                 return 0;
 515
 516         return hid_uid_match(adev, id->hid, id->uid);
 517 }
 518
 519 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
 520 {
 521         struct hid_uid data = {
 522                 .hid = hid,
 523                 .uid = uid,
 524         };
 525
 526         return bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
 527 }
 528
 529 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
 530 {
 531         struct acpi_handle_list dep_devices;
 532         acpi_status status;
 533         int i;
 534
 535         if (!acpi_has_method(adev->handle, "_DEP"))
 536                 return false;
 537
 538         status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
 539                                          &dep_devices);
 540         if (ACPI_FAILURE(status)) {
 541                 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
 542                 return false;
 543         }
 544
 545         for (i = 0; i < dep_devices.count; i++) {
 546                 if (dep_devices.handles[i] == handle)
 547                         return true;
 548         }
 549
 550         return false;
 551 }
 552
 553 static void acpi_lpss_link_consumer(struct device *dev1,
 554                                     const struct lpss_device_links *link)
 555 {
 556         struct device *dev2;
 557
 558         dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
 559         if (!dev2)
 560                 return;
 561
 562         if (acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
 563                 device_link_add(dev2, dev1, link->flags);
 564
 565         put_device(dev2);
 566 }
 567
 568 static void acpi_lpss_link_supplier(struct device *dev1,
 569                                     const struct lpss_device_links *link)
 570 {
 571         struct device *dev2;
 572
 573         dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
 574         if (!dev2)
 575                 return;
 576
 577         if (acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
 578                 device_link_add(dev1, dev2, link->flags);
 579
 580         put_device(dev2);
 581 }
 582
 583 static void acpi_lpss_create_device_links(struct acpi_device *adev,
 584                                           struct platform_device *pdev)
 585 {
 586         int i;
 587
 588         for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
 589                 const struct lpss_device_links *link = &lpss_device_links[i];
 590
 591                 if (acpi_lpss_is_supplier(adev, link))
 592                         acpi_lpss_link_consumer(&pdev->dev, link);
 593
 594                 if (acpi_lpss_is_consumer(adev, link))
 595                         acpi_lpss_link_supplier(&pdev->dev, link);
 596         }
 597 }
 598
 599 static int acpi_lpss_create_device(struct acpi_device *adev,
 600                                    const struct acpi_device_id *id)
 601 {
 602         const struct lpss_device_desc *dev_desc;
 603         struct lpss_private_data *pdata;
 604         struct resource_entry *rentry;
 605         struct list_head resource_list;
 606         struct platform_device *pdev;
 607         int ret;
 608
 609         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 610         if (!dev_desc) {
 611                 pdev = acpi_create_platform_device(adev, NULL);
 612                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 613         }
 614         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 615         if (!pdata)
 616                 return -ENOMEM;
 617
 618         INIT_LIST_HEAD(&resource_list);
 619         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 620         if (ret < 0)
 621                 goto err_out;
 622
 623         list_for_each_entry(rentry, &resource_list, node)
 624                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 625                         if (dev_desc->prv_size_override)
 626                                 pdata->mmio_size = dev_desc->prv_size_override;
 627                         else
 628                                 pdata->mmio_size = resource_size(rentry->res);
 629                         pdata->mmio_base = ioremap(rentry->res->start,
 630                                                    pdata->mmio_size);
 631                         break;
 632                 }
 633
 634         acpi_dev_free_resource_list(&resource_list);
 635
 636         if (!pdata->mmio_base) {
 637                 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
 638                 adev->pnp.type.platform_id = 0;
 639                 /* Skip the device, but continue the namespace scan. */
 640                 ret = 0;
 641                 goto err_out;
 642         }
 643
 644         pdata->adev = adev;
 645         pdata->dev_desc = dev_desc;
 646
 647         if (dev_desc->setup)
 648                 dev_desc->setup(pdata);
 649
 650         if (dev_desc->flags & LPSS_CLK) {
 651                 ret = register_device_clock(adev, pdata);
 652                 if (ret) {
 653                         /* Skip the device, but continue the namespace scan. */
 654                         ret = 0;
 655                         goto err_out;
 656                 }
 657         }
 658
 659         /*
 660          * This works around a known issue in ACPI tables where LPSS devices
 661          * have _PS0 and _PS3 without _PSC (and no power resources), so
 662          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 663          */
 664         ret = acpi_device_fix_up_power(adev);
 665         if (ret) {
 666                 /* Skip the device, but continue the namespace scan. */
 667                 ret = 0;
 668                 goto err_out;
 669         }
 670
 671         adev->driver_data = pdata;
 672         pdev = acpi_create_platform_device(adev, dev_desc->properties);
 673         if (!IS_ERR_OR_NULL(pdev)) {
 674                 acpi_lpss_create_device_links(adev, pdev);
 675                 return 1;
 676         }
 677
 678         ret = PTR_ERR(pdev);
 679         adev->driver_data = NULL;
 680
 681  err_out:
 682         kfree(pdata);
 683         return ret;
 684 }
 685
 686 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 687 {
 688         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 689 }
 690
 691 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 692                              unsigned int reg)
 693 {
 694         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 695 }
 696
 697 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 698 {
 699         struct acpi_device *adev;
 700         struct lpss_private_data *pdata;
 701         unsigned long flags;
 702         int ret;
 703
 704         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 705         if (WARN_ON(ret))
 706                 return ret;
 707
 708         spin_lock_irqsave(&dev->power.lock, flags);
 709         if (pm_runtime_suspended(dev)) {
 710                 ret = -EAGAIN;
 711                 goto out;
 712         }
 713         pdata = acpi_driver_data(adev);
 714         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 715                 ret = -ENODEV;
 716                 goto out;
 717         }
 718         *val = __lpss_reg_read(pdata, reg);
 719
 720  out:
 721         spin_unlock_irqrestore(&dev->power.lock, flags);
 722         return ret;
 723 }
 724
 725 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 726                              char *buf)
 727 {
 728         u32 ltr_value = 0;
 729         unsigned int reg;
 730         int ret;
 731
 732         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 733         ret = lpss_reg_read(dev, reg, &ltr_value);
 734         if (ret)
 735                 return ret;
 736
 737         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 738 }
 739
 740 static ssize_t lpss_ltr_mode_show(struct device *dev,
 741                                   struct device_attribute *attr, char *buf)
 742 {
 743         u32 ltr_mode = 0;
 744         char *outstr;
 745         int ret;
 746
 747         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 748         if (ret)
 749                 return ret;
 750
 751         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 752         return sprintf(buf, "%s\n", outstr);
 753 }
 754
 755 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 756 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 757 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 758
 759 static struct attribute *lpss_attrs[] = {
 760         &dev_attr_auto_ltr.attr,
 761         &dev_attr_sw_ltr.attr,
 762         &dev_attr_ltr_mode.attr,
 763         NULL,
 764 };
 765
 766 static const struct attribute_group lpss_attr_group = {
 767         .attrs = lpss_attrs,
 768         .name = "lpss_ltr",
 769 };
 770
 771 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 772 {
 773         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 774         u32 ltr_mode, ltr_val;
 775
 776         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 777         if (val < 0) {
 778                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 779                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 780                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 781                 }
 782                 return;
 783         }
 784         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 785         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 786                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 787                 val = LPSS_LTR_MAX_VAL;
 788         } else if (val > LPSS_LTR_MAX_VAL) {
 789                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 790                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 791         } else {
 792                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 793         }
 794         ltr_val |= val;
 795         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 796         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 797                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 798                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 799         }
 800 }
 801
 802 #ifdef CONFIG_PM
 803 /**
 804  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 805  * @dev: LPSS device
 806  * @pdata: pointer to the private data of the LPSS device
 807  *
 808  * Most LPSS devices have private registers which may loose their context when
 809  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 810  * prv_reg_ctx array.
 811  */
 812 static void acpi_lpss_save_ctx(struct device *dev,
 813                                struct lpss_private_data *pdata)
 814 {
 815         unsigned int i;
 816
 817         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 818                 unsigned long offset = i * sizeof(u32);
 819
 820                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 821                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 822                         pdata->prv_reg_ctx[i], offset);
 823         }
 824 }
 825
 826 /**
 827  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 828  * @dev: LPSS device
 829  * @pdata: pointer to the private data of the LPSS device
 830  *
 831  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 832  */
 833 static void acpi_lpss_restore_ctx(struct device *dev,
 834                                   struct lpss_private_data *pdata)
 835 {
 836         unsigned int i;
 837
 838         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 839                 unsigned long offset = i * sizeof(u32);
 840
 841                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 842                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 843                         pdata->prv_reg_ctx[i], offset);
 844         }
 845 }
 846
 847 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
 848 {
 849         /*
 850          * The following delay is needed or the subsequent write operations may
 851          * fail. The LPSS devices are actually PCI devices and the PCI spec
 852          * expects 10ms delay before the device can be accessed after D3 to D0
 853          * transition. However some platforms like BSW does not need this delay.
 854          */
 855         unsigned int delay = 10;        /* default 10ms delay */
 856
 857         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 858                 delay = 0;
 859
 860         msleep(delay);
 861 }
 862
 863 static int acpi_lpss_activate(struct device *dev)
 864 {
 865         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 866         int ret;
 867
 868         ret = acpi_dev_resume(dev);
 869         if (ret)
 870                 return ret;
 871
 872         acpi_lpss_d3_to_d0_delay(pdata);
 873
 874         /*
 875          * This is called only on ->probe() stage where a device is either in
 876          * known state defined by BIOS or most likely powered off. Due to this
 877          * we have to deassert reset line to be sure that ->probe() will
 878          * recognize the device.
 879          */
 880         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 881                 lpss_deassert_reset(pdata);
 882
 883         return 0;
 884 }
 885
 886 static void acpi_lpss_dismiss(struct device *dev)
 887 {
 888         acpi_dev_suspend(dev, false);
 889 }
 890
 891 /* IOSF SB for LPSS island */
 892 #define LPSS_IOSF_UNIT_LPIOEP           0xA0
 893 #define LPSS_IOSF_UNIT_LPIO1            0xAB
 894 #define LPSS_IOSF_UNIT_LPIO2            0xAC
 895
 896 #define LPSS_IOSF_PMCSR                 0x84
 897 #define LPSS_PMCSR_D0                   0
 898 #define LPSS_PMCSR_D3hot                3
 899 #define LPSS_PMCSR_Dx_MASK              GENMASK(1, 0)
 900
 901 #define LPSS_IOSF_GPIODEF0              0x154
 902 #define LPSS_GPIODEF0_DMA1_D3           BIT(2)
 903 #define LPSS_GPIODEF0_DMA2_D3           BIT(3)
 904 #define LPSS_GPIODEF0_DMA_D3_MASK       GENMASK(3, 2)
 905 #define LPSS_GPIODEF0_DMA_LLP           BIT(13)
 906
 907 static DEFINE_MUTEX(lpss_iosf_mutex);
 908 static bool lpss_iosf_d3_entered = true;
 909
 910 static void lpss_iosf_enter_d3_state(void)
 911 {
 912         u32 value1 = 0;
 913         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 914         u32 value2 = LPSS_PMCSR_D3hot;
 915         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 916         /*
 917          * PMC provides an information about actual status of the LPSS devices.
 918          * Here we read the values related to LPSS power island, i.e. LPSS
 919          * devices, excluding both LPSS DMA controllers, along with SCC domain.
 920          */
 921         u32 func_dis, d3_sts_0, pmc_status;
 922         int ret;
 923
 924         ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
 925         if (ret)
 926                 return;
 927
 928         mutex_lock(&lpss_iosf_mutex);
 929
 930         ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
 931         if (ret)
 932                 goto exit;
 933
 934         /*
 935          * Get the status of entire LPSS power island per device basis.
 936          * Shutdown both LPSS DMA controllers if and only if all other devices
 937          * are already in D3hot.
 938          */
 939         pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
 940         if (pmc_status)
 941                 goto exit;
 942
 943         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 944                         LPSS_IOSF_PMCSR, value2, mask2);
 945
 946         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 947                         LPSS_IOSF_PMCSR, value2, mask2);
 948
 949         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 950                         LPSS_IOSF_GPIODEF0, value1, mask1);
 951
 952         lpss_iosf_d3_entered = true;
 953
 954 exit:
 955         mutex_unlock(&lpss_iosf_mutex);
 956 }
 957
 958 static void lpss_iosf_exit_d3_state(void)
 959 {
 960         u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
 961                      LPSS_GPIODEF0_DMA_LLP;
 962         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 963         u32 value2 = LPSS_PMCSR_D0;
 964         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 965
 966         mutex_lock(&lpss_iosf_mutex);
 967
 968         if (!lpss_iosf_d3_entered)
 969                 goto exit;
 970
 971         lpss_iosf_d3_entered = false;
 972
 973         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 974                         LPSS_IOSF_GPIODEF0, value1, mask1);
 975
 976         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 977                         LPSS_IOSF_PMCSR, value2, mask2);
 978
 979         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 980                         LPSS_IOSF_PMCSR, value2, mask2);
 981
 982 exit:
 983         mutex_unlock(&lpss_iosf_mutex);
 984 }
 985
 986 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
 987 {
 988         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 989         int ret;
 990
 991         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 992                 acpi_lpss_save_ctx(dev, pdata);
 993
 994         ret = acpi_dev_suspend(dev, wakeup);
 995
 996         /*
 997          * This call must be last in the sequence, otherwise PMC will return
 998          * wrong status for devices being about to be powered off. See
 999          * lpss_iosf_enter_d3_state() for further information.
1000          */
1001         if (acpi_target_system_state() == ACPI_STATE_S0 &&
1002             lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1003                 lpss_iosf_enter_d3_state();
1004
1005         return ret;
1006 }
1007
1008 static int acpi_lpss_resume(struct device *dev)
1009 {
1010         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1011         int ret;
1012
1013         /*
1014          * This call is kept first to be in symmetry with
1015          * acpi_lpss_runtime_suspend() one.
1016          */
1017         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1018                 lpss_iosf_exit_d3_state();
1019
1020         ret = acpi_dev_resume(dev);
1021         if (ret)
1022                 return ret;
1023
1024         acpi_lpss_d3_to_d0_delay(pdata);
1025
1026         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1027                 acpi_lpss_restore_ctx(dev, pdata);
1028
1029         return 0;
1030 }
1031
1032 #ifdef CONFIG_PM_SLEEP
1033 static int acpi_lpss_suspend_late(struct device *dev)
1034 {
1035         int ret;
1036
1037         if (dev_pm_smart_suspend_and_suspended(dev))
1038                 return 0;
1039
1040         ret = pm_generic_suspend_late(dev);
1041         return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1042 }
1043
1044 static int acpi_lpss_resume_early(struct device *dev)
1045 {
1046         int ret = acpi_lpss_resume(dev);
1047
1048         return ret ? ret : pm_generic_resume_early(dev);
1049 }
1050 #endif /* CONFIG_PM_SLEEP */
1051
1052 static int acpi_lpss_runtime_suspend(struct device *dev)
1053 {
1054         int ret = pm_generic_runtime_suspend(dev);
1055
1056         return ret ? ret : acpi_lpss_suspend(dev, true);
1057 }
1058
1059 static int acpi_lpss_runtime_resume(struct device *dev)
1060 {
1061         int ret = acpi_lpss_resume(dev);
1062
1063         return ret ? ret : pm_generic_runtime_resume(dev);
1064 }
1065 #endif /* CONFIG_PM */
1066
1067 static struct dev_pm_domain acpi_lpss_pm_domain = {
1068 #ifdef CONFIG_PM
1069         .activate = acpi_lpss_activate,
1070         .dismiss = acpi_lpss_dismiss,
1071 #endif
1072         .ops = {
1073 #ifdef CONFIG_PM
1074 #ifdef CONFIG_PM_SLEEP
1075                 .prepare = acpi_subsys_prepare,
1076                 .complete = acpi_subsys_complete,
1077                 .suspend = acpi_subsys_suspend,
1078                 .suspend_late = acpi_lpss_suspend_late,
1079                 .suspend_noirq = acpi_subsys_suspend_noirq,
1080                 .resume_noirq = acpi_subsys_resume_noirq,
1081                 .resume_early = acpi_lpss_resume_early,
1082                 .freeze = acpi_subsys_freeze,
1083                 .freeze_late = acpi_subsys_freeze_late,
1084                 .freeze_noirq = acpi_subsys_freeze_noirq,
1085                 .thaw_noirq = acpi_subsys_thaw_noirq,
1086                 .poweroff = acpi_subsys_suspend,
1087                 .poweroff_late = acpi_lpss_suspend_late,
1088                 .poweroff_noirq = acpi_subsys_suspend_noirq,
1089                 .restore_noirq = acpi_subsys_resume_noirq,
1090                 .restore_early = acpi_lpss_resume_early,
1091 #endif
1092                 .runtime_suspend = acpi_lpss_runtime_suspend,
1093                 .runtime_resume = acpi_lpss_runtime_resume,
1094 #endif
1095         },
1096 };
1097
1098 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1099                                      unsigned long action, void *data)
1100 {
1101         struct platform_device *pdev = to_platform_device(data);
1102         struct lpss_private_data *pdata;
1103         struct acpi_device *adev;
1104         const struct acpi_device_id *id;
1105
1106         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1107         if (!id || !id->driver_data)
1108                 return 0;
1109
1110         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1111                 return 0;
1112
1113         pdata = acpi_driver_data(adev);
1114         if (!pdata)
1115                 return 0;
1116
1117         if (pdata->mmio_base &&
1118             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1119                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1120                 return 0;
1121         }
1122
1123         switch (action) {
1124         case BUS_NOTIFY_BIND_DRIVER:
1125                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1126                 break;
1127         case BUS_NOTIFY_DRIVER_NOT_BOUND:
1128         case BUS_NOTIFY_UNBOUND_DRIVER:
1129                 dev_pm_domain_set(&pdev->dev, NULL);
1130                 break;
1131         case BUS_NOTIFY_ADD_DEVICE:
1132                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1133                 if (pdata->dev_desc->flags & LPSS_LTR)
1134                         return sysfs_create_group(&pdev->dev.kobj,
1135                                                   &lpss_attr_group);
1136                 break;
1137         case BUS_NOTIFY_DEL_DEVICE:
1138                 if (pdata->dev_desc->flags & LPSS_LTR)
1139                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1140                 dev_pm_domain_set(&pdev->dev, NULL);
1141                 break;
1142         default:
1143                 break;
1144         }
1145
1146         return 0;
1147 }
1148
1149 static struct notifier_block acpi_lpss_nb = {
1150         .notifier_call = acpi_lpss_platform_notify,
1151 };
1152
1153 static void acpi_lpss_bind(struct device *dev)
1154 {
1155         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1156
1157         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1158                 return;
1159
1160         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1161                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1162         else
1163                 dev_err(dev, "MMIO size insufficient to access LTR\n");
1164 }
1165
1166 static void acpi_lpss_unbind(struct device *dev)
1167 {
1168         dev->power.set_latency_tolerance = NULL;
1169 }
1170
1171 static struct acpi_scan_handler lpss_handler = {
1172         .ids = acpi_lpss_device_ids,
1173         .attach = acpi_lpss_create_device,
1174         .bind = acpi_lpss_bind,
1175         .unbind = acpi_lpss_unbind,
1176 };
1177
1178 void __init acpi_lpss_init(void)
1179 {
1180         const struct x86_cpu_id *id;
1181         int ret;
1182
1183         ret = lpt_clk_init();
1184         if (ret)
1185                 return;
1186
1187         id = x86_match_cpu(lpss_cpu_ids);
1188         if (id)
1189                 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1190
1191         bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1192         acpi_scan_add_handler(&lpss_handler);
1193 }
1194
1195 #else
1196
1197 static struct acpi_scan_handler lpss_handler = {
1198         .ids = acpi_lpss_device_ids,
1199 };
1200
1201 void __init acpi_lpss_init(void)
1202 {
1203         acpi_scan_add_handler(&lpss_handler);
1204 }
1205
1206 #endif /* CONFIG_X86_INTEL_LPSS */