drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/mutex.h>
  19 #include <linux/pci.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/platform_data/clk-lpss.h>
  22 #include <linux/platform_data/x86/pmc_atom.h>
  23 #include <linux/pm_domain.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/pwm.h>
  26 #include <linux/suspend.h>
  27 #include <linux/delay.h>
  28
  29 #include "internal.h"
  30
  31 ACPI_MODULE_NAME("acpi_lpss");
  32
  33 #ifdef CONFIG_X86_INTEL_LPSS
  34
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/intel-family.h>
  37 #include <asm/iosf_mbi.h>
  38
  39 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  40
  41 #define LPSS_CLK_SIZE   0x04
  42 #define LPSS_LTR_SIZE   0x18
  43
  44 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  45 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  46 #define LPSS_RESETS                     0x04
  47 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  48 #define LPSS_RESETS_RESET_APB           BIT(1)
  49 #define LPSS_GENERAL                    0x08
  50 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  51 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  52 #define LPSS_SW_LTR                     0x10
  53 #define LPSS_AUTO_LTR                   0x14
  54 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  55 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  56 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  57 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  58 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  59 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  60 #define LPSS_LTR_MAX_VAL                0x3FF
  61 #define LPSS_TX_INT                     0x20
  62 #define LPSS_TX_INT_MASK                BIT(1)
  63
  64 #define LPSS_PRV_REG_COUNT              9
  65
  66 /* LPSS Flags */
  67 #define LPSS_CLK                        BIT(0)
  68 #define LPSS_CLK_GATE                   BIT(1)
  69 #define LPSS_CLK_DIVIDER                BIT(2)
  70 #define LPSS_LTR                        BIT(3)
  71 #define LPSS_SAVE_CTX                   BIT(4)
  72 #define LPSS_NO_D3_DELAY                BIT(5)
  73
  74 /* Crystal Cove PMIC shares same ACPI ID between different platforms */
  75 #define BYT_CRC_HRV                     2
  76 #define CHT_CRC_HRV                     3
  77
  78 struct lpss_private_data;
  79
  80 struct lpss_device_desc {
  81         unsigned int flags;
  82         const char *clk_con_id;
  83         unsigned int prv_offset;
  84         size_t prv_size_override;
  85         struct property_entry *properties;
  86         void (*setup)(struct lpss_private_data *pdata);
  87 };
  88
  89 static const struct lpss_device_desc lpss_dma_desc = {
  90         .flags = LPSS_CLK,
  91 };
  92
  93 struct lpss_private_data {
  94         struct acpi_device *adev;
  95         void __iomem *mmio_base;
  96         resource_size_t mmio_size;
  97         unsigned int fixed_clk_rate;
  98         struct clk *clk;
  99         const struct lpss_device_desc *dev_desc;
 100         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
 101 };
 102
 103 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
 104 static u32 pmc_atom_d3_mask = 0xfe000ffe;
 105
 106 /* LPSS run time quirks */
 107 static unsigned int lpss_quirks;
 108
 109 /*
 110  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
 111  *
 112  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
 113  * it can be powered off automatically whenever the last LPSS device goes down.
 114  * In case of no power any access to the DMA controller will hang the system.
 115  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
 116  * well as on ASuS T100TA transformer.
 117  *
 118  * This quirk overrides power state of entire LPSS island to keep DMA powered
 119  * on whenever we have at least one other device in use.
 120  */
 121 #define LPSS_QUIRK_ALWAYS_POWER_ON      BIT(0)
 122
 123 /* UART Component Parameter Register */
 124 #define LPSS_UART_CPR                   0xF4
 125 #define LPSS_UART_CPR_AFCE              BIT(4)
 126
 127 static void lpss_uart_setup(struct lpss_private_data *pdata)
 128 {
 129         unsigned int offset;
 130         u32 val;
 131
 132         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 133         val = readl(pdata->mmio_base + offset);
 134         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 135
 136         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 137         if (!(val & LPSS_UART_CPR_AFCE)) {
 138                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 139                 val = readl(pdata->mmio_base + offset);
 140                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 141                 writel(val, pdata->mmio_base + offset);
 142         }
 143 }
 144
 145 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 146 {
 147         unsigned int offset;
 148         u32 val;
 149
 150         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 151         val = readl(pdata->mmio_base + offset);
 152         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 153         writel(val, pdata->mmio_base + offset);
 154 }
 155
 156 /*
 157  * BYT PWM used for backlight control by the i915 driver on systems without
 158  * the Crystal Cove PMIC.
 159  */
 160 static struct pwm_lookup byt_pwm_lookup[] = {
 161         PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
 162                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 163                                "pwm-lpss-platform"),
 164 };
 165
 166 static void byt_pwm_setup(struct lpss_private_data *pdata)
 167 {
 168         struct acpi_device *adev = pdata->adev;
 169
 170         /* Only call pwm_add_table for the first PWM controller */
 171         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 172                 return;
 173
 174         if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
 175                 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
 176 }
 177
 178 #define LPSS_I2C_ENABLE                 0x6c
 179
 180 static void byt_i2c_setup(struct lpss_private_data *pdata)
 181 {
 182         const char *uid_str = acpi_device_uid(pdata->adev);
 183         acpi_handle handle = pdata->adev->handle;
 184         unsigned long long shared_host = 0;
 185         acpi_status status;
 186         long uid = 0;
 187
 188         /* Expected to always be true, but better safe then sorry */
 189         if (uid_str)
 190                 uid = simple_strtol(uid_str, NULL, 10);
 191
 192         /* Detect I2C bus shared with PUNIT and ignore its d3 status */
 193         status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
 194         if (ACPI_SUCCESS(status) && shared_host && uid)
 195                 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
 196
 197         lpss_deassert_reset(pdata);
 198
 199         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 200                 pdata->fixed_clk_rate = 133000000;
 201
 202         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 203 }
 204
 205 /* BSW PWM used for backlight control by the i915 driver */
 206 static struct pwm_lookup bsw_pwm_lookup[] = {
 207         PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
 208                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 209                                "pwm-lpss-platform"),
 210 };
 211
 212 static void bsw_pwm_setup(struct lpss_private_data *pdata)
 213 {
 214         struct acpi_device *adev = pdata->adev;
 215
 216         /* Only call pwm_add_table for the first PWM controller */
 217         if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
 218                 return;
 219
 220         pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
 221 }
 222
 223 static const struct lpss_device_desc lpt_dev_desc = {
 224         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 225         .prv_offset = 0x800,
 226 };
 227
 228 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 229         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 230         .prv_offset = 0x800,
 231 };
 232
 233 static struct property_entry uart_properties[] = {
 234         PROPERTY_ENTRY_U32("reg-io-width", 4),
 235         PROPERTY_ENTRY_U32("reg-shift", 2),
 236         PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
 237         { },
 238 };
 239
 240 static const struct lpss_device_desc lpt_uart_dev_desc = {
 241         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 242         .clk_con_id = "baudclk",
 243         .prv_offset = 0x800,
 244         .setup = lpss_uart_setup,
 245         .properties = uart_properties,
 246 };
 247
 248 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 249         .flags = LPSS_LTR,
 250         .prv_offset = 0x1000,
 251         .prv_size_override = 0x1018,
 252 };
 253
 254 static const struct lpss_device_desc byt_pwm_dev_desc = {
 255         .flags = LPSS_SAVE_CTX,
 256         .prv_offset = 0x800,
 257         .setup = byt_pwm_setup,
 258 };
 259
 260 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 261         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 262         .prv_offset = 0x800,
 263         .setup = bsw_pwm_setup,
 264 };
 265
 266 static const struct lpss_device_desc byt_uart_dev_desc = {
 267         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 268         .clk_con_id = "baudclk",
 269         .prv_offset = 0x800,
 270         .setup = lpss_uart_setup,
 271         .properties = uart_properties,
 272 };
 273
 274 static const struct lpss_device_desc bsw_uart_dev_desc = {
 275         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 276                         | LPSS_NO_D3_DELAY,
 277         .clk_con_id = "baudclk",
 278         .prv_offset = 0x800,
 279         .setup = lpss_uart_setup,
 280         .properties = uart_properties,
 281 };
 282
 283 static const struct lpss_device_desc byt_spi_dev_desc = {
 284         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 285         .prv_offset = 0x400,
 286 };
 287
 288 static const struct lpss_device_desc byt_sdio_dev_desc = {
 289         .flags = LPSS_CLK,
 290 };
 291
 292 static const struct lpss_device_desc byt_i2c_dev_desc = {
 293         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 294         .prv_offset = 0x800,
 295         .setup = byt_i2c_setup,
 296 };
 297
 298 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 299         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 300         .prv_offset = 0x800,
 301         .setup = byt_i2c_setup,
 302 };
 303
 304 static const struct lpss_device_desc bsw_spi_dev_desc = {
 305         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 306                         | LPSS_NO_D3_DELAY,
 307         .prv_offset = 0x400,
 308         .setup = lpss_deassert_reset,
 309 };
 310
 311 #define ICPU(model)     { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 312
 313 static const struct x86_cpu_id lpss_cpu_ids[] = {
 314         ICPU(INTEL_FAM6_ATOM_SILVERMONT1),      /* Valleyview, Bay Trail */
 315         ICPU(INTEL_FAM6_ATOM_AIRMONT),  /* Braswell, Cherry Trail */
 316         {}
 317 };
 318
 319 #else
 320
 321 #define LPSS_ADDR(desc) (0UL)
 322
 323 #endif /* CONFIG_X86_INTEL_LPSS */
 324
 325 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 326         /* Generic LPSS devices */
 327         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 328
 329         /* Lynxpoint LPSS devices */
 330         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 331         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 332         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 333         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 334         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 335         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 336         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 337         { "INT33C7", },
 338
 339         /* BayTrail LPSS devices */
 340         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 341         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 342         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 343         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 344         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 345         { "INT33B2", },
 346         { "INT33FC", },
 347
 348         /* Braswell LPSS devices */
 349         { "80862286", LPSS_ADDR(lpss_dma_desc) },
 350         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 351         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 352         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 353         { "808622C0", LPSS_ADDR(lpss_dma_desc) },
 354         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 355
 356         /* Broadwell LPSS devices */
 357         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 358         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 359         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 360         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 361         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 362         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 363         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 364         { "INT3437", },
 365
 366         /* Wildcat Point LPSS devices */
 367         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 368
 369         { }
 370 };
 371
 372 #ifdef CONFIG_X86_INTEL_LPSS
 373
 374 static int is_memory(struct acpi_resource *res, void *not_used)
 375 {
 376         struct resource r;
 377         return !acpi_dev_resource_memory(res, &r);
 378 }
 379
 380 /* LPSS main clock device. */
 381 static struct platform_device *lpss_clk_dev;
 382
 383 static inline void lpt_register_clock_device(void)
 384 {
 385         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 386 }
 387
 388 static int register_device_clock(struct acpi_device *adev,
 389                                  struct lpss_private_data *pdata)
 390 {
 391         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 392         const char *devname = dev_name(&adev->dev);
 393         struct clk *clk;
 394         struct lpss_clk_data *clk_data;
 395         const char *parent, *clk_name;
 396         void __iomem *prv_base;
 397
 398         if (!lpss_clk_dev)
 399                 lpt_register_clock_device();
 400
 401         clk_data = platform_get_drvdata(lpss_clk_dev);
 402         if (!clk_data)
 403                 return -ENODEV;
 404         clk = clk_data->clk;
 405
 406         if (!pdata->mmio_base
 407             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 408                 return -ENODATA;
 409
 410         parent = clk_data->name;
 411         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 412
 413         if (pdata->fixed_clk_rate) {
 414                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 415                                               pdata->fixed_clk_rate);
 416                 goto out;
 417         }
 418
 419         if (dev_desc->flags & LPSS_CLK_GATE) {
 420                 clk = clk_register_gate(NULL, devname, parent, 0,
 421                                         prv_base, 0, 0, NULL);
 422                 parent = devname;
 423         }
 424
 425         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 426                 /* Prevent division by zero */
 427                 if (!readl(prv_base))
 428                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 429
 430                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 431                 if (!clk_name)
 432                         return -ENOMEM;
 433                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 434                                                       0, prv_base,
 435                                                       1, 15, 16, 15, 0, NULL);
 436                 parent = clk_name;
 437
 438                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 439                 if (!clk_name) {
 440                         kfree(parent);
 441                         return -ENOMEM;
 442                 }
 443                 clk = clk_register_gate(NULL, clk_name, parent,
 444                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 445                                         prv_base, 31, 0, NULL);
 446                 kfree(parent);
 447                 kfree(clk_name);
 448         }
 449 out:
 450         if (IS_ERR(clk))
 451                 return PTR_ERR(clk);
 452
 453         pdata->clk = clk;
 454         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 455         return 0;
 456 }
 457
 458 struct lpss_device_links {
 459         const char *supplier_hid;
 460         const char *supplier_uid;
 461         const char *consumer_hid;
 462         const char *consumer_uid;
 463         u32 flags;
 464 };
 465
 466 /*
 467  * The _DEP method is used to identify dependencies but instead of creating
 468  * device links for every handle in _DEP, only links in the following list are
 469  * created. That is necessary because, in the general case, _DEP can refer to
 470  * devices that might not have drivers, or that are on different buses, or where
 471  * the supplier is not enumerated until after the consumer is probed.
 472  */
 473 static const struct lpss_device_links lpss_device_links[] = {
 474         {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
 475         {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
 476         {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
 477 };
 478
 479 static bool hid_uid_match(struct acpi_device *adev,
 480                           const char *hid2, const char *uid2)
 481 {
 482         const char *hid1 = acpi_device_hid(adev);
 483         const char *uid1 = acpi_device_uid(adev);
 484
 485         if (strcmp(hid1, hid2))
 486                 return false;
 487
 488         if (!uid2)
 489                 return true;
 490
 491         return uid1 && !strcmp(uid1, uid2);
 492 }
 493
 494 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
 495                                   const struct lpss_device_links *link)
 496 {
 497         return hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
 498 }
 499
 500 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
 501                                   const struct lpss_device_links *link)
 502 {
 503         return hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
 504 }
 505
 506 struct hid_uid {
 507         const char *hid;
 508         const char *uid;
 509 };
 510
 511 static int match_hid_uid(struct device *dev, void *data)
 512 {
 513         struct acpi_device *adev = ACPI_COMPANION(dev);
 514         struct hid_uid *id = data;
 515
 516         if (!adev)
 517                 return 0;
 518
 519         return hid_uid_match(adev, id->hid, id->uid);
 520 }
 521
 522 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
 523 {
 524         struct device *dev;
 525
 526         struct hid_uid data = {
 527                 .hid = hid,
 528                 .uid = uid,
 529         };
 530
 531         dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
 532         if (dev)
 533                 return dev;
 534
 535         return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
 536 }
 537
 538 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
 539 {
 540         struct acpi_handle_list dep_devices;
 541         acpi_status status;
 542         int i;
 543
 544         if (!acpi_has_method(adev->handle, "_DEP"))
 545                 return false;
 546
 547         status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
 548                                          &dep_devices);
 549         if (ACPI_FAILURE(status)) {
 550                 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
 551                 return false;
 552         }
 553
 554         for (i = 0; i < dep_devices.count; i++) {
 555                 if (dep_devices.handles[i] == handle)
 556                         return true;
 557         }
 558
 559         return false;
 560 }
 561
 562 static void acpi_lpss_link_consumer(struct device *dev1,
 563                                     const struct lpss_device_links *link)
 564 {
 565         struct device *dev2;
 566
 567         dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
 568         if (!dev2)
 569                 return;
 570
 571         if (acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
 572                 device_link_add(dev2, dev1, link->flags);
 573
 574         put_device(dev2);
 575 }
 576
 577 static void acpi_lpss_link_supplier(struct device *dev1,
 578                                     const struct lpss_device_links *link)
 579 {
 580         struct device *dev2;
 581
 582         dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
 583         if (!dev2)
 584                 return;
 585
 586         if (acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
 587                 device_link_add(dev1, dev2, link->flags);
 588
 589         put_device(dev2);
 590 }
 591
 592 static void acpi_lpss_create_device_links(struct acpi_device *adev,
 593                                           struct platform_device *pdev)
 594 {
 595         int i;
 596
 597         for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
 598                 const struct lpss_device_links *link = &lpss_device_links[i];
 599
 600                 if (acpi_lpss_is_supplier(adev, link))
 601                         acpi_lpss_link_consumer(&pdev->dev, link);
 602
 603                 if (acpi_lpss_is_consumer(adev, link))
 604                         acpi_lpss_link_supplier(&pdev->dev, link);
 605         }
 606 }
 607
 608 static int acpi_lpss_create_device(struct acpi_device *adev,
 609                                    const struct acpi_device_id *id)
 610 {
 611         const struct lpss_device_desc *dev_desc;
 612         struct lpss_private_data *pdata;
 613         struct resource_entry *rentry;
 614         struct list_head resource_list;
 615         struct platform_device *pdev;
 616         int ret;
 617
 618         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 619         if (!dev_desc) {
 620                 pdev = acpi_create_platform_device(adev, NULL);
 621                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 622         }
 623         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 624         if (!pdata)
 625                 return -ENOMEM;
 626
 627         INIT_LIST_HEAD(&resource_list);
 628         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 629         if (ret < 0)
 630                 goto err_out;
 631
 632         list_for_each_entry(rentry, &resource_list, node)
 633                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 634                         if (dev_desc->prv_size_override)
 635                                 pdata->mmio_size = dev_desc->prv_size_override;
 636                         else
 637                                 pdata->mmio_size = resource_size(rentry->res);
 638                         pdata->mmio_base = ioremap(rentry->res->start,
 639                                                    pdata->mmio_size);
 640                         break;
 641                 }
 642
 643         acpi_dev_free_resource_list(&resource_list);
 644
 645         if (!pdata->mmio_base) {
 646                 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
 647                 adev->pnp.type.platform_id = 0;
 648                 /* Skip the device, but continue the namespace scan. */
 649                 ret = 0;
 650                 goto err_out;
 651         }
 652
 653         pdata->adev = adev;
 654         pdata->dev_desc = dev_desc;
 655
 656         if (dev_desc->setup)
 657                 dev_desc->setup(pdata);
 658
 659         if (dev_desc->flags & LPSS_CLK) {
 660                 ret = register_device_clock(adev, pdata);
 661                 if (ret) {
 662                         /* Skip the device, but continue the namespace scan. */
 663                         ret = 0;
 664                         goto err_out;
 665                 }
 666         }
 667
 668         /*
 669          * This works around a known issue in ACPI tables where LPSS devices
 670          * have _PS0 and _PS3 without _PSC (and no power resources), so
 671          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 672          */
 673         ret = acpi_device_fix_up_power(adev);
 674         if (ret) {
 675                 /* Skip the device, but continue the namespace scan. */
 676                 ret = 0;
 677                 goto err_out;
 678         }
 679
 680         adev->driver_data = pdata;
 681         pdev = acpi_create_platform_device(adev, dev_desc->properties);
 682         if (!IS_ERR_OR_NULL(pdev)) {
 683                 acpi_lpss_create_device_links(adev, pdev);
 684                 return 1;
 685         }
 686
 687         ret = PTR_ERR(pdev);
 688         adev->driver_data = NULL;
 689
 690  err_out:
 691         kfree(pdata);
 692         return ret;
 693 }
 694
 695 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 696 {
 697         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 698 }
 699
 700 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 701                              unsigned int reg)
 702 {
 703         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 704 }
 705
 706 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 707 {
 708         struct acpi_device *adev;
 709         struct lpss_private_data *pdata;
 710         unsigned long flags;
 711         int ret;
 712
 713         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 714         if (WARN_ON(ret))
 715                 return ret;
 716
 717         spin_lock_irqsave(&dev->power.lock, flags);
 718         if (pm_runtime_suspended(dev)) {
 719                 ret = -EAGAIN;
 720                 goto out;
 721         }
 722         pdata = acpi_driver_data(adev);
 723         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 724                 ret = -ENODEV;
 725                 goto out;
 726         }
 727         *val = __lpss_reg_read(pdata, reg);
 728
 729  out:
 730         spin_unlock_irqrestore(&dev->power.lock, flags);
 731         return ret;
 732 }
 733
 734 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 735                              char *buf)
 736 {
 737         u32 ltr_value = 0;
 738         unsigned int reg;
 739         int ret;
 740
 741         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 742         ret = lpss_reg_read(dev, reg, &ltr_value);
 743         if (ret)
 744                 return ret;
 745
 746         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 747 }
 748
 749 static ssize_t lpss_ltr_mode_show(struct device *dev,
 750                                   struct device_attribute *attr, char *buf)
 751 {
 752         u32 ltr_mode = 0;
 753         char *outstr;
 754         int ret;
 755
 756         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 757         if (ret)
 758                 return ret;
 759
 760         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 761         return sprintf(buf, "%s\n", outstr);
 762 }
 763
 764 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 765 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 766 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 767
 768 static struct attribute *lpss_attrs[] = {
 769         &dev_attr_auto_ltr.attr,
 770         &dev_attr_sw_ltr.attr,
 771         &dev_attr_ltr_mode.attr,
 772         NULL,
 773 };
 774
 775 static const struct attribute_group lpss_attr_group = {
 776         .attrs = lpss_attrs,
 777         .name = "lpss_ltr",
 778 };
 779
 780 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 781 {
 782         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 783         u32 ltr_mode, ltr_val;
 784
 785         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 786         if (val < 0) {
 787                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 788                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 789                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 790                 }
 791                 return;
 792         }
 793         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 794         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 795                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 796                 val = LPSS_LTR_MAX_VAL;
 797         } else if (val > LPSS_LTR_MAX_VAL) {
 798                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 799                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 800         } else {
 801                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 802         }
 803         ltr_val |= val;
 804         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 805         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 806                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 807                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 808         }
 809 }
 810
 811 #ifdef CONFIG_PM
 812 /**
 813  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 814  * @dev: LPSS device
 815  * @pdata: pointer to the private data of the LPSS device
 816  *
 817  * Most LPSS devices have private registers which may loose their context when
 818  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 819  * prv_reg_ctx array.
 820  */
 821 static void acpi_lpss_save_ctx(struct device *dev,
 822                                struct lpss_private_data *pdata)
 823 {
 824         unsigned int i;
 825
 826         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 827                 unsigned long offset = i * sizeof(u32);
 828
 829                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 830                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 831                         pdata->prv_reg_ctx[i], offset);
 832         }
 833 }
 834
 835 /**
 836  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 837  * @dev: LPSS device
 838  * @pdata: pointer to the private data of the LPSS device
 839  *
 840  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 841  */
 842 static void acpi_lpss_restore_ctx(struct device *dev,
 843                                   struct lpss_private_data *pdata)
 844 {
 845         unsigned int i;
 846
 847         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 848                 unsigned long offset = i * sizeof(u32);
 849
 850                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 851                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 852                         pdata->prv_reg_ctx[i], offset);
 853         }
 854 }
 855
 856 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
 857 {
 858         /*
 859          * The following delay is needed or the subsequent write operations may
 860          * fail. The LPSS devices are actually PCI devices and the PCI spec
 861          * expects 10ms delay before the device can be accessed after D3 to D0
 862          * transition. However some platforms like BSW does not need this delay.
 863          */
 864         unsigned int delay = 10;        /* default 10ms delay */
 865
 866         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 867                 delay = 0;
 868
 869         msleep(delay);
 870 }
 871
 872 static int acpi_lpss_activate(struct device *dev)
 873 {
 874         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 875         int ret;
 876
 877         ret = acpi_dev_resume(dev);
 878         if (ret)
 879                 return ret;
 880
 881         acpi_lpss_d3_to_d0_delay(pdata);
 882
 883         /*
 884          * This is called only on ->probe() stage where a device is either in
 885          * known state defined by BIOS or most likely powered off. Due to this
 886          * we have to deassert reset line to be sure that ->probe() will
 887          * recognize the device.
 888          */
 889         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 890                 lpss_deassert_reset(pdata);
 891
 892         return 0;
 893 }
 894
 895 static void acpi_lpss_dismiss(struct device *dev)
 896 {
 897         acpi_dev_suspend(dev, false);
 898 }
 899
 900 /* IOSF SB for LPSS island */
 901 #define LPSS_IOSF_UNIT_LPIOEP           0xA0
 902 #define LPSS_IOSF_UNIT_LPIO1            0xAB
 903 #define LPSS_IOSF_UNIT_LPIO2            0xAC
 904
 905 #define LPSS_IOSF_PMCSR                 0x84
 906 #define LPSS_PMCSR_D0                   0
 907 #define LPSS_PMCSR_D3hot                3
 908 #define LPSS_PMCSR_Dx_MASK              GENMASK(1, 0)
 909
 910 #define LPSS_IOSF_GPIODEF0              0x154
 911 #define LPSS_GPIODEF0_DMA1_D3           BIT(2)
 912 #define LPSS_GPIODEF0_DMA2_D3           BIT(3)
 913 #define LPSS_GPIODEF0_DMA_D3_MASK       GENMASK(3, 2)
 914 #define LPSS_GPIODEF0_DMA_LLP           BIT(13)
 915
 916 static DEFINE_MUTEX(lpss_iosf_mutex);
 917 static bool lpss_iosf_d3_entered = true;
 918
 919 static void lpss_iosf_enter_d3_state(void)
 920 {
 921         u32 value1 = 0;
 922         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 923         u32 value2 = LPSS_PMCSR_D3hot;
 924         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 925         /*
 926          * PMC provides an information about actual status of the LPSS devices.
 927          * Here we read the values related to LPSS power island, i.e. LPSS
 928          * devices, excluding both LPSS DMA controllers, along with SCC domain.
 929          */
 930         u32 func_dis, d3_sts_0, pmc_status;
 931         int ret;
 932
 933         ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
 934         if (ret)
 935                 return;
 936
 937         mutex_lock(&lpss_iosf_mutex);
 938
 939         ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
 940         if (ret)
 941                 goto exit;
 942
 943         /*
 944          * Get the status of entire LPSS power island per device basis.
 945          * Shutdown both LPSS DMA controllers if and only if all other devices
 946          * are already in D3hot.
 947          */
 948         pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
 949         if (pmc_status)
 950                 goto exit;
 951
 952         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 953                         LPSS_IOSF_PMCSR, value2, mask2);
 954
 955         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 956                         LPSS_IOSF_PMCSR, value2, mask2);
 957
 958         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 959                         LPSS_IOSF_GPIODEF0, value1, mask1);
 960
 961         lpss_iosf_d3_entered = true;
 962
 963 exit:
 964         mutex_unlock(&lpss_iosf_mutex);
 965 }
 966
 967 static void lpss_iosf_exit_d3_state(void)
 968 {
 969         u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
 970                      LPSS_GPIODEF0_DMA_LLP;
 971         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 972         u32 value2 = LPSS_PMCSR_D0;
 973         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 974
 975         mutex_lock(&lpss_iosf_mutex);
 976
 977         if (!lpss_iosf_d3_entered)
 978                 goto exit;
 979
 980         lpss_iosf_d3_entered = false;
 981
 982         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 983                         LPSS_IOSF_GPIODEF0, value1, mask1);
 984
 985         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 986                         LPSS_IOSF_PMCSR, value2, mask2);
 987
 988         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 989                         LPSS_IOSF_PMCSR, value2, mask2);
 990
 991 exit:
 992         mutex_unlock(&lpss_iosf_mutex);
 993 }
 994
 995 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
 996 {
 997         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 998         int ret;
 999
1000         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1001                 acpi_lpss_save_ctx(dev, pdata);
1002
1003         ret = acpi_dev_suspend(dev, wakeup);
1004
1005         /*
1006          * This call must be last in the sequence, otherwise PMC will return
1007          * wrong status for devices being about to be powered off. See
1008          * lpss_iosf_enter_d3_state() for further information.
1009          */
1010         if (acpi_target_system_state() == ACPI_STATE_S0 &&
1011             lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1012                 lpss_iosf_enter_d3_state();
1013
1014         return ret;
1015 }
1016
1017 static int acpi_lpss_resume(struct device *dev)
1018 {
1019         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1020         int ret;
1021
1022         /*
1023          * This call is kept first to be in symmetry with
1024          * acpi_lpss_runtime_suspend() one.
1025          */
1026         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1027                 lpss_iosf_exit_d3_state();
1028
1029         ret = acpi_dev_resume(dev);
1030         if (ret)
1031                 return ret;
1032
1033         acpi_lpss_d3_to_d0_delay(pdata);
1034
1035         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1036                 acpi_lpss_restore_ctx(dev, pdata);
1037
1038         return 0;
1039 }
1040
1041 #ifdef CONFIG_PM_SLEEP
1042 static int acpi_lpss_suspend_late(struct device *dev)
1043 {
1044         int ret;
1045
1046         if (dev_pm_smart_suspend_and_suspended(dev))
1047                 return 0;
1048
1049         ret = pm_generic_suspend_late(dev);
1050         return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1051 }
1052
1053 static int acpi_lpss_resume_early(struct device *dev)
1054 {
1055         int ret = acpi_lpss_resume(dev);
1056
1057         return ret ? ret : pm_generic_resume_early(dev);
1058 }
1059 #endif /* CONFIG_PM_SLEEP */
1060
1061 static int acpi_lpss_runtime_suspend(struct device *dev)
1062 {
1063         int ret = pm_generic_runtime_suspend(dev);
1064
1065         return ret ? ret : acpi_lpss_suspend(dev, true);
1066 }
1067
1068 static int acpi_lpss_runtime_resume(struct device *dev)
1069 {
1070         int ret = acpi_lpss_resume(dev);
1071
1072         return ret ? ret : pm_generic_runtime_resume(dev);
1073 }
1074 #endif /* CONFIG_PM */
1075
1076 static struct dev_pm_domain acpi_lpss_pm_domain = {
1077 #ifdef CONFIG_PM
1078         .activate = acpi_lpss_activate,
1079         .dismiss = acpi_lpss_dismiss,
1080 #endif
1081         .ops = {
1082 #ifdef CONFIG_PM
1083 #ifdef CONFIG_PM_SLEEP
1084                 .prepare = acpi_subsys_prepare,
1085                 .complete = acpi_subsys_complete,
1086                 .suspend = acpi_subsys_suspend,
1087                 .suspend_late = acpi_lpss_suspend_late,
1088                 .suspend_noirq = acpi_subsys_suspend_noirq,
1089                 .resume_noirq = acpi_subsys_resume_noirq,
1090                 .resume_early = acpi_lpss_resume_early,
1091                 .freeze = acpi_subsys_freeze,
1092                 .freeze_late = acpi_subsys_freeze_late,
1093                 .freeze_noirq = acpi_subsys_freeze_noirq,
1094                 .thaw_noirq = acpi_subsys_thaw_noirq,
1095                 .poweroff = acpi_subsys_suspend,
1096                 .poweroff_late = acpi_lpss_suspend_late,
1097                 .poweroff_noirq = acpi_subsys_suspend_noirq,
1098                 .restore_noirq = acpi_subsys_resume_noirq,
1099                 .restore_early = acpi_lpss_resume_early,
1100 #endif
1101                 .runtime_suspend = acpi_lpss_runtime_suspend,
1102                 .runtime_resume = acpi_lpss_runtime_resume,
1103 #endif
1104         },
1105 };
1106
1107 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1108                                      unsigned long action, void *data)
1109 {
1110         struct platform_device *pdev = to_platform_device(data);
1111         struct lpss_private_data *pdata;
1112         struct acpi_device *adev;
1113         const struct acpi_device_id *id;
1114
1115         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1116         if (!id || !id->driver_data)
1117                 return 0;
1118
1119         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1120                 return 0;
1121
1122         pdata = acpi_driver_data(adev);
1123         if (!pdata)
1124                 return 0;
1125
1126         if (pdata->mmio_base &&
1127             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1128                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1129                 return 0;
1130         }
1131
1132         switch (action) {
1133         case BUS_NOTIFY_BIND_DRIVER:
1134                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1135                 break;
1136         case BUS_NOTIFY_DRIVER_NOT_BOUND:
1137         case BUS_NOTIFY_UNBOUND_DRIVER:
1138                 dev_pm_domain_set(&pdev->dev, NULL);
1139                 break;
1140         case BUS_NOTIFY_ADD_DEVICE:
1141                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1142                 if (pdata->dev_desc->flags & LPSS_LTR)
1143                         return sysfs_create_group(&pdev->dev.kobj,
1144                                                   &lpss_attr_group);
1145                 break;
1146         case BUS_NOTIFY_DEL_DEVICE:
1147                 if (pdata->dev_desc->flags & LPSS_LTR)
1148                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1149                 dev_pm_domain_set(&pdev->dev, NULL);
1150                 break;
1151         default:
1152                 break;
1153         }
1154
1155         return 0;
1156 }
1157
1158 static struct notifier_block acpi_lpss_nb = {
1159         .notifier_call = acpi_lpss_platform_notify,
1160 };
1161
1162 static void acpi_lpss_bind(struct device *dev)
1163 {
1164         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1165
1166         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1167                 return;
1168
1169         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1170                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1171         else
1172                 dev_err(dev, "MMIO size insufficient to access LTR\n");
1173 }
1174
1175 static void acpi_lpss_unbind(struct device *dev)
1176 {
1177         dev->power.set_latency_tolerance = NULL;
1178 }
1179
1180 static struct acpi_scan_handler lpss_handler = {
1181         .ids = acpi_lpss_device_ids,
1182         .attach = acpi_lpss_create_device,
1183         .bind = acpi_lpss_bind,
1184         .unbind = acpi_lpss_unbind,
1185 };
1186
1187 void __init acpi_lpss_init(void)
1188 {
1189         const struct x86_cpu_id *id;
1190         int ret;
1191
1192         ret = lpt_clk_init();
1193         if (ret)
1194                 return;
1195
1196         id = x86_match_cpu(lpss_cpu_ids);
1197         if (id)
1198                 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1199
1200         bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1201         acpi_scan_add_handler(&lpss_handler);
1202 }
1203
1204 #else
1205
1206 static struct acpi_scan_handler lpss_handler = {
1207         .ids = acpi_lpss_device_ids,
1208 };
1209
1210 void __init acpi_lpss_init(void)
1211 {
1212         acpi_scan_add_handler(&lpss_handler);
1213 }
1214
1215 #endif /* CONFIG_X86_INTEL_LPSS */