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nvme: disable irqs in nvme_freeze_queues
[uclinux-h8/linux.git] / drivers / block / nvme-core.c
1 /*
2  * NVM Express device driver
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14
15 #include <linux/nvme.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kthread.h>
31 #include <linux/kernel.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
42 #include <scsi/sg.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
44
45 #define NVME_MINORS             (1U << MINORBITS)
46 #define NVME_Q_DEPTH            1024
47 #define NVME_AQ_DEPTH           256
48 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
49 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
50 #define ADMIN_TIMEOUT           (admin_timeout * HZ)
51 #define SHUTDOWN_TIMEOUT        (shutdown_timeout * HZ)
52
53 static unsigned char admin_timeout = 60;
54 module_param(admin_timeout, byte, 0644);
55 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
56
57 unsigned char nvme_io_timeout = 30;
58 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
59 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
60
61 static unsigned char shutdown_timeout = 5;
62 module_param(shutdown_timeout, byte, 0644);
63 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
64
65 static int nvme_major;
66 module_param(nvme_major, int, 0);
67
68 static int nvme_char_major;
69 module_param(nvme_char_major, int, 0);
70
71 static int use_threaded_interrupts;
72 module_param(use_threaded_interrupts, int, 0);
73
74 static DEFINE_SPINLOCK(dev_list_lock);
75 static LIST_HEAD(dev_list);
76 static struct task_struct *nvme_thread;
77 static struct workqueue_struct *nvme_workq;
78 static wait_queue_head_t nvme_kthread_wait;
79
80 static struct class *nvme_class;
81
82 static void nvme_reset_failed_dev(struct work_struct *ws);
83 static int nvme_process_cq(struct nvme_queue *nvmeq);
84
85 struct async_cmd_info {
86         struct kthread_work work;
87         struct kthread_worker *worker;
88         struct request *req;
89         u32 result;
90         int status;
91         void *ctx;
92 };
93
94 /*
95  * An NVM Express queue.  Each device has at least two (one for admin
96  * commands and one for I/O commands).
97  */
98 struct nvme_queue {
99         struct device *q_dmadev;
100         struct nvme_dev *dev;
101         char irqname[24];       /* nvme4294967295-65535\0 */
102         spinlock_t q_lock;
103         struct nvme_command *sq_cmds;
104         volatile struct nvme_completion *cqes;
105         dma_addr_t sq_dma_addr;
106         dma_addr_t cq_dma_addr;
107         u32 __iomem *q_db;
108         u16 q_depth;
109         s16 cq_vector;
110         u16 sq_head;
111         u16 sq_tail;
112         u16 cq_head;
113         u16 qid;
114         u8 cq_phase;
115         u8 cqe_seen;
116         struct async_cmd_info cmdinfo;
117         struct blk_mq_hw_ctx *hctx;
118 };
119
120 /*
121  * Check we didin't inadvertently grow the command struct
122  */
123 static inline void _nvme_check_size(void)
124 {
125         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
130         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
131         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
132         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
136         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
137 }
138
139 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
140                                                 struct nvme_completion *);
141
142 struct nvme_cmd_info {
143         nvme_completion_fn fn;
144         void *ctx;
145         int aborted;
146         struct nvme_queue *nvmeq;
147         struct nvme_iod iod[0];
148 };
149
150 /*
151  * Max size of iod being embedded in the request payload
152  */
153 #define NVME_INT_PAGES          2
154 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->page_size)
155 #define NVME_INT_MASK           0x01
156
157 /*
158  * Will slightly overestimate the number of pages needed.  This is OK
159  * as it only leads to a small amount of wasted memory for the lifetime of
160  * the I/O.
161  */
162 static int nvme_npages(unsigned size, struct nvme_dev *dev)
163 {
164         unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
165         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
166 }
167
168 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
169 {
170         unsigned int ret = sizeof(struct nvme_cmd_info);
171
172         ret += sizeof(struct nvme_iod);
173         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
174         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
175
176         return ret;
177 }
178
179 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
180                                 unsigned int hctx_idx)
181 {
182         struct nvme_dev *dev = data;
183         struct nvme_queue *nvmeq = dev->queues[0];
184
185         WARN_ON(nvmeq->hctx);
186         nvmeq->hctx = hctx;
187         hctx->driver_data = nvmeq;
188         return 0;
189 }
190
191 static int nvme_admin_init_request(void *data, struct request *req,
192                                 unsigned int hctx_idx, unsigned int rq_idx,
193                                 unsigned int numa_node)
194 {
195         struct nvme_dev *dev = data;
196         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
197         struct nvme_queue *nvmeq = dev->queues[0];
198
199         BUG_ON(!nvmeq);
200         cmd->nvmeq = nvmeq;
201         return 0;
202 }
203
204 static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
205 {
206         struct nvme_queue *nvmeq = hctx->driver_data;
207
208         nvmeq->hctx = NULL;
209 }
210
211 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
212                           unsigned int hctx_idx)
213 {
214         struct nvme_dev *dev = data;
215         struct nvme_queue *nvmeq = dev->queues[
216                                         (hctx_idx % dev->queue_count) + 1];
217
218         if (!nvmeq->hctx)
219                 nvmeq->hctx = hctx;
220
221         /* nvmeq queues are shared between namespaces. We assume here that
222          * blk-mq map the tags so they match up with the nvme queue tags. */
223         WARN_ON(nvmeq->hctx->tags != hctx->tags);
224
225         hctx->driver_data = nvmeq;
226         return 0;
227 }
228
229 static int nvme_init_request(void *data, struct request *req,
230                                 unsigned int hctx_idx, unsigned int rq_idx,
231                                 unsigned int numa_node)
232 {
233         struct nvme_dev *dev = data;
234         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
235         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
236
237         BUG_ON(!nvmeq);
238         cmd->nvmeq = nvmeq;
239         return 0;
240 }
241
242 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
243                                 nvme_completion_fn handler)
244 {
245         cmd->fn = handler;
246         cmd->ctx = ctx;
247         cmd->aborted = 0;
248         blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
249 }
250
251 static void *iod_get_private(struct nvme_iod *iod)
252 {
253         return (void *) (iod->private & ~0x1UL);
254 }
255
256 /*
257  * If bit 0 is set, the iod is embedded in the request payload.
258  */
259 static bool iod_should_kfree(struct nvme_iod *iod)
260 {
261         return (iod->private & NVME_INT_MASK) == 0;
262 }
263
264 /* Special values must be less than 0x1000 */
265 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
266 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
267 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
268 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
269
270 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
271                                                 struct nvme_completion *cqe)
272 {
273         if (ctx == CMD_CTX_CANCELLED)
274                 return;
275         if (ctx == CMD_CTX_COMPLETED) {
276                 dev_warn(nvmeq->q_dmadev,
277                                 "completed id %d twice on queue %d\n",
278                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
279                 return;
280         }
281         if (ctx == CMD_CTX_INVALID) {
282                 dev_warn(nvmeq->q_dmadev,
283                                 "invalid id %d completed on queue %d\n",
284                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
285                 return;
286         }
287         dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
288 }
289
290 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
291 {
292         void *ctx;
293
294         if (fn)
295                 *fn = cmd->fn;
296         ctx = cmd->ctx;
297         cmd->fn = special_completion;
298         cmd->ctx = CMD_CTX_CANCELLED;
299         return ctx;
300 }
301
302 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
303                                                 struct nvme_completion *cqe)
304 {
305         u32 result = le32_to_cpup(&cqe->result);
306         u16 status = le16_to_cpup(&cqe->status) >> 1;
307
308         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
309                 ++nvmeq->dev->event_limit;
310         if (status == NVME_SC_SUCCESS)
311                 dev_warn(nvmeq->q_dmadev,
312                         "async event result %08x\n", result);
313 }
314
315 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
316                                                 struct nvme_completion *cqe)
317 {
318         struct request *req = ctx;
319
320         u16 status = le16_to_cpup(&cqe->status) >> 1;
321         u32 result = le32_to_cpup(&cqe->result);
322
323         blk_mq_free_hctx_request(nvmeq->hctx, req);
324
325         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
326         ++nvmeq->dev->abort_limit;
327 }
328
329 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
330                                                 struct nvme_completion *cqe)
331 {
332         struct async_cmd_info *cmdinfo = ctx;
333         cmdinfo->result = le32_to_cpup(&cqe->result);
334         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
335         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
336         blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
337 }
338
339 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
340                                   unsigned int tag)
341 {
342         struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
343         struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
344
345         return blk_mq_rq_to_pdu(req);
346 }
347
348 /*
349  * Called with local interrupts disabled and the q_lock held.  May not sleep.
350  */
351 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
352                                                 nvme_completion_fn *fn)
353 {
354         struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
355         void *ctx;
356         if (tag >= nvmeq->q_depth) {
357                 *fn = special_completion;
358                 return CMD_CTX_INVALID;
359         }
360         if (fn)
361                 *fn = cmd->fn;
362         ctx = cmd->ctx;
363         cmd->fn = special_completion;
364         cmd->ctx = CMD_CTX_COMPLETED;
365         return ctx;
366 }
367
368 /**
369  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
370  * @nvmeq: The queue to use
371  * @cmd: The command to send
372  *
373  * Safe to use from interrupt context
374  */
375 static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
376 {
377         u16 tail = nvmeq->sq_tail;
378
379         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
380         if (++tail == nvmeq->q_depth)
381                 tail = 0;
382         writel(tail, nvmeq->q_db);
383         nvmeq->sq_tail = tail;
384
385         return 0;
386 }
387
388 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
389 {
390         unsigned long flags;
391         int ret;
392         spin_lock_irqsave(&nvmeq->q_lock, flags);
393         ret = __nvme_submit_cmd(nvmeq, cmd);
394         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
395         return ret;
396 }
397
398 static __le64 **iod_list(struct nvme_iod *iod)
399 {
400         return ((void *)iod) + iod->offset;
401 }
402
403 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
404                             unsigned nseg, unsigned long private)
405 {
406         iod->private = private;
407         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
408         iod->npages = -1;
409         iod->length = nbytes;
410         iod->nents = 0;
411 }
412
413 static struct nvme_iod *
414 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
415                  unsigned long priv, gfp_t gfp)
416 {
417         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
418                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
419                                 sizeof(struct scatterlist) * nseg, gfp);
420
421         if (iod)
422                 iod_init(iod, bytes, nseg, priv);
423
424         return iod;
425 }
426
427 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
428                                        gfp_t gfp)
429 {
430         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
431                                                 sizeof(struct nvme_dsm_range);
432         struct nvme_iod *iod;
433
434         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
435             size <= NVME_INT_BYTES(dev)) {
436                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
437
438                 iod = cmd->iod;
439                 iod_init(iod, size, rq->nr_phys_segments,
440                                 (unsigned long) rq | NVME_INT_MASK);
441                 return iod;
442         }
443
444         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
445                                 (unsigned long) rq, gfp);
446 }
447
448 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
449 {
450         const int last_prp = dev->page_size / 8 - 1;
451         int i;
452         __le64 **list = iod_list(iod);
453         dma_addr_t prp_dma = iod->first_dma;
454
455         if (iod->npages == 0)
456                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
457         for (i = 0; i < iod->npages; i++) {
458                 __le64 *prp_list = list[i];
459                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
460                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
461                 prp_dma = next_prp_dma;
462         }
463
464         if (iod_should_kfree(iod))
465                 kfree(iod);
466 }
467
468 static int nvme_error_status(u16 status)
469 {
470         switch (status & 0x7ff) {
471         case NVME_SC_SUCCESS:
472                 return 0;
473         case NVME_SC_CAP_EXCEEDED:
474                 return -ENOSPC;
475         default:
476                 return -EIO;
477         }
478 }
479
480 #ifdef CONFIG_BLK_DEV_INTEGRITY
481 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
482 {
483         if (be32_to_cpu(pi->ref_tag) == v)
484                 pi->ref_tag = cpu_to_be32(p);
485 }
486
487 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
488 {
489         if (be32_to_cpu(pi->ref_tag) == p)
490                 pi->ref_tag = cpu_to_be32(v);
491 }
492
493 /**
494  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
495  *
496  * The virtual start sector is the one that was originally submitted by the
497  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
498  * start sector may be different. Remap protection information to match the
499  * physical LBA on writes, and back to the original seed on reads.
500  *
501  * Type 0 and 3 do not have a ref tag, so no remapping required.
502  */
503 static void nvme_dif_remap(struct request *req,
504                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
505 {
506         struct nvme_ns *ns = req->rq_disk->private_data;
507         struct bio_integrity_payload *bip;
508         struct t10_pi_tuple *pi;
509         void *p, *pmap;
510         u32 i, nlb, ts, phys, virt;
511
512         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
513                 return;
514
515         bip = bio_integrity(req->bio);
516         if (!bip)
517                 return;
518
519         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
520
521         p = pmap;
522         virt = bip_get_seed(bip);
523         phys = nvme_block_nr(ns, blk_rq_pos(req));
524         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
525         ts = ns->disk->integrity->tuple_size;
526
527         for (i = 0; i < nlb; i++, virt++, phys++) {
528                 pi = (struct t10_pi_tuple *)p;
529                 dif_swap(phys, virt, pi);
530                 p += ts;
531         }
532         kunmap_atomic(pmap);
533 }
534
535 static int nvme_noop_verify(struct blk_integrity_iter *iter)
536 {
537         return 0;
538 }
539
540 static int nvme_noop_generate(struct blk_integrity_iter *iter)
541 {
542         return 0;
543 }
544
545 struct blk_integrity nvme_meta_noop = {
546         .name                   = "NVME_META_NOOP",
547         .generate_fn            = nvme_noop_generate,
548         .verify_fn              = nvme_noop_verify,
549 };
550
551 static void nvme_init_integrity(struct nvme_ns *ns)
552 {
553         struct blk_integrity integrity;
554
555         switch (ns->pi_type) {
556         case NVME_NS_DPS_PI_TYPE3:
557                 integrity = t10_pi_type3_crc;
558                 break;
559         case NVME_NS_DPS_PI_TYPE1:
560         case NVME_NS_DPS_PI_TYPE2:
561                 integrity = t10_pi_type1_crc;
562                 break;
563         default:
564                 integrity = nvme_meta_noop;
565                 break;
566         }
567         integrity.tuple_size = ns->ms;
568         blk_integrity_register(ns->disk, &integrity);
569         blk_queue_max_integrity_segments(ns->queue, 1);
570 }
571 #else /* CONFIG_BLK_DEV_INTEGRITY */
572 static void nvme_dif_remap(struct request *req,
573                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
574 {
575 }
576 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
577 {
578 }
579 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
580 {
581 }
582 static void nvme_init_integrity(struct nvme_ns *ns)
583 {
584 }
585 #endif
586
587 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
588                                                 struct nvme_completion *cqe)
589 {
590         struct nvme_iod *iod = ctx;
591         struct request *req = iod_get_private(iod);
592         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
593
594         u16 status = le16_to_cpup(&cqe->status) >> 1;
595
596         if (unlikely(status)) {
597                 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
598                     && (jiffies - req->start_time) < req->timeout) {
599                         unsigned long flags;
600
601                         blk_mq_requeue_request(req);
602                         spin_lock_irqsave(req->q->queue_lock, flags);
603                         if (!blk_queue_stopped(req->q))
604                                 blk_mq_kick_requeue_list(req->q);
605                         spin_unlock_irqrestore(req->q->queue_lock, flags);
606                         return;
607                 }
608                 req->errors = nvme_error_status(status);
609         } else
610                 req->errors = 0;
611
612         if (cmd_rq->aborted)
613                 dev_warn(&nvmeq->dev->pci_dev->dev,
614                         "completing aborted command with status:%04x\n",
615                         status);
616
617         if (iod->nents) {
618                 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
619                         rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
620                 if (blk_integrity_rq(req)) {
621                         if (!rq_data_dir(req))
622                                 nvme_dif_remap(req, nvme_dif_complete);
623                         dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1,
624                                 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
625                 }
626         }
627         nvme_free_iod(nvmeq->dev, iod);
628
629         blk_mq_complete_request(req);
630 }
631
632 /* length is in bytes.  gfp flags indicates whether we may sleep. */
633 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
634                                                                 gfp_t gfp)
635 {
636         struct dma_pool *pool;
637         int length = total_len;
638         struct scatterlist *sg = iod->sg;
639         int dma_len = sg_dma_len(sg);
640         u64 dma_addr = sg_dma_address(sg);
641         u32 page_size = dev->page_size;
642         int offset = dma_addr & (page_size - 1);
643         __le64 *prp_list;
644         __le64 **list = iod_list(iod);
645         dma_addr_t prp_dma;
646         int nprps, i;
647
648         length -= (page_size - offset);
649         if (length <= 0)
650                 return total_len;
651
652         dma_len -= (page_size - offset);
653         if (dma_len) {
654                 dma_addr += (page_size - offset);
655         } else {
656                 sg = sg_next(sg);
657                 dma_addr = sg_dma_address(sg);
658                 dma_len = sg_dma_len(sg);
659         }
660
661         if (length <= page_size) {
662                 iod->first_dma = dma_addr;
663                 return total_len;
664         }
665
666         nprps = DIV_ROUND_UP(length, page_size);
667         if (nprps <= (256 / 8)) {
668                 pool = dev->prp_small_pool;
669                 iod->npages = 0;
670         } else {
671                 pool = dev->prp_page_pool;
672                 iod->npages = 1;
673         }
674
675         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
676         if (!prp_list) {
677                 iod->first_dma = dma_addr;
678                 iod->npages = -1;
679                 return (total_len - length) + page_size;
680         }
681         list[0] = prp_list;
682         iod->first_dma = prp_dma;
683         i = 0;
684         for (;;) {
685                 if (i == page_size >> 3) {
686                         __le64 *old_prp_list = prp_list;
687                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
688                         if (!prp_list)
689                                 return total_len - length;
690                         list[iod->npages++] = prp_list;
691                         prp_list[0] = old_prp_list[i - 1];
692                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
693                         i = 1;
694                 }
695                 prp_list[i++] = cpu_to_le64(dma_addr);
696                 dma_len -= page_size;
697                 dma_addr += page_size;
698                 length -= page_size;
699                 if (length <= 0)
700                         break;
701                 if (dma_len > 0)
702                         continue;
703                 BUG_ON(dma_len < 0);
704                 sg = sg_next(sg);
705                 dma_addr = sg_dma_address(sg);
706                 dma_len = sg_dma_len(sg);
707         }
708
709         return total_len;
710 }
711
712 /*
713  * We reuse the small pool to allocate the 16-byte range here as it is not
714  * worth having a special pool for these or additional cases to handle freeing
715  * the iod.
716  */
717 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
718                 struct request *req, struct nvme_iod *iod)
719 {
720         struct nvme_dsm_range *range =
721                                 (struct nvme_dsm_range *)iod_list(iod)[0];
722         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
723
724         range->cattr = cpu_to_le32(0);
725         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
726         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
727
728         memset(cmnd, 0, sizeof(*cmnd));
729         cmnd->dsm.opcode = nvme_cmd_dsm;
730         cmnd->dsm.command_id = req->tag;
731         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
732         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
733         cmnd->dsm.nr = 0;
734         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
735
736         if (++nvmeq->sq_tail == nvmeq->q_depth)
737                 nvmeq->sq_tail = 0;
738         writel(nvmeq->sq_tail, nvmeq->q_db);
739 }
740
741 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
742                                                                 int cmdid)
743 {
744         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
745
746         memset(cmnd, 0, sizeof(*cmnd));
747         cmnd->common.opcode = nvme_cmd_flush;
748         cmnd->common.command_id = cmdid;
749         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
750
751         if (++nvmeq->sq_tail == nvmeq->q_depth)
752                 nvmeq->sq_tail = 0;
753         writel(nvmeq->sq_tail, nvmeq->q_db);
754 }
755
756 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
757                                                         struct nvme_ns *ns)
758 {
759         struct request *req = iod_get_private(iod);
760         struct nvme_command *cmnd;
761         u16 control = 0;
762         u32 dsmgmt = 0;
763
764         if (req->cmd_flags & REQ_FUA)
765                 control |= NVME_RW_FUA;
766         if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
767                 control |= NVME_RW_LR;
768
769         if (req->cmd_flags & REQ_RAHEAD)
770                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
771
772         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
773         memset(cmnd, 0, sizeof(*cmnd));
774
775         cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
776         cmnd->rw.command_id = req->tag;
777         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
778         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
779         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
780         cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
781         cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
782
783         if (blk_integrity_rq(req)) {
784                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
785                 switch (ns->pi_type) {
786                 case NVME_NS_DPS_PI_TYPE3:
787                         control |= NVME_RW_PRINFO_PRCHK_GUARD;
788                         break;
789                 case NVME_NS_DPS_PI_TYPE1:
790                 case NVME_NS_DPS_PI_TYPE2:
791                         control |= NVME_RW_PRINFO_PRCHK_GUARD |
792                                         NVME_RW_PRINFO_PRCHK_REF;
793                         cmnd->rw.reftag = cpu_to_le32(
794                                         nvme_block_nr(ns, blk_rq_pos(req)));
795                         break;
796                 }
797         } else if (ns->ms)
798                 control |= NVME_RW_PRINFO_PRACT;
799
800         cmnd->rw.control = cpu_to_le16(control);
801         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
802
803         if (++nvmeq->sq_tail == nvmeq->q_depth)
804                 nvmeq->sq_tail = 0;
805         writel(nvmeq->sq_tail, nvmeq->q_db);
806
807         return 0;
808 }
809
810 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
811                          const struct blk_mq_queue_data *bd)
812 {
813         struct nvme_ns *ns = hctx->queue->queuedata;
814         struct nvme_queue *nvmeq = hctx->driver_data;
815         struct request *req = bd->rq;
816         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
817         struct nvme_iod *iod;
818         enum dma_data_direction dma_dir;
819
820         /*
821          * If formated with metadata, require the block layer provide a buffer
822          * unless this namespace is formated such that the metadata can be
823          * stripped/generated by the controller with PRACT=1.
824          */
825         if (ns->ms && !blk_integrity_rq(req)) {
826                 if (!(ns->pi_type && ns->ms == 8)) {
827                         req->errors = -EFAULT;
828                         blk_mq_complete_request(req);
829                         return BLK_MQ_RQ_QUEUE_OK;
830                 }
831         }
832
833         iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
834         if (!iod)
835                 return BLK_MQ_RQ_QUEUE_BUSY;
836
837         if (req->cmd_flags & REQ_DISCARD) {
838                 void *range;
839                 /*
840                  * We reuse the small pool to allocate the 16-byte range here
841                  * as it is not worth having a special pool for these or
842                  * additional cases to handle freeing the iod.
843                  */
844                 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
845                                                 GFP_ATOMIC,
846                                                 &iod->first_dma);
847                 if (!range)
848                         goto retry_cmd;
849                 iod_list(iod)[0] = (__le64 *)range;
850                 iod->npages = 0;
851         } else if (req->nr_phys_segments) {
852                 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
853
854                 sg_init_table(iod->sg, req->nr_phys_segments);
855                 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
856                 if (!iod->nents)
857                         goto error_cmd;
858
859                 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
860                         goto retry_cmd;
861
862                 if (blk_rq_bytes(req) !=
863                     nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
864                         dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
865                                         iod->nents, dma_dir);
866                         goto retry_cmd;
867                 }
868                 if (blk_integrity_rq(req)) {
869                         if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
870                                 goto error_cmd;
871
872                         sg_init_table(iod->meta_sg, 1);
873                         if (blk_rq_map_integrity_sg(
874                                         req->q, req->bio, iod->meta_sg) != 1)
875                                 goto error_cmd;
876
877                         if (rq_data_dir(req))
878                                 nvme_dif_remap(req, nvme_dif_prep);
879
880                         if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
881                                 goto error_cmd;
882                 }
883         }
884
885         nvme_set_info(cmd, iod, req_completion);
886         spin_lock_irq(&nvmeq->q_lock);
887         if (req->cmd_flags & REQ_DISCARD)
888                 nvme_submit_discard(nvmeq, ns, req, iod);
889         else if (req->cmd_flags & REQ_FLUSH)
890                 nvme_submit_flush(nvmeq, ns, req->tag);
891         else
892                 nvme_submit_iod(nvmeq, iod, ns);
893
894         nvme_process_cq(nvmeq);
895         spin_unlock_irq(&nvmeq->q_lock);
896         return BLK_MQ_RQ_QUEUE_OK;
897
898  error_cmd:
899         nvme_free_iod(nvmeq->dev, iod);
900         return BLK_MQ_RQ_QUEUE_ERROR;
901  retry_cmd:
902         nvme_free_iod(nvmeq->dev, iod);
903         return BLK_MQ_RQ_QUEUE_BUSY;
904 }
905
906 static int nvme_process_cq(struct nvme_queue *nvmeq)
907 {
908         u16 head, phase;
909
910         head = nvmeq->cq_head;
911         phase = nvmeq->cq_phase;
912
913         for (;;) {
914                 void *ctx;
915                 nvme_completion_fn fn;
916                 struct nvme_completion cqe = nvmeq->cqes[head];
917                 if ((le16_to_cpu(cqe.status) & 1) != phase)
918                         break;
919                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
920                 if (++head == nvmeq->q_depth) {
921                         head = 0;
922                         phase = !phase;
923                 }
924                 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
925                 fn(nvmeq, ctx, &cqe);
926         }
927
928         /* If the controller ignores the cq head doorbell and continuously
929          * writes to the queue, it is theoretically possible to wrap around
930          * the queue twice and mistakenly return IRQ_NONE.  Linux only
931          * requires that 0.1% of your interrupts are handled, so this isn't
932          * a big problem.
933          */
934         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
935                 return 0;
936
937         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
938         nvmeq->cq_head = head;
939         nvmeq->cq_phase = phase;
940
941         nvmeq->cqe_seen = 1;
942         return 1;
943 }
944
945 /* Admin queue isn't initialized as a request queue. If at some point this
946  * happens anyway, make sure to notify the user */
947 static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
948                                const struct blk_mq_queue_data *bd)
949 {
950         WARN_ON_ONCE(1);
951         return BLK_MQ_RQ_QUEUE_ERROR;
952 }
953
954 static irqreturn_t nvme_irq(int irq, void *data)
955 {
956         irqreturn_t result;
957         struct nvme_queue *nvmeq = data;
958         spin_lock(&nvmeq->q_lock);
959         nvme_process_cq(nvmeq);
960         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
961         nvmeq->cqe_seen = 0;
962         spin_unlock(&nvmeq->q_lock);
963         return result;
964 }
965
966 static irqreturn_t nvme_irq_check(int irq, void *data)
967 {
968         struct nvme_queue *nvmeq = data;
969         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
970         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
971                 return IRQ_NONE;
972         return IRQ_WAKE_THREAD;
973 }
974
975 struct sync_cmd_info {
976         struct task_struct *task;
977         u32 result;
978         int status;
979 };
980
981 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
982                                                 struct nvme_completion *cqe)
983 {
984         struct sync_cmd_info *cmdinfo = ctx;
985         cmdinfo->result = le32_to_cpup(&cqe->result);
986         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
987         wake_up_process(cmdinfo->task);
988 }
989
990 /*
991  * Returns 0 on success.  If the result is negative, it's a Linux error code;
992  * if the result is positive, it's an NVM Express status code
993  */
994 static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
995                                                 u32 *result, unsigned timeout)
996 {
997         struct sync_cmd_info cmdinfo;
998         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
999         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1000
1001         cmdinfo.task = current;
1002         cmdinfo.status = -EINTR;
1003
1004         cmd->common.command_id = req->tag;
1005
1006         nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
1007
1008         set_current_state(TASK_UNINTERRUPTIBLE);
1009         nvme_submit_cmd(nvmeq, cmd);
1010         schedule();
1011
1012         if (result)
1013                 *result = cmdinfo.result;
1014         return cmdinfo.status;
1015 }
1016
1017 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1018 {
1019         struct nvme_queue *nvmeq = dev->queues[0];
1020         struct nvme_command c;
1021         struct nvme_cmd_info *cmd_info;
1022         struct request *req;
1023
1024         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
1025         if (IS_ERR(req))
1026                 return PTR_ERR(req);
1027
1028         req->cmd_flags |= REQ_NO_TIMEOUT;
1029         cmd_info = blk_mq_rq_to_pdu(req);
1030         nvme_set_info(cmd_info, NULL, async_req_completion);
1031
1032         memset(&c, 0, sizeof(c));
1033         c.common.opcode = nvme_admin_async_event;
1034         c.common.command_id = req->tag;
1035
1036         blk_mq_free_hctx_request(nvmeq->hctx, req);
1037         return __nvme_submit_cmd(nvmeq, &c);
1038 }
1039
1040 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1041                         struct nvme_command *cmd,
1042                         struct async_cmd_info *cmdinfo, unsigned timeout)
1043 {
1044         struct nvme_queue *nvmeq = dev->queues[0];
1045         struct request *req;
1046         struct nvme_cmd_info *cmd_rq;
1047
1048         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1049         if (IS_ERR(req))
1050                 return PTR_ERR(req);
1051
1052         req->timeout = timeout;
1053         cmd_rq = blk_mq_rq_to_pdu(req);
1054         cmdinfo->req = req;
1055         nvme_set_info(cmd_rq, cmdinfo, async_completion);
1056         cmdinfo->status = -EINTR;
1057
1058         cmd->common.command_id = req->tag;
1059
1060         return nvme_submit_cmd(nvmeq, cmd);
1061 }
1062
1063 static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
1064                                                 u32 *result, unsigned timeout)
1065 {
1066         int res;
1067         struct request *req;
1068
1069         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1070         if (IS_ERR(req))
1071                 return PTR_ERR(req);
1072         res = nvme_submit_sync_cmd(req, cmd, result, timeout);
1073         blk_mq_free_request(req);
1074         return res;
1075 }
1076
1077 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
1078                                                                 u32 *result)
1079 {
1080         return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
1081 }
1082
1083 int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1084                                         struct nvme_command *cmd, u32 *result)
1085 {
1086         int res;
1087         struct request *req;
1088
1089         req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
1090                                                                         false);
1091         if (IS_ERR(req))
1092                 return PTR_ERR(req);
1093         res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
1094         blk_mq_free_request(req);
1095         return res;
1096 }
1097
1098 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1099 {
1100         struct nvme_command c;
1101
1102         memset(&c, 0, sizeof(c));
1103         c.delete_queue.opcode = opcode;
1104         c.delete_queue.qid = cpu_to_le16(id);
1105
1106         return nvme_submit_admin_cmd(dev, &c, NULL);
1107 }
1108
1109 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1110                                                 struct nvme_queue *nvmeq)
1111 {
1112         struct nvme_command c;
1113         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1114
1115         memset(&c, 0, sizeof(c));
1116         c.create_cq.opcode = nvme_admin_create_cq;
1117         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1118         c.create_cq.cqid = cpu_to_le16(qid);
1119         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1120         c.create_cq.cq_flags = cpu_to_le16(flags);
1121         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1122
1123         return nvme_submit_admin_cmd(dev, &c, NULL);
1124 }
1125
1126 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1127                                                 struct nvme_queue *nvmeq)
1128 {
1129         struct nvme_command c;
1130         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1131
1132         memset(&c, 0, sizeof(c));
1133         c.create_sq.opcode = nvme_admin_create_sq;
1134         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1135         c.create_sq.sqid = cpu_to_le16(qid);
1136         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1137         c.create_sq.sq_flags = cpu_to_le16(flags);
1138         c.create_sq.cqid = cpu_to_le16(qid);
1139
1140         return nvme_submit_admin_cmd(dev, &c, NULL);
1141 }
1142
1143 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1144 {
1145         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1146 }
1147
1148 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1149 {
1150         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1151 }
1152
1153 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
1154                                                         dma_addr_t dma_addr)
1155 {
1156         struct nvme_command c;
1157
1158         memset(&c, 0, sizeof(c));
1159         c.identify.opcode = nvme_admin_identify;
1160         c.identify.nsid = cpu_to_le32(nsid);
1161         c.identify.prp1 = cpu_to_le64(dma_addr);
1162         c.identify.cns = cpu_to_le32(cns);
1163
1164         return nvme_submit_admin_cmd(dev, &c, NULL);
1165 }
1166
1167 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1168                                         dma_addr_t dma_addr, u32 *result)
1169 {
1170         struct nvme_command c;
1171
1172         memset(&c, 0, sizeof(c));
1173         c.features.opcode = nvme_admin_get_features;
1174         c.features.nsid = cpu_to_le32(nsid);
1175         c.features.prp1 = cpu_to_le64(dma_addr);
1176         c.features.fid = cpu_to_le32(fid);
1177
1178         return nvme_submit_admin_cmd(dev, &c, result);
1179 }
1180
1181 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1182                                         dma_addr_t dma_addr, u32 *result)
1183 {
1184         struct nvme_command c;
1185
1186         memset(&c, 0, sizeof(c));
1187         c.features.opcode = nvme_admin_set_features;
1188         c.features.prp1 = cpu_to_le64(dma_addr);
1189         c.features.fid = cpu_to_le32(fid);
1190         c.features.dword11 = cpu_to_le32(dword11);
1191
1192         return nvme_submit_admin_cmd(dev, &c, result);
1193 }
1194
1195 /**
1196  * nvme_abort_req - Attempt aborting a request
1197  *
1198  * Schedule controller reset if the command was already aborted once before and
1199  * still hasn't been returned to the driver, or if this is the admin queue.
1200  */
1201 static void nvme_abort_req(struct request *req)
1202 {
1203         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1204         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1205         struct nvme_dev *dev = nvmeq->dev;
1206         struct request *abort_req;
1207         struct nvme_cmd_info *abort_cmd;
1208         struct nvme_command cmd;
1209
1210         if (!nvmeq->qid || cmd_rq->aborted) {
1211                 unsigned long flags;
1212
1213                 spin_lock_irqsave(&dev_list_lock, flags);
1214                 if (work_busy(&dev->reset_work))
1215                         goto out;
1216                 list_del_init(&dev->node);
1217                 dev_warn(&dev->pci_dev->dev,
1218                         "I/O %d QID %d timeout, reset controller\n",
1219                                                         req->tag, nvmeq->qid);
1220                 dev->reset_workfn = nvme_reset_failed_dev;
1221                 queue_work(nvme_workq, &dev->reset_work);
1222  out:
1223                 spin_unlock_irqrestore(&dev_list_lock, flags);
1224                 return;
1225         }
1226
1227         if (!dev->abort_limit)
1228                 return;
1229
1230         abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1231                                                                         false);
1232         if (IS_ERR(abort_req))
1233                 return;
1234
1235         abort_cmd = blk_mq_rq_to_pdu(abort_req);
1236         nvme_set_info(abort_cmd, abort_req, abort_completion);
1237
1238         memset(&cmd, 0, sizeof(cmd));
1239         cmd.abort.opcode = nvme_admin_abort_cmd;
1240         cmd.abort.cid = req->tag;
1241         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1242         cmd.abort.command_id = abort_req->tag;
1243
1244         --dev->abort_limit;
1245         cmd_rq->aborted = 1;
1246
1247         dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1248                                                         nvmeq->qid);
1249         if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1250                 dev_warn(nvmeq->q_dmadev,
1251                                 "Could not abort I/O %d QID %d",
1252                                 req->tag, nvmeq->qid);
1253                 blk_mq_free_request(abort_req);
1254         }
1255 }
1256
1257 static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1258                                 struct request *req, void *data, bool reserved)
1259 {
1260         struct nvme_queue *nvmeq = data;
1261         void *ctx;
1262         nvme_completion_fn fn;
1263         struct nvme_cmd_info *cmd;
1264         struct nvme_completion cqe;
1265
1266         if (!blk_mq_request_started(req))
1267                 return;
1268
1269         cmd = blk_mq_rq_to_pdu(req);
1270
1271         if (cmd->ctx == CMD_CTX_CANCELLED)
1272                 return;
1273
1274         if (blk_queue_dying(req->q))
1275                 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1276         else
1277                 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1278
1279
1280         dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1281                                                 req->tag, nvmeq->qid);
1282         ctx = cancel_cmd_info(cmd, &fn);
1283         fn(nvmeq, ctx, &cqe);
1284 }
1285
1286 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1287 {
1288         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1289         struct nvme_queue *nvmeq = cmd->nvmeq;
1290
1291         dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1292                                                         nvmeq->qid);
1293         spin_lock_irq(&nvmeq->q_lock);
1294         nvme_abort_req(req);
1295         spin_unlock_irq(&nvmeq->q_lock);
1296
1297         /*
1298          * The aborted req will be completed on receiving the abort req.
1299          * We enable the timer again. If hit twice, it'll cause a device reset,
1300          * as the device then is in a faulty state.
1301          */
1302         return BLK_EH_RESET_TIMER;
1303 }
1304
1305 static void nvme_free_queue(struct nvme_queue *nvmeq)
1306 {
1307         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1308                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1309         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1310                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1311         kfree(nvmeq);
1312 }
1313
1314 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1315 {
1316         int i;
1317
1318         for (i = dev->queue_count - 1; i >= lowest; i--) {
1319                 struct nvme_queue *nvmeq = dev->queues[i];
1320                 dev->queue_count--;
1321                 dev->queues[i] = NULL;
1322                 nvme_free_queue(nvmeq);
1323         }
1324 }
1325
1326 /**
1327  * nvme_suspend_queue - put queue into suspended state
1328  * @nvmeq - queue to suspend
1329  */
1330 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1331 {
1332         int vector;
1333
1334         spin_lock_irq(&nvmeq->q_lock);
1335         if (nvmeq->cq_vector == -1) {
1336                 spin_unlock_irq(&nvmeq->q_lock);
1337                 return 1;
1338         }
1339         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1340         nvmeq->dev->online_queues--;
1341         nvmeq->cq_vector = -1;
1342         spin_unlock_irq(&nvmeq->q_lock);
1343
1344         if (!nvmeq->qid && nvmeq->dev->admin_q)
1345                 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1346
1347         irq_set_affinity_hint(vector, NULL);
1348         free_irq(vector, nvmeq);
1349
1350         return 0;
1351 }
1352
1353 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1354 {
1355         struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1356
1357         spin_lock_irq(&nvmeq->q_lock);
1358         if (hctx && hctx->tags)
1359                 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
1360         spin_unlock_irq(&nvmeq->q_lock);
1361 }
1362
1363 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1364 {
1365         struct nvme_queue *nvmeq = dev->queues[qid];
1366
1367         if (!nvmeq)
1368                 return;
1369         if (nvme_suspend_queue(nvmeq))
1370                 return;
1371
1372         /* Don't tell the adapter to delete the admin queue.
1373          * Don't tell a removed adapter to delete IO queues. */
1374         if (qid && readl(&dev->bar->csts) != -1) {
1375                 adapter_delete_sq(dev, qid);
1376                 adapter_delete_cq(dev, qid);
1377         }
1378
1379         spin_lock_irq(&nvmeq->q_lock);
1380         nvme_process_cq(nvmeq);
1381         spin_unlock_irq(&nvmeq->q_lock);
1382 }
1383
1384 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1385                                                         int depth)
1386 {
1387         struct device *dmadev = &dev->pci_dev->dev;
1388         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1389         if (!nvmeq)
1390                 return NULL;
1391
1392         nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1393                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1394         if (!nvmeq->cqes)
1395                 goto free_nvmeq;
1396
1397         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1398                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1399         if (!nvmeq->sq_cmds)
1400                 goto free_cqdma;
1401
1402         nvmeq->q_dmadev = dmadev;
1403         nvmeq->dev = dev;
1404         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1405                         dev->instance, qid);
1406         spin_lock_init(&nvmeq->q_lock);
1407         nvmeq->cq_head = 0;
1408         nvmeq->cq_phase = 1;
1409         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1410         nvmeq->q_depth = depth;
1411         nvmeq->qid = qid;
1412         dev->queue_count++;
1413         dev->queues[qid] = nvmeq;
1414
1415         return nvmeq;
1416
1417  free_cqdma:
1418         dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1419                                                         nvmeq->cq_dma_addr);
1420  free_nvmeq:
1421         kfree(nvmeq);
1422         return NULL;
1423 }
1424
1425 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1426                                                         const char *name)
1427 {
1428         if (use_threaded_interrupts)
1429                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1430                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1431                                         name, nvmeq);
1432         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1433                                 IRQF_SHARED, name, nvmeq);
1434 }
1435
1436 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1437 {
1438         struct nvme_dev *dev = nvmeq->dev;
1439
1440         spin_lock_irq(&nvmeq->q_lock);
1441         nvmeq->sq_tail = 0;
1442         nvmeq->cq_head = 0;
1443         nvmeq->cq_phase = 1;
1444         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1445         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1446         dev->online_queues++;
1447         spin_unlock_irq(&nvmeq->q_lock);
1448 }
1449
1450 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1451 {
1452         struct nvme_dev *dev = nvmeq->dev;
1453         int result;
1454
1455         nvmeq->cq_vector = qid - 1;
1456         result = adapter_alloc_cq(dev, qid, nvmeq);
1457         if (result < 0)
1458                 return result;
1459
1460         result = adapter_alloc_sq(dev, qid, nvmeq);
1461         if (result < 0)
1462                 goto release_cq;
1463
1464         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1465         if (result < 0)
1466                 goto release_sq;
1467
1468         nvme_init_queue(nvmeq, qid);
1469         return result;
1470
1471  release_sq:
1472         adapter_delete_sq(dev, qid);
1473  release_cq:
1474         adapter_delete_cq(dev, qid);
1475         return result;
1476 }
1477
1478 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1479 {
1480         unsigned long timeout;
1481         u32 bit = enabled ? NVME_CSTS_RDY : 0;
1482
1483         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1484
1485         while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1486                 msleep(100);
1487                 if (fatal_signal_pending(current))
1488                         return -EINTR;
1489                 if (time_after(jiffies, timeout)) {
1490                         dev_err(&dev->pci_dev->dev,
1491                                 "Device not ready; aborting %s\n", enabled ?
1492                                                 "initialisation" : "reset");
1493                         return -ENODEV;
1494                 }
1495         }
1496
1497         return 0;
1498 }
1499
1500 /*
1501  * If the device has been passed off to us in an enabled state, just clear
1502  * the enabled bit.  The spec says we should set the 'shutdown notification
1503  * bits', but doing so may cause the device to complete commands to the
1504  * admin queue ... and we don't know what memory that might be pointing at!
1505  */
1506 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1507 {
1508         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1509         dev->ctrl_config &= ~NVME_CC_ENABLE;
1510         writel(dev->ctrl_config, &dev->bar->cc);
1511
1512         return nvme_wait_ready(dev, cap, false);
1513 }
1514
1515 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1516 {
1517         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1518         dev->ctrl_config |= NVME_CC_ENABLE;
1519         writel(dev->ctrl_config, &dev->bar->cc);
1520
1521         return nvme_wait_ready(dev, cap, true);
1522 }
1523
1524 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1525 {
1526         unsigned long timeout;
1527
1528         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1529         dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1530
1531         writel(dev->ctrl_config, &dev->bar->cc);
1532
1533         timeout = SHUTDOWN_TIMEOUT + jiffies;
1534         while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1535                                                         NVME_CSTS_SHST_CMPLT) {
1536                 msleep(100);
1537                 if (fatal_signal_pending(current))
1538                         return -EINTR;
1539                 if (time_after(jiffies, timeout)) {
1540                         dev_err(&dev->pci_dev->dev,
1541                                 "Device shutdown incomplete; abort shutdown\n");
1542                         return -ENODEV;
1543                 }
1544         }
1545
1546         return 0;
1547 }
1548
1549 static struct blk_mq_ops nvme_mq_admin_ops = {
1550         .queue_rq       = nvme_admin_queue_rq,
1551         .map_queue      = blk_mq_map_queue,
1552         .init_hctx      = nvme_admin_init_hctx,
1553         .exit_hctx      = nvme_exit_hctx,
1554         .init_request   = nvme_admin_init_request,
1555         .timeout        = nvme_timeout,
1556 };
1557
1558 static struct blk_mq_ops nvme_mq_ops = {
1559         .queue_rq       = nvme_queue_rq,
1560         .map_queue      = blk_mq_map_queue,
1561         .init_hctx      = nvme_init_hctx,
1562         .exit_hctx      = nvme_exit_hctx,
1563         .init_request   = nvme_init_request,
1564         .timeout        = nvme_timeout,
1565 };
1566
1567 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1568 {
1569         if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1570                 blk_cleanup_queue(dev->admin_q);
1571                 blk_mq_free_tag_set(&dev->admin_tagset);
1572         }
1573 }
1574
1575 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1576 {
1577         if (!dev->admin_q) {
1578                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1579                 dev->admin_tagset.nr_hw_queues = 1;
1580                 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1581                 dev->admin_tagset.reserved_tags = 1;
1582                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1583                 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1584                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1585                 dev->admin_tagset.driver_data = dev;
1586
1587                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1588                         return -ENOMEM;
1589
1590                 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1591                 if (IS_ERR(dev->admin_q)) {
1592                         blk_mq_free_tag_set(&dev->admin_tagset);
1593                         return -ENOMEM;
1594                 }
1595                 if (!blk_get_queue(dev->admin_q)) {
1596                         nvme_dev_remove_admin(dev);
1597                         return -ENODEV;
1598                 }
1599         } else
1600                 blk_mq_unfreeze_queue(dev->admin_q);
1601
1602         return 0;
1603 }
1604
1605 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1606 {
1607         int result;
1608         u32 aqa;
1609         u64 cap = readq(&dev->bar->cap);
1610         struct nvme_queue *nvmeq;
1611         unsigned page_shift = PAGE_SHIFT;
1612         unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1613         unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1614
1615         if (page_shift < dev_page_min) {
1616                 dev_err(&dev->pci_dev->dev,
1617                                 "Minimum device page size (%u) too large for "
1618                                 "host (%u)\n", 1 << dev_page_min,
1619                                 1 << page_shift);
1620                 return -ENODEV;
1621         }
1622         if (page_shift > dev_page_max) {
1623                 dev_info(&dev->pci_dev->dev,
1624                                 "Device maximum page size (%u) smaller than "
1625                                 "host (%u); enabling work-around\n",
1626                                 1 << dev_page_max, 1 << page_shift);
1627                 page_shift = dev_page_max;
1628         }
1629
1630         result = nvme_disable_ctrl(dev, cap);
1631         if (result < 0)
1632                 return result;
1633
1634         nvmeq = dev->queues[0];
1635         if (!nvmeq) {
1636                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1637                 if (!nvmeq)
1638                         return -ENOMEM;
1639         }
1640
1641         aqa = nvmeq->q_depth - 1;
1642         aqa |= aqa << 16;
1643
1644         dev->page_size = 1 << page_shift;
1645
1646         dev->ctrl_config = NVME_CC_CSS_NVM;
1647         dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1648         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1649         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1650
1651         writel(aqa, &dev->bar->aqa);
1652         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1653         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1654
1655         result = nvme_enable_ctrl(dev, cap);
1656         if (result)
1657                 goto free_nvmeq;
1658
1659         nvmeq->cq_vector = 0;
1660         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1661         if (result)
1662                 goto free_nvmeq;
1663
1664         return result;
1665
1666  free_nvmeq:
1667         nvme_free_queues(dev, 0);
1668         return result;
1669 }
1670
1671 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1672                                 unsigned long addr, unsigned length)
1673 {
1674         int i, err, count, nents, offset;
1675         struct scatterlist *sg;
1676         struct page **pages;
1677         struct nvme_iod *iod;
1678
1679         if (addr & 3)
1680                 return ERR_PTR(-EINVAL);
1681         if (!length || length > INT_MAX - PAGE_SIZE)
1682                 return ERR_PTR(-EINVAL);
1683
1684         offset = offset_in_page(addr);
1685         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1686         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1687         if (!pages)
1688                 return ERR_PTR(-ENOMEM);
1689
1690         err = get_user_pages_fast(addr, count, 1, pages);
1691         if (err < count) {
1692                 count = err;
1693                 err = -EFAULT;
1694                 goto put_pages;
1695         }
1696
1697         err = -ENOMEM;
1698         iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
1699         if (!iod)
1700                 goto put_pages;
1701
1702         sg = iod->sg;
1703         sg_init_table(sg, count);
1704         for (i = 0; i < count; i++) {
1705                 sg_set_page(&sg[i], pages[i],
1706                             min_t(unsigned, length, PAGE_SIZE - offset),
1707                             offset);
1708                 length -= (PAGE_SIZE - offset);
1709                 offset = 0;
1710         }
1711         sg_mark_end(&sg[i - 1]);
1712         iod->nents = count;
1713
1714         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1715                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1716         if (!nents)
1717                 goto free_iod;
1718
1719         kfree(pages);
1720         return iod;
1721
1722  free_iod:
1723         kfree(iod);
1724  put_pages:
1725         for (i = 0; i < count; i++)
1726                 put_page(pages[i]);
1727         kfree(pages);
1728         return ERR_PTR(err);
1729 }
1730
1731 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1732                         struct nvme_iod *iod)
1733 {
1734         int i;
1735
1736         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1737                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1738
1739         for (i = 0; i < iod->nents; i++)
1740                 put_page(sg_page(&iod->sg[i]));
1741 }
1742
1743 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1744 {
1745         struct nvme_dev *dev = ns->dev;
1746         struct nvme_user_io io;
1747         struct nvme_command c;
1748         unsigned length, meta_len, prp_len;
1749         int status, write;
1750         struct nvme_iod *iod;
1751         dma_addr_t meta_dma = 0;
1752         void *meta = NULL;
1753
1754         if (copy_from_user(&io, uio, sizeof(io)))
1755                 return -EFAULT;
1756         length = (io.nblocks + 1) << ns->lba_shift;
1757         meta_len = (io.nblocks + 1) * ns->ms;
1758
1759         if (meta_len && ((io.metadata & 3) || !io.metadata) && !ns->ext)
1760                 return -EINVAL;
1761         else if (meta_len && ns->ext) {
1762                 length += meta_len;
1763                 meta_len = 0;
1764         }
1765
1766         write = io.opcode & 1;
1767
1768         switch (io.opcode) {
1769         case nvme_cmd_write:
1770         case nvme_cmd_read:
1771         case nvme_cmd_compare:
1772                 iod = nvme_map_user_pages(dev, write, io.addr, length);
1773                 break;
1774         default:
1775                 return -EINVAL;
1776         }
1777
1778         if (IS_ERR(iod))
1779                 return PTR_ERR(iod);
1780
1781         prp_len = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1782         if (length != prp_len) {
1783                 status = -ENOMEM;
1784                 goto unmap;
1785         }
1786         if (meta_len) {
1787                 meta = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1788                                                 &meta_dma, GFP_KERNEL);
1789                 if (!meta) {
1790                         status = -ENOMEM;
1791                         goto unmap;
1792                 }
1793                 if (write) {
1794                         if (copy_from_user(meta, (void __user *)io.metadata,
1795                                                                 meta_len)) {
1796                                 status = -EFAULT;
1797                                 goto unmap;
1798                         }
1799                 }
1800         }
1801
1802         memset(&c, 0, sizeof(c));
1803         c.rw.opcode = io.opcode;
1804         c.rw.flags = io.flags;
1805         c.rw.nsid = cpu_to_le32(ns->ns_id);
1806         c.rw.slba = cpu_to_le64(io.slba);
1807         c.rw.length = cpu_to_le16(io.nblocks);
1808         c.rw.control = cpu_to_le16(io.control);
1809         c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1810         c.rw.reftag = cpu_to_le32(io.reftag);
1811         c.rw.apptag = cpu_to_le16(io.apptag);
1812         c.rw.appmask = cpu_to_le16(io.appmask);
1813         c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1814         c.rw.prp2 = cpu_to_le64(iod->first_dma);
1815         c.rw.metadata = cpu_to_le64(meta_dma);
1816         status = nvme_submit_io_cmd(dev, ns, &c, NULL);
1817  unmap:
1818         nvme_unmap_user_pages(dev, write, iod);
1819         nvme_free_iod(dev, iod);
1820         if (meta) {
1821                 if (status == NVME_SC_SUCCESS && !write) {
1822                         if (copy_to_user((void __user *)io.metadata, meta,
1823                                                                 meta_len))
1824                                 status = -EFAULT;
1825                 }
1826                 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta, meta_dma);
1827         }
1828         return status;
1829 }
1830
1831 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1832                         struct nvme_passthru_cmd __user *ucmd)
1833 {
1834         struct nvme_passthru_cmd cmd;
1835         struct nvme_command c;
1836         int status, length;
1837         struct nvme_iod *uninitialized_var(iod);
1838         unsigned timeout;
1839
1840         if (!capable(CAP_SYS_ADMIN))
1841                 return -EACCES;
1842         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1843                 return -EFAULT;
1844
1845         memset(&c, 0, sizeof(c));
1846         c.common.opcode = cmd.opcode;
1847         c.common.flags = cmd.flags;
1848         c.common.nsid = cpu_to_le32(cmd.nsid);
1849         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1850         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1851         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1852         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1853         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1854         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1855         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1856         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1857
1858         length = cmd.data_len;
1859         if (cmd.data_len) {
1860                 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1861                                                                 length);
1862                 if (IS_ERR(iod))
1863                         return PTR_ERR(iod);
1864                 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1865                 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1866                 c.common.prp2 = cpu_to_le64(iod->first_dma);
1867         }
1868
1869         timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1870                                                                 ADMIN_TIMEOUT;
1871
1872         if (length != cmd.data_len)
1873                 status = -ENOMEM;
1874         else if (ns) {
1875                 struct request *req;
1876
1877                 req = blk_mq_alloc_request(ns->queue, WRITE,
1878                                                 (GFP_KERNEL|__GFP_WAIT), false);
1879                 if (IS_ERR(req))
1880                         status = PTR_ERR(req);
1881                 else {
1882                         status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1883                                                                 timeout);
1884                         blk_mq_free_request(req);
1885                 }
1886         } else
1887                 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
1888
1889         if (cmd.data_len) {
1890                 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1891                 nvme_free_iod(dev, iod);
1892         }
1893
1894         if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1895                                                         sizeof(cmd.result)))
1896                 status = -EFAULT;
1897
1898         return status;
1899 }
1900
1901 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1902                                                         unsigned long arg)
1903 {
1904         struct nvme_ns *ns = bdev->bd_disk->private_data;
1905
1906         switch (cmd) {
1907         case NVME_IOCTL_ID:
1908                 force_successful_syscall_return();
1909                 return ns->ns_id;
1910         case NVME_IOCTL_ADMIN_CMD:
1911                 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1912         case NVME_IOCTL_IO_CMD:
1913                 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1914         case NVME_IOCTL_SUBMIT_IO:
1915                 return nvme_submit_io(ns, (void __user *)arg);
1916         case SG_GET_VERSION_NUM:
1917                 return nvme_sg_get_version_num((void __user *)arg);
1918         case SG_IO:
1919                 return nvme_sg_io(ns, (void __user *)arg);
1920         default:
1921                 return -ENOTTY;
1922         }
1923 }
1924
1925 #ifdef CONFIG_COMPAT
1926 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1927                                         unsigned int cmd, unsigned long arg)
1928 {
1929         switch (cmd) {
1930         case SG_IO:
1931                 return -ENOIOCTLCMD;
1932         }
1933         return nvme_ioctl(bdev, mode, cmd, arg);
1934 }
1935 #else
1936 #define nvme_compat_ioctl       NULL
1937 #endif
1938
1939 static int nvme_open(struct block_device *bdev, fmode_t mode)
1940 {
1941         int ret = 0;
1942         struct nvme_ns *ns;
1943
1944         spin_lock(&dev_list_lock);
1945         ns = bdev->bd_disk->private_data;
1946         if (!ns)
1947                 ret = -ENXIO;
1948         else if (!kref_get_unless_zero(&ns->dev->kref))
1949                 ret = -ENXIO;
1950         spin_unlock(&dev_list_lock);
1951
1952         return ret;
1953 }
1954
1955 static void nvme_free_dev(struct kref *kref);
1956
1957 static void nvme_release(struct gendisk *disk, fmode_t mode)
1958 {
1959         struct nvme_ns *ns = disk->private_data;
1960         struct nvme_dev *dev = ns->dev;
1961
1962         kref_put(&dev->kref, nvme_free_dev);
1963 }
1964
1965 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1966 {
1967         /* some standard values */
1968         geo->heads = 1 << 6;
1969         geo->sectors = 1 << 5;
1970         geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1971         return 0;
1972 }
1973
1974 static void nvme_config_discard(struct nvme_ns *ns)
1975 {
1976         u32 logical_block_size = queue_logical_block_size(ns->queue);
1977         ns->queue->limits.discard_zeroes_data = 0;
1978         ns->queue->limits.discard_alignment = logical_block_size;
1979         ns->queue->limits.discard_granularity = logical_block_size;
1980         ns->queue->limits.max_discard_sectors = 0xffffffff;
1981         queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1982 }
1983
1984 static int nvme_revalidate_disk(struct gendisk *disk)
1985 {
1986         struct nvme_ns *ns = disk->private_data;
1987         struct nvme_dev *dev = ns->dev;
1988         struct nvme_id_ns *id;
1989         dma_addr_t dma_addr;
1990         u8 lbaf, pi_type;
1991         u16 old_ms;
1992         unsigned short bs;
1993
1994         id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1995                                                                 GFP_KERNEL);
1996         if (!id) {
1997                 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1998                                                                 __func__);
1999                 return 0;
2000         }
2001         if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) {
2002                 dev_warn(&dev->pci_dev->dev,
2003                         "identify failed ns:%d, setting capacity to 0\n",
2004                         ns->ns_id);
2005                 memset(id, 0, sizeof(*id));
2006         }
2007
2008         old_ms = ns->ms;
2009         lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2010         ns->lba_shift = id->lbaf[lbaf].ds;
2011         ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2012         ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
2013
2014         /*
2015          * If identify namespace failed, use default 512 byte block size so
2016          * block layer can use before failing read/write for 0 capacity.
2017          */
2018         if (ns->lba_shift == 0)
2019                 ns->lba_shift = 9;
2020         bs = 1 << ns->lba_shift;
2021
2022         /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2023         pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2024                                         id->dps & NVME_NS_DPS_PI_MASK : 0;
2025
2026         if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2027                                 ns->ms != old_ms ||
2028                                 bs != queue_logical_block_size(disk->queue) ||
2029                                 (ns->ms && ns->ext)))
2030                 blk_integrity_unregister(disk);
2031
2032         ns->pi_type = pi_type;
2033         blk_queue_logical_block_size(ns->queue, bs);
2034
2035         if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
2036                                                                 !ns->ext)
2037                 nvme_init_integrity(ns);
2038
2039         if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
2040                 set_capacity(disk, 0);
2041         else
2042                 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2043
2044         if (dev->oncs & NVME_CTRL_ONCS_DSM)
2045                 nvme_config_discard(ns);
2046
2047         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
2048         return 0;
2049 }
2050
2051 static const struct block_device_operations nvme_fops = {
2052         .owner          = THIS_MODULE,
2053         .ioctl          = nvme_ioctl,
2054         .compat_ioctl   = nvme_compat_ioctl,
2055         .open           = nvme_open,
2056         .release        = nvme_release,
2057         .getgeo         = nvme_getgeo,
2058         .revalidate_disk= nvme_revalidate_disk,
2059 };
2060
2061 static int nvme_kthread(void *data)
2062 {
2063         struct nvme_dev *dev, *next;
2064
2065         while (!kthread_should_stop()) {
2066                 set_current_state(TASK_INTERRUPTIBLE);
2067                 spin_lock(&dev_list_lock);
2068                 list_for_each_entry_safe(dev, next, &dev_list, node) {
2069                         int i;
2070                         if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
2071                                 if (work_busy(&dev->reset_work))
2072                                         continue;
2073                                 list_del_init(&dev->node);
2074                                 dev_warn(&dev->pci_dev->dev,
2075                                         "Failed status: %x, reset controller\n",
2076                                         readl(&dev->bar->csts));
2077                                 dev->reset_workfn = nvme_reset_failed_dev;
2078                                 queue_work(nvme_workq, &dev->reset_work);
2079                                 continue;
2080                         }
2081                         for (i = 0; i < dev->queue_count; i++) {
2082                                 struct nvme_queue *nvmeq = dev->queues[i];
2083                                 if (!nvmeq)
2084                                         continue;
2085                                 spin_lock_irq(&nvmeq->q_lock);
2086                                 nvme_process_cq(nvmeq);
2087
2088                                 while ((i == 0) && (dev->event_limit > 0)) {
2089                                         if (nvme_submit_async_admin_req(dev))
2090                                                 break;
2091                                         dev->event_limit--;
2092                                 }
2093                                 spin_unlock_irq(&nvmeq->q_lock);
2094                         }
2095                 }
2096                 spin_unlock(&dev_list_lock);
2097                 schedule_timeout(round_jiffies_relative(HZ));
2098         }
2099         return 0;
2100 }
2101
2102 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2103 {
2104         struct nvme_ns *ns;
2105         struct gendisk *disk;
2106         int node = dev_to_node(&dev->pci_dev->dev);
2107
2108         ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2109         if (!ns)
2110                 return;
2111
2112         ns->queue = blk_mq_init_queue(&dev->tagset);
2113         if (IS_ERR(ns->queue))
2114                 goto out_free_ns;
2115         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2116         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2117         queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
2118         ns->dev = dev;
2119         ns->queue->queuedata = ns;
2120
2121         disk = alloc_disk_node(0, node);
2122         if (!disk)
2123                 goto out_free_queue;
2124
2125         ns->ns_id = nsid;
2126         ns->disk = disk;
2127         ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2128         list_add_tail(&ns->list, &dev->namespaces);
2129
2130         blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2131         if (dev->max_hw_sectors)
2132                 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2133         if (dev->stripe_size)
2134                 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2135         if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2136                 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2137
2138         disk->major = nvme_major;
2139         disk->first_minor = 0;
2140         disk->fops = &nvme_fops;
2141         disk->private_data = ns;
2142         disk->queue = ns->queue;
2143         disk->driverfs_dev = dev->device;
2144         disk->flags = GENHD_FL_EXT_DEVT;
2145         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2146
2147         /*
2148          * Initialize capacity to 0 until we establish the namespace format and
2149          * setup integrity extentions if necessary. The revalidate_disk after
2150          * add_disk allows the driver to register with integrity if the format
2151          * requires it.
2152          */
2153         set_capacity(disk, 0);
2154         nvme_revalidate_disk(ns->disk);
2155         add_disk(ns->disk);
2156         if (ns->ms)
2157                 revalidate_disk(ns->disk);
2158         return;
2159  out_free_queue:
2160         blk_cleanup_queue(ns->queue);
2161  out_free_ns:
2162         kfree(ns);
2163 }
2164
2165 static void nvme_create_io_queues(struct nvme_dev *dev)
2166 {
2167         unsigned i;
2168
2169         for (i = dev->queue_count; i <= dev->max_qid; i++)
2170                 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2171                         break;
2172
2173         for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2174                 if (nvme_create_queue(dev->queues[i], i))
2175                         break;
2176 }
2177
2178 static int set_queue_count(struct nvme_dev *dev, int count)
2179 {
2180         int status;
2181         u32 result;
2182         u32 q_count = (count - 1) | ((count - 1) << 16);
2183
2184         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2185                                                                 &result);
2186         if (status < 0)
2187                 return status;
2188         if (status > 0) {
2189                 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2190                                                                         status);
2191                 return 0;
2192         }
2193         return min(result & 0xffff, result >> 16) + 1;
2194 }
2195
2196 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2197 {
2198         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2199 }
2200
2201 static int nvme_setup_io_queues(struct nvme_dev *dev)
2202 {
2203         struct nvme_queue *adminq = dev->queues[0];
2204         struct pci_dev *pdev = dev->pci_dev;
2205         int result, i, vecs, nr_io_queues, size;
2206
2207         nr_io_queues = num_possible_cpus();
2208         result = set_queue_count(dev, nr_io_queues);
2209         if (result <= 0)
2210                 return result;
2211         if (result < nr_io_queues)
2212                 nr_io_queues = result;
2213
2214         size = db_bar_size(dev, nr_io_queues);
2215         if (size > 8192) {
2216                 iounmap(dev->bar);
2217                 do {
2218                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2219                         if (dev->bar)
2220                                 break;
2221                         if (!--nr_io_queues)
2222                                 return -ENOMEM;
2223                         size = db_bar_size(dev, nr_io_queues);
2224                 } while (1);
2225                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2226                 adminq->q_db = dev->dbs;
2227         }
2228
2229         /* Deregister the admin queue's interrupt */
2230         free_irq(dev->entry[0].vector, adminq);
2231
2232         /*
2233          * If we enable msix early due to not intx, disable it again before
2234          * setting up the full range we need.
2235          */
2236         if (!pdev->irq)
2237                 pci_disable_msix(pdev);
2238
2239         for (i = 0; i < nr_io_queues; i++)
2240                 dev->entry[i].entry = i;
2241         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2242         if (vecs < 0) {
2243                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2244                 if (vecs < 0) {
2245                         vecs = 1;
2246                 } else {
2247                         for (i = 0; i < vecs; i++)
2248                                 dev->entry[i].vector = i + pdev->irq;
2249                 }
2250         }
2251
2252         /*
2253          * Should investigate if there's a performance win from allocating
2254          * more queues than interrupt vectors; it might allow the submission
2255          * path to scale better, even if the receive path is limited by the
2256          * number of interrupts.
2257          */
2258         nr_io_queues = vecs;
2259         dev->max_qid = nr_io_queues;
2260
2261         result = queue_request_irq(dev, adminq, adminq->irqname);
2262         if (result)
2263                 goto free_queues;
2264
2265         /* Free previously allocated queues that are no longer usable */
2266         nvme_free_queues(dev, nr_io_queues + 1);
2267         nvme_create_io_queues(dev);
2268
2269         return 0;
2270
2271  free_queues:
2272         nvme_free_queues(dev, 1);
2273         return result;
2274 }
2275
2276 /*
2277  * Return: error value if an error occurred setting up the queues or calling
2278  * Identify Device.  0 if these succeeded, even if adding some of the
2279  * namespaces failed.  At the moment, these failures are silent.  TBD which
2280  * failures should be reported.
2281  */
2282 static int nvme_dev_add(struct nvme_dev *dev)
2283 {
2284         struct pci_dev *pdev = dev->pci_dev;
2285         int res;
2286         unsigned nn, i;
2287         struct nvme_id_ctrl *ctrl;
2288         void *mem;
2289         dma_addr_t dma_addr;
2290         int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2291
2292         mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL);
2293         if (!mem)
2294                 return -ENOMEM;
2295
2296         res = nvme_identify(dev, 0, 1, dma_addr);
2297         if (res) {
2298                 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
2299                 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2300                 return -EIO;
2301         }
2302
2303         ctrl = mem;
2304         nn = le32_to_cpup(&ctrl->nn);
2305         dev->oncs = le16_to_cpup(&ctrl->oncs);
2306         dev->abort_limit = ctrl->acl + 1;
2307         dev->vwc = ctrl->vwc;
2308         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2309         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2310         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2311         if (ctrl->mdts)
2312                 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2313         if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2314                         (pdev->device == 0x0953) && ctrl->vs[3]) {
2315                 unsigned int max_hw_sectors;
2316
2317                 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2318                 max_hw_sectors = dev->stripe_size >> (shift - 9);
2319                 if (dev->max_hw_sectors) {
2320                         dev->max_hw_sectors = min(max_hw_sectors,
2321                                                         dev->max_hw_sectors);
2322                 } else
2323                         dev->max_hw_sectors = max_hw_sectors;
2324         }
2325         dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2326
2327         dev->tagset.ops = &nvme_mq_ops;
2328         dev->tagset.nr_hw_queues = dev->online_queues - 1;
2329         dev->tagset.timeout = NVME_IO_TIMEOUT;
2330         dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2331         dev->tagset.queue_depth =
2332                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2333         dev->tagset.cmd_size = nvme_cmd_size(dev);
2334         dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2335         dev->tagset.driver_data = dev;
2336
2337         if (blk_mq_alloc_tag_set(&dev->tagset))
2338                 return 0;
2339
2340         for (i = 1; i <= nn; i++)
2341                 nvme_alloc_ns(dev, i);
2342
2343         return 0;
2344 }
2345
2346 static int nvme_dev_map(struct nvme_dev *dev)
2347 {
2348         u64 cap;
2349         int bars, result = -ENOMEM;
2350         struct pci_dev *pdev = dev->pci_dev;
2351
2352         if (pci_enable_device_mem(pdev))
2353                 return result;
2354
2355         dev->entry[0].vector = pdev->irq;
2356         pci_set_master(pdev);
2357         bars = pci_select_bars(pdev, IORESOURCE_MEM);
2358         if (!bars)
2359                 goto disable_pci;
2360
2361         if (pci_request_selected_regions(pdev, bars, "nvme"))
2362                 goto disable_pci;
2363
2364         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2365             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2366                 goto disable;
2367
2368         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2369         if (!dev->bar)
2370                 goto disable;
2371
2372         if (readl(&dev->bar->csts) == -1) {
2373                 result = -ENODEV;
2374                 goto unmap;
2375         }
2376
2377         /*
2378          * Some devices don't advertse INTx interrupts, pre-enable a single
2379          * MSIX vec for setup. We'll adjust this later.
2380          */
2381         if (!pdev->irq) {
2382                 result = pci_enable_msix(pdev, dev->entry, 1);
2383                 if (result < 0)
2384                         goto unmap;
2385         }
2386
2387         cap = readq(&dev->bar->cap);
2388         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2389         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2390         dev->dbs = ((void __iomem *)dev->bar) + 4096;
2391
2392         return 0;
2393
2394  unmap:
2395         iounmap(dev->bar);
2396         dev->bar = NULL;
2397  disable:
2398         pci_release_regions(pdev);
2399  disable_pci:
2400         pci_disable_device(pdev);
2401         return result;
2402 }
2403
2404 static void nvme_dev_unmap(struct nvme_dev *dev)
2405 {
2406         if (dev->pci_dev->msi_enabled)
2407                 pci_disable_msi(dev->pci_dev);
2408         else if (dev->pci_dev->msix_enabled)
2409                 pci_disable_msix(dev->pci_dev);
2410
2411         if (dev->bar) {
2412                 iounmap(dev->bar);
2413                 dev->bar = NULL;
2414                 pci_release_regions(dev->pci_dev);
2415         }
2416
2417         if (pci_is_enabled(dev->pci_dev))
2418                 pci_disable_device(dev->pci_dev);
2419 }
2420
2421 struct nvme_delq_ctx {
2422         struct task_struct *waiter;
2423         struct kthread_worker *worker;
2424         atomic_t refcount;
2425 };
2426
2427 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2428 {
2429         dq->waiter = current;
2430         mb();
2431
2432         for (;;) {
2433                 set_current_state(TASK_KILLABLE);
2434                 if (!atomic_read(&dq->refcount))
2435                         break;
2436                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2437                                         fatal_signal_pending(current)) {
2438                         /*
2439                          * Disable the controller first since we can't trust it
2440                          * at this point, but leave the admin queue enabled
2441                          * until all queue deletion requests are flushed.
2442                          * FIXME: This may take a while if there are more h/w
2443                          * queues than admin tags.
2444                          */
2445                         set_current_state(TASK_RUNNING);
2446                         nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2447                         nvme_clear_queue(dev->queues[0]);
2448                         flush_kthread_worker(dq->worker);
2449                         nvme_disable_queue(dev, 0);
2450                         return;
2451                 }
2452         }
2453         set_current_state(TASK_RUNNING);
2454 }
2455
2456 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2457 {
2458         atomic_dec(&dq->refcount);
2459         if (dq->waiter)
2460                 wake_up_process(dq->waiter);
2461 }
2462
2463 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2464 {
2465         atomic_inc(&dq->refcount);
2466         return dq;
2467 }
2468
2469 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2470 {
2471         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2472         nvme_put_dq(dq);
2473 }
2474
2475 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2476                                                 kthread_work_func_t fn)
2477 {
2478         struct nvme_command c;
2479
2480         memset(&c, 0, sizeof(c));
2481         c.delete_queue.opcode = opcode;
2482         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2483
2484         init_kthread_work(&nvmeq->cmdinfo.work, fn);
2485         return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2486                                                                 ADMIN_TIMEOUT);
2487 }
2488
2489 static void nvme_del_cq_work_handler(struct kthread_work *work)
2490 {
2491         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2492                                                         cmdinfo.work);
2493         nvme_del_queue_end(nvmeq);
2494 }
2495
2496 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2497 {
2498         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2499                                                 nvme_del_cq_work_handler);
2500 }
2501
2502 static void nvme_del_sq_work_handler(struct kthread_work *work)
2503 {
2504         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2505                                                         cmdinfo.work);
2506         int status = nvmeq->cmdinfo.status;
2507
2508         if (!status)
2509                 status = nvme_delete_cq(nvmeq);
2510         if (status)
2511                 nvme_del_queue_end(nvmeq);
2512 }
2513
2514 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2515 {
2516         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2517                                                 nvme_del_sq_work_handler);
2518 }
2519
2520 static void nvme_del_queue_start(struct kthread_work *work)
2521 {
2522         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2523                                                         cmdinfo.work);
2524         if (nvme_delete_sq(nvmeq))
2525                 nvme_del_queue_end(nvmeq);
2526 }
2527
2528 static void nvme_disable_io_queues(struct nvme_dev *dev)
2529 {
2530         int i;
2531         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2532         struct nvme_delq_ctx dq;
2533         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2534                                         &worker, "nvme%d", dev->instance);
2535
2536         if (IS_ERR(kworker_task)) {
2537                 dev_err(&dev->pci_dev->dev,
2538                         "Failed to create queue del task\n");
2539                 for (i = dev->queue_count - 1; i > 0; i--)
2540                         nvme_disable_queue(dev, i);
2541                 return;
2542         }
2543
2544         dq.waiter = NULL;
2545         atomic_set(&dq.refcount, 0);
2546         dq.worker = &worker;
2547         for (i = dev->queue_count - 1; i > 0; i--) {
2548                 struct nvme_queue *nvmeq = dev->queues[i];
2549
2550                 if (nvme_suspend_queue(nvmeq))
2551                         continue;
2552                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2553                 nvmeq->cmdinfo.worker = dq.worker;
2554                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2555                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2556         }
2557         nvme_wait_dq(&dq, dev);
2558         kthread_stop(kworker_task);
2559 }
2560
2561 /*
2562 * Remove the node from the device list and check
2563 * for whether or not we need to stop the nvme_thread.
2564 */
2565 static void nvme_dev_list_remove(struct nvme_dev *dev)
2566 {
2567         struct task_struct *tmp = NULL;
2568
2569         spin_lock(&dev_list_lock);
2570         list_del_init(&dev->node);
2571         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2572                 tmp = nvme_thread;
2573                 nvme_thread = NULL;
2574         }
2575         spin_unlock(&dev_list_lock);
2576
2577         if (tmp)
2578                 kthread_stop(tmp);
2579 }
2580
2581 static void nvme_freeze_queues(struct nvme_dev *dev)
2582 {
2583         struct nvme_ns *ns;
2584
2585         list_for_each_entry(ns, &dev->namespaces, list) {
2586                 blk_mq_freeze_queue_start(ns->queue);
2587
2588                 spin_lock_irq(ns->queue->queue_lock);
2589                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2590                 spin_unlock_irq(ns->queue->queue_lock);
2591
2592                 blk_mq_cancel_requeue_work(ns->queue);
2593                 blk_mq_stop_hw_queues(ns->queue);
2594         }
2595 }
2596
2597 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2598 {
2599         struct nvme_ns *ns;
2600
2601         list_for_each_entry(ns, &dev->namespaces, list) {
2602                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2603                 blk_mq_unfreeze_queue(ns->queue);
2604                 blk_mq_start_stopped_hw_queues(ns->queue, true);
2605                 blk_mq_kick_requeue_list(ns->queue);
2606         }
2607 }
2608
2609 static void nvme_dev_shutdown(struct nvme_dev *dev)
2610 {
2611         int i;
2612         u32 csts = -1;
2613
2614         nvme_dev_list_remove(dev);
2615
2616         if (dev->bar) {
2617                 nvme_freeze_queues(dev);
2618                 csts = readl(&dev->bar->csts);
2619         }
2620         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2621                 for (i = dev->queue_count - 1; i >= 0; i--) {
2622                         struct nvme_queue *nvmeq = dev->queues[i];
2623                         nvme_suspend_queue(nvmeq);
2624                 }
2625         } else {
2626                 nvme_disable_io_queues(dev);
2627                 nvme_shutdown_ctrl(dev);
2628                 nvme_disable_queue(dev, 0);
2629         }
2630         nvme_dev_unmap(dev);
2631
2632         for (i = dev->queue_count - 1; i >= 0; i--)
2633                 nvme_clear_queue(dev->queues[i]);
2634 }
2635
2636 static void nvme_dev_remove(struct nvme_dev *dev)
2637 {
2638         struct nvme_ns *ns;
2639
2640         list_for_each_entry(ns, &dev->namespaces, list) {
2641                 if (ns->disk->flags & GENHD_FL_UP) {
2642                         if (blk_get_integrity(ns->disk))
2643                                 blk_integrity_unregister(ns->disk);
2644                         del_gendisk(ns->disk);
2645                 }
2646                 if (!blk_queue_dying(ns->queue)) {
2647                         blk_mq_abort_requeue_list(ns->queue);
2648                         blk_cleanup_queue(ns->queue);
2649                 }
2650         }
2651 }
2652
2653 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2654 {
2655         struct device *dmadev = &dev->pci_dev->dev;
2656         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2657                                                 PAGE_SIZE, PAGE_SIZE, 0);
2658         if (!dev->prp_page_pool)
2659                 return -ENOMEM;
2660
2661         /* Optimisation for I/Os between 4k and 128k */
2662         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2663                                                 256, 256, 0);
2664         if (!dev->prp_small_pool) {
2665                 dma_pool_destroy(dev->prp_page_pool);
2666                 return -ENOMEM;
2667         }
2668         return 0;
2669 }
2670
2671 static void nvme_release_prp_pools(struct nvme_dev *dev)
2672 {
2673         dma_pool_destroy(dev->prp_page_pool);
2674         dma_pool_destroy(dev->prp_small_pool);
2675 }
2676
2677 static DEFINE_IDA(nvme_instance_ida);
2678
2679 static int nvme_set_instance(struct nvme_dev *dev)
2680 {
2681         int instance, error;
2682
2683         do {
2684                 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2685                         return -ENODEV;
2686
2687                 spin_lock(&dev_list_lock);
2688                 error = ida_get_new(&nvme_instance_ida, &instance);
2689                 spin_unlock(&dev_list_lock);
2690         } while (error == -EAGAIN);
2691
2692         if (error)
2693                 return -ENODEV;
2694
2695         dev->instance = instance;
2696         return 0;
2697 }
2698
2699 static void nvme_release_instance(struct nvme_dev *dev)
2700 {
2701         spin_lock(&dev_list_lock);
2702         ida_remove(&nvme_instance_ida, dev->instance);
2703         spin_unlock(&dev_list_lock);
2704 }
2705
2706 static void nvme_free_namespaces(struct nvme_dev *dev)
2707 {
2708         struct nvme_ns *ns, *next;
2709
2710         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2711                 list_del(&ns->list);
2712
2713                 spin_lock(&dev_list_lock);
2714                 ns->disk->private_data = NULL;
2715                 spin_unlock(&dev_list_lock);
2716
2717                 put_disk(ns->disk);
2718                 kfree(ns);
2719         }
2720 }
2721
2722 static void nvme_free_dev(struct kref *kref)
2723 {
2724         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2725
2726         pci_dev_put(dev->pci_dev);
2727         put_device(dev->device);
2728         nvme_free_namespaces(dev);
2729         nvme_release_instance(dev);
2730         blk_mq_free_tag_set(&dev->tagset);
2731         blk_put_queue(dev->admin_q);
2732         kfree(dev->queues);
2733         kfree(dev->entry);
2734         kfree(dev);
2735 }
2736
2737 static int nvme_dev_open(struct inode *inode, struct file *f)
2738 {
2739         struct nvme_dev *dev;
2740         int instance = iminor(inode);
2741         int ret = -ENODEV;
2742
2743         spin_lock(&dev_list_lock);
2744         list_for_each_entry(dev, &dev_list, node) {
2745                 if (dev->instance == instance) {
2746                         if (!dev->admin_q) {
2747                                 ret = -EWOULDBLOCK;
2748                                 break;
2749                         }
2750                         if (!kref_get_unless_zero(&dev->kref))
2751                                 break;
2752                         f->private_data = dev;
2753                         ret = 0;
2754                         break;
2755                 }
2756         }
2757         spin_unlock(&dev_list_lock);
2758
2759         return ret;
2760 }
2761
2762 static int nvme_dev_release(struct inode *inode, struct file *f)
2763 {
2764         struct nvme_dev *dev = f->private_data;
2765         kref_put(&dev->kref, nvme_free_dev);
2766         return 0;
2767 }
2768
2769 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2770 {
2771         struct nvme_dev *dev = f->private_data;
2772         struct nvme_ns *ns;
2773
2774         switch (cmd) {
2775         case NVME_IOCTL_ADMIN_CMD:
2776                 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2777         case NVME_IOCTL_IO_CMD:
2778                 if (list_empty(&dev->namespaces))
2779                         return -ENOTTY;
2780                 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2781                 return nvme_user_cmd(dev, ns, (void __user *)arg);
2782         default:
2783                 return -ENOTTY;
2784         }
2785 }
2786
2787 static const struct file_operations nvme_dev_fops = {
2788         .owner          = THIS_MODULE,
2789         .open           = nvme_dev_open,
2790         .release        = nvme_dev_release,
2791         .unlocked_ioctl = nvme_dev_ioctl,
2792         .compat_ioctl   = nvme_dev_ioctl,
2793 };
2794
2795 static void nvme_set_irq_hints(struct nvme_dev *dev)
2796 {
2797         struct nvme_queue *nvmeq;
2798         int i;
2799
2800         for (i = 0; i < dev->online_queues; i++) {
2801                 nvmeq = dev->queues[i];
2802
2803                 if (!nvmeq->hctx)
2804                         continue;
2805
2806                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2807                                                         nvmeq->hctx->cpumask);
2808         }
2809 }
2810
2811 static int nvme_dev_start(struct nvme_dev *dev)
2812 {
2813         int result;
2814         bool start_thread = false;
2815
2816         result = nvme_dev_map(dev);
2817         if (result)
2818                 return result;
2819
2820         result = nvme_configure_admin_queue(dev);
2821         if (result)
2822                 goto unmap;
2823
2824         spin_lock(&dev_list_lock);
2825         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2826                 start_thread = true;
2827                 nvme_thread = NULL;
2828         }
2829         list_add(&dev->node, &dev_list);
2830         spin_unlock(&dev_list_lock);
2831
2832         if (start_thread) {
2833                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2834                 wake_up_all(&nvme_kthread_wait);
2835         } else
2836                 wait_event_killable(nvme_kthread_wait, nvme_thread);
2837
2838         if (IS_ERR_OR_NULL(nvme_thread)) {
2839                 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2840                 goto disable;
2841         }
2842
2843         nvme_init_queue(dev->queues[0], 0);
2844         result = nvme_alloc_admin_tags(dev);
2845         if (result)
2846                 goto disable;
2847
2848         result = nvme_setup_io_queues(dev);
2849         if (result)
2850                 goto free_tags;
2851
2852         nvme_set_irq_hints(dev);
2853
2854         dev->event_limit = 1;
2855         return result;
2856
2857  free_tags:
2858         nvme_dev_remove_admin(dev);
2859  disable:
2860         nvme_disable_queue(dev, 0);
2861         nvme_dev_list_remove(dev);
2862  unmap:
2863         nvme_dev_unmap(dev);
2864         return result;
2865 }
2866
2867 static int nvme_remove_dead_ctrl(void *arg)
2868 {
2869         struct nvme_dev *dev = (struct nvme_dev *)arg;
2870         struct pci_dev *pdev = dev->pci_dev;
2871
2872         if (pci_get_drvdata(pdev))
2873                 pci_stop_and_remove_bus_device_locked(pdev);
2874         kref_put(&dev->kref, nvme_free_dev);
2875         return 0;
2876 }
2877
2878 static void nvme_remove_disks(struct work_struct *ws)
2879 {
2880         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2881
2882         nvme_free_queues(dev, 1);
2883         nvme_dev_remove(dev);
2884 }
2885
2886 static int nvme_dev_resume(struct nvme_dev *dev)
2887 {
2888         int ret;
2889
2890         ret = nvme_dev_start(dev);
2891         if (ret)
2892                 return ret;
2893         if (dev->online_queues < 2) {
2894                 spin_lock(&dev_list_lock);
2895                 dev->reset_workfn = nvme_remove_disks;
2896                 queue_work(nvme_workq, &dev->reset_work);
2897                 spin_unlock(&dev_list_lock);
2898         } else {
2899                 nvme_unfreeze_queues(dev);
2900                 nvme_set_irq_hints(dev);
2901         }
2902         return 0;
2903 }
2904
2905 static void nvme_dev_reset(struct nvme_dev *dev)
2906 {
2907         nvme_dev_shutdown(dev);
2908         if (nvme_dev_resume(dev)) {
2909                 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
2910                 kref_get(&dev->kref);
2911                 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2912                                                         dev->instance))) {
2913                         dev_err(&dev->pci_dev->dev,
2914                                 "Failed to start controller remove task\n");
2915                         kref_put(&dev->kref, nvme_free_dev);
2916                 }
2917         }
2918 }
2919
2920 static void nvme_reset_failed_dev(struct work_struct *ws)
2921 {
2922         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2923         nvme_dev_reset(dev);
2924 }
2925
2926 static void nvme_reset_workfn(struct work_struct *work)
2927 {
2928         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2929         dev->reset_workfn(work);
2930 }
2931
2932 static void nvme_async_probe(struct work_struct *work);
2933 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2934 {
2935         int node, result = -ENOMEM;
2936         struct nvme_dev *dev;
2937
2938         node = dev_to_node(&pdev->dev);
2939         if (node == NUMA_NO_NODE)
2940                 set_dev_node(&pdev->dev, 0);
2941
2942         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2943         if (!dev)
2944                 return -ENOMEM;
2945         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2946                                                         GFP_KERNEL, node);
2947         if (!dev->entry)
2948                 goto free;
2949         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2950                                                         GFP_KERNEL, node);
2951         if (!dev->queues)
2952                 goto free;
2953
2954         INIT_LIST_HEAD(&dev->namespaces);
2955         dev->reset_workfn = nvme_reset_failed_dev;
2956         INIT_WORK(&dev->reset_work, nvme_reset_workfn);
2957         dev->pci_dev = pci_dev_get(pdev);
2958         pci_set_drvdata(pdev, dev);
2959         result = nvme_set_instance(dev);
2960         if (result)
2961                 goto put_pci;
2962
2963         result = nvme_setup_prp_pools(dev);
2964         if (result)
2965                 goto release;
2966
2967         kref_init(&dev->kref);
2968         dev->device = device_create(nvme_class, &pdev->dev,
2969                                 MKDEV(nvme_char_major, dev->instance),
2970                                 dev, "nvme%d", dev->instance);
2971         if (IS_ERR(dev->device)) {
2972                 result = PTR_ERR(dev->device);
2973                 goto release_pools;
2974         }
2975         get_device(dev->device);
2976
2977         INIT_LIST_HEAD(&dev->node);
2978         INIT_WORK(&dev->probe_work, nvme_async_probe);
2979         schedule_work(&dev->probe_work);
2980         return 0;
2981
2982  release_pools:
2983         nvme_release_prp_pools(dev);
2984  release:
2985         nvme_release_instance(dev);
2986  put_pci:
2987         pci_dev_put(dev->pci_dev);
2988  free:
2989         kfree(dev->queues);
2990         kfree(dev->entry);
2991         kfree(dev);
2992         return result;
2993 }
2994
2995 static void nvme_async_probe(struct work_struct *work)
2996 {
2997         struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2998         int result;
2999
3000         result = nvme_dev_start(dev);
3001         if (result)
3002                 goto reset;
3003
3004         if (dev->online_queues > 1)
3005                 result = nvme_dev_add(dev);
3006         if (result)
3007                 goto reset;
3008
3009         nvme_set_irq_hints(dev);
3010         return;
3011  reset:
3012         if (!work_busy(&dev->reset_work)) {
3013                 dev->reset_workfn = nvme_reset_failed_dev;
3014                 queue_work(nvme_workq, &dev->reset_work);
3015         }
3016 }
3017
3018 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3019 {
3020         struct nvme_dev *dev = pci_get_drvdata(pdev);
3021
3022         if (prepare)
3023                 nvme_dev_shutdown(dev);
3024         else
3025                 nvme_dev_resume(dev);
3026 }
3027
3028 static void nvme_shutdown(struct pci_dev *pdev)
3029 {
3030         struct nvme_dev *dev = pci_get_drvdata(pdev);
3031         nvme_dev_shutdown(dev);
3032 }
3033
3034 static void nvme_remove(struct pci_dev *pdev)
3035 {
3036         struct nvme_dev *dev = pci_get_drvdata(pdev);
3037
3038         spin_lock(&dev_list_lock);
3039         list_del_init(&dev->node);
3040         spin_unlock(&dev_list_lock);
3041
3042         pci_set_drvdata(pdev, NULL);
3043         flush_work(&dev->probe_work);
3044         flush_work(&dev->reset_work);
3045         nvme_dev_shutdown(dev);
3046         nvme_dev_remove(dev);
3047         nvme_dev_remove_admin(dev);
3048         device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3049         nvme_free_queues(dev, 0);
3050         nvme_release_prp_pools(dev);
3051         kref_put(&dev->kref, nvme_free_dev);
3052 }
3053
3054 /* These functions are yet to be implemented */
3055 #define nvme_error_detected NULL
3056 #define nvme_dump_registers NULL
3057 #define nvme_link_reset NULL
3058 #define nvme_slot_reset NULL
3059 #define nvme_error_resume NULL
3060
3061 #ifdef CONFIG_PM_SLEEP
3062 static int nvme_suspend(struct device *dev)
3063 {
3064         struct pci_dev *pdev = to_pci_dev(dev);
3065         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3066
3067         nvme_dev_shutdown(ndev);
3068         return 0;
3069 }
3070
3071 static int nvme_resume(struct device *dev)
3072 {
3073         struct pci_dev *pdev = to_pci_dev(dev);
3074         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3075
3076         if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
3077                 ndev->reset_workfn = nvme_reset_failed_dev;
3078                 queue_work(nvme_workq, &ndev->reset_work);
3079         }
3080         return 0;
3081 }
3082 #endif
3083
3084 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3085
3086 static const struct pci_error_handlers nvme_err_handler = {
3087         .error_detected = nvme_error_detected,
3088         .mmio_enabled   = nvme_dump_registers,
3089         .link_reset     = nvme_link_reset,
3090         .slot_reset     = nvme_slot_reset,
3091         .resume         = nvme_error_resume,
3092         .reset_notify   = nvme_reset_notify,
3093 };
3094
3095 /* Move to pci_ids.h later */
3096 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
3097
3098 static const struct pci_device_id nvme_id_table[] = {
3099         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3100         { 0, }
3101 };
3102 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3103
3104 static struct pci_driver nvme_driver = {
3105         .name           = "nvme",
3106         .id_table       = nvme_id_table,
3107         .probe          = nvme_probe,
3108         .remove         = nvme_remove,
3109         .shutdown       = nvme_shutdown,
3110         .driver         = {
3111                 .pm     = &nvme_dev_pm_ops,
3112         },
3113         .err_handler    = &nvme_err_handler,
3114 };
3115
3116 static int __init nvme_init(void)
3117 {
3118         int result;
3119
3120         init_waitqueue_head(&nvme_kthread_wait);
3121
3122         nvme_workq = create_singlethread_workqueue("nvme");
3123         if (!nvme_workq)
3124                 return -ENOMEM;
3125
3126         result = register_blkdev(nvme_major, "nvme");
3127         if (result < 0)
3128                 goto kill_workq;
3129         else if (result > 0)
3130                 nvme_major = result;
3131
3132         result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3133                                                         &nvme_dev_fops);
3134         if (result < 0)
3135                 goto unregister_blkdev;
3136         else if (result > 0)
3137                 nvme_char_major = result;
3138
3139         nvme_class = class_create(THIS_MODULE, "nvme");
3140         if (IS_ERR(nvme_class)) {
3141                 result = PTR_ERR(nvme_class);
3142                 goto unregister_chrdev;
3143         }
3144
3145         result = pci_register_driver(&nvme_driver);
3146         if (result)
3147                 goto destroy_class;
3148         return 0;
3149
3150  destroy_class:
3151         class_destroy(nvme_class);
3152  unregister_chrdev:
3153         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3154  unregister_blkdev:
3155         unregister_blkdev(nvme_major, "nvme");
3156  kill_workq:
3157         destroy_workqueue(nvme_workq);
3158         return result;
3159 }
3160
3161 static void __exit nvme_exit(void)
3162 {
3163         pci_unregister_driver(&nvme_driver);
3164         unregister_blkdev(nvme_major, "nvme");
3165         destroy_workqueue(nvme_workq);
3166         class_destroy(nvme_class);
3167         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3168         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3169         _nvme_check_size();
3170 }
3171
3172 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3173 MODULE_LICENSE("GPL");
3174 MODULE_VERSION("1.0");
3175 module_init(nvme_init);
3176 module_exit(nvme_exit);