1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Renesas Electronics Corp.
8 #include <linux/clk-provider.h>
9 #include <linux/device.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
13 #include <dt-bindings/clock/r9a07g044-cpg.h>
15 #include "rzg2l-cpg.h"
18 /* Core Clock Outputs exported to DT */
19 LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
21 /* External Input Clocks */
24 /* Internal Core Clocks */
59 static const struct clk_div_table dtable_1_8[] = {
67 static const struct clk_div_table dtable_1_32[] = {
76 /* Mux clock tables */
77 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
78 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
79 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
81 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
82 /* External Clock Inputs */
83 DEF_INPUT("extal", CLK_EXTAL),
85 /* Internal Core Clocks */
86 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
87 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
88 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
89 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
90 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
91 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
92 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
94 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
95 DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
97 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
99 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
100 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
101 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
102 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
103 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
105 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
106 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
108 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
109 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
110 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
111 DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
112 DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
113 sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
114 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
115 DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
117 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
118 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
120 /* Core output clk */
121 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
122 CLK_DIVIDER_HIWORD_MASK),
123 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
124 dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
125 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
126 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
127 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
128 DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
129 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
130 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
131 DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
132 DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
133 DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
134 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
135 sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
136 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
137 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
138 DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
139 sel_shdi, ARRAY_SIZE(sel_shdi)),
140 DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
141 sel_shdi, ARRAY_SIZE(sel_shdi)),
142 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
143 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
146 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
147 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
149 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
151 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
153 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
155 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
157 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
159 DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
161 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
163 DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
165 DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
167 DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
169 DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
171 DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
173 DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
175 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
177 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
179 DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
181 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
183 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
185 DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
187 DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
189 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
191 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
193 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
195 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
197 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
199 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
201 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
203 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
205 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
207 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
209 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
211 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
213 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
215 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
217 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
219 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
221 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
223 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
225 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
227 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
229 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
231 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
233 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
235 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
237 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
239 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
241 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
243 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
245 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
247 DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
249 DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
251 DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
253 DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
255 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
257 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
259 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
261 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
265 static struct rzg2l_reset r9a07g044_resets[] = {
266 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
267 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
268 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
269 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
270 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
271 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
272 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
273 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
274 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
275 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
276 DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
277 DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
278 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
279 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
280 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
281 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
282 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
283 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
284 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
285 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
286 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
287 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
288 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
289 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
290 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
291 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
292 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
293 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
294 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
295 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
296 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
297 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
298 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
299 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
300 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
301 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
302 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
303 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
304 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
305 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
306 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
307 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
308 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
309 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
310 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
313 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
314 MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
315 MOD_CLK_BASE + R9A07G044_IA55_CLK,
316 MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
319 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
321 .core_clks = r9a07g044_core_clks,
322 .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
323 .last_dt_core_clk = LAST_DT_CORE_CLK,
324 .num_total_core_clks = MOD_CLK_BASE,
326 /* Critical Module Clocks */
327 .crit_mod_clks = r9a07g044_crit_mod_clks,
328 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
331 .mod_clks = r9a07g044_mod_clks,
332 .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
333 .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
336 .resets = r9a07g044_resets,
337 .num_resets = ARRAY_SIZE(r9a07g044_resets),