2 * Copyright 2014 Google, Inc
3 * Author: Alexandru M Stan <amstan@chromium.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/slab.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
20 #include <linux/kernel.h>
23 struct rockchip_mmc_clock {
30 #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
32 #define RK3288_MMC_CLKGEN_DIV 2
34 static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
35 unsigned long parent_rate)
37 return parent_rate / RK3288_MMC_CLKGEN_DIV;
40 #define ROCKCHIP_MMC_DELAY_SEL BIT(10)
41 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
42 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
43 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
44 #define ROCKCHIP_MMC_INIT_STATE_RESET 0x1
45 #define ROCKCHIP_MMC_INIT_STATE_SHIFT 1
47 #define PSECS_PER_SEC 1000000000000LL
50 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
51 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
53 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
55 static int rockchip_mmc_get_phase(struct clk_hw *hw)
57 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
58 unsigned long rate = clk_get_rate(hw->clk);
63 /* See the comment for rockchip_mmc_set_phase below */
67 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
69 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
71 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
72 /* degrees/delaynum * 10000 */
73 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
74 36 * (rate / 1000000);
76 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
77 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
78 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
84 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
86 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
87 unsigned long rate = clk_get_rate(hw->clk);
88 u8 nineties, remainder;
94 * The below calculation is based on the output clock from
95 * MMC host to the card, which expects the phase clock inherits
96 * the clock rate from its parent, namely the output clock
97 * provider of MMC host. However, things may go wrong if
99 * (2) It is assigned to the wrong parent.
101 * This check help debug the case (1), which seems to be the
102 * most likely problem we often face and which makes it difficult
103 * for people to debug unstable mmc tuning results.
106 pr_err("%s: invalid clk rate\n", __func__);
110 nineties = degrees / 90;
111 remainder = (degrees % 90);
114 * Due to the inexact nature of the "fine" delay, we might
115 * actually go non-monotonic. We don't go _too_ monotonic
116 * though, so we should be OK. Here are options of how we may
119 * Ideally we end up with:
120 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0
122 * On one extreme (if delay is actually 44ps):
123 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0
124 * The other (if delay is actually 77ps):
125 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
127 * It's possible we might make a delay that is up to 25
128 * degrees off from what we think we're making. That's OK
129 * though because we should be REALLY far from any bad range.
133 * Convert to delay; do a little extra work to make sure we
134 * don't overflow 32-bit / 64-bit numbers.
136 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
138 delay = DIV_ROUND_CLOSEST(delay,
140 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
142 delay_num = (u8) min_t(u32, delay, 255);
144 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
145 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
146 raw_value |= nineties;
147 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg);
149 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
150 clk_hw_get_name(hw), degrees, delay_num,
151 mmc_clock->reg, raw_value>>(mmc_clock->shift),
152 rockchip_mmc_get_phase(hw)
158 static const struct clk_ops rockchip_mmc_clk_ops = {
159 .recalc_rate = rockchip_mmc_recalc,
160 .get_phase = rockchip_mmc_get_phase,
161 .set_phase = rockchip_mmc_set_phase,
164 struct clk *rockchip_clk_register_mmc(const char *name,
165 const char *const *parent_names, u8 num_parents,
166 void __iomem *reg, int shift)
168 struct clk_init_data init;
169 struct rockchip_mmc_clock *mmc_clock;
172 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
178 init.num_parents = num_parents;
179 init.parent_names = parent_names;
180 init.ops = &rockchip_mmc_clk_ops;
182 mmc_clock->hw.init = &init;
183 mmc_clock->reg = reg;
184 mmc_clock->shift = shift;
187 * Assert init_state to soft reset the CLKGEN
188 * for mmc tuning phase and degree
190 if (mmc_clock->shift == ROCKCHIP_MMC_INIT_STATE_SHIFT)
191 writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_RESET,
192 ROCKCHIP_MMC_INIT_STATE_RESET,
193 mmc_clock->shift), mmc_clock->reg);
195 clk = clk_register(NULL, &mmc_clock->hw);