drivers/crypto/ccree/cc_cipher.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <crypto/algapi.h>
   7 #include <crypto/internal/skcipher.h>
   8 #include <crypto/des.h>
   9 #include <crypto/xts.h>
  10 #include <crypto/sm4.h>
  11 #include <crypto/scatterwalk.h>
  12
  13 #include "cc_driver.h"
  14 #include "cc_lli_defs.h"
  15 #include "cc_buffer_mgr.h"
  16 #include "cc_cipher.h"
  17 #include "cc_request_mgr.h"
  18
  19 #define MAX_ABLKCIPHER_SEQ_LEN 6
  20
  21 #define template_skcipher       template_u.skcipher
  22
  23 struct cc_cipher_handle {
  24         struct list_head alg_list;
  25 };
  26
  27 struct cc_user_key_info {
  28         u8 *key;
  29         dma_addr_t key_dma_addr;
  30 };
  31
  32 struct cc_hw_key_info {
  33         enum cc_hw_crypto_key key1_slot;
  34         enum cc_hw_crypto_key key2_slot;
  35 };
  36
  37 struct cc_cpp_key_info {
  38         u8 slot;
  39         enum cc_cpp_alg alg;
  40 };
  41
  42 enum cc_key_type {
  43         CC_UNPROTECTED_KEY,             /* User key */
  44         CC_HW_PROTECTED_KEY,            /* HW (FDE) key */
  45         CC_POLICY_PROTECTED_KEY,        /* CPP key */
  46         CC_INVALID_PROTECTED_KEY        /* Invalid key */
  47 };
  48
  49 struct cc_cipher_ctx {
  50         struct cc_drvdata *drvdata;
  51         int keylen;
  52         int key_round_number;
  53         int cipher_mode;
  54         int flow_mode;
  55         unsigned int flags;
  56         enum cc_key_type key_type;
  57         struct cc_user_key_info user;
  58         union {
  59                 struct cc_hw_key_info hw;
  60                 struct cc_cpp_key_info cpp;
  61         };
  62         struct crypto_shash *shash_tfm;
  63 };
  64
  65 static void cc_cipher_complete(struct device *dev, void *cc_req, int err);
  66
  67 static inline enum cc_key_type cc_key_type(struct crypto_tfm *tfm)
  68 {
  69         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
  70
  71         return ctx_p->key_type;
  72 }
  73
  74 static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size)
  75 {
  76         switch (ctx_p->flow_mode) {
  77         case S_DIN_to_AES:
  78                 switch (size) {
  79                 case CC_AES_128_BIT_KEY_SIZE:
  80                 case CC_AES_192_BIT_KEY_SIZE:
  81                         if (ctx_p->cipher_mode != DRV_CIPHER_XTS &&
  82                             ctx_p->cipher_mode != DRV_CIPHER_ESSIV &&
  83                             ctx_p->cipher_mode != DRV_CIPHER_BITLOCKER)
  84                                 return 0;
  85                         break;
  86                 case CC_AES_256_BIT_KEY_SIZE:
  87                         return 0;
  88                 case (CC_AES_192_BIT_KEY_SIZE * 2):
  89                 case (CC_AES_256_BIT_KEY_SIZE * 2):
  90                         if (ctx_p->cipher_mode == DRV_CIPHER_XTS ||
  91                             ctx_p->cipher_mode == DRV_CIPHER_ESSIV ||
  92                             ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)
  93                                 return 0;
  94                         break;
  95                 default:
  96                         break;
  97                 }
  98                 break;
  99         case S_DIN_to_DES:
 100                 if (size == DES3_EDE_KEY_SIZE || size == DES_KEY_SIZE)
 101                         return 0;
 102                 break;
 103         case S_DIN_to_SM4:
 104                 if (size == SM4_KEY_SIZE)
 105                         return 0;
 106         default:
 107                 break;
 108         }
 109         return -EINVAL;
 110 }
 111
 112 static int validate_data_size(struct cc_cipher_ctx *ctx_p,
 113                               unsigned int size)
 114 {
 115         switch (ctx_p->flow_mode) {
 116         case S_DIN_to_AES:
 117                 switch (ctx_p->cipher_mode) {
 118                 case DRV_CIPHER_XTS:
 119                         if (size >= AES_BLOCK_SIZE &&
 120                             IS_ALIGNED(size, AES_BLOCK_SIZE))
 121                                 return 0;
 122                         break;
 123                 case DRV_CIPHER_CBC_CTS:
 124                         if (size >= AES_BLOCK_SIZE)
 125                                 return 0;
 126                         break;
 127                 case DRV_CIPHER_OFB:
 128                 case DRV_CIPHER_CTR:
 129                                 return 0;
 130                 case DRV_CIPHER_ECB:
 131                 case DRV_CIPHER_CBC:
 132                 case DRV_CIPHER_ESSIV:
 133                 case DRV_CIPHER_BITLOCKER:
 134                         if (IS_ALIGNED(size, AES_BLOCK_SIZE))
 135                                 return 0;
 136                         break;
 137                 default:
 138                         break;
 139                 }
 140                 break;
 141         case S_DIN_to_DES:
 142                 if (IS_ALIGNED(size, DES_BLOCK_SIZE))
 143                         return 0;
 144                 break;
 145         case S_DIN_to_SM4:
 146                 switch (ctx_p->cipher_mode) {
 147                 case DRV_CIPHER_CTR:
 148                         return 0;
 149                 case DRV_CIPHER_ECB:
 150                 case DRV_CIPHER_CBC:
 151                         if (IS_ALIGNED(size, SM4_BLOCK_SIZE))
 152                                 return 0;
 153                 default:
 154                         break;
 155                 }
 156         default:
 157                 break;
 158         }
 159         return -EINVAL;
 160 }
 161
 162 static int cc_cipher_init(struct crypto_tfm *tfm)
 163 {
 164         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 165         struct cc_crypto_alg *cc_alg =
 166                         container_of(tfm->__crt_alg, struct cc_crypto_alg,
 167                                      skcipher_alg.base);
 168         struct device *dev = drvdata_to_dev(cc_alg->drvdata);
 169         unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
 170         int rc = 0;
 171
 172         dev_dbg(dev, "Initializing context @%p for %s\n", ctx_p,
 173                 crypto_tfm_alg_name(tfm));
 174
 175         crypto_skcipher_set_reqsize(__crypto_skcipher_cast(tfm),
 176                                     sizeof(struct cipher_req_ctx));
 177
 178         ctx_p->cipher_mode = cc_alg->cipher_mode;
 179         ctx_p->flow_mode = cc_alg->flow_mode;
 180         ctx_p->drvdata = cc_alg->drvdata;
 181
 182         /* Allocate key buffer, cache line aligned */
 183         ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL);
 184         if (!ctx_p->user.key)
 185                 return -ENOMEM;
 186
 187         dev_dbg(dev, "Allocated key buffer in context. key=@%p\n",
 188                 ctx_p->user.key);
 189
 190         /* Map key buffer */
 191         ctx_p->user.key_dma_addr = dma_map_single(dev, (void *)ctx_p->user.key,
 192                                                   max_key_buf_size,
 193                                                   DMA_TO_DEVICE);
 194         if (dma_mapping_error(dev, ctx_p->user.key_dma_addr)) {
 195                 dev_err(dev, "Mapping Key %u B at va=%pK for DMA failed\n",
 196                         max_key_buf_size, ctx_p->user.key);
 197                 return -ENOMEM;
 198         }
 199         dev_dbg(dev, "Mapped key %u B at va=%pK to dma=%pad\n",
 200                 max_key_buf_size, ctx_p->user.key, &ctx_p->user.key_dma_addr);
 201
 202         if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
 203                 /* Alloc hash tfm for essiv */
 204                 ctx_p->shash_tfm = crypto_alloc_shash("sha256-generic", 0, 0);
 205                 if (IS_ERR(ctx_p->shash_tfm)) {
 206                         dev_err(dev, "Error allocating hash tfm for ESSIV.\n");
 207                         return PTR_ERR(ctx_p->shash_tfm);
 208                 }
 209         }
 210
 211         return rc;
 212 }
 213
 214 static void cc_cipher_exit(struct crypto_tfm *tfm)
 215 {
 216         struct crypto_alg *alg = tfm->__crt_alg;
 217         struct cc_crypto_alg *cc_alg =
 218                         container_of(alg, struct cc_crypto_alg,
 219                                      skcipher_alg.base);
 220         unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
 221         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 222         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 223
 224         dev_dbg(dev, "Clearing context @%p for %s\n",
 225                 crypto_tfm_ctx(tfm), crypto_tfm_alg_name(tfm));
 226
 227         if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
 228                 /* Free hash tfm for essiv */
 229                 crypto_free_shash(ctx_p->shash_tfm);
 230                 ctx_p->shash_tfm = NULL;
 231         }
 232
 233         /* Unmap key buffer */
 234         dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size,
 235                          DMA_TO_DEVICE);
 236         dev_dbg(dev, "Unmapped key buffer key_dma_addr=%pad\n",
 237                 &ctx_p->user.key_dma_addr);
 238
 239         /* Free key buffer in context */
 240         kzfree(ctx_p->user.key);
 241         dev_dbg(dev, "Free key buffer in context. key=@%p\n", ctx_p->user.key);
 242 }
 243
 244 struct tdes_keys {
 245         u8      key1[DES_KEY_SIZE];
 246         u8      key2[DES_KEY_SIZE];
 247         u8      key3[DES_KEY_SIZE];
 248 };
 249
 250 static enum cc_hw_crypto_key cc_slot_to_hw_key(u8 slot_num)
 251 {
 252         switch (slot_num) {
 253         case 0:
 254                 return KFDE0_KEY;
 255         case 1:
 256                 return KFDE1_KEY;
 257         case 2:
 258                 return KFDE2_KEY;
 259         case 3:
 260                 return KFDE3_KEY;
 261         }
 262         return END_OF_KEYS;
 263 }
 264
 265 static u8 cc_slot_to_cpp_key(u8 slot_num)
 266 {
 267         return (slot_num - CC_FIRST_CPP_KEY_SLOT);
 268 }
 269
 270 static inline enum cc_key_type cc_slot_to_key_type(u8 slot_num)
 271 {
 272         if (slot_num >= CC_FIRST_HW_KEY_SLOT && slot_num <= CC_LAST_HW_KEY_SLOT)
 273                 return CC_HW_PROTECTED_KEY;
 274         else if (slot_num >=  CC_FIRST_CPP_KEY_SLOT &&
 275                  slot_num <=  CC_LAST_CPP_KEY_SLOT)
 276                 return CC_POLICY_PROTECTED_KEY;
 277         else
 278                 return CC_INVALID_PROTECTED_KEY;
 279 }
 280
 281 static int cc_cipher_sethkey(struct crypto_skcipher *sktfm, const u8 *key,
 282                              unsigned int keylen)
 283 {
 284         struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
 285         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 286         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 287         struct cc_hkey_info hki;
 288
 289         dev_dbg(dev, "Setting HW key in context @%p for %s. keylen=%u\n",
 290                 ctx_p, crypto_tfm_alg_name(tfm), keylen);
 291         dump_byte_array("key", (u8 *)key, keylen);
 292
 293         /* STAT_PHASE_0: Init and sanity checks */
 294
 295         /* This check the size of the protected key token */
 296         if (keylen != sizeof(hki)) {
 297                 dev_err(dev, "Unsupported protected key size %d.\n", keylen);
 298                 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
 299                 return -EINVAL;
 300         }
 301
 302         memcpy(&hki, key, keylen);
 303
 304         /* The real key len for crypto op is the size of the HW key
 305          * referenced by the HW key slot, not the hardware key token
 306          */
 307         keylen = hki.keylen;
 308
 309         if (validate_keys_sizes(ctx_p, keylen)) {
 310                 dev_err(dev, "Unsupported key size %d.\n", keylen);
 311                 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
 312                 return -EINVAL;
 313         }
 314
 315         ctx_p->keylen = keylen;
 316
 317         switch (cc_slot_to_key_type(hki.hw_key1)) {
 318         case CC_HW_PROTECTED_KEY:
 319                 if (ctx_p->flow_mode == S_DIN_to_SM4) {
 320                         dev_err(dev, "Only AES HW protected keys are supported\n");
 321                         return -EINVAL;
 322                 }
 323
 324                 ctx_p->hw.key1_slot = cc_slot_to_hw_key(hki.hw_key1);
 325                 if (ctx_p->hw.key1_slot == END_OF_KEYS) {
 326                         dev_err(dev, "Unsupported hw key1 number (%d)\n",
 327                                 hki.hw_key1);
 328                         return -EINVAL;
 329                 }
 330
 331                 if (ctx_p->cipher_mode == DRV_CIPHER_XTS ||
 332                     ctx_p->cipher_mode == DRV_CIPHER_ESSIV ||
 333                     ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER) {
 334                         if (hki.hw_key1 == hki.hw_key2) {
 335                                 dev_err(dev, "Illegal hw key numbers (%d,%d)\n",
 336                                         hki.hw_key1, hki.hw_key2);
 337                                 return -EINVAL;
 338                         }
 339
 340                         ctx_p->hw.key2_slot = cc_slot_to_hw_key(hki.hw_key2);
 341                         if (ctx_p->hw.key2_slot == END_OF_KEYS) {
 342                                 dev_err(dev, "Unsupported hw key2 number (%d)\n",
 343                                         hki.hw_key2);
 344                                 return -EINVAL;
 345                         }
 346                 }
 347
 348                 ctx_p->key_type = CC_HW_PROTECTED_KEY;
 349                 dev_dbg(dev, "HW protected key  %d/%d set\n.",
 350                         ctx_p->hw.key1_slot, ctx_p->hw.key2_slot);
 351                 break;
 352
 353         case CC_POLICY_PROTECTED_KEY:
 354                 if (ctx_p->drvdata->hw_rev < CC_HW_REV_713) {
 355                         dev_err(dev, "CPP keys not supported in this hardware revision.\n");
 356                         return -EINVAL;
 357                 }
 358
 359                 if (ctx_p->cipher_mode != DRV_CIPHER_CBC &&
 360                     ctx_p->cipher_mode != DRV_CIPHER_CTR) {
 361                         dev_err(dev, "CPP keys only supported in CBC or CTR modes.\n");
 362                         return -EINVAL;
 363                 }
 364
 365                 ctx_p->cpp.slot = cc_slot_to_cpp_key(hki.hw_key1);
 366                 if (ctx_p->flow_mode == S_DIN_to_AES)
 367                         ctx_p->cpp.alg = CC_CPP_AES;
 368                 else /* Must be SM4 since due to sethkey registration */
 369                         ctx_p->cpp.alg = CC_CPP_SM4;
 370                 ctx_p->key_type = CC_POLICY_PROTECTED_KEY;
 371                 dev_dbg(dev, "policy protedcted key alg: %d slot: %d.\n",
 372                         ctx_p->cpp.alg, ctx_p->cpp.slot);
 373                 break;
 374
 375         default:
 376                 dev_err(dev, "Unsupported protected key (%d)\n", hki.hw_key1);
 377                 return -EINVAL;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int cc_cipher_setkey(struct crypto_skcipher *sktfm, const u8 *key,
 384                             unsigned int keylen)
 385 {
 386         struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
 387         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 388         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 389         struct cc_crypto_alg *cc_alg =
 390                         container_of(tfm->__crt_alg, struct cc_crypto_alg,
 391                                      skcipher_alg.base);
 392         unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
 393
 394         dev_dbg(dev, "Setting key in context @%p for %s. keylen=%u\n",
 395                 ctx_p, crypto_tfm_alg_name(tfm), keylen);
 396         dump_byte_array("key", (u8 *)key, keylen);
 397
 398         /* STAT_PHASE_0: Init and sanity checks */
 399
 400         if (validate_keys_sizes(ctx_p, keylen)) {
 401                 dev_err(dev, "Unsupported key size %d.\n", keylen);
 402                 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
 403                 return -EINVAL;
 404         }
 405
 406         ctx_p->key_type = CC_UNPROTECTED_KEY;
 407
 408         /*
 409          * Verify DES weak keys
 410          * Note that we're dropping the expanded key since the
 411          * HW does the expansion on its own.
 412          */
 413         if (ctx_p->flow_mode == S_DIN_to_DES) {
 414                 u32 tmp[DES3_EDE_EXPKEY_WORDS];
 415                 if (keylen == DES3_EDE_KEY_SIZE &&
 416                     __des3_ede_setkey(tmp, &tfm->crt_flags, key,
 417                                       DES3_EDE_KEY_SIZE)) {
 418                         dev_dbg(dev, "weak 3DES key");
 419                         return -EINVAL;
 420                 } else if (!des_ekey(tmp, key) &&
 421                            (crypto_tfm_get_flags(tfm) &
 422                             CRYPTO_TFM_REQ_FORBID_WEAK_KEYS)) {
 423                         tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
 424                         dev_dbg(dev, "weak DES key");
 425                         return -EINVAL;
 426                 }
 427         }
 428
 429         if (ctx_p->cipher_mode == DRV_CIPHER_XTS &&
 430             xts_check_key(tfm, key, keylen)) {
 431                 dev_dbg(dev, "weak XTS key");
 432                 return -EINVAL;
 433         }
 434
 435         /* STAT_PHASE_1: Copy key to ctx */
 436         dma_sync_single_for_cpu(dev, ctx_p->user.key_dma_addr,
 437                                 max_key_buf_size, DMA_TO_DEVICE);
 438
 439         memcpy(ctx_p->user.key, key, keylen);
 440         if (keylen == 24)
 441                 memset(ctx_p->user.key + 24, 0, CC_AES_KEY_SIZE_MAX - 24);
 442
 443         if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
 444                 /* sha256 for key2 - use sw implementation */
 445                 int key_len = keylen >> 1;
 446                 int err;
 447
 448                 SHASH_DESC_ON_STACK(desc, ctx_p->shash_tfm);
 449
 450                 desc->tfm = ctx_p->shash_tfm;
 451
 452                 err = crypto_shash_digest(desc, ctx_p->user.key, key_len,
 453                                           ctx_p->user.key + key_len);
 454                 if (err) {
 455                         dev_err(dev, "Failed to hash ESSIV key.\n");
 456                         return err;
 457                 }
 458         }
 459         dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr,
 460                                    max_key_buf_size, DMA_TO_DEVICE);
 461         ctx_p->keylen = keylen;
 462
 463         dev_dbg(dev, "return safely");
 464         return 0;
 465 }
 466
 467 static int cc_out_setup_mode(struct cc_cipher_ctx *ctx_p)
 468 {
 469         switch (ctx_p->flow_mode) {
 470         case S_DIN_to_AES:
 471                 return S_AES_to_DOUT;
 472         case S_DIN_to_DES:
 473                 return S_DES_to_DOUT;
 474         case S_DIN_to_SM4:
 475                 return S_SM4_to_DOUT;
 476         default:
 477                 return ctx_p->flow_mode;
 478         }
 479 }
 480
 481 static void cc_setup_readiv_desc(struct crypto_tfm *tfm,
 482                                  struct cipher_req_ctx *req_ctx,
 483                                  unsigned int ivsize, struct cc_hw_desc desc[],
 484                                  unsigned int *seq_size)
 485 {
 486         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 487         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 488         int cipher_mode = ctx_p->cipher_mode;
 489         int flow_mode = cc_out_setup_mode(ctx_p);
 490         int direction = req_ctx->gen_ctx.op_type;
 491         dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr;
 492
 493         if (ctx_p->key_type == CC_POLICY_PROTECTED_KEY)
 494                 return;
 495
 496         switch (cipher_mode) {
 497         case DRV_CIPHER_ECB:
 498                 break;
 499         case DRV_CIPHER_CBC:
 500         case DRV_CIPHER_CBC_CTS:
 501         case DRV_CIPHER_CTR:
 502         case DRV_CIPHER_OFB:
 503                 /* Read next IV */
 504                 hw_desc_init(&desc[*seq_size]);
 505                 set_dout_dlli(&desc[*seq_size], iv_dma_addr, ivsize, NS_BIT, 1);
 506                 set_cipher_config0(&desc[*seq_size], direction);
 507                 set_flow_mode(&desc[*seq_size], flow_mode);
 508                 set_cipher_mode(&desc[*seq_size], cipher_mode);
 509                 if (cipher_mode == DRV_CIPHER_CTR ||
 510                     cipher_mode == DRV_CIPHER_OFB) {
 511                         set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);
 512                 } else {
 513                         set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE0);
 514                 }
 515                 set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
 516                 (*seq_size)++;
 517                 break;
 518         case DRV_CIPHER_XTS:
 519         case DRV_CIPHER_ESSIV:
 520         case DRV_CIPHER_BITLOCKER:
 521                 /*  IV */
 522                 hw_desc_init(&desc[*seq_size]);
 523                 set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);
 524                 set_cipher_mode(&desc[*seq_size], cipher_mode);
 525                 set_cipher_config0(&desc[*seq_size], direction);
 526                 set_flow_mode(&desc[*seq_size], flow_mode);
 527                 set_dout_dlli(&desc[*seq_size], iv_dma_addr, CC_AES_BLOCK_SIZE,
 528                              NS_BIT, 1);
 529                 set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
 530                 (*seq_size)++;
 531                 break;
 532         default:
 533                 dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
 534         }
 535 }
 536
 537 static void cc_setup_state_desc(struct crypto_tfm *tfm,
 538                                  struct cipher_req_ctx *req_ctx,
 539                                  unsigned int ivsize, unsigned int nbytes,
 540                                  struct cc_hw_desc desc[],
 541                                  unsigned int *seq_size)
 542 {
 543         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 544         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 545         int cipher_mode = ctx_p->cipher_mode;
 546         int flow_mode = ctx_p->flow_mode;
 547         int direction = req_ctx->gen_ctx.op_type;
 548         dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr;
 549         unsigned int key_len = ctx_p->keylen;
 550         dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr;
 551         unsigned int du_size = nbytes;
 552
 553         struct cc_crypto_alg *cc_alg =
 554                 container_of(tfm->__crt_alg, struct cc_crypto_alg,
 555                              skcipher_alg.base);
 556
 557         if (cc_alg->data_unit)
 558                 du_size = cc_alg->data_unit;
 559
 560         switch (cipher_mode) {
 561         case DRV_CIPHER_ECB:
 562                 break;
 563         case DRV_CIPHER_CBC:
 564         case DRV_CIPHER_CBC_CTS:
 565         case DRV_CIPHER_CTR:
 566         case DRV_CIPHER_OFB:
 567                 /* Load IV */
 568                 hw_desc_init(&desc[*seq_size]);
 569                 set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize,
 570                              NS_BIT);
 571                 set_cipher_config0(&desc[*seq_size], direction);
 572                 set_flow_mode(&desc[*seq_size], flow_mode);
 573                 set_cipher_mode(&desc[*seq_size], cipher_mode);
 574                 if (cipher_mode == DRV_CIPHER_CTR ||
 575                     cipher_mode == DRV_CIPHER_OFB) {
 576                         set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
 577                 } else {
 578                         set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);
 579                 }
 580                 (*seq_size)++;
 581                 break;
 582         case DRV_CIPHER_XTS:
 583         case DRV_CIPHER_ESSIV:
 584         case DRV_CIPHER_BITLOCKER:
 585                 /* load XEX key */
 586                 hw_desc_init(&desc[*seq_size]);
 587                 set_cipher_mode(&desc[*seq_size], cipher_mode);
 588                 set_cipher_config0(&desc[*seq_size], direction);
 589                 if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
 590                         set_hw_crypto_key(&desc[*seq_size],
 591                                           ctx_p->hw.key2_slot);
 592                 } else {
 593                         set_din_type(&desc[*seq_size], DMA_DLLI,
 594                                      (key_dma_addr + (key_len / 2)),
 595                                      (key_len / 2), NS_BIT);
 596                 }
 597                 set_xex_data_unit_size(&desc[*seq_size], du_size);
 598                 set_flow_mode(&desc[*seq_size], S_DIN_to_AES2);
 599                 set_key_size_aes(&desc[*seq_size], (key_len / 2));
 600                 set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY);
 601                 (*seq_size)++;
 602
 603                 /* Load IV */
 604                 hw_desc_init(&desc[*seq_size]);
 605                 set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
 606                 set_cipher_mode(&desc[*seq_size], cipher_mode);
 607                 set_cipher_config0(&desc[*seq_size], direction);
 608                 set_key_size_aes(&desc[*seq_size], (key_len / 2));
 609                 set_flow_mode(&desc[*seq_size], flow_mode);
 610                 set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr,
 611                              CC_AES_BLOCK_SIZE, NS_BIT);
 612                 (*seq_size)++;
 613                 break;
 614         default:
 615                 dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
 616         }
 617 }
 618
 619 static int cc_out_flow_mode(struct cc_cipher_ctx *ctx_p)
 620 {
 621         switch (ctx_p->flow_mode) {
 622         case S_DIN_to_AES:
 623                 return DIN_AES_DOUT;
 624         case S_DIN_to_DES:
 625                 return DIN_DES_DOUT;
 626         case S_DIN_to_SM4:
 627                 return DIN_SM4_DOUT;
 628         default:
 629                 return ctx_p->flow_mode;
 630         }
 631 }
 632
 633 static void cc_setup_key_desc(struct crypto_tfm *tfm,
 634                               struct cipher_req_ctx *req_ctx,
 635                               unsigned int nbytes, struct cc_hw_desc desc[],
 636                               unsigned int *seq_size)
 637 {
 638         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 639         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 640         int cipher_mode = ctx_p->cipher_mode;
 641         int flow_mode = ctx_p->flow_mode;
 642         int direction = req_ctx->gen_ctx.op_type;
 643         dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr;
 644         unsigned int key_len = ctx_p->keylen;
 645         unsigned int du_size = nbytes;
 646         unsigned int din_size;
 647
 648         struct cc_crypto_alg *cc_alg =
 649                 container_of(tfm->__crt_alg, struct cc_crypto_alg,
 650                              skcipher_alg.base);
 651
 652         if (cc_alg->data_unit)
 653                 du_size = cc_alg->data_unit;
 654
 655         switch (cipher_mode) {
 656         case DRV_CIPHER_CBC:
 657         case DRV_CIPHER_CBC_CTS:
 658         case DRV_CIPHER_CTR:
 659         case DRV_CIPHER_OFB:
 660         case DRV_CIPHER_ECB:
 661                 /* Load key */
 662                 hw_desc_init(&desc[*seq_size]);
 663                 set_cipher_mode(&desc[*seq_size], cipher_mode);
 664                 set_cipher_config0(&desc[*seq_size], direction);
 665
 666                 if (cc_key_type(tfm) == CC_POLICY_PROTECTED_KEY) {
 667                         /* We use the AES key size coding for all CPP algs */
 668                         set_key_size_aes(&desc[*seq_size], key_len);
 669                         set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.slot);
 670                         flow_mode = cc_out_flow_mode(ctx_p);
 671                 } else {
 672                         if (flow_mode == S_DIN_to_AES) {
 673                                 if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
 674                                         set_hw_crypto_key(&desc[*seq_size],
 675                                                           ctx_p->hw.key1_slot);
 676                                 } else {
 677                                         /* CC_POLICY_UNPROTECTED_KEY
 678                                          * Invalid keys are filtered out in
 679                                          * sethkey()
 680                                          */
 681                                         din_size = (key_len == 24) ?
 682                                                 AES_MAX_KEY_SIZE : key_len;
 683
 684                                         set_din_type(&desc[*seq_size], DMA_DLLI,
 685                                                      key_dma_addr, din_size,
 686                                                      NS_BIT);
 687                                 }
 688                                 set_key_size_aes(&desc[*seq_size], key_len);
 689                         } else {
 690                                 /*des*/
 691                                 set_din_type(&desc[*seq_size], DMA_DLLI,
 692                                              key_dma_addr, key_len, NS_BIT);
 693                                 set_key_size_des(&desc[*seq_size], key_len);
 694                         }
 695                         set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
 696                 }
 697                 set_flow_mode(&desc[*seq_size], flow_mode);
 698                 (*seq_size)++;
 699                 break;
 700         case DRV_CIPHER_XTS:
 701         case DRV_CIPHER_ESSIV:
 702         case DRV_CIPHER_BITLOCKER:
 703                 /* Load AES key */
 704                 hw_desc_init(&desc[*seq_size]);
 705                 set_cipher_mode(&desc[*seq_size], cipher_mode);
 706                 set_cipher_config0(&desc[*seq_size], direction);
 707                 if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
 708                         set_hw_crypto_key(&desc[*seq_size],
 709                                           ctx_p->hw.key1_slot);
 710                 } else {
 711                         set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,
 712                                      (key_len / 2), NS_BIT);
 713                 }
 714                 set_key_size_aes(&desc[*seq_size], (key_len / 2));
 715                 set_flow_mode(&desc[*seq_size], flow_mode);
 716                 set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
 717                 (*seq_size)++;
 718                 break;
 719         default:
 720                 dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
 721         }
 722 }
 723
 724 static void cc_setup_mlli_desc(struct crypto_tfm *tfm,
 725                                struct cipher_req_ctx *req_ctx,
 726                                struct scatterlist *dst, struct scatterlist *src,
 727                                unsigned int nbytes, void *areq,
 728                                struct cc_hw_desc desc[], unsigned int *seq_size)
 729 {
 730         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 731         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 732
 733         if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
 734                 /* bypass */
 735                 dev_dbg(dev, " bypass params addr %pad length 0x%X addr 0x%08X\n",
 736                         &req_ctx->mlli_params.mlli_dma_addr,
 737                         req_ctx->mlli_params.mlli_len,
 738                         (unsigned int)ctx_p->drvdata->mlli_sram_addr);
 739                 hw_desc_init(&desc[*seq_size]);
 740                 set_din_type(&desc[*seq_size], DMA_DLLI,
 741                              req_ctx->mlli_params.mlli_dma_addr,
 742                              req_ctx->mlli_params.mlli_len, NS_BIT);
 743                 set_dout_sram(&desc[*seq_size],
 744                               ctx_p->drvdata->mlli_sram_addr,
 745                               req_ctx->mlli_params.mlli_len);
 746                 set_flow_mode(&desc[*seq_size], BYPASS);
 747                 (*seq_size)++;
 748         }
 749 }
 750
 751 static void cc_setup_flow_desc(struct crypto_tfm *tfm,
 752                                struct cipher_req_ctx *req_ctx,
 753                                struct scatterlist *dst, struct scatterlist *src,
 754                                unsigned int nbytes, struct cc_hw_desc desc[],
 755                                unsigned int *seq_size)
 756 {
 757         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 758         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 759         unsigned int flow_mode = cc_out_flow_mode(ctx_p);
 760         bool last_desc = (ctx_p->key_type == CC_POLICY_PROTECTED_KEY ||
 761                           ctx_p->cipher_mode == DRV_CIPHER_ECB);
 762
 763         /* Process */
 764         if (req_ctx->dma_buf_type == CC_DMA_BUF_DLLI) {
 765                 dev_dbg(dev, " data params addr %pad length 0x%X\n",
 766                         &sg_dma_address(src), nbytes);
 767                 dev_dbg(dev, " data params addr %pad length 0x%X\n",
 768                         &sg_dma_address(dst), nbytes);
 769                 hw_desc_init(&desc[*seq_size]);
 770                 set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),
 771                              nbytes, NS_BIT);
 772                 set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),
 773                               nbytes, NS_BIT, (!last_desc ? 0 : 1));
 774                 if (last_desc)
 775                         set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
 776
 777                 set_flow_mode(&desc[*seq_size], flow_mode);
 778                 (*seq_size)++;
 779         } else {
 780                 hw_desc_init(&desc[*seq_size]);
 781                 set_din_type(&desc[*seq_size], DMA_MLLI,
 782                              ctx_p->drvdata->mlli_sram_addr,
 783                              req_ctx->in_mlli_nents, NS_BIT);
 784                 if (req_ctx->out_nents == 0) {
 785                         dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",
 786                                 (unsigned int)ctx_p->drvdata->mlli_sram_addr,
 787                                 (unsigned int)ctx_p->drvdata->mlli_sram_addr);
 788                         set_dout_mlli(&desc[*seq_size],
 789                                       ctx_p->drvdata->mlli_sram_addr,
 790                                       req_ctx->in_mlli_nents, NS_BIT,
 791                                       (!last_desc ? 0 : 1));
 792                 } else {
 793                         dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",
 794                                 (unsigned int)ctx_p->drvdata->mlli_sram_addr,
 795                                 (unsigned int)ctx_p->drvdata->mlli_sram_addr +
 796                                 (u32)LLI_ENTRY_BYTE_SIZE * req_ctx->in_nents);
 797                         set_dout_mlli(&desc[*seq_size],
 798                                       (ctx_p->drvdata->mlli_sram_addr +
 799                                        (LLI_ENTRY_BYTE_SIZE *
 800                                         req_ctx->in_mlli_nents)),
 801                                       req_ctx->out_mlli_nents, NS_BIT,
 802                                       (!last_desc ? 0 : 1));
 803                 }
 804                 if (last_desc)
 805                         set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
 806
 807                 set_flow_mode(&desc[*seq_size], flow_mode);
 808                 (*seq_size)++;
 809         }
 810 }
 811
 812 static void cc_cipher_complete(struct device *dev, void *cc_req, int err)
 813 {
 814         struct skcipher_request *req = (struct skcipher_request *)cc_req;
 815         struct scatterlist *dst = req->dst;
 816         struct scatterlist *src = req->src;
 817         struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
 818         struct crypto_skcipher *sk_tfm = crypto_skcipher_reqtfm(req);
 819         unsigned int ivsize = crypto_skcipher_ivsize(sk_tfm);
 820
 821         if (err != -EINPROGRESS) {
 822                 /* Not a BACKLOG notification */
 823                 cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
 824                 memcpy(req->iv, req_ctx->iv, ivsize);
 825                 kzfree(req_ctx->iv);
 826         }
 827
 828         skcipher_request_complete(req, err);
 829 }
 830
 831 static int cc_cipher_process(struct skcipher_request *req,
 832                              enum drv_crypto_direction direction)
 833 {
 834         struct crypto_skcipher *sk_tfm = crypto_skcipher_reqtfm(req);
 835         struct crypto_tfm *tfm = crypto_skcipher_tfm(sk_tfm);
 836         struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
 837         unsigned int ivsize = crypto_skcipher_ivsize(sk_tfm);
 838         struct scatterlist *dst = req->dst;
 839         struct scatterlist *src = req->src;
 840         unsigned int nbytes = req->cryptlen;
 841         void *iv = req->iv;
 842         struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 843         struct device *dev = drvdata_to_dev(ctx_p->drvdata);
 844         struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN];
 845         struct cc_crypto_req cc_req = {};
 846         int rc;
 847         unsigned int seq_len = 0;
 848         gfp_t flags = cc_gfp_flags(&req->base);
 849
 850         dev_dbg(dev, "%s req=%p iv=%p nbytes=%d\n",
 851                 ((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
 852                 "Encrypt" : "Decrypt"), req, iv, nbytes);
 853
 854         /* STAT_PHASE_0: Init and sanity checks */
 855
 856         /* TODO: check data length according to mode */
 857         if (validate_data_size(ctx_p, nbytes)) {
 858                 dev_err(dev, "Unsupported data size %d.\n", nbytes);
 859                 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_BLOCK_LEN);
 860                 rc = -EINVAL;
 861                 goto exit_process;
 862         }
 863         if (nbytes == 0) {
 864                 /* No data to process is valid */
 865                 rc = 0;
 866                 goto exit_process;
 867         }
 868
 869         /* The IV we are handed may be allocted from the stack so
 870          * we must copy it to a DMAable buffer before use.
 871          */
 872         req_ctx->iv = kmemdup(iv, ivsize, flags);
 873         if (!req_ctx->iv) {
 874                 rc = -ENOMEM;
 875                 goto exit_process;
 876         }
 877
 878         /* Setup request structure */
 879         cc_req.user_cb = (void *)cc_cipher_complete;
 880         cc_req.user_arg = (void *)req;
 881
 882         /* Setup CPP operation details */
 883         if (ctx_p->key_type == CC_POLICY_PROTECTED_KEY) {
 884                 cc_req.cpp.is_cpp = true;
 885                 cc_req.cpp.alg = ctx_p->cpp.alg;
 886                 cc_req.cpp.slot = ctx_p->cpp.slot;
 887         }
 888
 889         /* Setup request context */
 890         req_ctx->gen_ctx.op_type = direction;
 891
 892         /* STAT_PHASE_1: Map buffers */
 893
 894         rc = cc_map_cipher_request(ctx_p->drvdata, req_ctx, ivsize, nbytes,
 895                                       req_ctx->iv, src, dst, flags);
 896         if (rc) {
 897                 dev_err(dev, "map_request() failed\n");
 898                 goto exit_process;
 899         }
 900
 901         /* STAT_PHASE_2: Create sequence */
 902
 903         /* Setup IV and XEX key used */
 904         cc_setup_state_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len);
 905         /* Setup MLLI line, if needed */
 906         cc_setup_mlli_desc(tfm, req_ctx, dst, src, nbytes, req, desc, &seq_len);
 907         /* Setup key */
 908         cc_setup_key_desc(tfm, req_ctx, nbytes, desc, &seq_len);
 909         /* Data processing */
 910         cc_setup_flow_desc(tfm, req_ctx, dst, src, nbytes, desc, &seq_len);
 911         /* Read next IV */
 912         cc_setup_readiv_desc(tfm, req_ctx, ivsize, desc, &seq_len);
 913
 914         /* STAT_PHASE_3: Lock HW and push sequence */
 915
 916         rc = cc_send_request(ctx_p->drvdata, &cc_req, desc, seq_len,
 917                              &req->base);
 918         if (rc != -EINPROGRESS && rc != -EBUSY) {
 919                 /* Failed to send the request or request completed
 920                  * synchronously
 921                  */
 922                 cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
 923         }
 924
 925 exit_process:
 926         if (rc != -EINPROGRESS && rc != -EBUSY) {
 927                 kzfree(req_ctx->iv);
 928         }
 929
 930         return rc;
 931 }
 932
 933 static int cc_cipher_encrypt(struct skcipher_request *req)
 934 {
 935         struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
 936
 937         memset(req_ctx, 0, sizeof(*req_ctx));
 938
 939         return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_ENCRYPT);
 940 }
 941
 942 static int cc_cipher_decrypt(struct skcipher_request *req)
 943 {
 944         struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
 945
 946         memset(req_ctx, 0, sizeof(*req_ctx));
 947
 948         return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_DECRYPT);
 949 }
 950
 951 /* Block cipher alg */
 952 static const struct cc_alg_template skcipher_algs[] = {
 953         {
 954                 .name = "xts(paes)",
 955                 .driver_name = "xts-paes-ccree",
 956                 .blocksize = AES_BLOCK_SIZE,
 957                 .template_skcipher = {
 958                         .setkey = cc_cipher_sethkey,
 959                         .encrypt = cc_cipher_encrypt,
 960                         .decrypt = cc_cipher_decrypt,
 961                         .min_keysize = CC_HW_KEY_SIZE,
 962                         .max_keysize = CC_HW_KEY_SIZE,
 963                         .ivsize = AES_BLOCK_SIZE,
 964                         },
 965                 .cipher_mode = DRV_CIPHER_XTS,
 966                 .flow_mode = S_DIN_to_AES,
 967                 .min_hw_rev = CC_HW_REV_630,
 968                 .std_body = CC_STD_NIST,
 969                 .sec_func = true,
 970         },
 971         {
 972                 .name = "xts512(paes)",
 973                 .driver_name = "xts-paes-du512-ccree",
 974                 .blocksize = AES_BLOCK_SIZE,
 975                 .template_skcipher = {
 976                         .setkey = cc_cipher_sethkey,
 977                         .encrypt = cc_cipher_encrypt,
 978                         .decrypt = cc_cipher_decrypt,
 979                         .min_keysize = CC_HW_KEY_SIZE,
 980                         .max_keysize = CC_HW_KEY_SIZE,
 981                         .ivsize = AES_BLOCK_SIZE,
 982                         },
 983                 .cipher_mode = DRV_CIPHER_XTS,
 984                 .flow_mode = S_DIN_to_AES,
 985                 .data_unit = 512,
 986                 .min_hw_rev = CC_HW_REV_712,
 987                 .std_body = CC_STD_NIST,
 988                 .sec_func = true,
 989         },
 990         {
 991                 .name = "xts4096(paes)",
 992                 .driver_name = "xts-paes-du4096-ccree",
 993                 .blocksize = AES_BLOCK_SIZE,
 994                 .template_skcipher = {
 995                         .setkey = cc_cipher_sethkey,
 996                         .encrypt = cc_cipher_encrypt,
 997                         .decrypt = cc_cipher_decrypt,
 998                         .min_keysize = CC_HW_KEY_SIZE,
 999                         .max_keysize = CC_HW_KEY_SIZE,
1000                         .ivsize = AES_BLOCK_SIZE,
1001                         },
1002                 .cipher_mode = DRV_CIPHER_XTS,
1003                 .flow_mode = S_DIN_to_AES,
1004                 .data_unit = 4096,
1005                 .min_hw_rev = CC_HW_REV_712,
1006                 .std_body = CC_STD_NIST,
1007                 .sec_func = true,
1008         },
1009         {
1010                 .name = "essiv(paes)",
1011                 .driver_name = "essiv-paes-ccree",
1012                 .blocksize = AES_BLOCK_SIZE,
1013                 .template_skcipher = {
1014                         .setkey = cc_cipher_sethkey,
1015                         .encrypt = cc_cipher_encrypt,
1016                         .decrypt = cc_cipher_decrypt,
1017                         .min_keysize = CC_HW_KEY_SIZE,
1018                         .max_keysize = CC_HW_KEY_SIZE,
1019                         .ivsize = AES_BLOCK_SIZE,
1020                         },
1021                 .cipher_mode = DRV_CIPHER_ESSIV,
1022                 .flow_mode = S_DIN_to_AES,
1023                 .min_hw_rev = CC_HW_REV_712,
1024                 .std_body = CC_STD_NIST,
1025                 .sec_func = true,
1026         },
1027         {
1028                 .name = "essiv512(paes)",
1029                 .driver_name = "essiv-paes-du512-ccree",
1030                 .blocksize = AES_BLOCK_SIZE,
1031                 .template_skcipher = {
1032                         .setkey = cc_cipher_sethkey,
1033                         .encrypt = cc_cipher_encrypt,
1034                         .decrypt = cc_cipher_decrypt,
1035                         .min_keysize = CC_HW_KEY_SIZE,
1036                         .max_keysize = CC_HW_KEY_SIZE,
1037                         .ivsize = AES_BLOCK_SIZE,
1038                         },
1039                 .cipher_mode = DRV_CIPHER_ESSIV,
1040                 .flow_mode = S_DIN_to_AES,
1041                 .data_unit = 512,
1042                 .min_hw_rev = CC_HW_REV_712,
1043                 .std_body = CC_STD_NIST,
1044                 .sec_func = true,
1045         },
1046         {
1047                 .name = "essiv4096(paes)",
1048                 .driver_name = "essiv-paes-du4096-ccree",
1049                 .blocksize = AES_BLOCK_SIZE,
1050                 .template_skcipher = {
1051                         .setkey = cc_cipher_sethkey,
1052                         .encrypt = cc_cipher_encrypt,
1053                         .decrypt = cc_cipher_decrypt,
1054                         .min_keysize = CC_HW_KEY_SIZE,
1055                         .max_keysize = CC_HW_KEY_SIZE,
1056                         .ivsize = AES_BLOCK_SIZE,
1057                         },
1058                 .cipher_mode = DRV_CIPHER_ESSIV,
1059                 .flow_mode = S_DIN_to_AES,
1060                 .data_unit = 4096,
1061                 .min_hw_rev = CC_HW_REV_712,
1062                 .std_body = CC_STD_NIST,
1063                 .sec_func = true,
1064         },
1065         {
1066                 .name = "bitlocker(paes)",
1067                 .driver_name = "bitlocker-paes-ccree",
1068                 .blocksize = AES_BLOCK_SIZE,
1069                 .template_skcipher = {
1070                         .setkey = cc_cipher_sethkey,
1071                         .encrypt = cc_cipher_encrypt,
1072                         .decrypt = cc_cipher_decrypt,
1073                         .min_keysize = CC_HW_KEY_SIZE,
1074                         .max_keysize = CC_HW_KEY_SIZE,
1075                         .ivsize = AES_BLOCK_SIZE,
1076                         },
1077                 .cipher_mode = DRV_CIPHER_BITLOCKER,
1078                 .flow_mode = S_DIN_to_AES,
1079                 .min_hw_rev = CC_HW_REV_712,
1080                 .std_body = CC_STD_NIST,
1081                 .sec_func = true,
1082         },
1083         {
1084                 .name = "bitlocker512(paes)",
1085                 .driver_name = "bitlocker-paes-du512-ccree",
1086                 .blocksize = AES_BLOCK_SIZE,
1087                 .template_skcipher = {
1088                         .setkey = cc_cipher_sethkey,
1089                         .encrypt = cc_cipher_encrypt,
1090                         .decrypt = cc_cipher_decrypt,
1091                         .min_keysize = CC_HW_KEY_SIZE,
1092                         .max_keysize = CC_HW_KEY_SIZE,
1093                         .ivsize = AES_BLOCK_SIZE,
1094                         },
1095                 .cipher_mode = DRV_CIPHER_BITLOCKER,
1096                 .flow_mode = S_DIN_to_AES,
1097                 .data_unit = 512,
1098                 .min_hw_rev = CC_HW_REV_712,
1099                 .std_body = CC_STD_NIST,
1100                 .sec_func = true,
1101         },
1102         {
1103                 .name = "bitlocker4096(paes)",
1104                 .driver_name = "bitlocker-paes-du4096-ccree",
1105                 .blocksize = AES_BLOCK_SIZE,
1106                 .template_skcipher = {
1107                         .setkey = cc_cipher_sethkey,
1108                         .encrypt = cc_cipher_encrypt,
1109                         .decrypt = cc_cipher_decrypt,
1110                         .min_keysize = CC_HW_KEY_SIZE,
1111                         .max_keysize =  CC_HW_KEY_SIZE,
1112                         .ivsize = AES_BLOCK_SIZE,
1113                         },
1114                 .cipher_mode = DRV_CIPHER_BITLOCKER,
1115                 .flow_mode = S_DIN_to_AES,
1116                 .data_unit = 4096,
1117                 .min_hw_rev = CC_HW_REV_712,
1118                 .std_body = CC_STD_NIST,
1119                 .sec_func = true,
1120         },
1121         {
1122                 .name = "ecb(paes)",
1123                 .driver_name = "ecb-paes-ccree",
1124                 .blocksize = AES_BLOCK_SIZE,
1125                 .template_skcipher = {
1126                         .setkey = cc_cipher_sethkey,
1127                         .encrypt = cc_cipher_encrypt,
1128                         .decrypt = cc_cipher_decrypt,
1129                         .min_keysize = CC_HW_KEY_SIZE,
1130                         .max_keysize = CC_HW_KEY_SIZE,
1131                         .ivsize = 0,
1132                         },
1133                 .cipher_mode = DRV_CIPHER_ECB,
1134                 .flow_mode = S_DIN_to_AES,
1135                 .min_hw_rev = CC_HW_REV_712,
1136                 .std_body = CC_STD_NIST,
1137                 .sec_func = true,
1138         },
1139         {
1140                 .name = "cbc(paes)",
1141                 .driver_name = "cbc-paes-ccree",
1142                 .blocksize = AES_BLOCK_SIZE,
1143                 .template_skcipher = {
1144                         .setkey = cc_cipher_sethkey,
1145                         .encrypt = cc_cipher_encrypt,
1146                         .decrypt = cc_cipher_decrypt,
1147                         .min_keysize = CC_HW_KEY_SIZE,
1148                         .max_keysize = CC_HW_KEY_SIZE,
1149                         .ivsize = AES_BLOCK_SIZE,
1150                 },
1151                 .cipher_mode = DRV_CIPHER_CBC,
1152                 .flow_mode = S_DIN_to_AES,
1153                 .min_hw_rev = CC_HW_REV_712,
1154                 .std_body = CC_STD_NIST,
1155                 .sec_func = true,
1156         },
1157         {
1158                 .name = "ofb(paes)",
1159                 .driver_name = "ofb-paes-ccree",
1160                 .blocksize = AES_BLOCK_SIZE,
1161                 .template_skcipher = {
1162                         .setkey = cc_cipher_sethkey,
1163                         .encrypt = cc_cipher_encrypt,
1164                         .decrypt = cc_cipher_decrypt,
1165                         .min_keysize = CC_HW_KEY_SIZE,
1166                         .max_keysize = CC_HW_KEY_SIZE,
1167                         .ivsize = AES_BLOCK_SIZE,
1168                         },
1169                 .cipher_mode = DRV_CIPHER_OFB,
1170                 .flow_mode = S_DIN_to_AES,
1171                 .min_hw_rev = CC_HW_REV_712,
1172                 .std_body = CC_STD_NIST,
1173                 .sec_func = true,
1174         },
1175         {
1176                 .name = "cts(cbc(paes))",
1177                 .driver_name = "cts-cbc-paes-ccree",
1178                 .blocksize = AES_BLOCK_SIZE,
1179                 .template_skcipher = {
1180                         .setkey = cc_cipher_sethkey,
1181                         .encrypt = cc_cipher_encrypt,
1182                         .decrypt = cc_cipher_decrypt,
1183                         .min_keysize = CC_HW_KEY_SIZE,
1184                         .max_keysize = CC_HW_KEY_SIZE,
1185                         .ivsize = AES_BLOCK_SIZE,
1186                         },
1187                 .cipher_mode = DRV_CIPHER_CBC_CTS,
1188                 .flow_mode = S_DIN_to_AES,
1189                 .min_hw_rev = CC_HW_REV_712,
1190                 .std_body = CC_STD_NIST,
1191                 .sec_func = true,
1192         },
1193         {
1194                 .name = "ctr(paes)",
1195                 .driver_name = "ctr-paes-ccree",
1196                 .blocksize = 1,
1197                 .template_skcipher = {
1198                         .setkey = cc_cipher_sethkey,
1199                         .encrypt = cc_cipher_encrypt,
1200                         .decrypt = cc_cipher_decrypt,
1201                         .min_keysize = CC_HW_KEY_SIZE,
1202                         .max_keysize = CC_HW_KEY_SIZE,
1203                         .ivsize = AES_BLOCK_SIZE,
1204                         },
1205                 .cipher_mode = DRV_CIPHER_CTR,
1206                 .flow_mode = S_DIN_to_AES,
1207                 .min_hw_rev = CC_HW_REV_712,
1208                 .std_body = CC_STD_NIST,
1209                 .sec_func = true,
1210         },
1211         {
1212                 .name = "xts(aes)",
1213                 .driver_name = "xts-aes-ccree",
1214                 .blocksize = AES_BLOCK_SIZE,
1215                 .template_skcipher = {
1216                         .setkey = cc_cipher_setkey,
1217                         .encrypt = cc_cipher_encrypt,
1218                         .decrypt = cc_cipher_decrypt,
1219                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1220                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1221                         .ivsize = AES_BLOCK_SIZE,
1222                         },
1223                 .cipher_mode = DRV_CIPHER_XTS,
1224                 .flow_mode = S_DIN_to_AES,
1225                 .min_hw_rev = CC_HW_REV_630,
1226                 .std_body = CC_STD_NIST,
1227         },
1228         {
1229                 .name = "xts512(aes)",
1230                 .driver_name = "xts-aes-du512-ccree",
1231                 .blocksize = AES_BLOCK_SIZE,
1232                 .template_skcipher = {
1233                         .setkey = cc_cipher_setkey,
1234                         .encrypt = cc_cipher_encrypt,
1235                         .decrypt = cc_cipher_decrypt,
1236                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1237                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1238                         .ivsize = AES_BLOCK_SIZE,
1239                         },
1240                 .cipher_mode = DRV_CIPHER_XTS,
1241                 .flow_mode = S_DIN_to_AES,
1242                 .data_unit = 512,
1243                 .min_hw_rev = CC_HW_REV_712,
1244                 .std_body = CC_STD_NIST,
1245         },
1246         {
1247                 .name = "xts4096(aes)",
1248                 .driver_name = "xts-aes-du4096-ccree",
1249                 .blocksize = AES_BLOCK_SIZE,
1250                 .template_skcipher = {
1251                         .setkey = cc_cipher_setkey,
1252                         .encrypt = cc_cipher_encrypt,
1253                         .decrypt = cc_cipher_decrypt,
1254                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1255                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1256                         .ivsize = AES_BLOCK_SIZE,
1257                         },
1258                 .cipher_mode = DRV_CIPHER_XTS,
1259                 .flow_mode = S_DIN_to_AES,
1260                 .data_unit = 4096,
1261                 .min_hw_rev = CC_HW_REV_712,
1262                 .std_body = CC_STD_NIST,
1263         },
1264         {
1265                 .name = "essiv(aes)",
1266                 .driver_name = "essiv-aes-ccree",
1267                 .blocksize = AES_BLOCK_SIZE,
1268                 .template_skcipher = {
1269                         .setkey = cc_cipher_setkey,
1270                         .encrypt = cc_cipher_encrypt,
1271                         .decrypt = cc_cipher_decrypt,
1272                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1273                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1274                         .ivsize = AES_BLOCK_SIZE,
1275                         },
1276                 .cipher_mode = DRV_CIPHER_ESSIV,
1277                 .flow_mode = S_DIN_to_AES,
1278                 .min_hw_rev = CC_HW_REV_712,
1279                 .std_body = CC_STD_NIST,
1280         },
1281         {
1282                 .name = "essiv512(aes)",
1283                 .driver_name = "essiv-aes-du512-ccree",
1284                 .blocksize = AES_BLOCK_SIZE,
1285                 .template_skcipher = {
1286                         .setkey = cc_cipher_setkey,
1287                         .encrypt = cc_cipher_encrypt,
1288                         .decrypt = cc_cipher_decrypt,
1289                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1290                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1291                         .ivsize = AES_BLOCK_SIZE,
1292                         },
1293                 .cipher_mode = DRV_CIPHER_ESSIV,
1294                 .flow_mode = S_DIN_to_AES,
1295                 .data_unit = 512,
1296                 .min_hw_rev = CC_HW_REV_712,
1297                 .std_body = CC_STD_NIST,
1298         },
1299         {
1300                 .name = "essiv4096(aes)",
1301                 .driver_name = "essiv-aes-du4096-ccree",
1302                 .blocksize = AES_BLOCK_SIZE,
1303                 .template_skcipher = {
1304                         .setkey = cc_cipher_setkey,
1305                         .encrypt = cc_cipher_encrypt,
1306                         .decrypt = cc_cipher_decrypt,
1307                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1308                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1309                         .ivsize = AES_BLOCK_SIZE,
1310                         },
1311                 .cipher_mode = DRV_CIPHER_ESSIV,
1312                 .flow_mode = S_DIN_to_AES,
1313                 .data_unit = 4096,
1314                 .min_hw_rev = CC_HW_REV_712,
1315                 .std_body = CC_STD_NIST,
1316         },
1317         {
1318                 .name = "bitlocker(aes)",
1319                 .driver_name = "bitlocker-aes-ccree",
1320                 .blocksize = AES_BLOCK_SIZE,
1321                 .template_skcipher = {
1322                         .setkey = cc_cipher_setkey,
1323                         .encrypt = cc_cipher_encrypt,
1324                         .decrypt = cc_cipher_decrypt,
1325                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1326                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1327                         .ivsize = AES_BLOCK_SIZE,
1328                         },
1329                 .cipher_mode = DRV_CIPHER_BITLOCKER,
1330                 .flow_mode = S_DIN_to_AES,
1331                 .min_hw_rev = CC_HW_REV_712,
1332                 .std_body = CC_STD_NIST,
1333         },
1334         {
1335                 .name = "bitlocker512(aes)",
1336                 .driver_name = "bitlocker-aes-du512-ccree",
1337                 .blocksize = AES_BLOCK_SIZE,
1338                 .template_skcipher = {
1339                         .setkey = cc_cipher_setkey,
1340                         .encrypt = cc_cipher_encrypt,
1341                         .decrypt = cc_cipher_decrypt,
1342                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1343                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1344                         .ivsize = AES_BLOCK_SIZE,
1345                         },
1346                 .cipher_mode = DRV_CIPHER_BITLOCKER,
1347                 .flow_mode = S_DIN_to_AES,
1348                 .data_unit = 512,
1349                 .min_hw_rev = CC_HW_REV_712,
1350                 .std_body = CC_STD_NIST,
1351         },
1352         {
1353                 .name = "bitlocker4096(aes)",
1354                 .driver_name = "bitlocker-aes-du4096-ccree",
1355                 .blocksize = AES_BLOCK_SIZE,
1356                 .template_skcipher = {
1357                         .setkey = cc_cipher_setkey,
1358                         .encrypt = cc_cipher_encrypt,
1359                         .decrypt = cc_cipher_decrypt,
1360                         .min_keysize = AES_MIN_KEY_SIZE * 2,
1361                         .max_keysize = AES_MAX_KEY_SIZE * 2,
1362                         .ivsize = AES_BLOCK_SIZE,
1363                         },
1364                 .cipher_mode = DRV_CIPHER_BITLOCKER,
1365                 .flow_mode = S_DIN_to_AES,
1366                 .data_unit = 4096,
1367                 .min_hw_rev = CC_HW_REV_712,
1368                 .std_body = CC_STD_NIST,
1369         },
1370         {
1371                 .name = "ecb(aes)",
1372                 .driver_name = "ecb-aes-ccree",
1373                 .blocksize = AES_BLOCK_SIZE,
1374                 .template_skcipher = {
1375                         .setkey = cc_cipher_setkey,
1376                         .encrypt = cc_cipher_encrypt,
1377                         .decrypt = cc_cipher_decrypt,
1378                         .min_keysize = AES_MIN_KEY_SIZE,
1379                         .max_keysize = AES_MAX_KEY_SIZE,
1380                         .ivsize = 0,
1381                         },
1382                 .cipher_mode = DRV_CIPHER_ECB,
1383                 .flow_mode = S_DIN_to_AES,
1384                 .min_hw_rev = CC_HW_REV_630,
1385                 .std_body = CC_STD_NIST,
1386         },
1387         {
1388                 .name = "cbc(aes)",
1389                 .driver_name = "cbc-aes-ccree",
1390                 .blocksize = AES_BLOCK_SIZE,
1391                 .template_skcipher = {
1392                         .setkey = cc_cipher_setkey,
1393                         .encrypt = cc_cipher_encrypt,
1394                         .decrypt = cc_cipher_decrypt,
1395                         .min_keysize = AES_MIN_KEY_SIZE,
1396                         .max_keysize = AES_MAX_KEY_SIZE,
1397                         .ivsize = AES_BLOCK_SIZE,
1398                 },
1399                 .cipher_mode = DRV_CIPHER_CBC,
1400                 .flow_mode = S_DIN_to_AES,
1401                 .min_hw_rev = CC_HW_REV_630,
1402                 .std_body = CC_STD_NIST,
1403         },
1404         {
1405                 .name = "ofb(aes)",
1406                 .driver_name = "ofb-aes-ccree",
1407                 .blocksize = AES_BLOCK_SIZE,
1408                 .template_skcipher = {
1409                         .setkey = cc_cipher_setkey,
1410                         .encrypt = cc_cipher_encrypt,
1411                         .decrypt = cc_cipher_decrypt,
1412                         .min_keysize = AES_MIN_KEY_SIZE,
1413                         .max_keysize = AES_MAX_KEY_SIZE,
1414                         .ivsize = AES_BLOCK_SIZE,
1415                         },
1416                 .cipher_mode = DRV_CIPHER_OFB,
1417                 .flow_mode = S_DIN_to_AES,
1418                 .min_hw_rev = CC_HW_REV_630,
1419                 .std_body = CC_STD_NIST,
1420         },
1421         {
1422                 .name = "cts(cbc(aes))",
1423                 .driver_name = "cts-cbc-aes-ccree",
1424                 .blocksize = AES_BLOCK_SIZE,
1425                 .template_skcipher = {
1426                         .setkey = cc_cipher_setkey,
1427                         .encrypt = cc_cipher_encrypt,
1428                         .decrypt = cc_cipher_decrypt,
1429                         .min_keysize = AES_MIN_KEY_SIZE,
1430                         .max_keysize = AES_MAX_KEY_SIZE,
1431                         .ivsize = AES_BLOCK_SIZE,
1432                         },
1433                 .cipher_mode = DRV_CIPHER_CBC_CTS,
1434                 .flow_mode = S_DIN_to_AES,
1435                 .min_hw_rev = CC_HW_REV_630,
1436                 .std_body = CC_STD_NIST,
1437         },
1438         {
1439                 .name = "ctr(aes)",
1440                 .driver_name = "ctr-aes-ccree",
1441                 .blocksize = 1,
1442                 .template_skcipher = {
1443                         .setkey = cc_cipher_setkey,
1444                         .encrypt = cc_cipher_encrypt,
1445                         .decrypt = cc_cipher_decrypt,
1446                         .min_keysize = AES_MIN_KEY_SIZE,
1447                         .max_keysize = AES_MAX_KEY_SIZE,
1448                         .ivsize = AES_BLOCK_SIZE,
1449                         },
1450                 .cipher_mode = DRV_CIPHER_CTR,
1451                 .flow_mode = S_DIN_to_AES,
1452                 .min_hw_rev = CC_HW_REV_630,
1453                 .std_body = CC_STD_NIST,
1454         },
1455         {
1456                 .name = "cbc(des3_ede)",
1457                 .driver_name = "cbc-3des-ccree",
1458                 .blocksize = DES3_EDE_BLOCK_SIZE,
1459                 .template_skcipher = {
1460                         .setkey = cc_cipher_setkey,
1461                         .encrypt = cc_cipher_encrypt,
1462                         .decrypt = cc_cipher_decrypt,
1463                         .min_keysize = DES3_EDE_KEY_SIZE,
1464                         .max_keysize = DES3_EDE_KEY_SIZE,
1465                         .ivsize = DES3_EDE_BLOCK_SIZE,
1466                         },
1467                 .cipher_mode = DRV_CIPHER_CBC,
1468                 .flow_mode = S_DIN_to_DES,
1469                 .min_hw_rev = CC_HW_REV_630,
1470                 .std_body = CC_STD_NIST,
1471         },
1472         {
1473                 .name = "ecb(des3_ede)",
1474                 .driver_name = "ecb-3des-ccree",
1475                 .blocksize = DES3_EDE_BLOCK_SIZE,
1476                 .template_skcipher = {
1477                         .setkey = cc_cipher_setkey,
1478                         .encrypt = cc_cipher_encrypt,
1479                         .decrypt = cc_cipher_decrypt,
1480                         .min_keysize = DES3_EDE_KEY_SIZE,
1481                         .max_keysize = DES3_EDE_KEY_SIZE,
1482                         .ivsize = 0,
1483                         },
1484                 .cipher_mode = DRV_CIPHER_ECB,
1485                 .flow_mode = S_DIN_to_DES,
1486                 .min_hw_rev = CC_HW_REV_630,
1487                 .std_body = CC_STD_NIST,
1488         },
1489         {
1490                 .name = "cbc(des)",
1491                 .driver_name = "cbc-des-ccree",
1492                 .blocksize = DES_BLOCK_SIZE,
1493                 .template_skcipher = {
1494                         .setkey = cc_cipher_setkey,
1495                         .encrypt = cc_cipher_encrypt,
1496                         .decrypt = cc_cipher_decrypt,
1497                         .min_keysize = DES_KEY_SIZE,
1498                         .max_keysize = DES_KEY_SIZE,
1499                         .ivsize = DES_BLOCK_SIZE,
1500                         },
1501                 .cipher_mode = DRV_CIPHER_CBC,
1502                 .flow_mode = S_DIN_to_DES,
1503                 .min_hw_rev = CC_HW_REV_630,
1504                 .std_body = CC_STD_NIST,
1505         },
1506         {
1507                 .name = "ecb(des)",
1508                 .driver_name = "ecb-des-ccree",
1509                 .blocksize = DES_BLOCK_SIZE,
1510                 .template_skcipher = {
1511                         .setkey = cc_cipher_setkey,
1512                         .encrypt = cc_cipher_encrypt,
1513                         .decrypt = cc_cipher_decrypt,
1514                         .min_keysize = DES_KEY_SIZE,
1515                         .max_keysize = DES_KEY_SIZE,
1516                         .ivsize = 0,
1517                         },
1518                 .cipher_mode = DRV_CIPHER_ECB,
1519                 .flow_mode = S_DIN_to_DES,
1520                 .min_hw_rev = CC_HW_REV_630,
1521                 .std_body = CC_STD_NIST,
1522         },
1523         {
1524                 .name = "cbc(sm4)",
1525                 .driver_name = "cbc-sm4-ccree",
1526                 .blocksize = SM4_BLOCK_SIZE,
1527                 .template_skcipher = {
1528                         .setkey = cc_cipher_setkey,
1529                         .encrypt = cc_cipher_encrypt,
1530                         .decrypt = cc_cipher_decrypt,
1531                         .min_keysize = SM4_KEY_SIZE,
1532                         .max_keysize = SM4_KEY_SIZE,
1533                         .ivsize = SM4_BLOCK_SIZE,
1534                         },
1535                 .cipher_mode = DRV_CIPHER_CBC,
1536                 .flow_mode = S_DIN_to_SM4,
1537                 .min_hw_rev = CC_HW_REV_713,
1538                 .std_body = CC_STD_OSCCA,
1539         },
1540         {
1541                 .name = "ecb(sm4)",
1542                 .driver_name = "ecb-sm4-ccree",
1543                 .blocksize = SM4_BLOCK_SIZE,
1544                 .template_skcipher = {
1545                         .setkey = cc_cipher_setkey,
1546                         .encrypt = cc_cipher_encrypt,
1547                         .decrypt = cc_cipher_decrypt,
1548                         .min_keysize = SM4_KEY_SIZE,
1549                         .max_keysize = SM4_KEY_SIZE,
1550                         .ivsize = 0,
1551                         },
1552                 .cipher_mode = DRV_CIPHER_ECB,
1553                 .flow_mode = S_DIN_to_SM4,
1554                 .min_hw_rev = CC_HW_REV_713,
1555                 .std_body = CC_STD_OSCCA,
1556         },
1557         {
1558                 .name = "ctr(sm4)",
1559                 .driver_name = "ctr-sm4-ccree",
1560                 .blocksize = SM4_BLOCK_SIZE,
1561                 .template_skcipher = {
1562                         .setkey = cc_cipher_setkey,
1563                         .encrypt = cc_cipher_encrypt,
1564                         .decrypt = cc_cipher_decrypt,
1565                         .min_keysize = SM4_KEY_SIZE,
1566                         .max_keysize = SM4_KEY_SIZE,
1567                         .ivsize = SM4_BLOCK_SIZE,
1568                         },
1569                 .cipher_mode = DRV_CIPHER_CTR,
1570                 .flow_mode = S_DIN_to_SM4,
1571                 .min_hw_rev = CC_HW_REV_713,
1572                 .std_body = CC_STD_OSCCA,
1573         },
1574         {
1575                 .name = "cbc(psm4)",
1576                 .driver_name = "cbc-psm4-ccree",
1577                 .blocksize = SM4_BLOCK_SIZE,
1578                 .template_skcipher = {
1579                         .setkey = cc_cipher_sethkey,
1580                         .encrypt = cc_cipher_encrypt,
1581                         .decrypt = cc_cipher_decrypt,
1582                         .min_keysize = CC_HW_KEY_SIZE,
1583                         .max_keysize = CC_HW_KEY_SIZE,
1584                         .ivsize = SM4_BLOCK_SIZE,
1585                         },
1586                 .cipher_mode = DRV_CIPHER_CBC,
1587                 .flow_mode = S_DIN_to_SM4,
1588                 .min_hw_rev = CC_HW_REV_713,
1589                 .std_body = CC_STD_OSCCA,
1590                 .sec_func = true,
1591         },
1592         {
1593                 .name = "ctr(psm4)",
1594                 .driver_name = "ctr-psm4-ccree",
1595                 .blocksize = SM4_BLOCK_SIZE,
1596                 .template_skcipher = {
1597                         .setkey = cc_cipher_sethkey,
1598                         .encrypt = cc_cipher_encrypt,
1599                         .decrypt = cc_cipher_decrypt,
1600                         .min_keysize = CC_HW_KEY_SIZE,
1601                         .max_keysize = CC_HW_KEY_SIZE,
1602                         .ivsize = SM4_BLOCK_SIZE,
1603                         },
1604                 .cipher_mode = DRV_CIPHER_CTR,
1605                 .flow_mode = S_DIN_to_SM4,
1606                 .min_hw_rev = CC_HW_REV_713,
1607                 .std_body = CC_STD_OSCCA,
1608                 .sec_func = true,
1609         },
1610 };
1611
1612 static struct cc_crypto_alg *cc_create_alg(const struct cc_alg_template *tmpl,
1613                                            struct device *dev)
1614 {
1615         struct cc_crypto_alg *t_alg;
1616         struct skcipher_alg *alg;
1617
1618         t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
1619         if (!t_alg)
1620                 return ERR_PTR(-ENOMEM);
1621
1622         alg = &t_alg->skcipher_alg;
1623
1624         memcpy(alg, &tmpl->template_skcipher, sizeof(*alg));
1625
1626         snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1627         snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1628                  tmpl->driver_name);
1629         alg->base.cra_module = THIS_MODULE;
1630         alg->base.cra_priority = CC_CRA_PRIO;
1631         alg->base.cra_blocksize = tmpl->blocksize;
1632         alg->base.cra_alignmask = 0;
1633         alg->base.cra_ctxsize = sizeof(struct cc_cipher_ctx);
1634
1635         alg->base.cra_init = cc_cipher_init;
1636         alg->base.cra_exit = cc_cipher_exit;
1637         alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
1638
1639         t_alg->cipher_mode = tmpl->cipher_mode;
1640         t_alg->flow_mode = tmpl->flow_mode;
1641         t_alg->data_unit = tmpl->data_unit;
1642
1643         return t_alg;
1644 }
1645
1646 int cc_cipher_free(struct cc_drvdata *drvdata)
1647 {
1648         struct cc_crypto_alg *t_alg, *n;
1649         struct cc_cipher_handle *cipher_handle = drvdata->cipher_handle;
1650
1651         if (cipher_handle) {
1652                 /* Remove registered algs */
1653                 list_for_each_entry_safe(t_alg, n, &cipher_handle->alg_list,
1654                                          entry) {
1655                         crypto_unregister_skcipher(&t_alg->skcipher_alg);
1656                         list_del(&t_alg->entry);
1657                         kfree(t_alg);
1658                 }
1659                 kfree(cipher_handle);
1660                 drvdata->cipher_handle = NULL;
1661         }
1662         return 0;
1663 }
1664
1665 int cc_cipher_alloc(struct cc_drvdata *drvdata)
1666 {
1667         struct cc_cipher_handle *cipher_handle;
1668         struct cc_crypto_alg *t_alg;
1669         struct device *dev = drvdata_to_dev(drvdata);
1670         int rc = -ENOMEM;
1671         int alg;
1672
1673         cipher_handle = kmalloc(sizeof(*cipher_handle), GFP_KERNEL);
1674         if (!cipher_handle)
1675                 return -ENOMEM;
1676
1677         INIT_LIST_HEAD(&cipher_handle->alg_list);
1678         drvdata->cipher_handle = cipher_handle;
1679
1680         /* Linux crypto */
1681         dev_dbg(dev, "Number of algorithms = %zu\n",
1682                 ARRAY_SIZE(skcipher_algs));
1683         for (alg = 0; alg < ARRAY_SIZE(skcipher_algs); alg++) {
1684                 if ((skcipher_algs[alg].min_hw_rev > drvdata->hw_rev) ||
1685                     !(drvdata->std_bodies & skcipher_algs[alg].std_body) ||
1686                     (drvdata->sec_disabled && skcipher_algs[alg].sec_func))
1687                         continue;
1688
1689                 dev_dbg(dev, "creating %s\n", skcipher_algs[alg].driver_name);
1690                 t_alg = cc_create_alg(&skcipher_algs[alg], dev);
1691                 if (IS_ERR(t_alg)) {
1692                         rc = PTR_ERR(t_alg);
1693                         dev_err(dev, "%s alg allocation failed\n",
1694                                 skcipher_algs[alg].driver_name);
1695                         goto fail0;
1696                 }
1697                 t_alg->drvdata = drvdata;
1698
1699                 dev_dbg(dev, "registering %s\n",
1700                         skcipher_algs[alg].driver_name);
1701                 rc = crypto_register_skcipher(&t_alg->skcipher_alg);
1702                 dev_dbg(dev, "%s alg registration rc = %x\n",
1703                         t_alg->skcipher_alg.base.cra_driver_name, rc);
1704                 if (rc) {
1705                         dev_err(dev, "%s alg registration failed\n",
1706                                 t_alg->skcipher_alg.base.cra_driver_name);
1707                         kfree(t_alg);
1708                         goto fail0;
1709                 } else {
1710                         list_add_tail(&t_alg->entry,
1711                                       &cipher_handle->alg_list);
1712                         dev_dbg(dev, "Registered %s\n",
1713                                 t_alg->skcipher_alg.base.cra_driver_name);
1714                 }
1715         }
1716         return 0;
1717
1718 fail0:
1719         cc_cipher_free(drvdata);
1720         return rc;
1721 }