drivers/crypto/ux500/hash/hash_core.c

   1 /*
   2  * Cryptographic API.
   3  * Support for Nomadik hardware crypto engine.
   4
   5  * Copyright (C) ST-Ericsson SA 2010
   6  * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson
   7  * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
   8  * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
   9  * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
  10  * Author: Andreas Westin <andreas.westin@stericsson.com> for ST-Ericsson.
  11  * License terms: GNU General Public License (GPL) version 2
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/err.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/klist.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/crypto.h>
  24
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/dmaengine.h>
  27 #include <linux/bitops.h>
  28
  29 #include <crypto/internal/hash.h>
  30 #include <crypto/sha.h>
  31 #include <crypto/scatterwalk.h>
  32 #include <crypto/algapi.h>
  33
  34 #include <linux/platform_data/crypto-ux500.h>
  35
  36 #include "hash_alg.h"
  37
  38 #define DEV_DBG_NAME "hashX hashX:"
  39
  40 static int hash_mode;
  41 module_param(hash_mode, int, 0);
  42 MODULE_PARM_DESC(hash_mode, "CPU or DMA mode. CPU = 0 (default), DMA = 1");
  43
  44 /**
  45  * Pre-calculated empty message digests.
  46  */
  47 static u8 zero_message_hash_sha1[SHA1_DIGEST_SIZE] = {
  48         0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
  49         0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90,
  50         0xaf, 0xd8, 0x07, 0x09
  51 };
  52
  53 static u8 zero_message_hash_sha256[SHA256_DIGEST_SIZE] = {
  54         0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
  55         0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
  56         0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
  57         0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55
  58 };
  59
  60 /* HMAC-SHA1, no key */
  61 static u8 zero_message_hmac_sha1[SHA1_DIGEST_SIZE] = {
  62         0xfb, 0xdb, 0x1d, 0x1b, 0x18, 0xaa, 0x6c, 0x08,
  63         0x32, 0x4b, 0x7d, 0x64, 0xb7, 0x1f, 0xb7, 0x63,
  64         0x70, 0x69, 0x0e, 0x1d
  65 };
  66
  67 /* HMAC-SHA256, no key */
  68 static u8 zero_message_hmac_sha256[SHA256_DIGEST_SIZE] = {
  69         0xb6, 0x13, 0x67, 0x9a, 0x08, 0x14, 0xd9, 0xec,
  70         0x77, 0x2f, 0x95, 0xd7, 0x78, 0xc3, 0x5f, 0xc5,
  71         0xff, 0x16, 0x97, 0xc4, 0x93, 0x71, 0x56, 0x53,
  72         0xc6, 0xc7, 0x12, 0x14, 0x42, 0x92, 0xc5, 0xad
  73 };
  74
  75 /**
  76  * struct hash_driver_data - data specific to the driver.
  77  *
  78  * @device_list:        A list of registered devices to choose from.
  79  * @device_allocation:  A semaphore initialized with number of devices.
  80  */
  81 struct hash_driver_data {
  82         struct klist            device_list;
  83         struct semaphore        device_allocation;
  84 };
  85
  86 static struct hash_driver_data  driver_data;
  87
  88 /* Declaration of functions */
  89 /**
  90  * hash_messagepad - Pads a message and write the nblw bits.
  91  * @device_data:        Structure for the hash device.
  92  * @message:            Last word of a message
  93  * @index_bytes:        The number of bytes in the last message
  94  *
  95  * This function manages the final part of the digest calculation, when less
  96  * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
  97  *
  98  */
  99 static void hash_messagepad(struct hash_device_data *device_data,
 100                 const u32 *message, u8 index_bytes);
 101
 102 /**
 103  * release_hash_device - Releases a previously allocated hash device.
 104  * @device_data:        Structure for the hash device.
 105  *
 106  */
 107 static void release_hash_device(struct hash_device_data *device_data)
 108 {
 109         spin_lock(&device_data->ctx_lock);
 110         device_data->current_ctx->device = NULL;
 111         device_data->current_ctx = NULL;
 112         spin_unlock(&device_data->ctx_lock);
 113
 114         /*
 115          * The down_interruptible part for this semaphore is called in
 116          * cryp_get_device_data.
 117          */
 118         up(&driver_data.device_allocation);
 119 }
 120
 121 static void hash_dma_setup_channel(struct hash_device_data *device_data,
 122                                 struct device *dev)
 123 {
 124         struct hash_platform_data *platform_data = dev->platform_data;
 125         dma_cap_zero(device_data->dma.mask);
 126         dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 127
 128         device_data->dma.cfg_mem2hash = platform_data->mem_to_engine;
 129         device_data->dma.chan_mem2hash =
 130                 dma_request_channel(device_data->dma.mask,
 131                                 platform_data->dma_filter,
 132                                 device_data->dma.cfg_mem2hash);
 133
 134         init_completion(&device_data->dma.complete);
 135 }
 136
 137 static void hash_dma_callback(void *data)
 138 {
 139         struct hash_ctx *ctx = (struct hash_ctx *) data;
 140
 141         complete(&ctx->device->dma.complete);
 142 }
 143
 144 static int hash_set_dma_transfer(struct hash_ctx *ctx, struct scatterlist *sg,
 145                 int len, enum dma_data_direction direction)
 146 {
 147         struct dma_async_tx_descriptor *desc = NULL;
 148         struct dma_chan *channel = NULL;
 149         dma_cookie_t cookie;
 150
 151         if (direction != DMA_TO_DEVICE) {
 152                 dev_err(ctx->device->dev, "[%s] Invalid DMA direction",
 153                                 __func__);
 154                 return -EFAULT;
 155         }
 156
 157         sg->length = ALIGN(sg->length, HASH_DMA_ALIGN_SIZE);
 158
 159         channel = ctx->device->dma.chan_mem2hash;
 160         ctx->device->dma.sg = sg;
 161         ctx->device->dma.sg_len = dma_map_sg(channel->device->dev,
 162                         ctx->device->dma.sg, ctx->device->dma.nents,
 163                         direction);
 164
 165         if (!ctx->device->dma.sg_len) {
 166                 dev_err(ctx->device->dev,
 167                                 "[%s]: Could not map the sg list (TO_DEVICE)",
 168                                 __func__);
 169                 return -EFAULT;
 170         }
 171
 172         dev_dbg(ctx->device->dev, "[%s]: Setting up DMA for buffer "
 173                         "(TO_DEVICE)", __func__);
 174         desc = channel->device->device_prep_slave_sg(channel,
 175                         ctx->device->dma.sg, ctx->device->dma.sg_len,
 176                         direction, DMA_CTRL_ACK | DMA_PREP_INTERRUPT, NULL);
 177         if (!desc) {
 178                 dev_err(ctx->device->dev,
 179                         "[%s]: device_prep_slave_sg() failed!", __func__);
 180                 return -EFAULT;
 181         }
 182
 183         desc->callback = hash_dma_callback;
 184         desc->callback_param = ctx;
 185
 186         cookie = desc->tx_submit(desc);
 187         dma_async_issue_pending(channel);
 188
 189         return 0;
 190 }
 191
 192 static void hash_dma_done(struct hash_ctx *ctx)
 193 {
 194         struct dma_chan *chan;
 195
 196         chan = ctx->device->dma.chan_mem2hash;
 197         chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
 198         dma_unmap_sg(chan->device->dev, ctx->device->dma.sg,
 199                         ctx->device->dma.sg_len, DMA_TO_DEVICE);
 200
 201 }
 202
 203 static int hash_dma_write(struct hash_ctx *ctx,
 204                 struct scatterlist *sg, int len)
 205 {
 206         int error = hash_set_dma_transfer(ctx, sg, len, DMA_TO_DEVICE);
 207         if (error) {
 208                 dev_dbg(ctx->device->dev, "[%s]: hash_set_dma_transfer() "
 209                         "failed", __func__);
 210                 return error;
 211         }
 212
 213         return len;
 214 }
 215
 216 /**
 217  * get_empty_message_digest - Returns a pre-calculated digest for
 218  * the empty message.
 219  * @device_data:        Structure for the hash device.
 220  * @zero_hash:          Buffer to return the empty message digest.
 221  * @zero_hash_size:     Hash size of the empty message digest.
 222  * @zero_digest:        True if zero_digest returned.
 223  */
 224 static int get_empty_message_digest(
 225                 struct hash_device_data *device_data,
 226                 u8 *zero_hash, u32 *zero_hash_size, bool *zero_digest)
 227 {
 228         int ret = 0;
 229         struct hash_ctx *ctx = device_data->current_ctx;
 230         *zero_digest = false;
 231
 232         /**
 233          * Caller responsible for ctx != NULL.
 234          */
 235
 236         if (HASH_OPER_MODE_HASH == ctx->config.oper_mode) {
 237                 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
 238                         memcpy(zero_hash, &zero_message_hash_sha1[0],
 239                                         SHA1_DIGEST_SIZE);
 240                         *zero_hash_size = SHA1_DIGEST_SIZE;
 241                         *zero_digest = true;
 242                 } else if (HASH_ALGO_SHA256 ==
 243                                 ctx->config.algorithm) {
 244                         memcpy(zero_hash, &zero_message_hash_sha256[0],
 245                                         SHA256_DIGEST_SIZE);
 246                         *zero_hash_size = SHA256_DIGEST_SIZE;
 247                         *zero_digest = true;
 248                 } else {
 249                         dev_err(device_data->dev, "[%s] "
 250                                         "Incorrect algorithm!"
 251                                         , __func__);
 252                         ret = -EINVAL;
 253                         goto out;
 254                 }
 255         } else if (HASH_OPER_MODE_HMAC == ctx->config.oper_mode) {
 256                 if (!ctx->keylen) {
 257                         if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
 258                                 memcpy(zero_hash, &zero_message_hmac_sha1[0],
 259                                                 SHA1_DIGEST_SIZE);
 260                                 *zero_hash_size = SHA1_DIGEST_SIZE;
 261                                 *zero_digest = true;
 262                         } else if (HASH_ALGO_SHA256 == ctx->config.algorithm) {
 263                                 memcpy(zero_hash, &zero_message_hmac_sha256[0],
 264                                                 SHA256_DIGEST_SIZE);
 265                                 *zero_hash_size = SHA256_DIGEST_SIZE;
 266                                 *zero_digest = true;
 267                         } else {
 268                                 dev_err(device_data->dev, "[%s] "
 269                                                 "Incorrect algorithm!"
 270                                                 , __func__);
 271                                 ret = -EINVAL;
 272                                 goto out;
 273                         }
 274                 } else {
 275                         dev_dbg(device_data->dev, "[%s] Continue hash "
 276                                         "calculation, since hmac key avalable",
 277                                         __func__);
 278                 }
 279         }
 280 out:
 281
 282         return ret;
 283 }
 284
 285 /**
 286  * hash_disable_power - Request to disable power and clock.
 287  * @device_data:        Structure for the hash device.
 288  * @save_device_state:  If true, saves the current hw state.
 289  *
 290  * This function request for disabling power (regulator) and clock,
 291  * and could also save current hw state.
 292  */
 293 static int hash_disable_power(
 294                 struct hash_device_data *device_data,
 295                 bool                    save_device_state)
 296 {
 297         int ret = 0;
 298         struct device *dev = device_data->dev;
 299
 300         spin_lock(&device_data->power_state_lock);
 301         if (!device_data->power_state)
 302                 goto out;
 303
 304         if (save_device_state) {
 305                 hash_save_state(device_data,
 306                                 &device_data->state);
 307                 device_data->restore_dev_state = true;
 308         }
 309
 310         clk_disable(device_data->clk);
 311         ret = regulator_disable(device_data->regulator);
 312         if (ret)
 313                 dev_err(dev, "[%s] regulator_disable() failed!", __func__);
 314
 315         device_data->power_state = false;
 316
 317 out:
 318         spin_unlock(&device_data->power_state_lock);
 319
 320         return ret;
 321 }
 322
 323 /**
 324  * hash_enable_power - Request to enable power and clock.
 325  * @device_data:                Structure for the hash device.
 326  * @restore_device_state:       If true, restores a previous saved hw state.
 327  *
 328  * This function request for enabling power (regulator) and clock,
 329  * and could also restore a previously saved hw state.
 330  */
 331 static int hash_enable_power(
 332                 struct hash_device_data *device_data,
 333                 bool                    restore_device_state)
 334 {
 335         int ret = 0;
 336         struct device *dev = device_data->dev;
 337
 338         spin_lock(&device_data->power_state_lock);
 339         if (!device_data->power_state) {
 340                 ret = regulator_enable(device_data->regulator);
 341                 if (ret) {
 342                         dev_err(dev, "[%s]: regulator_enable() failed!",
 343                                         __func__);
 344                         goto out;
 345                 }
 346                 ret = clk_enable(device_data->clk);
 347                 if (ret) {
 348                         dev_err(dev, "[%s]: clk_enable() failed!",
 349                                         __func__);
 350                         ret = regulator_disable(
 351                                         device_data->regulator);
 352                         goto out;
 353                 }
 354                 device_data->power_state = true;
 355         }
 356
 357         if (device_data->restore_dev_state) {
 358                 if (restore_device_state) {
 359                         device_data->restore_dev_state = false;
 360                         hash_resume_state(device_data,
 361                                 &device_data->state);
 362                 }
 363         }
 364 out:
 365         spin_unlock(&device_data->power_state_lock);
 366
 367         return ret;
 368 }
 369
 370 /**
 371  * hash_get_device_data - Checks for an available hash device and return it.
 372  * @hash_ctx:           Structure for the hash context.
 373  * @device_data:        Structure for the hash device.
 374  *
 375  * This function check for an available hash device and return it to
 376  * the caller.
 377  * Note! Caller need to release the device, calling up().
 378  */
 379 static int hash_get_device_data(struct hash_ctx *ctx,
 380                                 struct hash_device_data **device_data)
 381 {
 382         int                     ret;
 383         struct klist_iter       device_iterator;
 384         struct klist_node       *device_node;
 385         struct hash_device_data *local_device_data = NULL;
 386
 387         /* Wait until a device is available */
 388         ret = down_interruptible(&driver_data.device_allocation);
 389         if (ret)
 390                 return ret;  /* Interrupted */
 391
 392         /* Select a device */
 393         klist_iter_init(&driver_data.device_list, &device_iterator);
 394         device_node = klist_next(&device_iterator);
 395         while (device_node) {
 396                 local_device_data = container_of(device_node,
 397                                            struct hash_device_data, list_node);
 398                 spin_lock(&local_device_data->ctx_lock);
 399                 /* current_ctx allocates a device, NULL = unallocated */
 400                 if (local_device_data->current_ctx) {
 401                         device_node = klist_next(&device_iterator);
 402                 } else {
 403                         local_device_data->current_ctx = ctx;
 404                         ctx->device = local_device_data;
 405                         spin_unlock(&local_device_data->ctx_lock);
 406                         break;
 407                 }
 408                 spin_unlock(&local_device_data->ctx_lock);
 409         }
 410         klist_iter_exit(&device_iterator);
 411
 412         if (!device_node) {
 413                 /**
 414                  * No free device found.
 415                  * Since we allocated a device with down_interruptible, this
 416                  * should not be able to happen.
 417                  * Number of available devices, which are contained in
 418                  * device_allocation, is therefore decremented by not doing
 419                  * an up(device_allocation).
 420                  */
 421                 return -EBUSY;
 422         }
 423
 424         *device_data = local_device_data;
 425
 426         return 0;
 427 }
 428
 429 /**
 430  * hash_hw_write_key - Writes the key to the hardware registries.
 431  *
 432  * @device_data:        Structure for the hash device.
 433  * @key:                Key to be written.
 434  * @keylen:             The lengt of the key.
 435  *
 436  * Note! This function DOES NOT write to the NBLW registry, even though
 437  * specified in the the hw design spec. Either due to incorrect info in the
 438  * spec or due to a bug in the hw.
 439  */
 440 static void hash_hw_write_key(struct hash_device_data *device_data,
 441                 const u8 *key, unsigned int keylen)
 442 {
 443         u32 word = 0;
 444         int nwords = 1;
 445
 446         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 447
 448         while (keylen >= 4) {
 449                 u32 *key_word = (u32 *)key;
 450
 451                 HASH_SET_DIN(key_word, nwords);
 452                 keylen -= 4;
 453                 key += 4;
 454         }
 455
 456         /* Take care of the remaining bytes in the last word */
 457         if (keylen) {
 458                 word = 0;
 459                 while (keylen) {
 460                         word |= (key[keylen - 1] << (8 * (keylen - 1)));
 461                         keylen--;
 462                 }
 463
 464                 HASH_SET_DIN(&word, nwords);
 465         }
 466
 467         while (device_data->base->str & HASH_STR_DCAL_MASK)
 468                 cpu_relax();
 469
 470         HASH_SET_DCAL;
 471
 472         while (device_data->base->str & HASH_STR_DCAL_MASK)
 473                 cpu_relax();
 474 }
 475
 476 /**
 477  * init_hash_hw - Initialise the hash hardware for a new calculation.
 478  * @device_data:        Structure for the hash device.
 479  * @ctx:                The hash context.
 480  *
 481  * This function will enable the bits needed to clear and start a new
 482  * calculation.
 483  */
 484 static int init_hash_hw(struct hash_device_data *device_data,
 485                 struct hash_ctx *ctx)
 486 {
 487         int ret = 0;
 488
 489         ret = hash_setconfiguration(device_data, &ctx->config);
 490         if (ret) {
 491                 dev_err(device_data->dev, "[%s] hash_setconfiguration() "
 492                                 "failed!", __func__);
 493                 return ret;
 494         }
 495
 496         hash_begin(device_data, ctx);
 497
 498         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
 499                 hash_hw_write_key(device_data, ctx->key, ctx->keylen);
 500
 501         return ret;
 502 }
 503
 504 /**
 505  * hash_get_nents - Return number of entries (nents) in scatterlist (sg).
 506  *
 507  * @sg:         Scatterlist.
 508  * @size:       Size in bytes.
 509  * @aligned:    True if sg data aligned to work in DMA mode.
 510  *
 511  */
 512 static int hash_get_nents(struct scatterlist *sg, int size, bool *aligned)
 513 {
 514         int nents = 0;
 515         bool aligned_data = true;
 516
 517         while (size > 0 && sg) {
 518                 nents++;
 519                 size -= sg->length;
 520
 521                 /* hash_set_dma_transfer will align last nent */
 522                 if ((aligned && !IS_ALIGNED(sg->offset, HASH_DMA_ALIGN_SIZE))
 523                         || (!IS_ALIGNED(sg->length, HASH_DMA_ALIGN_SIZE) &&
 524                                 size > 0))
 525                         aligned_data = false;
 526
 527                 sg = sg_next(sg);
 528         }
 529
 530         if (aligned)
 531                 *aligned = aligned_data;
 532
 533         if (size != 0)
 534                 return -EFAULT;
 535
 536         return nents;
 537 }
 538
 539 /**
 540  * hash_dma_valid_data - checks for dma valid sg data.
 541  * @sg:         Scatterlist.
 542  * @datasize:   Datasize in bytes.
 543  *
 544  * NOTE! This function checks for dma valid sg data, since dma
 545  * only accept datasizes of even wordsize.
 546  */
 547 static bool hash_dma_valid_data(struct scatterlist *sg, int datasize)
 548 {
 549         bool aligned;
 550
 551         /* Need to include at least one nent, else error */
 552         if (hash_get_nents(sg, datasize, &aligned) < 1)
 553                 return false;
 554
 555         return aligned;
 556 }
 557
 558 /**
 559  * hash_init - Common hash init function for SHA1/SHA2 (SHA256).
 560  * @req: The hash request for the job.
 561  *
 562  * Initialize structures.
 563  */
 564 static int hash_init(struct ahash_request *req)
 565 {
 566         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 567         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 568         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 569
 570         if (!ctx->key)
 571                 ctx->keylen = 0;
 572
 573         memset(&req_ctx->state, 0, sizeof(struct hash_state));
 574         req_ctx->updated = 0;
 575         if (hash_mode == HASH_MODE_DMA) {
 576                 if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
 577                         req_ctx->dma_mode = false; /* Don't use DMA */
 578
 579                         pr_debug(DEV_DBG_NAME " [%s] DMA mode, but direct "
 580                                         "to CPU mode for data size < %d",
 581                                         __func__, HASH_DMA_ALIGN_SIZE);
 582                 } else {
 583                         if (req->nbytes >= HASH_DMA_PERFORMANCE_MIN_SIZE &&
 584                                         hash_dma_valid_data(req->src,
 585                                                 req->nbytes)) {
 586                                 req_ctx->dma_mode = true;
 587                         } else {
 588                                 req_ctx->dma_mode = false;
 589                                 pr_debug(DEV_DBG_NAME " [%s] DMA mode, but use"
 590                                                 " CPU mode for datalength < %d"
 591                                                 " or non-aligned data, except "
 592                                                 "in last nent", __func__,
 593                                                 HASH_DMA_PERFORMANCE_MIN_SIZE);
 594                         }
 595                 }
 596         }
 597         return 0;
 598 }
 599
 600 /**
 601  * hash_processblock - This function processes a single block of 512 bits (64
 602  *                     bytes), word aligned, starting at message.
 603  * @device_data:        Structure for the hash device.
 604  * @message:            Block (512 bits) of message to be written to
 605  *                      the HASH hardware.
 606  *
 607  */
 608 static void hash_processblock(
 609                 struct hash_device_data *device_data,
 610                 const u32 *message, int length)
 611 {
 612         int len = length / HASH_BYTES_PER_WORD;
 613         /*
 614          * NBLW bits. Reset the number of bits in last word (NBLW).
 615          */
 616         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 617
 618         /*
 619          * Write message data to the HASH_DIN register.
 620          */
 621         HASH_SET_DIN(message, len);
 622 }
 623
 624 /**
 625  * hash_messagepad - Pads a message and write the nblw bits.
 626  * @device_data:        Structure for the hash device.
 627  * @message:            Last word of a message.
 628  * @index_bytes:        The number of bytes in the last message.
 629  *
 630  * This function manages the final part of the digest calculation, when less
 631  * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
 632  *
 633  */
 634 static void hash_messagepad(struct hash_device_data *device_data,
 635                 const u32 *message, u8 index_bytes)
 636 {
 637         int nwords = 1;
 638
 639         /*
 640          * Clear hash str register, only clear NBLW
 641          * since DCAL will be reset by hardware.
 642          */
 643         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 644
 645         /* Main loop */
 646         while (index_bytes >= 4) {
 647                 HASH_SET_DIN(message, nwords);
 648                 index_bytes -= 4;
 649                 message++;
 650         }
 651
 652         if (index_bytes)
 653                 HASH_SET_DIN(message, nwords);
 654
 655         while (device_data->base->str & HASH_STR_DCAL_MASK)
 656                 cpu_relax();
 657
 658         /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */
 659         HASH_SET_NBLW(index_bytes * 8);
 660         dev_dbg(device_data->dev, "[%s] DIN=0x%08x NBLW=%d", __func__,
 661                         readl_relaxed(&device_data->base->din),
 662                         (int)(readl_relaxed(&device_data->base->str) &
 663                                 HASH_STR_NBLW_MASK));
 664         HASH_SET_DCAL;
 665         dev_dbg(device_data->dev, "[%s] after dcal -> DIN=0x%08x NBLW=%d",
 666                         __func__, readl_relaxed(&device_data->base->din),
 667                         (int)(readl_relaxed(&device_data->base->str) &
 668                                 HASH_STR_NBLW_MASK));
 669
 670         while (device_data->base->str & HASH_STR_DCAL_MASK)
 671                 cpu_relax();
 672 }
 673
 674 /**
 675  * hash_incrementlength - Increments the length of the current message.
 676  * @ctx: Hash context
 677  * @incr: Length of message processed already
 678  *
 679  * Overflow cannot occur, because conditions for overflow are checked in
 680  * hash_hw_update.
 681  */
 682 static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
 683 {
 684         ctx->state.length.low_word += incr;
 685
 686         /* Check for wrap-around */
 687         if (ctx->state.length.low_word < incr)
 688                 ctx->state.length.high_word++;
 689 }
 690
 691 /**
 692  * hash_setconfiguration - Sets the required configuration for the hash
 693  *                         hardware.
 694  * @device_data:        Structure for the hash device.
 695  * @config:             Pointer to a configuration structure.
 696  */
 697 int hash_setconfiguration(struct hash_device_data *device_data,
 698                 struct hash_config *config)
 699 {
 700         int ret = 0;
 701
 702         if (config->algorithm != HASH_ALGO_SHA1 &&
 703             config->algorithm != HASH_ALGO_SHA256)
 704                 return -EPERM;
 705
 706         /*
 707          * DATAFORM bits. Set the DATAFORM bits to 0b11, which means the data
 708          * to be written to HASH_DIN is considered as 32 bits.
 709          */
 710         HASH_SET_DATA_FORMAT(config->data_format);
 711
 712         /*
 713          * ALGO bit. Set to 0b1 for SHA-1 and 0b0 for SHA-256
 714          */
 715         switch (config->algorithm) {
 716         case HASH_ALGO_SHA1:
 717                 HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
 718                 break;
 719
 720         case HASH_ALGO_SHA256:
 721                 HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
 722                 break;
 723
 724         default:
 725                 dev_err(device_data->dev, "[%s] Incorrect algorithm.",
 726                                 __func__);
 727                 return -EPERM;
 728         }
 729
 730         /*
 731          * MODE bit. This bit selects between HASH or HMAC mode for the
 732          * selected algorithm. 0b0 = HASH and 0b1 = HMAC.
 733          */
 734         if (HASH_OPER_MODE_HASH == config->oper_mode)
 735                 HASH_CLEAR_BITS(&device_data->base->cr,
 736                                 HASH_CR_MODE_MASK);
 737         else if (HASH_OPER_MODE_HMAC == config->oper_mode) {
 738                 HASH_SET_BITS(&device_data->base->cr,
 739                                 HASH_CR_MODE_MASK);
 740                 if (device_data->current_ctx->keylen > HASH_BLOCK_SIZE) {
 741                         /* Truncate key to blocksize */
 742                         dev_dbg(device_data->dev, "[%s] LKEY set", __func__);
 743                         HASH_SET_BITS(&device_data->base->cr,
 744                                         HASH_CR_LKEY_MASK);
 745                 } else {
 746                         dev_dbg(device_data->dev, "[%s] LKEY cleared",
 747                                         __func__);
 748                         HASH_CLEAR_BITS(&device_data->base->cr,
 749                                         HASH_CR_LKEY_MASK);
 750                 }
 751         } else {        /* Wrong hash mode */
 752                 ret = -EPERM;
 753                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
 754                                 __func__);
 755         }
 756         return ret;
 757 }
 758
 759 /**
 760  * hash_begin - This routine resets some globals and initializes the hash
 761  *              hardware.
 762  * @device_data:        Structure for the hash device.
 763  * @ctx:                Hash context.
 764  */
 765 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx)
 766 {
 767         /* HW and SW initializations */
 768         /* Note: there is no need to initialize buffer and digest members */
 769
 770         while (device_data->base->str & HASH_STR_DCAL_MASK)
 771                 cpu_relax();
 772
 773         /*
 774          * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
 775          * prepare the initialize the HASH accelerator to compute the message
 776          * digest of a new message.
 777          */
 778         HASH_INITIALIZE;
 779
 780         /*
 781          * NBLW bits. Reset the number of bits in last word (NBLW).
 782          */
 783         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 784 }
 785
 786 int hash_process_data(
 787                 struct hash_device_data *device_data,
 788                 struct hash_ctx *ctx, struct hash_req_ctx *req_ctx,
 789                 int msg_length, u8 *data_buffer, u8 *buffer, u8 *index)
 790 {
 791         int ret = 0;
 792         u32 count;
 793
 794         do {
 795                 if ((*index + msg_length) < HASH_BLOCK_SIZE) {
 796                         for (count = 0; count < msg_length; count++) {
 797                                 buffer[*index + count] =
 798                                         *(data_buffer + count);
 799                         }
 800                         *index += msg_length;
 801                         msg_length = 0;
 802                 } else {
 803                         if (req_ctx->updated) {
 804
 805                                 ret = hash_resume_state(device_data,
 806                                                 &device_data->state);
 807                                 memmove(req_ctx->state.buffer,
 808                                                 device_data->state.buffer,
 809                                                 HASH_BLOCK_SIZE / sizeof(u32));
 810                                 if (ret) {
 811                                         dev_err(device_data->dev, "[%s] "
 812                                                         "hash_resume_state()"
 813                                                         " failed!", __func__);
 814                                         goto out;
 815                                 }
 816                         } else {
 817                                 ret = init_hash_hw(device_data, ctx);
 818                                 if (ret) {
 819                                         dev_err(device_data->dev, "[%s] "
 820                                                         "init_hash_hw()"
 821                                                         " failed!", __func__);
 822                                         goto out;
 823                                 }
 824                                 req_ctx->updated = 1;
 825                         }
 826                         /*
 827                          * If 'data_buffer' is four byte aligned and
 828                          * local buffer does not have any data, we can
 829                          * write data directly from 'data_buffer' to
 830                          * HW peripheral, otherwise we first copy data
 831                          * to a local buffer
 832                          */
 833                         if ((0 == (((u32)data_buffer) % 4))
 834                                         && (0 == *index))
 835                                 hash_processblock(device_data,
 836                                                 (const u32 *)
 837                                                 data_buffer, HASH_BLOCK_SIZE);
 838                         else {
 839                                 for (count = 0; count <
 840                                                 (u32)(HASH_BLOCK_SIZE -
 841                                                         *index);
 842                                                 count++) {
 843                                         buffer[*index + count] =
 844                                                 *(data_buffer + count);
 845                                 }
 846                                 hash_processblock(device_data,
 847                                                 (const u32 *)buffer,
 848                                                 HASH_BLOCK_SIZE);
 849                         }
 850                         hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
 851                         data_buffer += (HASH_BLOCK_SIZE - *index);
 852
 853                         msg_length -= (HASH_BLOCK_SIZE - *index);
 854                         *index = 0;
 855
 856                         ret = hash_save_state(device_data,
 857                                         &device_data->state);
 858
 859                         memmove(device_data->state.buffer,
 860                                         req_ctx->state.buffer,
 861                                         HASH_BLOCK_SIZE / sizeof(u32));
 862                         if (ret) {
 863                                 dev_err(device_data->dev, "[%s] "
 864                                                 "hash_save_state()"
 865                                                 " failed!", __func__);
 866                                 goto out;
 867                         }
 868                 }
 869         } while (msg_length != 0);
 870 out:
 871
 872         return ret;
 873 }
 874
 875 /**
 876  * hash_dma_final - The hash dma final function for SHA1/SHA256.
 877  * @req:        The hash request for the job.
 878  */
 879 static int hash_dma_final(struct ahash_request *req)
 880 {
 881         int ret = 0;
 882         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 883         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 884         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 885         struct hash_device_data *device_data;
 886         u8 digest[SHA256_DIGEST_SIZE];
 887         int bytes_written = 0;
 888
 889         ret = hash_get_device_data(ctx, &device_data);
 890         if (ret)
 891                 return ret;
 892
 893         dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
 894
 895         if (req_ctx->updated) {
 896                 ret = hash_resume_state(device_data, &device_data->state);
 897
 898                 if (ret) {
 899                         dev_err(device_data->dev, "[%s] hash_resume_state() "
 900                                         "failed!", __func__);
 901                         goto out;
 902                 }
 903
 904         }
 905
 906         if (!req_ctx->updated) {
 907                 ret = hash_setconfiguration(device_data, &ctx->config);
 908                 if (ret) {
 909                         dev_err(device_data->dev, "[%s] "
 910                                         "hash_setconfiguration() failed!",
 911                                         __func__);
 912                         goto out;
 913                 }
 914
 915                 /* Enable DMA input */
 916                 if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode) {
 917                         HASH_CLEAR_BITS(&device_data->base->cr,
 918                                         HASH_CR_DMAE_MASK);
 919                 } else {
 920                         HASH_SET_BITS(&device_data->base->cr,
 921                                         HASH_CR_DMAE_MASK);
 922                         HASH_SET_BITS(&device_data->base->cr,
 923                                         HASH_CR_PRIVN_MASK);
 924                 }
 925
 926                 HASH_INITIALIZE;
 927
 928                 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
 929                         hash_hw_write_key(device_data, ctx->key, ctx->keylen);
 930
 931                 /* Number of bits in last word = (nbytes * 8) % 32 */
 932                 HASH_SET_NBLW((req->nbytes * 8) % 32);
 933                 req_ctx->updated = 1;
 934         }
 935
 936         /* Store the nents in the dma struct. */
 937         ctx->device->dma.nents = hash_get_nents(req->src, req->nbytes, NULL);
 938         if (!ctx->device->dma.nents) {
 939                 dev_err(device_data->dev, "[%s] "
 940                                 "ctx->device->dma.nents = 0", __func__);
 941                 ret = ctx->device->dma.nents;
 942                 goto out;
 943         }
 944
 945         bytes_written = hash_dma_write(ctx, req->src, req->nbytes);
 946         if (bytes_written != req->nbytes) {
 947                 dev_err(device_data->dev, "[%s] "
 948                                 "hash_dma_write() failed!", __func__);
 949                 ret = bytes_written;
 950                 goto out;
 951         }
 952
 953         wait_for_completion(&ctx->device->dma.complete);
 954         hash_dma_done(ctx);
 955
 956         while (device_data->base->str & HASH_STR_DCAL_MASK)
 957                 cpu_relax();
 958
 959         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
 960                 unsigned int keylen = ctx->keylen;
 961                 u8 *key = ctx->key;
 962
 963                 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
 964                                 ctx->keylen);
 965                 hash_hw_write_key(device_data, key, keylen);
 966         }
 967
 968         hash_get_digest(device_data, digest, ctx->config.algorithm);
 969         memcpy(req->result, digest, ctx->digestsize);
 970
 971 out:
 972         release_hash_device(device_data);
 973
 974         /**
 975          * Allocated in setkey, and only used in HMAC.
 976          */
 977         kfree(ctx->key);
 978
 979         return ret;
 980 }
 981
 982 /**
 983  * hash_hw_final - The final hash calculation function
 984  * @req:        The hash request for the job.
 985  */
 986 int hash_hw_final(struct ahash_request *req)
 987 {
 988         int ret = 0;
 989         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 990         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 991         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 992         struct hash_device_data *device_data;
 993         u8 digest[SHA256_DIGEST_SIZE];
 994
 995         ret = hash_get_device_data(ctx, &device_data);
 996         if (ret)
 997                 return ret;
 998
 999         dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
1000
1001         if (req_ctx->updated) {
1002                 ret = hash_resume_state(device_data, &device_data->state);
1003
1004                 if (ret) {
1005                         dev_err(device_data->dev, "[%s] hash_resume_state() "
1006                                         "failed!", __func__);
1007                         goto out;
1008                 }
1009         } else if (req->nbytes == 0 && ctx->keylen == 0) {
1010                 u8 zero_hash[SHA256_DIGEST_SIZE];
1011                 u32 zero_hash_size = 0;
1012                 bool zero_digest = false;
1013                 /**
1014                  * Use a pre-calculated empty message digest
1015                  * (workaround since hw return zeroes, hw bug!?)
1016                  */
1017                 ret = get_empty_message_digest(device_data, &zero_hash[0],
1018                                 &zero_hash_size, &zero_digest);
1019                 if (!ret && likely(zero_hash_size == ctx->digestsize) &&
1020                                 zero_digest) {
1021                         memcpy(req->result, &zero_hash[0], ctx->digestsize);
1022                         goto out;
1023                 } else if (!ret && !zero_digest) {
1024                         dev_dbg(device_data->dev, "[%s] HMAC zero msg with "
1025                                         "key, continue...", __func__);
1026                 } else {
1027                         dev_err(device_data->dev, "[%s] ret=%d, or wrong "
1028                                         "digest size? %s", __func__, ret,
1029                                         (zero_hash_size == ctx->digestsize) ?
1030                                         "true" : "false");
1031                         /* Return error */
1032                         goto out;
1033                 }
1034         } else if (req->nbytes == 0 && ctx->keylen > 0) {
1035                 dev_err(device_data->dev, "[%s] Empty message with "
1036                                 "keylength > 0, NOT supported.", __func__);
1037                 goto out;
1038         }
1039
1040         if (!req_ctx->updated) {
1041                 ret = init_hash_hw(device_data, ctx);
1042                 if (ret) {
1043                         dev_err(device_data->dev, "[%s] init_hash_hw() "
1044                                         "failed!", __func__);
1045                         goto out;
1046                 }
1047         }
1048
1049         if (req_ctx->state.index) {
1050                 hash_messagepad(device_data, req_ctx->state.buffer,
1051                                 req_ctx->state.index);
1052         } else {
1053                 HASH_SET_DCAL;
1054                 while (device_data->base->str & HASH_STR_DCAL_MASK)
1055                         cpu_relax();
1056         }
1057
1058         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
1059                 unsigned int keylen = ctx->keylen;
1060                 u8 *key = ctx->key;
1061
1062                 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
1063                                 ctx->keylen);
1064                 hash_hw_write_key(device_data, key, keylen);
1065         }
1066
1067         hash_get_digest(device_data, digest, ctx->config.algorithm);
1068         memcpy(req->result, digest, ctx->digestsize);
1069
1070 out:
1071         release_hash_device(device_data);
1072
1073         /**
1074          * Allocated in setkey, and only used in HMAC.
1075          */
1076         kfree(ctx->key);
1077
1078         return ret;
1079 }
1080
1081 /**
1082  * hash_hw_update - Updates current HASH computation hashing another part of
1083  *                  the message.
1084  * @req:        Byte array containing the message to be hashed (caller
1085  *              allocated).
1086  */
1087 int hash_hw_update(struct ahash_request *req)
1088 {
1089         int ret = 0;
1090         u8 index = 0;
1091         u8 *buffer;
1092         struct hash_device_data *device_data;
1093         u8 *data_buffer;
1094         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1095         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1096         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1097         struct crypto_hash_walk walk;
1098         int msg_length = crypto_hash_walk_first(req, &walk);
1099
1100         /* Empty message ("") is correct indata */
1101         if (msg_length == 0)
1102                 return ret;
1103
1104         index = req_ctx->state.index;
1105         buffer = (u8 *)req_ctx->state.buffer;
1106
1107         /* Check if ctx->state.length + msg_length
1108            overflows */
1109         if (msg_length > (req_ctx->state.length.low_word + msg_length) &&
1110                         HASH_HIGH_WORD_MAX_VAL ==
1111                         req_ctx->state.length.high_word) {
1112                 pr_err(DEV_DBG_NAME " [%s] HASH_MSG_LENGTH_OVERFLOW!",
1113                                 __func__);
1114                 return -EPERM;
1115         }
1116
1117         ret = hash_get_device_data(ctx, &device_data);
1118         if (ret)
1119                 return ret;
1120
1121         /* Main loop */
1122         while (0 != msg_length) {
1123                 data_buffer = walk.data;
1124                 ret = hash_process_data(device_data, ctx, req_ctx, msg_length,
1125                                 data_buffer, buffer, &index);
1126
1127                 if (ret) {
1128                         dev_err(device_data->dev, "[%s] hash_internal_hw_"
1129                                         "update() failed!", __func__);
1130                         goto out;
1131                 }
1132
1133                 msg_length = crypto_hash_walk_done(&walk, 0);
1134         }
1135
1136         req_ctx->state.index = index;
1137         dev_dbg(device_data->dev, "[%s] indata length=%d, bin=%d))",
1138                         __func__, req_ctx->state.index,
1139                         req_ctx->state.bit_index);
1140
1141 out:
1142         release_hash_device(device_data);
1143
1144         return ret;
1145 }
1146
1147 /**
1148  * hash_resume_state - Function that resumes the state of an calculation.
1149  * @device_data:        Pointer to the device structure.
1150  * @device_state:       The state to be restored in the hash hardware
1151  */
1152 int hash_resume_state(struct hash_device_data *device_data,
1153                 const struct hash_state *device_state)
1154 {
1155         u32 temp_cr;
1156         s32 count;
1157         int hash_mode = HASH_OPER_MODE_HASH;
1158
1159         if (NULL == device_state) {
1160                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1161                                 __func__);
1162                 return -EPERM;
1163         }
1164
1165         /* Check correctness of index and length members */
1166         if (device_state->index > HASH_BLOCK_SIZE
1167             || (device_state->length.low_word % HASH_BLOCK_SIZE) != 0) {
1168                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1169                                 __func__);
1170                 return -EPERM;
1171         }
1172
1173         /*
1174          * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
1175          * prepare the initialize the HASH accelerator to compute the message
1176          * digest of a new message.
1177          */
1178         HASH_INITIALIZE;
1179
1180         temp_cr = device_state->temp_cr;
1181         writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
1182
1183         if (device_data->base->cr & HASH_CR_MODE_MASK)
1184                 hash_mode = HASH_OPER_MODE_HMAC;
1185         else
1186                 hash_mode = HASH_OPER_MODE_HASH;
1187
1188         for (count = 0; count < HASH_CSR_COUNT; count++) {
1189                 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1190                         break;
1191
1192                 writel_relaxed(device_state->csr[count],
1193                                 &device_data->base->csrx[count]);
1194         }
1195
1196         writel_relaxed(device_state->csfull, &device_data->base->csfull);
1197         writel_relaxed(device_state->csdatain, &device_data->base->csdatain);
1198
1199         writel_relaxed(device_state->str_reg, &device_data->base->str);
1200         writel_relaxed(temp_cr, &device_data->base->cr);
1201
1202         return 0;
1203 }
1204
1205 /**
1206  * hash_save_state - Function that saves the state of hardware.
1207  * @device_data:        Pointer to the device structure.
1208  * @device_state:       The strucure where the hardware state should be saved.
1209  */
1210 int hash_save_state(struct hash_device_data *device_data,
1211                 struct hash_state *device_state)
1212 {
1213         u32 temp_cr;
1214         u32 count;
1215         int hash_mode = HASH_OPER_MODE_HASH;
1216
1217         if (NULL == device_state) {
1218                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1219                                 __func__);
1220                 return -ENOTSUPP;
1221         }
1222
1223         /* Write dummy value to force digest intermediate calculation. This
1224          * actually makes sure that there isn't any ongoing calculation in the
1225          * hardware.
1226          */
1227         while (device_data->base->str & HASH_STR_DCAL_MASK)
1228                 cpu_relax();
1229
1230         temp_cr = readl_relaxed(&device_data->base->cr);
1231
1232         device_state->str_reg = readl_relaxed(&device_data->base->str);
1233
1234         device_state->din_reg = readl_relaxed(&device_data->base->din);
1235
1236         if (device_data->base->cr & HASH_CR_MODE_MASK)
1237                 hash_mode = HASH_OPER_MODE_HMAC;
1238         else
1239                 hash_mode = HASH_OPER_MODE_HASH;
1240
1241         for (count = 0; count < HASH_CSR_COUNT; count++) {
1242                 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1243                         break;
1244
1245                 device_state->csr[count] =
1246                         readl_relaxed(&device_data->base->csrx[count]);
1247         }
1248
1249         device_state->csfull = readl_relaxed(&device_data->base->csfull);
1250         device_state->csdatain = readl_relaxed(&device_data->base->csdatain);
1251
1252         device_state->temp_cr = temp_cr;
1253
1254         return 0;
1255 }
1256
1257 /**
1258  * hash_check_hw - This routine checks for peripheral Ids and PCell Ids.
1259  * @device_data:
1260  *
1261  */
1262 int hash_check_hw(struct hash_device_data *device_data)
1263 {
1264         /* Checking Peripheral Ids  */
1265         if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0)
1266                 && HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1)
1267                 && HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2)
1268                 && HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3)
1269                 && HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0)
1270                 && HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1)
1271                 && HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2)
1272                 && HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)
1273            ) {
1274                 return 0;
1275         }
1276
1277         dev_err(device_data->dev, "[%s] HASH_UNSUPPORTED_HW!",
1278                         __func__);
1279         return -ENOTSUPP;
1280 }
1281
1282 /**
1283  * hash_get_digest - Gets the digest.
1284  * @device_data:        Pointer to the device structure.
1285  * @digest:             User allocated byte array for the calculated digest.
1286  * @algorithm:          The algorithm in use.
1287  */
1288 void hash_get_digest(struct hash_device_data *device_data,
1289                 u8 *digest, int algorithm)
1290 {
1291         u32 temp_hx_val, count;
1292         int loop_ctr;
1293
1294         if (algorithm != HASH_ALGO_SHA1 && algorithm != HASH_ALGO_SHA256) {
1295                 dev_err(device_data->dev, "[%s] Incorrect algorithm %d",
1296                                 __func__, algorithm);
1297                 return;
1298         }
1299
1300         if (algorithm == HASH_ALGO_SHA1)
1301                 loop_ctr = SHA1_DIGEST_SIZE / sizeof(u32);
1302         else
1303                 loop_ctr = SHA256_DIGEST_SIZE / sizeof(u32);
1304
1305         dev_dbg(device_data->dev, "[%s] digest array:(0x%x)",
1306                         __func__, (u32) digest);
1307
1308         /* Copy result into digest array */
1309         for (count = 0; count < loop_ctr; count++) {
1310                 temp_hx_val = readl_relaxed(&device_data->base->hx[count]);
1311                 digest[count * 4] = (u8) ((temp_hx_val >> 24) & 0xFF);
1312                 digest[count * 4 + 1] = (u8) ((temp_hx_val >> 16) & 0xFF);
1313                 digest[count * 4 + 2] = (u8) ((temp_hx_val >> 8) & 0xFF);
1314                 digest[count * 4 + 3] = (u8) ((temp_hx_val >> 0) & 0xFF);
1315         }
1316 }
1317
1318 /**
1319  * hash_update - The hash update function for SHA1/SHA2 (SHA256).
1320  * @req: The hash request for the job.
1321  */
1322 static int ahash_update(struct ahash_request *req)
1323 {
1324         int ret = 0;
1325         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1326
1327         if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode)
1328                 ret = hash_hw_update(req);
1329         /* Skip update for DMA, all data will be passed to DMA in final */
1330
1331         if (ret) {
1332                 pr_err(DEV_DBG_NAME " [%s] hash_hw_update() failed!",
1333                                 __func__);
1334         }
1335
1336         return ret;
1337 }
1338
1339 /**
1340  * hash_final - The hash final function for SHA1/SHA2 (SHA256).
1341  * @req:        The hash request for the job.
1342  */
1343 static int ahash_final(struct ahash_request *req)
1344 {
1345         int ret = 0;
1346         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1347
1348         pr_debug(DEV_DBG_NAME " [%s] data size: %d", __func__, req->nbytes);
1349
1350         if ((hash_mode == HASH_MODE_DMA) && req_ctx->dma_mode)
1351                 ret = hash_dma_final(req);
1352         else
1353                 ret = hash_hw_final(req);
1354
1355         if (ret) {
1356                 pr_err(DEV_DBG_NAME " [%s] hash_hw/dma_final() failed",
1357                                 __func__);
1358         }
1359
1360         return ret;
1361 }
1362
1363 static int hash_setkey(struct crypto_ahash *tfm,
1364                 const u8 *key, unsigned int keylen, int alg)
1365 {
1366         int ret = 0;
1367         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1368
1369         /**
1370          * Freed in final.
1371          */
1372         ctx->key = kmemdup(key, keylen, GFP_KERNEL);
1373         if (!ctx->key) {
1374                 pr_err(DEV_DBG_NAME " [%s] Failed to allocate ctx->key "
1375                        "for %d\n", __func__, alg);
1376                 return -ENOMEM;
1377         }
1378         ctx->keylen = keylen;
1379
1380         return ret;
1381 }
1382
1383 static int ahash_sha1_init(struct ahash_request *req)
1384 {
1385         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1386         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1387
1388         ctx->config.data_format = HASH_DATA_8_BITS;
1389         ctx->config.algorithm = HASH_ALGO_SHA1;
1390         ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1391         ctx->digestsize = SHA1_DIGEST_SIZE;
1392
1393         return hash_init(req);
1394 }
1395
1396 static int ahash_sha256_init(struct ahash_request *req)
1397 {
1398         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1399         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1400
1401         ctx->config.data_format = HASH_DATA_8_BITS;
1402         ctx->config.algorithm = HASH_ALGO_SHA256;
1403         ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1404         ctx->digestsize = SHA256_DIGEST_SIZE;
1405
1406         return hash_init(req);
1407 }
1408
1409 static int ahash_sha1_digest(struct ahash_request *req)
1410 {
1411         int ret2, ret1;
1412
1413         ret1 = ahash_sha1_init(req);
1414         if (ret1)
1415                 goto out;
1416
1417         ret1 = ahash_update(req);
1418         ret2 = ahash_final(req);
1419
1420 out:
1421         return ret1 ? ret1 : ret2;
1422 }
1423
1424 static int ahash_sha256_digest(struct ahash_request *req)
1425 {
1426         int ret2, ret1;
1427
1428         ret1 = ahash_sha256_init(req);
1429         if (ret1)
1430                 goto out;
1431
1432         ret1 = ahash_update(req);
1433         ret2 = ahash_final(req);
1434
1435 out:
1436         return ret1 ? ret1 : ret2;
1437 }
1438
1439 static int hmac_sha1_init(struct ahash_request *req)
1440 {
1441         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1442         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1443
1444         ctx->config.data_format = HASH_DATA_8_BITS;
1445         ctx->config.algorithm   = HASH_ALGO_SHA1;
1446         ctx->config.oper_mode   = HASH_OPER_MODE_HMAC;
1447         ctx->digestsize         = SHA1_DIGEST_SIZE;
1448
1449         return hash_init(req);
1450 }
1451
1452 static int hmac_sha256_init(struct ahash_request *req)
1453 {
1454         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1455         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1456
1457         ctx->config.data_format = HASH_DATA_8_BITS;
1458         ctx->config.algorithm   = HASH_ALGO_SHA256;
1459         ctx->config.oper_mode   = HASH_OPER_MODE_HMAC;
1460         ctx->digestsize         = SHA256_DIGEST_SIZE;
1461
1462         return hash_init(req);
1463 }
1464
1465 static int hmac_sha1_digest(struct ahash_request *req)
1466 {
1467         int ret2, ret1;
1468
1469         ret1 = hmac_sha1_init(req);
1470         if (ret1)
1471                 goto out;
1472
1473         ret1 = ahash_update(req);
1474         ret2 = ahash_final(req);
1475
1476 out:
1477         return ret1 ? ret1 : ret2;
1478 }
1479
1480 static int hmac_sha256_digest(struct ahash_request *req)
1481 {
1482         int ret2, ret1;
1483
1484         ret1 = hmac_sha256_init(req);
1485         if (ret1)
1486                 goto out;
1487
1488         ret1 = ahash_update(req);
1489         ret2 = ahash_final(req);
1490
1491 out:
1492         return ret1 ? ret1 : ret2;
1493 }
1494
1495 static int hmac_sha1_setkey(struct crypto_ahash *tfm,
1496                 const u8 *key, unsigned int keylen)
1497 {
1498         return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA1);
1499 }
1500
1501 static int hmac_sha256_setkey(struct crypto_ahash *tfm,
1502                 const u8 *key, unsigned int keylen)
1503 {
1504         return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA256);
1505 }
1506
1507 struct hash_algo_template {
1508         struct hash_config conf;
1509         struct ahash_alg hash;
1510 };
1511
1512 static int hash_cra_init(struct crypto_tfm *tfm)
1513 {
1514         struct hash_ctx *ctx = crypto_tfm_ctx(tfm);
1515         struct crypto_alg *alg = tfm->__crt_alg;
1516         struct hash_algo_template *hash_alg;
1517
1518         hash_alg = container_of(__crypto_ahash_alg(alg),
1519                         struct hash_algo_template,
1520                         hash);
1521
1522         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1523                         sizeof(struct hash_req_ctx));
1524
1525         ctx->config.data_format = HASH_DATA_8_BITS;
1526         ctx->config.algorithm = hash_alg->conf.algorithm;
1527         ctx->config.oper_mode = hash_alg->conf.oper_mode;
1528
1529         ctx->digestsize = hash_alg->hash.halg.digestsize;
1530
1531         return 0;
1532 }
1533
1534 static struct hash_algo_template hash_algs[] = {
1535         {
1536                         .conf.algorithm = HASH_ALGO_SHA1,
1537                         .conf.oper_mode = HASH_OPER_MODE_HASH,
1538                         .hash = {
1539                                 .init = hash_init,
1540                                 .update = ahash_update,
1541                                 .final = ahash_final,
1542                                 .digest = ahash_sha1_digest,
1543                                 .halg.digestsize = SHA1_DIGEST_SIZE,
1544                                 .halg.statesize = sizeof(struct hash_ctx),
1545                                 .halg.base = {
1546                                         .cra_name = "sha1",
1547                                         .cra_driver_name = "sha1-ux500",
1548                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1549                                                         CRYPTO_ALG_ASYNC,
1550                                         .cra_blocksize = SHA1_BLOCK_SIZE,
1551                                         .cra_ctxsize = sizeof(struct hash_ctx),
1552                                         .cra_init = hash_cra_init,
1553                                         .cra_module = THIS_MODULE,
1554                         }
1555                 }
1556         },
1557         {
1558                         .conf.algorithm         = HASH_ALGO_SHA256,
1559                         .conf.oper_mode         = HASH_OPER_MODE_HASH,
1560                         .hash = {
1561                                 .init = hash_init,
1562                                 .update = ahash_update,
1563                                 .final = ahash_final,
1564                                 .digest = ahash_sha256_digest,
1565                                 .halg.digestsize = SHA256_DIGEST_SIZE,
1566                                 .halg.statesize = sizeof(struct hash_ctx),
1567                                 .halg.base = {
1568                                         .cra_name = "sha256",
1569                                         .cra_driver_name = "sha256-ux500",
1570                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1571                                                         CRYPTO_ALG_ASYNC,
1572                                         .cra_blocksize = SHA256_BLOCK_SIZE,
1573                                         .cra_ctxsize = sizeof(struct hash_ctx),
1574                                         .cra_type = &crypto_ahash_type,
1575                                         .cra_init = hash_cra_init,
1576                                         .cra_module = THIS_MODULE,
1577                                 }
1578                         }
1579
1580         },
1581         {
1582                         .conf.algorithm         = HASH_ALGO_SHA1,
1583                         .conf.oper_mode         = HASH_OPER_MODE_HMAC,
1584                         .hash = {
1585                                 .init = hash_init,
1586                                 .update = ahash_update,
1587                                 .final = ahash_final,
1588                                 .digest = hmac_sha1_digest,
1589                                 .setkey = hmac_sha1_setkey,
1590                                 .halg.digestsize = SHA1_DIGEST_SIZE,
1591                                 .halg.statesize = sizeof(struct hash_ctx),
1592                                 .halg.base = {
1593                                         .cra_name = "hmac(sha1)",
1594                                         .cra_driver_name = "hmac-sha1-ux500",
1595                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1596                                                         CRYPTO_ALG_ASYNC,
1597                                         .cra_blocksize = SHA1_BLOCK_SIZE,
1598                                         .cra_ctxsize = sizeof(struct hash_ctx),
1599                                         .cra_type = &crypto_ahash_type,
1600                                         .cra_init = hash_cra_init,
1601                                         .cra_module = THIS_MODULE,
1602                                 }
1603                         }
1604         },
1605         {
1606                         .conf.algorithm         = HASH_ALGO_SHA256,
1607                         .conf.oper_mode         = HASH_OPER_MODE_HMAC,
1608                         .hash = {
1609                                 .init = hash_init,
1610                                 .update = ahash_update,
1611                                 .final = ahash_final,
1612                                 .digest = hmac_sha256_digest,
1613                                 .setkey = hmac_sha256_setkey,
1614                                 .halg.digestsize = SHA256_DIGEST_SIZE,
1615                                 .halg.statesize = sizeof(struct hash_ctx),
1616                                 .halg.base = {
1617                                         .cra_name = "hmac(sha256)",
1618                                         .cra_driver_name = "hmac-sha256-ux500",
1619                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1620                                                         CRYPTO_ALG_ASYNC,
1621                                         .cra_blocksize = SHA256_BLOCK_SIZE,
1622                                         .cra_ctxsize = sizeof(struct hash_ctx),
1623                                         .cra_type = &crypto_ahash_type,
1624                                         .cra_init = hash_cra_init,
1625                                         .cra_module = THIS_MODULE,
1626                                 }
1627                         }
1628         }
1629 };
1630
1631 /**
1632  * hash_algs_register_all -
1633  */
1634 static int ahash_algs_register_all(struct hash_device_data *device_data)
1635 {
1636         int ret;
1637         int i;
1638         int count;
1639
1640         for (i = 0; i < ARRAY_SIZE(hash_algs); i++) {
1641                 ret = crypto_register_ahash(&hash_algs[i].hash);
1642                 if (ret) {
1643                         count = i;
1644                         dev_err(device_data->dev, "[%s] alg registration failed",
1645                                 hash_algs[i].hash.halg.base.cra_driver_name);
1646                         goto unreg;
1647                 }
1648         }
1649         return 0;
1650 unreg:
1651         for (i = 0; i < count; i++)
1652                 crypto_unregister_ahash(&hash_algs[i].hash);
1653         return ret;
1654 }
1655
1656 /**
1657  * hash_algs_unregister_all -
1658  */
1659 static void ahash_algs_unregister_all(struct hash_device_data *device_data)
1660 {
1661         int i;
1662
1663         for (i = 0; i < ARRAY_SIZE(hash_algs); i++)
1664                 crypto_unregister_ahash(&hash_algs[i].hash);
1665 }
1666
1667 /**
1668  * ux500_hash_probe - Function that probes the hash hardware.
1669  * @pdev: The platform device.
1670  */
1671 static int ux500_hash_probe(struct platform_device *pdev)
1672 {
1673         int                     ret = 0;
1674         struct resource         *res = NULL;
1675         struct hash_device_data *device_data;
1676         struct device           *dev = &pdev->dev;
1677
1678         device_data = kzalloc(sizeof(struct hash_device_data), GFP_ATOMIC);
1679         if (!device_data) {
1680                 dev_dbg(dev, "[%s] kzalloc() failed!", __func__);
1681                 ret = -ENOMEM;
1682                 goto out;
1683         }
1684
1685         device_data->dev = dev;
1686         device_data->current_ctx = NULL;
1687
1688         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1689         if (!res) {
1690                 dev_dbg(dev, "[%s] platform_get_resource() failed!", __func__);
1691                 ret = -ENODEV;
1692                 goto out_kfree;
1693         }
1694
1695         res = request_mem_region(res->start, resource_size(res), pdev->name);
1696         if (res == NULL) {
1697                 dev_dbg(dev, "[%s] request_mem_region() failed!", __func__);
1698                 ret = -EBUSY;
1699                 goto out_kfree;
1700         }
1701
1702         device_data->base = ioremap(res->start, resource_size(res));
1703         if (!device_data->base) {
1704                 dev_err(dev, "[%s] ioremap() failed!",
1705                                 __func__);
1706                 ret = -ENOMEM;
1707                 goto out_free_mem;
1708         }
1709         spin_lock_init(&device_data->ctx_lock);
1710         spin_lock_init(&device_data->power_state_lock);
1711
1712         /* Enable power for HASH1 hardware block */
1713         device_data->regulator = regulator_get(dev, "v-ape");
1714         if (IS_ERR(device_data->regulator)) {
1715                 dev_err(dev, "[%s] regulator_get() failed!", __func__);
1716                 ret = PTR_ERR(device_data->regulator);
1717                 device_data->regulator = NULL;
1718                 goto out_unmap;
1719         }
1720
1721         /* Enable the clock for HASH1 hardware block */
1722         device_data->clk = clk_get(dev, NULL);
1723         if (IS_ERR(device_data->clk)) {
1724                 dev_err(dev, "[%s] clk_get() failed!", __func__);
1725                 ret = PTR_ERR(device_data->clk);
1726                 goto out_regulator;
1727         }
1728
1729         /* Enable device power (and clock) */
1730         ret = hash_enable_power(device_data, false);
1731         if (ret) {
1732                 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1733                 goto out_clk;
1734         }
1735
1736         ret = hash_check_hw(device_data);
1737         if (ret) {
1738                 dev_err(dev, "[%s] hash_check_hw() failed!", __func__);
1739                 goto out_power;
1740         }
1741
1742         if (hash_mode == HASH_MODE_DMA)
1743                 hash_dma_setup_channel(device_data, dev);
1744
1745         platform_set_drvdata(pdev, device_data);
1746
1747         /* Put the new device into the device list... */
1748         klist_add_tail(&device_data->list_node, &driver_data.device_list);
1749         /* ... and signal that a new device is available. */
1750         up(&driver_data.device_allocation);
1751
1752         ret = ahash_algs_register_all(device_data);
1753         if (ret) {
1754                 dev_err(dev, "[%s] ahash_algs_register_all() "
1755                                 "failed!", __func__);
1756                 goto out_power;
1757         }
1758
1759         dev_info(dev, "[%s] successfully probed\n", __func__);
1760         return 0;
1761
1762 out_power:
1763         hash_disable_power(device_data, false);
1764
1765 out_clk:
1766         clk_put(device_data->clk);
1767
1768 out_regulator:
1769         regulator_put(device_data->regulator);
1770
1771 out_unmap:
1772         iounmap(device_data->base);
1773
1774 out_free_mem:
1775         release_mem_region(res->start, resource_size(res));
1776
1777 out_kfree:
1778         kfree(device_data);
1779 out:
1780         return ret;
1781 }
1782
1783 /**
1784  * ux500_hash_remove - Function that removes the hash device from the platform.
1785  * @pdev: The platform device.
1786  */
1787 static int ux500_hash_remove(struct platform_device *pdev)
1788 {
1789         struct resource         *res;
1790         struct hash_device_data *device_data;
1791         struct device           *dev = &pdev->dev;
1792
1793         device_data = platform_get_drvdata(pdev);
1794         if (!device_data) {
1795                 dev_err(dev, "[%s]: platform_get_drvdata() failed!",
1796                         __func__);
1797                 return -ENOMEM;
1798         }
1799
1800         /* Try to decrease the number of available devices. */
1801         if (down_trylock(&driver_data.device_allocation))
1802                 return -EBUSY;
1803
1804         /* Check that the device is free */
1805         spin_lock(&device_data->ctx_lock);
1806         /* current_ctx allocates a device, NULL = unallocated */
1807         if (device_data->current_ctx) {
1808                 /* The device is busy */
1809                 spin_unlock(&device_data->ctx_lock);
1810                 /* Return the device to the pool. */
1811                 up(&driver_data.device_allocation);
1812                 return -EBUSY;
1813         }
1814
1815         spin_unlock(&device_data->ctx_lock);
1816
1817         /* Remove the device from the list */
1818         if (klist_node_attached(&device_data->list_node))
1819                 klist_remove(&device_data->list_node);
1820
1821         /* If this was the last device, remove the services */
1822         if (list_empty(&driver_data.device_list.k_list))
1823                 ahash_algs_unregister_all(device_data);
1824
1825         if (hash_disable_power(device_data, false))
1826                 dev_err(dev, "[%s]: hash_disable_power() failed",
1827                         __func__);
1828
1829         clk_put(device_data->clk);
1830         regulator_put(device_data->regulator);
1831
1832         iounmap(device_data->base);
1833
1834         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1835         if (res)
1836                 release_mem_region(res->start, resource_size(res));
1837
1838         kfree(device_data);
1839
1840         return 0;
1841 }
1842
1843 /**
1844  * ux500_hash_shutdown - Function that shutdown the hash device.
1845  * @pdev: The platform device
1846  */
1847 static void ux500_hash_shutdown(struct platform_device *pdev)
1848 {
1849         struct resource *res = NULL;
1850         struct hash_device_data *device_data;
1851
1852         device_data = platform_get_drvdata(pdev);
1853         if (!device_data) {
1854                 dev_err(&pdev->dev, "[%s] platform_get_drvdata() failed!",
1855                                 __func__);
1856                 return;
1857         }
1858
1859         /* Check that the device is free */
1860         spin_lock(&device_data->ctx_lock);
1861         /* current_ctx allocates a device, NULL = unallocated */
1862         if (!device_data->current_ctx) {
1863                 if (down_trylock(&driver_data.device_allocation))
1864                         dev_dbg(&pdev->dev, "[%s]: Cryp still in use!"
1865                                 "Shutting down anyway...", __func__);
1866                 /**
1867                  * (Allocate the device)
1868                  * Need to set this to non-null (dummy) value,
1869                  * to avoid usage if context switching.
1870                  */
1871                 device_data->current_ctx++;
1872         }
1873         spin_unlock(&device_data->ctx_lock);
1874
1875         /* Remove the device from the list */
1876         if (klist_node_attached(&device_data->list_node))
1877                 klist_remove(&device_data->list_node);
1878
1879         /* If this was the last device, remove the services */
1880         if (list_empty(&driver_data.device_list.k_list))
1881                 ahash_algs_unregister_all(device_data);
1882
1883         iounmap(device_data->base);
1884
1885         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886         if (res)
1887                 release_mem_region(res->start, resource_size(res));
1888
1889         if (hash_disable_power(device_data, false))
1890                 dev_err(&pdev->dev, "[%s] hash_disable_power() failed",
1891                                 __func__);
1892 }
1893
1894 /**
1895  * ux500_hash_suspend - Function that suspends the hash device.
1896  * @dev:        Device to suspend.
1897  */
1898 static int ux500_hash_suspend(struct device *dev)
1899 {
1900         int ret;
1901         struct hash_device_data *device_data;
1902         struct hash_ctx *temp_ctx = NULL;
1903
1904         device_data = dev_get_drvdata(dev);
1905         if (!device_data) {
1906                 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1907                 return -ENOMEM;
1908         }
1909
1910         spin_lock(&device_data->ctx_lock);
1911         if (!device_data->current_ctx)
1912                 device_data->current_ctx++;
1913         spin_unlock(&device_data->ctx_lock);
1914
1915         if (device_data->current_ctx == ++temp_ctx) {
1916                 if (down_interruptible(&driver_data.device_allocation))
1917                         dev_dbg(dev, "[%s]: down_interruptible() failed",
1918                                 __func__);
1919                 ret = hash_disable_power(device_data, false);
1920
1921         } else
1922                 ret = hash_disable_power(device_data, true);
1923
1924         if (ret)
1925                 dev_err(dev, "[%s]: hash_disable_power()", __func__);
1926
1927         return ret;
1928 }
1929
1930 /**
1931  * ux500_hash_resume - Function that resume the hash device.
1932  * @dev:        Device to resume.
1933  */
1934 static int ux500_hash_resume(struct device *dev)
1935 {
1936         int ret = 0;
1937         struct hash_device_data *device_data;
1938         struct hash_ctx *temp_ctx = NULL;
1939
1940         device_data = dev_get_drvdata(dev);
1941         if (!device_data) {
1942                 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1943                 return -ENOMEM;
1944         }
1945
1946         spin_lock(&device_data->ctx_lock);
1947         if (device_data->current_ctx == ++temp_ctx)
1948                 device_data->current_ctx = NULL;
1949         spin_unlock(&device_data->ctx_lock);
1950
1951         if (!device_data->current_ctx)
1952                 up(&driver_data.device_allocation);
1953         else
1954                 ret = hash_enable_power(device_data, true);
1955
1956         if (ret)
1957                 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1958
1959         return ret;
1960 }
1961
1962 static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
1963
1964 static struct platform_driver hash_driver = {
1965         .probe  = ux500_hash_probe,
1966         .remove = ux500_hash_remove,
1967         .shutdown = ux500_hash_shutdown,
1968         .driver = {
1969                 .owner = THIS_MODULE,
1970                 .name  = "hash1",
1971                 .pm    = &ux500_hash_pm,
1972         }
1973 };
1974
1975 /**
1976  * ux500_hash_mod_init - The kernel module init function.
1977  */
1978 static int __init ux500_hash_mod_init(void)
1979 {
1980         klist_init(&driver_data.device_list, NULL, NULL);
1981         /* Initialize the semaphore to 0 devices (locked state) */
1982         sema_init(&driver_data.device_allocation, 0);
1983
1984         return platform_driver_register(&hash_driver);
1985 }
1986
1987 /**
1988  * ux500_hash_mod_fini - The kernel module exit function.
1989  */
1990 static void __exit ux500_hash_mod_fini(void)
1991 {
1992         platform_driver_unregister(&hash_driver);
1993 }
1994
1995 module_init(ux500_hash_mod_init);
1996 module_exit(ux500_hash_mod_fini);
1997
1998 MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine.");
1999 MODULE_LICENSE("GPL");
2000
2001 MODULE_ALIAS("sha1-all");
2002 MODULE_ALIAS("sha256-all");
2003 MODULE_ALIAS("hmac-sha1-all");
2004 MODULE_ALIAS("hmac-sha256-all");